Eddie Hung
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33862d0445
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WIP for fixing partitioning, temporarily do not partition
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2019-07-11 09:22:52 -07:00 |
Eddie Hung
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d357431df1
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Restore from master
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2019-07-10 22:54:39 -07:00 |
Eddie Hung
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f984e0cb34
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Another typo
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2019-07-10 22:33:35 -07:00 |
Eddie Hung
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375fcbe511
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abc_flop to also get topologically sorted
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2019-07-10 20:26:09 -07:00 |
Eddie Hung
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9f608d6be3
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write_verilog with *.v extension
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2019-07-10 20:25:59 -07:00 |
Eddie Hung
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ea6ffea2cd
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Fix clk_pol for FD*_1
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2019-07-10 20:10:20 -07:00 |
Eddie Hung
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7899a06ed6
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Another typo
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2019-07-10 19:59:24 -07:00 |
Eddie Hung
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ad35b509de
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Another typo
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2019-07-10 19:05:53 -07:00 |
Eddie Hung
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e603d719d6
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Fix spacing
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2019-07-10 19:04:22 -07:00 |
Eddie Hung
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f3511e4f93
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Use \$currQ
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2019-07-10 19:01:13 -07:00 |
Eddie Hung
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71acd3ddcf
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Remove -retime from abc9, revert to abc behav with separate clock/en domains
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2019-07-10 18:57:44 -07:00 |
Eddie Hung
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f030be3f1c
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Preserve all parameters, plus some extra ones for clk/en polarity
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2019-07-10 18:57:11 -07:00 |
Eddie Hung
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f8f0ffe786
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Small opt
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2019-07-10 18:56:50 -07:00 |
Eddie Hung
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4a995c5d80
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Change how to specify flops to ABC again
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2019-07-10 17:54:56 -07:00 |
Eddie Hung
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a092c48f03
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Use split_tokens()
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2019-07-10 17:34:51 -07:00 |
Eddie Hung
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3bb48facb2
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Remove params from FD*_1 variants
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2019-07-10 17:17:54 -07:00 |
Eddie Hung
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0372c900e8
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Fix typo, and have !{PRE,CLR} behave as CE
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2019-07-10 17:15:49 -07:00 |
Eddie Hung
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7b2599cb94
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Move ABC FF stuff to abc_ff.v; add support for other FD* types
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2019-07-10 17:06:05 -07:00 |
Eddie Hung
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0ab8f28bc7
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Uncomment IS_C_INVERTED parameter
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2019-07-10 16:23:15 -07:00 |
Eddie Hung
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838ae1a14c
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synth_xilinx's map_cells stage to techmap ff_map.v
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2019-07-10 16:15:57 -07:00 |
Eddie Hung
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73c8f1a59e
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Fix box numbering
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2019-07-10 16:12:33 -07:00 |
Eddie Hung
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052060f109
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-07-10 16:05:41 -07:00 |
Eddie Hung
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bb2144ae73
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Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Error out if -abc9 and -retime specified
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2019-07-10 14:38:13 -07:00 |
Eddie Hung
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2f990a7319
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Merge pull request #1148 from YosysHQ/xc7mux
synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
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2019-07-10 14:38:00 -07:00 |
Eddie Hung
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6bbd286e03
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Error out if -abc9 and -retime specified
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2019-07-10 12:47:48 -07:00 |
Eddie Hung
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58bb84e5b2
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Add some spacing
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2019-07-10 12:32:33 -07:00 |
Eddie Hung
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521971e32e
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Add some ASCII art explaining mux decomposition
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2019-07-10 12:20:04 -07:00 |
Clifford Wolf
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c66b4b9131
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Merge pull request #1177 from YosysHQ/clifford/async
Fix clk2fflogic adff reset semantic to negative hold time on reset
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2019-07-10 08:48:20 +02:00 |
Eddie Hung
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e573d024a2
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Call muxpack and pmux2shiftx before cmp2lut
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2019-07-09 21:26:38 -07:00 |
Eddie Hung
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c55530b901
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Restore opt_clean back to original place
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2019-07-09 14:29:58 -07:00 |
Eddie Hung
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5b48b18d29
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Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
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2019-07-09 14:28:54 -07:00 |
David Shah
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27b27b8781
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synth_ecp5: Fix typo in copyright header
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-09 22:26:10 +01:00 |
Clifford Wolf
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cae26bf330
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Merge pull request #1174 from YosysHQ/eddie/fix1173
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
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2019-07-09 22:59:51 +02:00 |
Clifford Wolf
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6dd33be7ce
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Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
write_verilog: fix placement of case attributes
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2019-07-09 22:51:25 +02:00 |
Clifford Wolf
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9546ccdbd3
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Fix tests/various/async FFL test
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-07-09 22:44:39 +02:00 |
Clifford Wolf
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5138621482
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Improve tests/various/async, disable failing ffl test
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-07-09 22:21:25 +02:00 |
Eddie Hung
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b1a048a703
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Extend using A[1] to preserve don't care
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2019-07-09 12:35:41 -07:00 |
Eddie Hung
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f604aa174e
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Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc
Revert "Add "synth -keepdc" option"
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2019-07-09 12:19:40 -07:00 |
Eddie Hung
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bee5d2b21a
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Merge remote-tracking branch 'origin/eddie/fix1173' into xc7mux
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2019-07-09 12:16:33 -07:00 |
whitequark
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37bb6b5e96
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write_verilog: fix placement of case attributes. NFC.
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2019-07-09 19:14:03 +00:00 |
Eddie Hung
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c2db70f41e
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Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
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2019-07-09 12:14:00 -07:00 |
Clifford Wolf
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c18b23f055
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Add tests/various/async.{sh,v}
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-07-09 20:58:59 +02:00 |
Clifford Wolf
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3dd92fcd15
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Improve tests/various/run-test.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-07-09 20:58:28 +02:00 |
Clifford Wolf
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f8512864cd
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Add tests/simple_abc9/.gitignore
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-07-09 20:58:01 +02:00 |
Eddie Hung
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93522b0ae1
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Extend during mux decomposition with 1'bx
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2019-07-09 10:59:37 -07:00 |
Eddie Hung
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c864995343
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Fix typo and comments
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2019-07-09 10:38:07 -07:00 |
Eddie Hung
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00d8a9dce2
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Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore
Rename __builtin_bswap32 -> bswap32
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2019-07-09 10:22:57 -07:00 |
Eddie Hung
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c91cb73562
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-07-09 10:22:49 -07:00 |
Eddie Hung
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c68b909210
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synth_xilinx to call commands of synth -coarse directly
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2019-07-09 10:21:54 -07:00 |
Eddie Hung
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737340327f
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Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""
This reverts commit 7f964859ec .
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2019-07-09 10:15:02 -07:00 |