riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
7,631 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

785 Commits

Author SHA1 Message Date
Eddie Hung 90a954bb9c Get rid of latch_* in write_xaiger 2019-10-07 13:09:13 -07:00
Eddie Hung 1504ca2cd9 Remove "write_xaiger -zinit" 2019-10-07 11:58:49 -07:00
Eddie Hung e1554b56dd Add comment on default flop init 2019-10-07 11:56:17 -07:00
Eddie Hung d9fba95177 Get rid of output_port lookup 2019-10-07 11:49:06 -07:00
Eddie Hung 3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung 3c6e5d82a6 Error if $currQ not found 2019-10-05 09:06:13 -07:00
Eddie Hung 7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung 7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 549d6ea467 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-03 10:55:23 -07:00
Clifford Wolf 2ed2e9c3e8 Change smtbmc "Warmup failed" status to "PREUNSAT" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 14:59:07 +02:00
Clifford Wolf a84a2d74c7 Fix btor back-end to use "state" instead of "input" for undef init bits 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-02 12:48:04 +02:00
Eddie Hung 1b96d29174 No need to punch ports at all 2019-09-30 17:02:20 -07:00
Eddie Hung e529872b01 Remove need for $currQ port connection 2019-09-30 16:33:40 -07:00
Eddie Hung eecfdda614 Cleanup 2019-09-30 15:24:03 -07:00
Eddie Hung 74678227c7 Use a cell_cache to instantiate once rather than opt_merge call 2019-09-30 13:21:07 -07:00
Eddie Hung a6994c5f16 scc call on active module module only, plus cleanup 2019-09-30 12:57:19 -07:00
Eddie Hung bd8356799a Use derived module 2019-09-30 12:34:28 -07:00
Eddie Hung 1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung f3e150d9a5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 09:21:51 -07:00
Miodrag Milanović ce0631c371
Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out 
Support binary files for backends, fixes #1407
 2019-09-29 10:37:34 +02:00
Eddie Hung 79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Miodrag Milanovic 0c380f0855 Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
Miodrag Milanovic d0493925ec Support binary files for backends, fixes #1407 2019-09-28 09:36:18 +02:00
Eddie Hung cfa6dd61ef Use abc_mergeability attr for "r" extension 2019-09-27 18:41:43 -07:00
Eddie Hung dc154c39a8 Fix infinite recursion 2019-09-27 17:45:49 -07:00
Eddie Hung 8f5710c464 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-27 15:14:31 -07:00
Aman Goel 5eebfabe42 Corrects btor2 backend 2019-09-27 12:40:17 -04:00
Eddie Hung 44374b1b2b "abc_padding" attr for blackbox outputs that were padded, remove them later 2019-09-23 21:58:40 -07:00
Eddie Hung c340fbfab2 Force $inout.out ports to begin with '$' to indicate internal 2019-09-23 21:58:04 -07:00
Eddie Hung 2d9484c12c When two boxes connect to each other, need not be a (* keep *) 2019-09-19 15:40:28 -07:00
Clifford Wolf 779ce3537f Add "write_aiger -L" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-18 13:33:02 +02:00
Clifford Wolf b88d2e5f30 Fix stupid bug in btor back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-18 11:56:14 +02:00
Sean Cross c1b628508d backends: smt2: use $(CXX) variable for compiler 
The Makefile assumes the compiler is called `gcc`, which isn't always
true.  In fact, if we're building on msys2 or msys2-64, the compiler
is called `i686-w64-mingw32-g++` or `x86_64-w64-mingw32-g++`.

Use the variable instead of hardcoding the name, to fix building on
these systems.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-08 15:47:09 +08:00
Eddie Hung e9bb252e77 Recognise built-in types (e.g. $_DFF_*) 2019-08-30 20:15:09 -07:00
Eddie Hung 3247442bf9 Revert "Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)"" 
This reverts commit 8f0c1232d7.
 2019-08-28 17:34:00 -07:00
Eddie Hung 082a01954b Revert "Output "h" extension only if boxes" 
This reverts commit 399ac760ff.
 2019-08-28 17:30:54 -07:00
Eddie Hung 399ac760ff Output "h" extension only if boxes 2019-08-21 11:31:18 -07:00
Eddie Hung 8f0c1232d7 Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)" 
This reverts commit 8182cb9d91.
 2019-08-21 11:29:40 -07:00
Eddie Hung 8182cb9d91 Fix omode which inserts an output if none exists (otherwise abc9 breaks) 2019-08-20 21:30:16 -07:00
Eddie Hung 4d123b7638 Revert "Only xaig if GetSize(output_bits) > 0" 
This reverts commit 7b646101e9.
 2019-08-20 21:22:38 -07:00
Eddie Hung 7b646101e9 Only xaig if GetSize(output_bits) > 0 2019-08-20 20:57:13 -07:00
Eddie Hung f1a206ba03 Revert "Remove sequential extension" 
This reverts commit 091bf4a18b.
 2019-08-20 18:17:14 -07:00
Eddie Hung 091bf4a18b Remove sequential extension 2019-08-20 18:16:37 -07:00
Eddie Hung 1b5d2de1d4 Do not sigmap! 2019-08-20 15:23:26 -07:00
Eddie Hung c00d72cdb3 Minor refactor 2019-08-20 14:47:58 -07:00
Eddie Hung 45d4b33f0c Output i/o/h extensions even if no boxes or flops 2019-08-19 13:17:31 -07:00
Eddie Hung 91687d3fea Add (* abc_arrival *) attribute 2019-08-19 12:33:24 -07:00
Eddie Hung 2f4e0a5388 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 10:07:27 -07:00