Commit Graph

1188 Commits

Author SHA1 Message Date
whitequark baf1875307
Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
2021-02-04 09:57:28 +00:00
Zachary Snow fe74b0cd95 verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.

Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.

1. Unlabled generate blocks are now implicitly named according to the LRM in
   `label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
   synthetic unnamed generate block to avoid creating extra hierarchy levels
   where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
   of the topmost scope, which is necessary because such wires and cells often
   appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
   invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
   scope, completely deferring the inspection and elaboration of nested scopes;
   names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
   to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
   in largely the same manner as other blocks
     before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
      after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
   than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
   prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
   or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode

Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
whitequark 708eb327a1
Merge pull request #2564 from whitequark/flatten-improve-error
flatten: clarify confusing error message
2021-01-29 02:55:51 +00:00
Claire Xen d0d7a360ed
Merge pull request #2535 from Ravenslofty/scc-specify
scc: Add -specify option to find loops in boxes
2021-01-28 19:01:29 +01:00
whitequark 2364820f50 flatten: clarify confusing error message. 2021-01-26 18:29:53 +00:00
Dan Ravensloft 74dad5afe7 scc: Add -specify option to find loops in boxes 2021-01-26 16:23:08 +00:00
whitequark f200a8fe1c
Merge pull request #2549 from pgadfort/support-multiple-libs
adding support for passing multiple liberty files to abc
2021-01-25 10:36:14 +00:00
Peter Gadfort 169234d6e9 adding support for passing multiple liberty files to abc 2021-01-18 16:47:49 -05:00
Tobias Faller 760a2c1343 Fixed missing goto statement in passes/techmap/abc.cc 2021-01-12 16:17:51 +01:00
Zachary Snow 0d8e5d965f Sign extend port connections where necessary
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
2020-12-18 20:33:14 -07:00
Miodrag Milanovic 829b5cca60 Expose abc and data paths as globals 2020-11-06 14:17:15 +01:00
Ethan Mahintorabi 5c36e7757c This patch adds support for defining the ABC location at runtime instead of at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase.
This change should be backwards compatible with the existing behavior.
2020-10-28 19:00:06 -07:00
whitequark 2d10d59d93
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap
flatten, techmap: don't canonicalize tpl driven bits via sigmap
2020-08-27 11:28:31 +00:00
whitequark 702f7c0253
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil
Replace "ILANG" with "RTLIL" everywhere
2020-08-27 11:24:06 +00:00
Marcelina Kościelnicka 880df4c897 dfflegalize: Fix decision tree for adffe.
When an adffe is being legalized, and is not natively supported,
prioritize unmapping to adff over converting to dffsre if dffsre is not
natively supported itself.

Fixes #2361.
2020-08-27 13:17:42 +02:00
whitequark 00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
whitequark 9f0892159e flatten, techmap: don't canonicalize tpl driven bits via sigmap.
For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:

    module foo(inout a, b);
      assign a = b;
    endmodule
    module bar(output c);
      foo f(c, 1'b0);
    endmodule

Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).

This issue was introduced in 9f772eb9.

Fixes #2183.
2020-08-26 16:29:42 +00:00
clairexen 6a68b8ed54
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup
Remove passes redundant with opt_dff
2020-08-20 16:21:58 +02:00
clairexen faf8e19511
Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix
techmap.CONSTMAP: Handle outputs before inputs.
2020-08-20 16:21:09 +02:00
clairexen 1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern
techmap: Add support for [] wildcards in techmap_celltype.
2020-08-20 16:18:40 +02:00
Marcelina Kościelnicka 54a0c083a1 Remove now-redundant dff2dffe pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 5693386a4e Remove now-redundant dff2dffs pass. 2020-08-07 13:21:34 +02:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka b4a4cb081d techmap.CONSTMAP: Handle outputs before inputs.
Fixes #2321.
2020-08-05 12:28:18 +02:00
Marcelina Kościelnicka 522788f016 techmap: Add support for [] wildcards in techmap_celltype.
Fixes #1826.
2020-08-02 22:46:48 +02:00
Marcelina Kościelnicka 18ad56ef41 Add dffunmap pass.
To be used with backends that cannot deal with fancy FF types (like blif
or smt).
2020-07-31 00:59:51 +02:00
Marcelina Kościelnicka 7b1a4fc1e6 techmap: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 9e72be3ae8 shregmap: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 522f367db3 abc: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 336b8c7786 dffinit: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka 1c8483b7dd zinit: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka e98382f6e2 dfflegalize: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
Marcelina Kościelnicka dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter.
This parameter will resolve to the name of the cell being mapped.  The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
2020-07-21 15:00:54 +02:00
Marcelina Kościelnicka 240351c44e dfflegalize: Gather init values from all wires.
Skipping non-selected wires is unsound in an obvious way.
2020-07-12 17:39:13 +02:00
Marcelina Kościelnicka 7ed9d18907 dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
Marcelina Kościelnicka 32d2cc8c28 clkbufmap: improve input pad handling.
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
  buffer
2020-07-09 18:48:01 +02:00
Marcelina Kościelnicka e9c2c1b717 dfflegalize: Add special support for const-D latches.
Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q.  Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
2020-07-09 18:11:32 +02:00
Marcelina Kościelnicka 943147b768 dfflegalize: typo fix 2020-07-07 15:00:52 +02:00
Marcelina Kościelnicka af54b8bc61 Naming fixes. 2020-07-05 22:21:59 +02:00
Marcelina Kościelnicka f3f55ae7c2 dfflegalize: Prefer mapping dff to sdff before adff
This ensures that, when both sync and async FFs are available and abc9
is involved, the sync FFs will be used, and will thus remain available
for sequential synthesis.
2020-07-05 12:01:43 +02:00
Eddie Hung 27a9d1b6e6 abc9: only techmap (* abc9_flop *) modules 2020-07-04 19:45:10 +02:00
Eddie Hung 0ba79feb6f abc9: techmap from user design to allow abc9_flop modules to be composed
from other primitives
2020-07-04 19:45:10 +02:00
Rupert Swarbrick a9b61080a4 Add newlines to help text for dfflegalize
I think these were probably missed by accident. Spotted because GCC
spits out lots of messages like this:

passes/techmap/dfflegalize.cc:114:7: warning: zero-length gnu_printf format string [-Wformat-zero-length]
  114 |   log("");
      |       ^~

(because we tell GCC that the first argument to log() looks like a
printf control string in log.h, and a zero length such string triggers
a warning).
2020-07-03 12:30:12 +02:00
Marcelina Kościelnicka e3564b4502 Add dfflegalize pass. 2020-07-01 01:57:15 +02:00
whitequark a97c13f0ca techmap: don't drop attributes on replaced cells.
This was introduced in 76c4ee4ea5.

Fixes #2204.
2020-06-29 23:14:13 +00:00
clairexen c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
Marcelina Kościelnicka 8f12c5b063 simplemap: Fix $dffsre mapping. 2020-06-23 23:16:43 +02:00
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Marcelina Kościelnicka 832acc8648 Add new FF types to simplemap. 2020-06-23 15:40:02 +02:00
whitequark 118e4caa37 Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00