Eddie Hung
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13ecd8b0df
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Add run-test.sh too
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2019-08-28 18:47:48 -07:00 |
Eddie Hung
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a4f641f230
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Do not overwrite LUT param
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2019-08-28 18:46:53 -07:00 |
Eddie Hung
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e301a3dadb
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Add SB_CARRY to ice40_opt test
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2019-08-28 18:46:53 -07:00 |
Eddie Hung
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dd42aa87b9
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Add ice40_opt test
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2019-08-28 18:46:53 -07:00 |
Eddie Hung
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d46d38e4d5
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Trailing comma
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2019-08-28 17:25:54 -07:00 |
Eddie Hung
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f5b4bc847c
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Adapt to $__ICE40_CARRY_WRAPPER
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2019-08-28 17:25:05 -07:00 |
Eddie Hung
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e569f13870
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Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"
This reverts commit 2aedee1f0e .
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2019-08-28 17:22:44 -07:00 |
Eddie Hung
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2aedee1f0e
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Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with
CARRY_WRAPPER in the same way since I0 and I3 could be used
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2019-08-28 17:07:36 -07:00 |
Eddie Hung
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077e9d4ada
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Update box size and timings
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2019-08-28 17:07:24 -07:00 |
Eddie Hung
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129df7184a
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Update to new $__ICE40_CARRY_WRAPPER
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2019-08-28 17:07:07 -07:00 |
Eddie Hung
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fc727fa5c9
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Merge pull request #1334 from YosysHQ/clifford/async2synclatch
Add $dlatch support to async2sync
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2019-08-28 12:36:06 -07:00 |
Eddie Hung
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9314a0a42e
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Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
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2019-08-28 10:51:39 -07:00 |
David Shah
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13424352cc
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Merge pull request #1332 from YosysHQ/dave/ecp5gsr
ecp5: Add GSR and SGSR support
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2019-08-28 12:44:02 +01:00 |
Clifford Wolf
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c84fef92df
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Merge pull request #1335 from YosysHQ/clifford/paramap
Add "paramap" pass
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2019-08-28 10:35:47 +02:00 |
Clifford Wolf
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47ffbf554e
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Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-28 10:06:42 +02:00 |
Clifford Wolf
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0fda0e821c
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Add "paramap" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-28 10:03:27 +02:00 |
Clifford Wolf
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c499dc3e73
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Add $dlatch support to async2sync
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-28 09:45:22 +02:00 |
Clifford Wolf
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70c0cddb1e
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Merge pull request #1325 from YosysHQ/eddie/sat_init
In sat: 'x' in init attr should be ignored
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2019-08-28 00:18:14 +02:00 |
Marcin Kościelnicki
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d361f5ab79
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xilinx: Add SRLC16E primitive.
Fixes #1331.
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2019-08-27 20:27:12 +02:00 |
Eddie Hung
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eab3c1432b
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Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap
Add clock buffer insertion pass, improve iopadmap.
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2019-08-27 10:19:27 -07:00 |
Eddie Hung
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28133432be
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Ignore all 1'bx in (* init *)
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2019-08-27 09:24:59 -07:00 |
Eddie Hung
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00387f3927
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Revert to using clean
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2019-08-27 09:24:32 -07:00 |
Marcin Kościelnicki
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5fb4b12cb5
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improve clkbuf_inhibit propagation upwards through hierarchy
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2019-08-27 17:26:47 +02:00 |
David Shah
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fc001b4731
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ecp5: Add GSR support
Signed-off-by: David Shah <dave@ds0.me>
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2019-08-27 13:07:06 +01:00 |
Clifford Wolf
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fdbcf78909
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Add "make bumpversion"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-27 10:15:25 +02:00 |
Eddie Hung
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528f1c8687
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Improve tests to check that clkbuf is connected to expected
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2019-08-26 13:45:16 -07:00 |
Eddie Hung
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a098205479
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Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-26 13:25:17 -07:00 |
Eddie Hung
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bd3773a17f
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Remove dupe in CHANGELOG, missing end quote
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2019-08-26 10:44:23 -07:00 |
Clifford Wolf
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8a4c6e6563
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Merge tag 'yosys-0.9'
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2019-08-26 11:14:22 +02:00 |
Clifford Wolf
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1979e0b1f2
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Yosys 0.9
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-08-26 10:37:53 +02:00 |
Clifford Wolf
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a3de83ef4a
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Merge pull request #1112 from acw1251/pyosys_sigsig_issue
Fixed pyosys commands returning RTLIL::SigSig
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2019-08-25 11:22:02 +02:00 |
Eddie Hung
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dc87372a97
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Wire with init on FF part, 1'bx on non-FF part
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2019-08-24 15:05:44 -07:00 |
Clifford Wolf
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dc9c47b5af
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Merge pull request #1327 from YosysHQ/clifford/pmgen
Add pmgen slices and choices
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2019-08-24 08:38:49 +02:00 |
Eddie Hung
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d7051b90de
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Add undocumented feature
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2019-08-23 16:41:32 -07:00 |
Eddie Hung
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967a36c125
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indo -> into
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2019-08-23 13:16:50 -07:00 |
Eddie Hung
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4a4e28b55e
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Revert earliest to gcc-4.8, compile iverilog with default compiler
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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b3dc28cf65
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Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!"
This reverts commit c82b2fa31f .
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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fcb102d60e
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Remove .0 from clang-8.0
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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fdc438e551
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Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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bf40f2f895
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bionic -> xenial as its on whitelist
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2019-08-23 12:29:57 -07:00 |
Eddie Hung
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43927e5910
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Bump gcc from 4.8 to 4.9 as undefined reference
... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
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2019-08-23 12:29:50 -07:00 |
Eddie Hung
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20f4d191b5
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Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-23 11:24:19 -07:00 |
Eddie Hung
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509c353fe9
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Forgot one
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2019-08-23 11:23:50 -07:00 |
Eddie Hung
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0d0ad15898
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Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-23 11:23:31 -07:00 |
Eddie Hung
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a270af00cc
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Put abc_* attributes above port
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2019-08-23 11:21:44 -07:00 |
Eddie Hung
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a0d85393e3
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Check clkbuf_inhibit=1 is ignored for custom selection
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2019-08-23 11:15:26 -07:00 |
Eddie Hung
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619f2414e5
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clkbufmap to only check clkbuf_inhibit if no selection given
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2019-08-23 11:14:42 -07:00 |
Eddie Hung
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5628e2ec53
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Add simple clkbufmap tests
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2019-08-23 11:10:02 -07:00 |
Eddie Hung
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d62c10d641
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tests/techmap/run-test.sh to cope with *.ys
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2019-08-23 11:09:50 -07:00 |
Eddie Hung
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4c0404ae02
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Mention clkbuf_inhibit can be overridden
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2019-08-23 10:24:59 -07:00 |