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14052 Commits

Author SHA1 Message Date
Catherine 5dadcc85b7
Merge pull request #3111 from whitequark/issue-3110 
Fix null pointer dereference after failing to extract DFF from memory
 2021-12-14 21:25:06 +00:00
Claire Xenia Wolf e1c7a9a647 Hotfix for run_shell auto-detection 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-14 21:38:58 +01:00
Catherine 48ed6d998b Fix null pointer dereference after failing to extract DFF from memory. 
Fixes #3110.
 2021-12-14 16:27:37 +00:00
github-actions[bot] b07ca8756a Bump version 2021-12-14 00:59:10 +00:00
Claire Xen 5e5c8a54ce
Merge pull request #3108 from YosysHQ/claire/verificdefs 
Add YOSYS to the implicitly defined verilog macros in verific
 2021-12-13 22:03:29 +01:00
Claire Xenia Wolf 313340aed5 Add YOSYS to the implicitly defined verilog macros in verific 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-13 18:20:08 +01:00
github-actions[bot] 19a38222e7 Bump version 2021-12-13 00:55:45 +00:00
Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
 2021-12-12 19:56:50 +01:00
Catherine bdc6ba019c
Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2 
cxxrtl: preserve interior memory pointers across reset
 2021-12-12 01:23:03 +00:00
github-actions[bot] 6a7253b46e Bump version 2021-12-12 01:12:53 +00:00
Marcelina Kościelnicka 26f0f6bb0b Fix unused param warning with ENABLE_NDEBUG. 2021-12-12 01:22:28 +01:00
Marcelina Kościelnicka d019b4e681 rtlil: Dump empty connections when whole module is selected. 
Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires.  This makes debugging rather confusing.
 2021-12-12 01:22:06 +01:00
Catherine 55c9fb3b18 cxxrtl: preserve interior memory pointers across reset. 
Before this commit, values, wires, and memories with an initializer
were value-initialized in emitted C++ code. After this commit, all
values, wires, and memories are default-initialized, and the default
constructor of generated modules calls the reset() method, which
assigns the members that have an initializer.
 2021-12-11 16:40:06 +00:00
Catherine 21fbdb6638
Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values 
write_verilog: dump zero width sigspecs correctly
 2021-12-11 16:24:47 +00:00
whitequark 7c9e498662 cxxrtl: use unique_ptr<value<>[]> to store memory contents. 
This makes the depth properly immutable.
 2021-12-11 14:52:37 +00:00
whitequark 86f2804dc3 write_verilog: dump zero width sigspecs correctly. 
Before this commit, zero width sigspecs were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

PR #1203 has addressed this issue before, but in an incomplete way.
 2021-12-11 12:01:52 +00:00
github-actions[bot] 8e91857fab Bump version 2021-12-11 00:54:59 +00:00
Miodrag Milanović 2412497c26
Merge pull request #3102 from YosysHQ/claire/enumxz 
Fix verific import of enum values with x and/or z
 2021-12-10 19:36:37 +01:00
Claire Xenia Wolf 2da214d721 Fix verific import of enum values with x and/or z 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 14:52:27 +01:00
Miodrag Milanović f8978f9e0a
Merge pull request #3097 from YosysHQ/modport 
If direction NONE use that from first bit
 2021-12-10 14:32:14 +01:00
Claire Xen 19773d093f
Update verific.cc 
Ad-hoc fixes/improvements
 2021-12-10 14:27:18 +01:00
Claire Xen ce82afe44f
Merge pull request #3099 from YosysHQ/claire/readargs 
Use "read" command to parse HDL files from Yosys command-line
 2021-12-10 11:23:53 +01:00
Claire Xenia Wolf d6e4d3f1ba Fix the tests we just broke 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:22:37 +01:00
Claire Xenia Wolf ce08046f44 Added "yosys -r <topmodule>" 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:15:37 +01:00
Claire Xenia Wolf 0cbdb42dcd Use "read" command to parse HDL files from Yosys command-line 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-09 10:33:55 +01:00
github-actions[bot] cdb5711875 Bump version 2021-12-09 00:55:26 +00:00
Marcelina Kościelnicka 1184a7f3b4 opt_mem_priority: Fix non-ascii char in help message. 
This is a fixed version of #3072.
 2021-12-09 00:56:14 +01:00
Miodrag Milanovic b06f547993 If direction NONE use that from first bit 2021-12-08 11:50:10 +01:00
github-actions[bot] d186ea7a2d Bump version 2021-12-04 00:54:12 +00:00
Miodrag Milanovic c23cd00f30 Next dev cycle 2021-12-03 12:51:34 +01:00
Miodrag Milanovic 2156e20db5 Release version 0.12 2021-12-03 12:48:49 +01:00
Miodrag Milanovic 71e762d68c Update manual 2021-12-03 09:57:14 +01:00
Miodrag Milanovic d65942b9ac Add gitignore for gatemate 2021-12-03 09:56:37 +01:00
Miodrag Milanovic 3ebfa3fb84 Make sure cell names are unique for wide operators 2021-12-03 09:49:05 +01:00
github-actions[bot] 2be110cb0b Bump version 2021-12-02 00:54:50 +00:00
Miodrag Milanovic 4792d925fc Update CHANGELOG and CODEOWNERS 2021-12-01 08:42:37 +01:00
github-actions[bot] 707d98b06c Bump version 2021-11-26 00:52:41 +00:00
gatecat b506f398dd Add read_liberty -wb 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-11-25 19:13:08 +00:00
Lofty a31c8a82be intel_alm: preliminary Arria V support 2021-11-25 17:20:36 +01:00
Lofty 77327b2544 sta: very crude static timing analysis pass 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2021-11-25 17:20:27 +01:00
github-actions[bot] 113c943841 Bump version 2021-11-18 00:54:02 +00:00
Miodrag Milanović d0fda4c0ef
Merge pull request #3080 from YosysHQ/micko/init_wire 
Give initial wire unique ID, fixes #2914
 2021-11-17 13:57:56 +01:00
Miodrag Milanovic c081c683a4 Give initial wire unique ID, fixes #2914 2021-11-17 12:19:06 +01:00
github-actions[bot] 07dde32bf1 Bump version 2021-11-17 00:53:07 +00:00
Kamil Rakoczy fdb19a5b3a
Support parameters using struct as a wiretype (#3050) 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-11-16 10:59:54 +01:00
github-actions[bot] 06bddb5e49 Bump version 2021-11-14 00:54:56 +00:00
Patrick Urban cb41209095 synth_gatemate Revert cascade A/B port mixup 2021-11-13 21:53:25 +01:00
Patrick Urban decdc743db synth_gatemate: Remove iob_map invokation 2021-11-13 21:53:25 +01:00
Patrick Urban 0d871b6c49 synth_gatemate: Add block RAM cascade support 
* add simulation model for block RAM cascade in 40K mode
* limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
 2021-11-13 21:53:25 +01:00
Patrick Urban 285ec0547b synth_gatemate: Remove obsolete iob_map 2021-11-13 21:53:25 +01:00