c016f6a423
proc_rmdead: use explicit pattern set when there are no wildcards
...
If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
2021-07-29 20:55:59 -04:00
54e75129e5
opt_lut: Allow more than one -dlogic per cell type.
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Fixes #2061 .
2021-07-29 17:30:07 +02:00
19720b970d
memory: Introduce $meminit_v2 cell, with EN input.
2021-07-28 23:18:38 +02:00
a0e912ba99
proc: Run opt_expr at the end
2021-07-27 20:44:45 +02:00
436d42c00c
opt_expr: Propagate constants to port connections.
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This adds one simple piece of functionality to opt_expr: when a cell
port is connected to a fully-constant signal (as determined by sigmap),
the port is reconnected directly to the constant value. This is just
enough optimization to fix the "non-constant $meminit input" problem
without requiring a full opt_clean or a separate pass.
2021-07-27 20:44:26 +02:00
7a25246a7e
Use new read_id_num helper function elsewhere in hierarchy.cc
2021-07-20 10:13:15 -04:00
8fd6b45a3c
Extract connection checking logic from expand_module in hierarchy.cc
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No functional change, but pulls more logic out of the expand_module
function.
2021-07-20 10:13:15 -04:00
7d50b83322
Extract missing module support in hierarchy.cc to a helper function
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I think the code is now a bit easier to follow (and has lost some
levels of indentation!).
The only non-trivial change is that I removed the check for
cell->type[0] != '$' when deciding whether to complain if we couldn't
find a module. This will always be true because of the early exit
earlier in the function.
2021-07-14 22:54:50 -04:00
88f20fa4dd
Delete unused found_init variable
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Spotted during compilation:
passes/proc/proc_init.cc: In function ‘void {anonymous}::proc_init(Yosys::RTLIL::Module*, Yosys::SigMap&, Yosys::RTLIL::Process*)’:
passes/proc/proc_init.cc:31:7: warning: variable ‘found_init’ set but not used [-Wunused-but-set-variable]
2021-07-14 10:19:07 +01:00
009940f56c
rtlil: Make Process handling more uniform with Cell and Wire.
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- add a backlink to module from Process
- make constructor and destructor protected, expose Module functions
to add and remove processes
2021-07-12 00:47:34 +02:00
e2c9580024
Move interface expansion in hierarchy.cc into a helper class
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There should be no functional change, but this splits up the control
flow across functions, using class fields to hold the state that's
being tracked. The result should be a bit easier to read.
This is part of work to add bind support, but I'm doing some
refactoring in the hierarchy pass to make the code a bit easier to
work with. The idea is that (eventually) the IFExpander object will
hold all the logic for expanding interfaces, and then other code can
do bind insertion.
2021-06-16 21:48:18 -04:00
6a6d049f1c
opt_muxtree: Update port_off and port_idx even for constant bits
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-11 12:06:35 +01:00
1667ad658b
opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.
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The previous code, in addition to being needlessly limitted to 32 bits
in the first place, also had UB for the 31th bit (doing 1 << 31).
2021-06-09 19:53:44 +02:00
12b3a9765d
opt_expr: Optimize div/mod by const 1.
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Turns out the code for div by a power of 2 is already almost capable of
optimizing this to a shift-by-0 or and-with-0, which will be further
folded into nothingness; let's beef it up to handle div by 1 as well.
Fixes #2820 .
2021-06-09 17:42:30 +02:00
55e8f5061a
Merge pull request #2817 from YosysHQ/claire/fixemails
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Fixing old e-mail addresses and deadnames
2021-06-09 13:22:52 +02:00
588137cd08
Fix deadname SVN links
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-06-09 12:44:37 +02:00
0ada13cbe2
Use HTTPS for website links, gatecat email
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git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g ;
2021-06-09 12:16:56 +02:00
d9f11bb7a6
autoname: simple perf optimizations
2021-06-08 15:02:42 -04:00
72787f52fc
Fixing old e-mail addresses and deadnames
...
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
13b901bf1c
memory_map: Improve start_offset handling.
...
Fixes #2775 .
2021-05-31 17:45:21 +02:00
82f5829aba
memory_share: Add read port merging.
...
This is mostly meant for wide port recognition, but may also happen to
merge some ports with compatible initial/reset values (eg. 0 vs x).
2021-05-29 16:05:58 +02:00
2d10caabbc
memory_share: Improve sat-based port sharing.
2021-05-28 14:25:33 +02:00
cbf6b719fe
Make a few passes auto-call Mem::narrow instead of rejecting wide ports.
...
This essentially adds wide port support for free in passes that don't
have a usefully better way of handling wide ports than just breaking
them up to narrow ports, avoiding "please run memory_narrow" annoyance.
2021-05-28 00:40:56 +02:00
1eae6025e7
memory_share: Improve same-address merging, recognize wide write ports.
2021-05-27 15:53:12 +02:00
83a218141c
kernel/mem: Add sub_addr helpers.
2021-05-26 03:34:02 +02:00
d99fce3bc7
mem/extract_rdff: Fix "no FF made" edge case.
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When converting a sync transparent read port with const address to async
read port, nothing at all needs to be done other than clk_enable change,
and thus we have no FF cell to return. Handle this case correctly in
the helper and in its users.
2021-05-25 23:42:31 +02:00
18806f1ef6
memory_bram: Reuse extract_rdff helper for make_outreg.
...
Also properly skip read ports with init value or reset when not making
use of make_outreg. Proper support for matching those will land later.
2021-05-25 22:42:03 +02:00
e6b078d156
opt_mem: Add reset/init value support.
2021-05-25 20:06:00 +02:00
96c7d60304
memory_bram: Respect write port priority.
2021-05-25 16:28:33 +02:00
5628f5a88f
opt_mem_feedback: Respect write port priority.
2021-05-25 15:59:41 +02:00
e0736c1622
Add memory_narrow pass.
2021-05-25 03:04:13 +02:00
47f958ce45
memory_share: Add wide port support.
2021-05-25 02:57:32 +02:00
9d5d5a48b1
opt_mem_feedback: Add wide port support.
2021-05-25 02:57:32 +02:00
c1a4730739
memory_map: Add wide port support.
2021-05-25 02:57:32 +02:00
1c903d3e47
sim: Add wide port support.
2021-05-25 02:57:32 +02:00
69bf5c81c7
Reject wide ports in some passes that will never support them.
2021-05-25 02:07:25 +02:00
835688bf80
opt_mem_feedback: Rewrite feedback path finding logic.
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Fixes #2766 .
2021-05-24 23:20:30 +02:00
b706adb809
opt_mem_feedback: Convert to Mem helpers.
2021-05-24 23:20:30 +02:00
df2b79ca76
memory_share: Use Mem helpers.
2021-05-23 23:16:12 +02:00
afd5366fc2
extract_rdff: Add initvals parameter.
...
This is not used yet, but will be needed when read port reset/initial
value support lands.
2021-05-23 22:05:26 +02:00
d905990d01
memory_share: Split off feedback path finding as a separate pass.
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memory_share is actually three passes in a trenchcoat. Split off the
one that has the least in common with the other two as a separate pass.
2021-05-23 18:30:39 +02:00
1eea06bcc0
Add new helper class for merging FFs into cells, use for memory_dff.
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Fixes #1854 .
2021-05-23 14:46:59 +02:00
a23d9409e7
opt_mem: Remove write ports with const-0 EN.
...
Fixes #2765 .
2021-05-23 14:30:56 +02:00
039f4f48d5
memory_memx: Use Mem helper.
2021-05-22 22:31:07 +02:00
c4cc888b2c
kernel/rtlil: Extract some helpers for checking memory cell types.
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There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00
8c734e07b8
memory_dff: Use Mem helper.
2021-05-21 02:26:27 +02:00
a6081b46ce
connect: Add -assert option, fix non-working sigmap.
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Should be useful for writing tests.
2021-05-08 15:49:41 +02:00
5c1e6a0e20
opt_dff: Fix NOT gates wired in reverse.
2021-05-04 21:03:40 +02:00
c5c57e3f5e
flatten: rewrite memid in memwr actions.
2021-04-09 09:46:53 +00:00
b7ea71e6e3
equiv: Suggest running async2sync or clk2fflogic where appropriate.
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See #2713 .
2021-03-30 18:20:21 +02:00
Zachary Snow
Marcelina Kościelnicka
Rupert Swarbrick
gatecat
Claire Xen
whitequark