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Author SHA1 Message Date
Eddie Hung 37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
Eddie Hung c22fb76664 ast: cap dynamic range select to size of signal, suppresses warnings 2020-04-01 09:59:23 -07:00
Claire Wolf 926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice 
ast: simplify to fully populate dynamic slicing case transformation
 2020-04-01 08:38:14 +02:00
Eddie Hung 5132f4099b ast: simplify to fully populate dynamic slicing case transformation 2020-03-31 11:52:14 -07:00
Eddie Hung 05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup 
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
 2020-03-30 13:06:10 -07:00
Alberto Gonzalez b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-03-30 18:14:32 +00:00
Claire Wolf 1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit 
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
 2020-03-27 17:28:26 +01:00
Alberto Gonzalez 6040593994
Revert over-aggressive change to a more modest cleanup. 2020-03-27 09:46:40 +00:00
Peter Crozier 6cad865d12 Simplify was not being called for packages. Broke typedef enums. 2020-03-22 18:20:46 -07:00
Eddie Hung 43092f063f Fix NDEBUG warnings 2020-03-19 08:48:39 -07:00
Alberto Gonzalez eb30d66d01
Clean up pseudo-private member usage in `frontends/ast/ast.cc`. 2020-03-19 07:29:00 +00:00
huaixv cd82ccd258 Add precise locations for asserts 2020-03-19 10:22:07 +08:00
Eddie Hung 4555b5b819 kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
Claire Wolf b597f85b13
Merge pull request #1718 from boqwxp/precise_locations 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
 2020-03-03 08:38:32 -08:00
Claire Wolf 91892465e1
Merge pull request #1681 from YosysHQ/eddie/fix1663 
verilog: instead of modifying localparam size, extend init constant expr
 2020-03-03 08:34:31 -08:00
Eddie Hung 4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify 
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
 2020-03-02 12:32:27 -08:00
Eddie Hung 5bba9c3640 ast: fixes #1710; do not generate RTLIL for unreachable ternary 2020-02-27 16:55:55 -08:00
Eddie Hung 825b96fdcf Comment out log() 2020-02-27 16:53:49 -08:00
Eddie Hung e79376d6cb ast: quiet down when deriving blackbox modules 2020-02-27 10:17:29 -08:00
Alberto Gonzalez f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Eddie Hung 760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve 
Improve specify parser
 2020-02-21 09:15:17 -08:00
Claire Wolf cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum 
Enum support
 2020-02-20 18:17:25 +01:00
Jeff Wang a31ba8e5d5 remove unnecessary blank line 2020-02-17 04:42:49 -05:00
Jeff Wang d12ba42a74 add attributes for enumerated values in ilang 
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
 2020-02-17 04:42:42 -05:00
Jeff Wang 6320f2692b separate out enum_item/param implementation when they should be different 2020-02-17 04:42:30 -05:00
Eddie Hung 7cfdf4ffa7 verilog: fix $specify3 check 2020-02-13 12:42:04 -08:00
whitequark c34d7b13f4 ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. 
Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
  reg [`WIDTH:0] mem [0:`DEPTH];
  integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.

After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.

As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
 2020-02-07 00:41:54 +00:00
Rodrigo Alejandro Melo da485dc007 Modified $readmem[hb] to use '\' or '/' according the OS 
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-06 10:10:29 -03:00
Eddie Hung fc33287bc1 verilog: instead of modifying localparam size, extend init constant expr 2020-02-05 17:19:42 -08:00
Rodrigo Alejandro Melo 313a425bd5 Merge branch 'master' of https://github.com/YosysHQ/yosys 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:56:41 -03:00
Rodrigo Alejandro Melo 71f3afb9a2 Replaced strlen by GetSize into simplify.cc 
As recommended in CodingReadme.

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:44:09 -03:00
Rodrigo Alejandro Melo b4c30cfc8d Fixed a bug in the new feature of $readmem[hb] when an empty string is provided 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 17:03:56 -03:00
Rodrigo Alejandro Melo d74b9604e3 Modified the new search for files of $readmem[hb] to be backward compatible 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-01-31 22:10:51 -03:00
Rodrigo Alejandro Melo 7b3fe404ab $readmem[hb] file inclusion is now relative to the Verilog file 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-01-31 18:20:22 -03:00
David Shah 22c967e35e ast: Add support for $sformatf system function 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-19 21:20:17 +00:00
Jeff Wang 98c6bd7630 fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6 
The if(str == node->str) is in fact necessary (otherwise causes generate
for in Multiplier_2D in tests/simple/multiplier.v to fail with error
message "Right hand side of 3rd expression of generate for-loop is not
constant!"). Note: in PeterCrozier's implementation, the break only
breaks out of the switch-case, not the outer for loop.
 2020-01-17 02:07:42 -05:00
Jeff Wang 549deb6373 fix enum in generate blocks 2020-01-16 18:13:30 -05:00
Jeff Wang 41a0a93dcc allow enums to be declared at toplevel scope 2020-01-16 18:13:14 -05:00
Jeff Wang 16ea4ea61a partial rebase of PeterCrozier's enum work onto current master 
I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.

Original commit:
"Initial implementation of enum, typedef, import.  Still a WIP."
881833aa73
 2020-01-16 13:51:47 -05:00
Eddie Hung 1ac1697e15 Stray log_dump 2019-12-11 16:59:00 -08:00
Eddie Hung af36943cb9 Preserve size of $genval$-s in for loops 2019-12-11 16:52:37 -08:00
Clifford Wolf e84cedfae4 Use "(id)" instead of "id" for types as temporary hack 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-14 05:24:31 +02:00
David Shah e46e8753c8 frontends/ast: code style 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:55:43 +01:00
David Shah 5501d9090a sv: Fix typedefs in blocks 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:45 +01:00
David Shah af25585170 sv: Add support for memories of a typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah 30d2326030 sv: Add support for memory typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah e70e4afb60 sv: Fix typedefs in packages 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah c962951612 sv: Fix typedef parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah f6b5e47e40 sv: Switch parser to glr, prep for typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
Eddie Hung 0a1af434e8 Fix for svinterfaces 2019-09-30 14:52:04 -07:00
Eddie Hung 08b55a20e3 module->derive() to be lazy and not touch ast if already derived 2019-09-30 14:11:01 -07:00
Clifford Wolf 8da0888bf6 Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-20 12:16:20 +02:00
Clifford Wolf 25b08b1afd Fix handling of range selects on loop variables, fixes #1372 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-16 11:25:37 +02:00
Clifford Wolf 4b7202c9c2
Merge pull request #1350 from YosysHQ/clifford/fixsby59 
Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
 2019-09-05 18:14:28 +02:00
Clifford Wolf 25e5fbac90 Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)" 
Fixes https://github.com/YosysHQ/SymbiYosys/issues/59

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-02 22:56:38 +02:00
Eddie Hung 83ffec26cb Remove newline 2019-08-29 09:08:58 -07:00
Eddie Hung 6510297712 Restore non-deferred code, deferred case to ignore non constant attr 2019-08-29 09:02:10 -07:00
Eddie Hung 34ae29295d read_verilog -defer should still populate module attributes 2019-08-28 19:59:09 -07:00
Eddie Hung fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
Jakob Wenzel 24971fda87 handle real values when deriving ast modules 2019-08-19 14:17:36 +02:00
Eddie Hung 12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
David Shah f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Eddie Hung 9776084eda Allow whitebox modules to be overwritten 2019-08-07 16:40:24 -07:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Eddie Hung ee7c970367 IdString::str().substr() -> IdString::substr() 2019-08-06 19:08:33 -07:00
Clifford Wolf f1f5b4e375 Fix handling of functions/tasks without top-level begin-end block, fixes #1231 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 18:06:14 +02:00
Jakob Wenzel e2fe8e0a4f initialize noblackbox and nowb in AstModule::clone 2019-07-22 10:37:40 +02:00
whitequark b1f400aeb8 genrtlil: emit \src attribute on CaseRule. 2019-07-08 12:29:08 +00:00
Clifford Wolf ec4565009a Add "read_verilog -pwires" feature, closes #1106 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 14:38:50 +02:00
Clifford Wolf 211d85cfcc Fixes and cleanups in AST_TECALL handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 12:41:09 +02:00
Clifford Wolf a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Stefan Biereigel 816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Stefan Biereigel cd12f2ddcf remove leftovers from ast data structures 2019-05-27 18:01:44 +02:00
Stefan Biereigel ed625a3102 move wand/wor resolution into hierarchy pass 2019-05-27 18:00:22 +02:00
Clifford Wolf 92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range 
Give error instead of asserting for invalid range, fixes #947
 2019-05-27 13:26:12 +02:00
Miodrag Milanovic 84ffb21708 Give error instead of asserting for invalid range, fixes #947 2019-05-27 12:25:18 +02:00
Miodrag Milanovic 34417ce55f Added support for unsized constants, fixes #1022 
Includes work from @sumit0190 and @AaronKel
 2019-05-27 11:42:10 +02:00
Stefan Biereigel 85de9d26c1 fix assignment of non-wires 2019-05-23 17:55:56 +02:00
Stefan Biereigel fd003e0e97 fix indentation across files 2019-05-23 13:57:27 +02:00
Stefan Biereigel 075a48d3fa implementation for assignments working 2019-05-23 13:57:27 +02:00
Stefan Biereigel 9df04d7e75 make lexer/parser aware of wand/wor net types 2019-05-23 13:57:27 +02:00
Clifford Wolf 752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify 
Add specify parser
 2019-05-06 20:57:15 +02:00
Clifford Wolf d187be39d6 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 2019-05-06 15:41:13 +02:00
Clifford Wolf 87426f5a06 Improve write_verilog specify support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 08:46:24 +02:00
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
 2019-05-03 03:10:43 +03:00
Clifford Wolf 6bbe2fdbf3 Add splitcmplxassign test case and silence splitcmplxassign warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 10:01:54 +02:00
Clifford Wolf 3b6a02d3a7 Fix width detection of memory access with bit slice, fixes #974 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:57:26 +02:00
Clifford Wolf 59d74a3348 Re-enable "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:02:39 +02:00
Clifford Wolf e35fe1344d Disabled "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 20:22:50 +02:00
Clifford Wolf 9af825e31e Add final loop variable assignment when unrolling for-loops, fixes #968 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:03:32 +02:00
Clifford Wolf 71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 012c6af088 Allow $specify[23] cells in blackbox modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf b232e027bf Checking and fixing specify cells in genRTLIL 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 4ad0ea5c3c Determine correct signedness and expression width in for loop unrolling, fixes #370 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 18:19:02 +02:00
Clifford Wolf b40af877f3
Merge pull request #909 from zachjs/master 
support repeat loops with constant repeat counts outside of constant functions
 2019-04-22 08:51:34 +02:00