2013-01-05 04:13:26 -06:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* This is the AST frontend library.
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*
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* The AST frontend library is not a frontend on it's own but provides a
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* generic abstract syntax tree (AST) abstraction for HDL code and can be
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* used by HDL frontends. See "ast.h" for an overview of the API and the
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* Verilog frontend for an usage example.
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*
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*/
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2014-12-29 07:30:33 -06:00
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#include "kernel/yosys.h"
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2013-02-27 02:32:19 -06:00
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#include "libs/sha1/sha1.h"
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2013-01-05 04:13:26 -06:00
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#include "ast.h"
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#include <sstream>
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#include <stdarg.h>
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2014-10-18 14:26:49 -05:00
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#if defined(__APPLE__)
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2014-10-19 11:42:03 -05:00
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# include <cmath>
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2014-10-18 14:26:49 -05:00
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#else
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2014-10-19 11:42:03 -05:00
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# include <math.h>
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2014-10-18 14:26:49 -05:00
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#endif
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2013-01-05 04:13:26 -06:00
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2014-07-31 06:19:47 -05:00
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YOSYS_NAMESPACE_BEGIN
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2013-01-05 04:13:26 -06:00
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using namespace AST;
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using namespace AST_INTERNAL;
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// instanciate global variables (public API)
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namespace AST {
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std::string current_filename;
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void (*set_line_num)(int) = NULL;
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int (*get_line_num)() = NULL;
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}
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// instanciate global variables (private API)
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namespace AST_INTERNAL {
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2014-02-17 07:28:52 -06:00
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bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
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2013-01-05 04:13:26 -06:00
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AstNode *current_ast, *current_ast_mod;
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std::map<std::string, AstNode*> current_scope;
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2014-12-28 12:24:24 -06:00
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const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
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2013-03-31 04:51:12 -05:00
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RTLIL::SigSpec ignoreThisSignalsInInitial;
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2013-01-05 04:13:26 -06:00
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AstNode *current_top_block, *current_block, *current_block_child;
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AstModule *current_module;
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}
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// convert node types to string
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std::string AST::type2str(AstNodeType type)
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{
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switch (type)
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{
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#define X(_item) case _item: return #_item;
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X(AST_NONE)
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X(AST_DESIGN)
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X(AST_MODULE)
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X(AST_TASK)
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X(AST_FUNCTION)
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2014-08-21 05:43:51 -05:00
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X(AST_DPI_FUNCTION)
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2013-01-05 04:13:26 -06:00
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X(AST_WIRE)
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X(AST_MEMORY)
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X(AST_AUTOWIRE)
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X(AST_PARAMETER)
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X(AST_LOCALPARAM)
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2013-07-04 07:12:33 -05:00
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X(AST_DEFPARAM)
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2013-01-05 04:13:26 -06:00
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X(AST_PARASET)
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X(AST_ARGUMENT)
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X(AST_RANGE)
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2014-08-06 08:43:46 -05:00
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X(AST_MULTIRANGE)
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2013-01-05 04:13:26 -06:00
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X(AST_CONSTANT)
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2014-06-13 04:29:23 -05:00
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X(AST_REALVALUE)
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2013-01-05 04:13:26 -06:00
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X(AST_CELLTYPE)
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X(AST_IDENTIFIER)
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2013-02-26 06:18:22 -06:00
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X(AST_PREFIX)
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2014-01-18 21:18:22 -06:00
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X(AST_ASSERT)
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2013-01-05 04:13:26 -06:00
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X(AST_FCALL)
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2014-02-01 06:50:23 -06:00
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X(AST_TO_BITS)
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2013-01-05 04:13:26 -06:00
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X(AST_TO_SIGNED)
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X(AST_TO_UNSIGNED)
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X(AST_CONCAT)
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X(AST_REPLICATE)
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X(AST_BIT_NOT)
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X(AST_BIT_AND)
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X(AST_BIT_OR)
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X(AST_BIT_XOR)
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X(AST_BIT_XNOR)
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X(AST_REDUCE_AND)
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X(AST_REDUCE_OR)
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X(AST_REDUCE_XOR)
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X(AST_REDUCE_XNOR)
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X(AST_REDUCE_BOOL)
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X(AST_SHIFT_LEFT)
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X(AST_SHIFT_RIGHT)
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X(AST_SHIFT_SLEFT)
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X(AST_SHIFT_SRIGHT)
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X(AST_LT)
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X(AST_LE)
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X(AST_EQ)
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X(AST_NE)
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2013-12-27 06:50:08 -06:00
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X(AST_EQX)
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X(AST_NEX)
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2013-01-05 04:13:26 -06:00
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X(AST_GE)
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X(AST_GT)
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X(AST_ADD)
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X(AST_SUB)
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X(AST_MUL)
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X(AST_DIV)
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X(AST_MOD)
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X(AST_POW)
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X(AST_POS)
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X(AST_NEG)
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X(AST_LOGIC_AND)
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X(AST_LOGIC_OR)
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X(AST_LOGIC_NOT)
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X(AST_TERNARY)
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X(AST_MEMRD)
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X(AST_MEMWR)
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X(AST_TCALL)
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X(AST_ASSIGN)
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X(AST_CELL)
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X(AST_PRIMITIVE)
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2014-06-07 04:48:50 -05:00
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X(AST_CELLARRAY)
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2013-01-05 04:13:26 -06:00
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X(AST_ALWAYS)
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2013-03-31 04:19:11 -05:00
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X(AST_INITIAL)
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2013-01-05 04:13:26 -06:00
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X(AST_BLOCK)
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X(AST_ASSIGN_EQ)
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X(AST_ASSIGN_LE)
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X(AST_CASE)
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X(AST_COND)
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X(AST_DEFAULT)
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X(AST_FOR)
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2014-02-14 13:33:22 -06:00
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X(AST_WHILE)
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2014-06-06 10:40:04 -05:00
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X(AST_REPEAT)
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2013-01-05 04:13:26 -06:00
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X(AST_GENVAR)
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X(AST_GENFOR)
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X(AST_GENIF)
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2013-12-04 14:06:54 -06:00
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X(AST_GENCASE)
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2013-01-05 04:13:26 -06:00
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X(AST_GENBLOCK)
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X(AST_POSEDGE)
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X(AST_NEGEDGE)
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X(AST_EDGE)
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#undef X
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default:
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2013-05-24 07:38:36 -05:00
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log_abort();
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2013-01-05 04:13:26 -06:00
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}
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}
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2013-10-24 04:20:13 -05:00
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// check if attribute exists and has non-zero value
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bool AstNode::get_bool_attribute(RTLIL::IdString id)
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{
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if (attributes.count(id) == 0)
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return false;
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AstNode *attr = attributes.at(id);
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if (attr->type != AST_CONSTANT)
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log_error("Attribute `%s' with non-constant value at %s:%d!\n",
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id.c_str(), attr->filename.c_str(), attr->linenum);
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return attr->integer != 0;
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}
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2013-01-05 04:13:26 -06:00
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// create new node (AstNode constructor)
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// (the optional child arguments make it easier to create AST trees)
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AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2)
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{
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2014-12-28 20:11:50 -06:00
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static unsigned int hashidx_count = 123456789;
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hashidx_count = mkhash_xorshift(hashidx_count);
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hashidx_ = hashidx_count;
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2013-01-05 04:13:26 -06:00
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this->type = type;
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filename = current_filename;
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linenum = get_line_num();
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is_input = false;
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is_output = false;
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is_reg = false;
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is_signed = false;
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2013-12-05 06:26:17 -06:00
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is_string = false;
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2013-01-05 04:13:26 -06:00
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range_valid = false;
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2014-07-28 07:25:03 -05:00
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range_swapped = false;
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2013-01-05 04:13:26 -06:00
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port_id = 0;
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range_left = -1;
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range_right = 0;
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integer = 0;
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2014-06-14 05:00:47 -05:00
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realvalue = 0;
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2013-01-05 04:13:26 -06:00
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id2ast = NULL;
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2014-01-20 13:25:20 -06:00
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basic_prep = false;
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2013-01-05 04:13:26 -06:00
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if (child1)
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children.push_back(child1);
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if (child2)
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children.push_back(child2);
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}
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// create a (deep recursive) copy of a node
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AstNode *AstNode::clone()
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{
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AstNode *that = new AstNode;
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*that = *this;
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for (auto &it : that->children)
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it = it->clone();
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for (auto &it : that->attributes)
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it.second = it.second->clone();
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return that;
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}
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// create a (deep recursive) copy of a node use 'other' as target root node
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void AstNode::cloneInto(AstNode *other)
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{
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AstNode *tmp = clone();
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other->delete_children();
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*other = *tmp;
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tmp->children.clear();
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tmp->attributes.clear();
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delete tmp;
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}
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// delete all children in this node
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void AstNode::delete_children()
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{
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for (auto &it : children)
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delete it;
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children.clear();
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for (auto &it : attributes)
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delete it.second;
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attributes.clear();
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}
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// AstNode destructor
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AstNode::~AstNode()
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{
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delete_children();
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}
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// create a nice text representation of the node
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// (traverse tree by recursion, use 'other' pointer for diffing two AST trees)
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2013-08-19 12:49:14 -05:00
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void AstNode::dumpAst(FILE *f, std::string indent)
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2013-01-05 04:13:26 -06:00
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{
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if (f == NULL) {
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for (auto f : log_files)
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2013-08-19 12:49:14 -05:00
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dumpAst(f, indent);
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2013-01-05 04:13:26 -06:00
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return;
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}
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std::string type_name = type2str(type);
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fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
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2014-03-05 12:56:31 -06:00
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if (id2ast)
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fprintf(f, " [%p -> %p]", this, id2ast);
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else
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fprintf(f, " [%p]", this);
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2013-01-05 04:13:26 -06:00
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if (!str.empty())
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fprintf(f, " str='%s'", str.c_str());
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if (!bits.empty()) {
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fprintf(f, " bits='");
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for (size_t i = bits.size(); i > 0; i--)
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fprintf(f, "%c", bits[i-1] == RTLIL::S0 ? '0' :
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bits[i-1] == RTLIL::S1 ? '1' :
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bits[i-1] == RTLIL::Sx ? 'x' :
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bits[i-1] == RTLIL::Sz ? 'z' : '?');
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2014-10-11 04:42:08 -05:00
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fprintf(f, "'(%d)", GetSize(bits));
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2013-01-05 04:13:26 -06:00
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}
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if (is_input)
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fprintf(f, " input");
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if (is_output)
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fprintf(f, " output");
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if (is_reg)
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fprintf(f, " reg");
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if (is_signed)
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fprintf(f, " signed");
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if (port_id > 0)
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fprintf(f, " port=%d", port_id);
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if (range_valid || range_left != -1 || range_right != 0)
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2014-07-28 07:25:03 -05:00
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fprintf(f, " %srange=[%d:%d]%s", range_swapped ? "swapped_" : "", range_left, range_right, range_valid ? "" : "!");
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2013-01-05 04:13:26 -06:00
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if (integer != 0)
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fprintf(f, " int=%u", (int)integer);
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2014-06-14 05:00:47 -05:00
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if (realvalue != 0)
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fprintf(f, " real=%e", realvalue);
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2014-08-06 08:43:46 -05:00
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if (!multirange_dimensions.empty()) {
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fprintf(f, " multirange=[");
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for (int v : multirange_dimensions)
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fprintf(f, " %d", v);
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fprintf(f, " ]");
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}
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2013-01-05 04:13:26 -06:00
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fprintf(f, "\n");
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2013-11-18 12:54:36 -06:00
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for (auto &it : attributes) {
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fprintf(f, "%s ATTR %s:\n", indent.c_str(), it.first.c_str());
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it.second->dumpAst(f, indent + " ");
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}
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2013-01-05 04:13:26 -06:00
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for (size_t i = 0; i < children.size(); i++)
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2013-08-19 12:49:14 -05:00
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children[i]->dumpAst(f, indent + " ");
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2013-01-05 04:13:26 -06:00
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}
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// helper function for AstNode::dumpVlog()
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static std::string id2vl(std::string txt)
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{
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if (txt.size() > 1 && txt[0] == '\\')
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txt = txt.substr(1);
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for (size_t i = 0; i < txt.size(); i++) {
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if ('A' <= txt[i] && txt[i] <= 'Z') continue;
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if ('a' <= txt[i] && txt[i] <= 'z') continue;
|
|
|
|
if ('0' <= txt[i] && txt[i] <= '9') continue;
|
|
|
|
if (txt[i] == '_') continue;
|
|
|
|
txt = "\\" + txt + " ";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return txt;
|
|
|
|
}
|
|
|
|
|
|
|
|
// dump AST node as verilog pseudo-code
|
|
|
|
void AstNode::dumpVlog(FILE *f, std::string indent)
|
|
|
|
{
|
|
|
|
bool first = true;
|
|
|
|
std::string txt;
|
|
|
|
std::vector<AstNode*> rem_children1, rem_children2;
|
|
|
|
|
|
|
|
if (f == NULL) {
|
|
|
|
for (auto f : log_files)
|
|
|
|
dumpVlog(f, indent);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-11-18 12:54:36 -06:00
|
|
|
for (auto &it : attributes) {
|
2014-08-01 17:45:25 -05:00
|
|
|
fprintf(f, "%s" "(* %s = ", indent.c_str(), id2vl(it.first.str()).c_str());
|
2013-11-18 12:54:36 -06:00
|
|
|
it.second->dumpVlog(f, "");
|
|
|
|
fprintf(f, " *)%s", indent.empty() ? "" : "\n");
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
switch (type)
|
|
|
|
{
|
|
|
|
case AST_MODULE:
|
|
|
|
fprintf(f, "%s" "module %s(", indent.c_str(), id2vl(str).c_str());
|
|
|
|
for (auto child : children)
|
|
|
|
if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
|
|
|
|
fprintf(f, "%s%s", first ? "" : ", ", id2vl(child->str).c_str());
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
fprintf(f, ");\n");
|
|
|
|
|
|
|
|
for (auto child : children)
|
2013-07-04 07:12:33 -05:00
|
|
|
if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || child->type == AST_DEFPARAM)
|
2013-01-05 04:13:26 -06:00
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
else
|
|
|
|
rem_children1.push_back(child);
|
|
|
|
|
|
|
|
for (auto child : rem_children1)
|
|
|
|
if (child->type == AST_WIRE || child->type == AST_AUTOWIRE || child->type == AST_MEMORY)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
else
|
|
|
|
rem_children2.push_back(child);
|
|
|
|
rem_children1.clear();
|
|
|
|
|
|
|
|
for (auto child : rem_children2)
|
|
|
|
if (child->type == AST_TASK || child->type == AST_FUNCTION)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
else
|
|
|
|
rem_children1.push_back(child);
|
|
|
|
rem_children2.clear();
|
|
|
|
|
|
|
|
for (auto child : rem_children1)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
rem_children1.clear();
|
|
|
|
|
|
|
|
fprintf(f, "%s" "endmodule\n", indent.c_str());
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_WIRE:
|
|
|
|
if (is_input && is_output)
|
|
|
|
fprintf(f, "%s" "inout", indent.c_str());
|
|
|
|
else if (is_input)
|
|
|
|
fprintf(f, "%s" "input", indent.c_str());
|
|
|
|
else if (is_output)
|
|
|
|
fprintf(f, "%s" "output", indent.c_str());
|
|
|
|
else if (!is_reg)
|
|
|
|
fprintf(f, "%s" "wire", indent.c_str());
|
|
|
|
if (is_reg)
|
|
|
|
fprintf(f, "%s" "reg", (is_input || is_output) ? " " : indent.c_str());
|
|
|
|
if (is_signed)
|
|
|
|
fprintf(f, " signed");
|
|
|
|
for (auto child : children) {
|
|
|
|
fprintf(f, " ");
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
}
|
|
|
|
fprintf(f, " %s", id2vl(str).c_str());
|
|
|
|
fprintf(f, ";\n");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_MEMORY:
|
|
|
|
fprintf(f, "%s" "memory", indent.c_str());
|
|
|
|
if (is_signed)
|
|
|
|
fprintf(f, " signed");
|
|
|
|
for (auto child : children) {
|
|
|
|
fprintf(f, " ");
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
if (first)
|
|
|
|
fprintf(f, " %s", id2vl(str).c_str());
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
fprintf(f, ";\n");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_RANGE:
|
|
|
|
if (range_valid)
|
|
|
|
fprintf(f, "[%d:%d]", range_left, range_right);
|
|
|
|
else {
|
|
|
|
for (auto child : children) {
|
|
|
|
fprintf(f, "%c", first ? '[' : ':');
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
fprintf(f, "]");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_ALWAYS:
|
|
|
|
fprintf(f, "%s" "always @(", indent.c_str());
|
|
|
|
for (auto child : children) {
|
|
|
|
if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
|
|
|
|
continue;
|
|
|
|
if (!first)
|
|
|
|
fprintf(f, ", ");
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
fprintf(f, ")\n");
|
|
|
|
for (auto child : children) {
|
|
|
|
if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2013-03-31 04:19:11 -05:00
|
|
|
case AST_INITIAL:
|
|
|
|
fprintf(f, "%s" "initial\n", indent.c_str());
|
|
|
|
for (auto child : children) {
|
|
|
|
if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
case AST_POSEDGE:
|
|
|
|
case AST_NEGEDGE:
|
|
|
|
case AST_EDGE:
|
|
|
|
if (type == AST_POSEDGE)
|
|
|
|
fprintf(f, "posedge ");
|
|
|
|
if (type == AST_NEGEDGE)
|
|
|
|
fprintf(f, "negedge ");
|
|
|
|
for (auto child : children)
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_IDENTIFIER:
|
|
|
|
fprintf(f, "%s", id2vl(str).c_str());
|
|
|
|
for (auto child : children)
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_CONSTANT:
|
|
|
|
if (!str.empty())
|
|
|
|
fprintf(f, "\"%s\"", str.c_str());
|
|
|
|
else if (bits.size() == 32)
|
|
|
|
fprintf(f, "%d", RTLIL::Const(bits).as_int());
|
|
|
|
else
|
2014-10-11 04:42:08 -05:00
|
|
|
fprintf(f, "%d'b %s", GetSize(bits), RTLIL::Const(bits).as_string().c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
break;
|
|
|
|
|
2014-06-13 04:29:23 -05:00
|
|
|
case AST_REALVALUE:
|
|
|
|
fprintf(f, "%e", realvalue);
|
|
|
|
break;
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
case AST_BLOCK:
|
|
|
|
if (children.size() == 1) {
|
|
|
|
children[0]->dumpVlog(f, indent);
|
|
|
|
} else {
|
|
|
|
fprintf(f, "%s" "begin\n", indent.c_str());
|
|
|
|
for (auto child : children)
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
fprintf(f, "%s" "end\n", indent.c_str());
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_CASE:
|
|
|
|
fprintf(f, "%s" "case (", indent.c_str());
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")\n");
|
|
|
|
for (size_t i = 1; i < children.size(); i++) {
|
|
|
|
AstNode *child = children[i];
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
}
|
|
|
|
fprintf(f, "%s" "endcase\n", indent.c_str());
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_COND:
|
|
|
|
for (auto child : children) {
|
|
|
|
if (child->type == AST_BLOCK) {
|
|
|
|
fprintf(f, ":\n");
|
|
|
|
child->dumpVlog(f, indent + " ");
|
|
|
|
first = true;
|
|
|
|
} else {
|
|
|
|
fprintf(f, "%s", first ? indent.c_str() : ", ");
|
|
|
|
if (child->type == AST_DEFAULT)
|
|
|
|
fprintf(f, "default");
|
|
|
|
else
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_ASSIGN_EQ:
|
|
|
|
case AST_ASSIGN_LE:
|
|
|
|
fprintf(f, "%s", indent.c_str());
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, " %s ", type == AST_ASSIGN_EQ ? "=" : "<=");
|
|
|
|
children[1]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ";\n");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_CONCAT:
|
|
|
|
fprintf(f, "{");
|
|
|
|
for (auto child : children) {
|
|
|
|
if (!first)
|
|
|
|
fprintf(f, ", ");
|
|
|
|
child->dumpVlog(f, "");
|
|
|
|
first = false;
|
|
|
|
}
|
|
|
|
fprintf(f, "}");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_REPLICATE:
|
|
|
|
fprintf(f, "{");
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, "{");
|
|
|
|
children[1]->dumpVlog(f, "");
|
|
|
|
fprintf(f, "}}");
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (0) { case AST_BIT_NOT: txt = "~"; }
|
|
|
|
if (0) { case AST_REDUCE_AND: txt = "&"; }
|
|
|
|
if (0) { case AST_REDUCE_OR: txt = "|"; }
|
|
|
|
if (0) { case AST_REDUCE_XOR: txt = "^"; }
|
|
|
|
if (0) { case AST_REDUCE_XNOR: txt = "~^"; }
|
|
|
|
if (0) { case AST_REDUCE_BOOL: txt = "|"; }
|
|
|
|
if (0) { case AST_POS: txt = "+"; }
|
|
|
|
if (0) { case AST_NEG: txt = "-"; }
|
|
|
|
if (0) { case AST_LOGIC_NOT: txt = "!"; }
|
|
|
|
fprintf(f, "%s(", txt.c_str());
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")");
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (0) { case AST_BIT_AND: txt = "&"; }
|
|
|
|
if (0) { case AST_BIT_OR: txt = "|"; }
|
|
|
|
if (0) { case AST_BIT_XOR: txt = "^"; }
|
|
|
|
if (0) { case AST_BIT_XNOR: txt = "~^"; }
|
|
|
|
if (0) { case AST_SHIFT_LEFT: txt = "<<"; }
|
|
|
|
if (0) { case AST_SHIFT_RIGHT: txt = ">>"; }
|
|
|
|
if (0) { case AST_SHIFT_SLEFT: txt = "<<<"; }
|
|
|
|
if (0) { case AST_SHIFT_SRIGHT: txt = ">>>"; }
|
|
|
|
if (0) { case AST_LT: txt = "<"; }
|
|
|
|
if (0) { case AST_LE: txt = "<="; }
|
|
|
|
if (0) { case AST_EQ: txt = "=="; }
|
|
|
|
if (0) { case AST_NE: txt = "!="; }
|
2013-12-27 06:50:08 -06:00
|
|
|
if (0) { case AST_EQX: txt = "==="; }
|
|
|
|
if (0) { case AST_NEX: txt = "!=="; }
|
2013-01-05 04:13:26 -06:00
|
|
|
if (0) { case AST_GE: txt = ">="; }
|
|
|
|
if (0) { case AST_GT: txt = ">"; }
|
|
|
|
if (0) { case AST_ADD: txt = "+"; }
|
|
|
|
if (0) { case AST_SUB: txt = "-"; }
|
|
|
|
if (0) { case AST_MUL: txt = "*"; }
|
|
|
|
if (0) { case AST_DIV: txt = "/"; }
|
|
|
|
if (0) { case AST_MOD: txt = "%"; }
|
|
|
|
if (0) { case AST_POW: txt = "**"; }
|
|
|
|
if (0) { case AST_LOGIC_AND: txt = "&&"; }
|
|
|
|
if (0) { case AST_LOGIC_OR: txt = "||"; }
|
|
|
|
fprintf(f, "(");
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")%s(", txt.c_str());
|
|
|
|
children[1]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")");
|
|
|
|
break;
|
|
|
|
|
|
|
|
case AST_TERNARY:
|
|
|
|
fprintf(f, "(");
|
|
|
|
children[0]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ") ? (");
|
|
|
|
children[1]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ") : (");
|
|
|
|
children[2]->dumpVlog(f, "");
|
|
|
|
fprintf(f, ")");
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
std::string type_name = type2str(type);
|
|
|
|
fprintf(f, "%s" "/** %s **/%s", indent.c_str(), type_name.c_str(), indent.empty() ? "" : "\n");
|
|
|
|
// dumpAst(f, indent, NULL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// check if two AST nodes are identical
|
|
|
|
bool AstNode::operator==(const AstNode &other) const
|
|
|
|
{
|
|
|
|
if (type != other.type)
|
|
|
|
return false;
|
|
|
|
if (children.size() != other.children.size())
|
|
|
|
return false;
|
|
|
|
if (str != other.str)
|
|
|
|
return false;
|
|
|
|
if (bits != other.bits)
|
|
|
|
return false;
|
|
|
|
if (is_input != other.is_input)
|
|
|
|
return false;
|
|
|
|
if (is_output != other.is_output)
|
|
|
|
return false;
|
|
|
|
if (is_reg != other.is_reg)
|
|
|
|
return false;
|
|
|
|
if (is_signed != other.is_signed)
|
|
|
|
return false;
|
2013-12-05 06:26:17 -06:00
|
|
|
if (is_string != other.is_string)
|
|
|
|
return false;
|
2013-01-05 04:13:26 -06:00
|
|
|
if (range_valid != other.range_valid)
|
|
|
|
return false;
|
2014-07-28 07:25:03 -05:00
|
|
|
if (range_swapped != other.range_swapped)
|
|
|
|
return false;
|
2013-01-05 04:13:26 -06:00
|
|
|
if (port_id != other.port_id)
|
|
|
|
return false;
|
|
|
|
if (range_left != other.range_left)
|
|
|
|
return false;
|
|
|
|
if (range_right != other.range_right)
|
|
|
|
return false;
|
|
|
|
if (integer != other.integer)
|
|
|
|
return false;
|
|
|
|
for (size_t i = 0; i < children.size(); i++)
|
|
|
|
if (*children[i] != *other.children[i])
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// check if two AST nodes are not identical
|
|
|
|
bool AstNode::operator!=(const AstNode &other) const
|
|
|
|
{
|
|
|
|
return !(*this == other);
|
|
|
|
}
|
|
|
|
|
|
|
|
// check if this AST contains the given node
|
|
|
|
bool AstNode::contains(const AstNode *other) const
|
|
|
|
{
|
|
|
|
if (this == other)
|
|
|
|
return true;
|
|
|
|
for (auto child : children)
|
|
|
|
if (child->contains(other))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// create an AST node for a constant (using a 32 bit int as value)
|
|
|
|
AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
|
|
|
|
{
|
|
|
|
AstNode *node = new AstNode(AST_CONSTANT);
|
|
|
|
node->integer = v;
|
|
|
|
node->is_signed = is_signed;
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
|
|
node->bits.push_back((v & 1) ? RTLIL::S1 : RTLIL::S0);
|
|
|
|
v = v >> 1;
|
|
|
|
}
|
|
|
|
node->range_valid = true;
|
|
|
|
node->range_left = width-1;
|
|
|
|
node->range_right = 0;
|
|
|
|
return node;
|
|
|
|
}
|
|
|
|
|
|
|
|
// create an AST node for a constant (using a bit vector as value)
|
|
|
|
AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
|
|
|
|
{
|
|
|
|
AstNode *node = new AstNode(AST_CONSTANT);
|
|
|
|
node->is_signed = is_signed;
|
|
|
|
node->bits = v;
|
|
|
|
for (size_t i = 0; i < 32; i++) {
|
|
|
|
if (i < node->bits.size())
|
|
|
|
node->integer |= (node->bits[i] == RTLIL::S1) << i;
|
|
|
|
else if (is_signed)
|
|
|
|
node->integer |= (node->bits.back() == RTLIL::S1) << i;
|
|
|
|
}
|
|
|
|
node->range_valid = true;
|
2013-07-07 08:40:26 -05:00
|
|
|
node->range_left = node->bits.size()-1;
|
2013-01-05 04:13:26 -06:00
|
|
|
node->range_right = 0;
|
|
|
|
return node;
|
|
|
|
}
|
|
|
|
|
2013-12-05 06:26:17 -06:00
|
|
|
// create an AST node for a constant (using a string in bit vector form as value)
|
|
|
|
AstNode *AstNode::mkconst_str(const std::vector<RTLIL::State> &v)
|
|
|
|
{
|
|
|
|
AstNode *node = mkconst_str(RTLIL::Const(v).decode_string());
|
2014-10-25 11:23:53 -05:00
|
|
|
while (GetSize(node->bits) < GetSize(v))
|
|
|
|
node->bits.push_back(RTLIL::State::S0);
|
2013-12-05 06:26:17 -06:00
|
|
|
log_assert(node->bits == v);
|
|
|
|
return node;
|
|
|
|
}
|
|
|
|
|
2013-12-05 05:53:49 -06:00
|
|
|
// create an AST node for a constant (using a string as value)
|
|
|
|
AstNode *AstNode::mkconst_str(const std::string &str)
|
|
|
|
{
|
|
|
|
std::vector<RTLIL::State> data;
|
|
|
|
data.reserve(str.size() * 8);
|
|
|
|
for (size_t i = 0; i < str.size(); i++) {
|
|
|
|
unsigned char ch = str[str.size() - i - 1];
|
|
|
|
for (int j = 0; j < 8; j++) {
|
|
|
|
data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
|
|
|
|
ch = ch >> 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
AstNode *node = AstNode::mkconst_bits(data, false);
|
2013-12-05 06:26:17 -06:00
|
|
|
node->is_string = true;
|
2013-12-05 05:53:49 -06:00
|
|
|
node->str = str;
|
|
|
|
return node;
|
|
|
|
}
|
|
|
|
|
2014-08-17 17:02:30 -05:00
|
|
|
bool AstNode::bits_only_01()
|
|
|
|
{
|
|
|
|
for (auto bit : bits)
|
|
|
|
if (bit != RTLIL::S0 && bit != RTLIL::S1)
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-11-02 07:00:17 -05:00
|
|
|
RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
|
|
|
|
{
|
|
|
|
std::vector<RTLIL::State> bits = this->bits;
|
|
|
|
if (width >= 0 && width < int(bits.size()))
|
|
|
|
bits.resize(width);
|
|
|
|
if (width >= 0 && width > int(bits.size())) {
|
|
|
|
RTLIL::State extbit = RTLIL::State::S0;
|
|
|
|
if (is_signed && !bits.empty())
|
|
|
|
extbit = bits.back();
|
|
|
|
while (width > int(bits.size()))
|
|
|
|
bits.push_back(extbit);
|
|
|
|
}
|
|
|
|
return RTLIL::Const(bits);
|
|
|
|
}
|
|
|
|
|
|
|
|
RTLIL::Const AstNode::bitsAsConst(int width)
|
|
|
|
{
|
|
|
|
return bitsAsConst(width, is_signed);
|
|
|
|
}
|
|
|
|
|
2013-12-04 07:14:05 -06:00
|
|
|
RTLIL::Const AstNode::asAttrConst()
|
|
|
|
{
|
|
|
|
log_assert(type == AST_CONSTANT);
|
|
|
|
|
|
|
|
RTLIL::Const val;
|
|
|
|
val.bits = bits;
|
|
|
|
|
2013-12-05 06:26:17 -06:00
|
|
|
if (is_string) {
|
2013-12-04 07:14:05 -06:00
|
|
|
val.flags |= RTLIL::CONST_FLAG_STRING;
|
|
|
|
log_assert(val.decode_string() == str);
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
RTLIL::Const AstNode::asParaConst()
|
|
|
|
{
|
|
|
|
RTLIL::Const val = asAttrConst();
|
|
|
|
if (is_signed)
|
|
|
|
val.flags |= RTLIL::CONST_FLAG_SIGNED;
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2013-12-04 14:06:54 -06:00
|
|
|
bool AstNode::asBool()
|
|
|
|
{
|
|
|
|
log_assert(type == AST_CONSTANT);
|
|
|
|
for (auto &bit : bits)
|
|
|
|
if (bit == RTLIL::State::S1)
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-06-14 01:51:22 -05:00
|
|
|
int AstNode::isConst()
|
|
|
|
{
|
|
|
|
if (type == AST_CONSTANT)
|
|
|
|
return 1;
|
|
|
|
if (type == AST_REALVALUE)
|
|
|
|
return 2;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-08-21 10:11:51 -05:00
|
|
|
uint64_t AstNode::asInt(bool is_signed)
|
|
|
|
{
|
|
|
|
if (type == AST_CONSTANT)
|
|
|
|
{
|
|
|
|
RTLIL::Const v = bitsAsConst(64, is_signed);
|
|
|
|
uint64_t ret = 0;
|
|
|
|
|
|
|
|
for (int i = 0; i < 64; i++)
|
|
|
|
if (v.bits.at(i) == RTLIL::State::S1)
|
|
|
|
ret |= uint64_t(1) << i;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (type == AST_REALVALUE)
|
|
|
|
return realvalue;
|
|
|
|
|
|
|
|
log_abort();
|
|
|
|
}
|
|
|
|
|
2014-06-14 01:51:22 -05:00
|
|
|
double AstNode::asReal(bool is_signed)
|
|
|
|
{
|
2014-08-21 10:11:51 -05:00
|
|
|
if (type == AST_CONSTANT)
|
|
|
|
{
|
2014-06-15 01:38:31 -05:00
|
|
|
RTLIL::Const val(bits);
|
2014-06-14 01:51:22 -05:00
|
|
|
|
2014-06-15 01:38:31 -05:00
|
|
|
bool is_negative = is_signed && val.bits.back() == RTLIL::State::S1;
|
|
|
|
if (is_negative)
|
|
|
|
val = const_neg(val, val, false, false, val.bits.size());
|
2014-06-14 01:51:22 -05:00
|
|
|
|
2014-06-15 01:38:31 -05:00
|
|
|
double v = 0;
|
|
|
|
for (size_t i = 0; i < val.bits.size(); i++)
|
2014-06-16 08:05:37 -05:00
|
|
|
// IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
|
|
|
|
// the net or the variable shall be treated as zero upon conversion.
|
2014-06-15 01:38:31 -05:00
|
|
|
if (val.bits.at(i) == RTLIL::State::S1)
|
|
|
|
v += exp2(i);
|
|
|
|
if (is_negative)
|
|
|
|
v *= -1;
|
|
|
|
|
|
|
|
return v;
|
2014-06-14 01:51:22 -05:00
|
|
|
}
|
2014-06-14 05:00:47 -05:00
|
|
|
|
2014-06-14 01:51:22 -05:00
|
|
|
if (type == AST_REALVALUE)
|
|
|
|
return realvalue;
|
2014-06-14 05:00:47 -05:00
|
|
|
|
|
|
|
log_abort();
|
2014-06-14 01:51:22 -05:00
|
|
|
}
|
|
|
|
|
2014-06-14 13:38:05 -05:00
|
|
|
RTLIL::Const AstNode::realAsConst(int width)
|
|
|
|
{
|
|
|
|
double v = round(realvalue);
|
|
|
|
RTLIL::Const result;
|
2014-08-22 09:09:13 -05:00
|
|
|
#ifdef EMSCRIPTEN
|
|
|
|
if (!isfinite(v)) {
|
|
|
|
#else
|
2014-07-31 06:19:47 -05:00
|
|
|
if (!std::isfinite(v)) {
|
2014-08-22 09:09:13 -05:00
|
|
|
#endif
|
2014-06-14 13:38:05 -05:00
|
|
|
result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
|
|
|
|
} else {
|
|
|
|
bool is_negative = v < 0;
|
|
|
|
if (is_negative)
|
|
|
|
v *= -1;
|
|
|
|
for (int i = 0; i < width; i++, v /= 2)
|
2014-06-15 02:27:09 -05:00
|
|
|
result.bits.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0);
|
2014-06-14 13:38:05 -05:00
|
|
|
if (is_negative)
|
|
|
|
result = const_neg(result, result, false, false, result.bits.size());
|
|
|
|
}
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// create a new AstModule from an AST_MODULE AST node
|
2014-02-13 06:59:13 -06:00
|
|
|
static AstModule* process_module(AstNode *ast, bool defer)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(ast->type == AST_MODULE);
|
2014-02-13 06:59:13 -06:00
|
|
|
|
|
|
|
if (defer)
|
|
|
|
log("Storing AST representation for module `%s'.\n", ast->str.c_str());
|
|
|
|
else
|
|
|
|
log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2013-11-02 07:00:17 -05:00
|
|
|
current_module = new AstModule;
|
|
|
|
current_module->ast = NULL;
|
2014-02-20 12:12:32 -06:00
|
|
|
current_module->name = ast->str;
|
2013-11-02 07:00:17 -05:00
|
|
|
current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
current_ast_mod = ast;
|
|
|
|
AstNode *ast_before_simplify = ast->clone();
|
|
|
|
|
2013-08-19 12:49:14 -05:00
|
|
|
if (flag_dump_ast1) {
|
|
|
|
log("Dumping verilog AST before simplification:\n");
|
|
|
|
ast->dumpAst(NULL, " ");
|
|
|
|
log("--- END OF AST DUMP ---\n");
|
|
|
|
}
|
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
if (!defer)
|
|
|
|
{
|
2014-02-14 12:56:44 -06:00
|
|
|
while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
if (flag_dump_ast2) {
|
|
|
|
log("Dumping verilog AST after simplification:\n");
|
|
|
|
ast->dumpAst(NULL, " ");
|
|
|
|
log("--- END OF AST DUMP ---\n");
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
if (flag_dump_vlog) {
|
|
|
|
log("Dumping verilog AST (as requested by dump_vlog option):\n");
|
|
|
|
ast->dumpVlog(NULL, " ");
|
|
|
|
log("--- END OF AST DUMP ---\n");
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
if (flag_lib) {
|
|
|
|
std::vector<AstNode*> new_children;
|
|
|
|
for (auto child : ast->children) {
|
|
|
|
if (child->type == AST_WIRE && (child->is_input || child->is_output))
|
|
|
|
new_children.push_back(child);
|
|
|
|
else
|
|
|
|
delete child;
|
|
|
|
}
|
|
|
|
ast->children.swap(new_children);
|
|
|
|
ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
|
2013-03-28 03:20:10 -05:00
|
|
|
}
|
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
ignoreThisSignalsInInitial = RTLIL::SigSpec();
|
2013-03-31 04:51:12 -05:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
for (auto &attr : ast->attributes) {
|
|
|
|
if (attr.second->type != AST_CONSTANT)
|
|
|
|
log_error("Attribute `%s' with non-constant value at %s:%d!\n",
|
|
|
|
attr.first.c_str(), ast->filename.c_str(), ast->linenum);
|
|
|
|
current_module->attributes[attr.first] = attr.second->asAttrConst();
|
|
|
|
}
|
|
|
|
for (size_t i = 0; i < ast->children.size(); i++) {
|
|
|
|
AstNode *node = ast->children[i];
|
|
|
|
if (node->type == AST_WIRE || node->type == AST_MEMORY)
|
|
|
|
node->genRTLIL();
|
|
|
|
}
|
|
|
|
for (size_t i = 0; i < ast->children.size(); i++) {
|
|
|
|
AstNode *node = ast->children[i];
|
|
|
|
if (node->type != AST_WIRE && node->type != AST_MEMORY && node->type != AST_INITIAL)
|
|
|
|
node->genRTLIL();
|
|
|
|
}
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
ignoreThisSignalsInInitial.sort_and_unify();
|
2013-03-31 04:51:12 -05:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
for (size_t i = 0; i < ast->children.size(); i++) {
|
|
|
|
AstNode *node = ast->children[i];
|
|
|
|
if (node->type == AST_INITIAL)
|
|
|
|
node->genRTLIL();
|
|
|
|
}
|
2013-03-31 04:51:12 -05:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
ignoreThisSignalsInInitial = RTLIL::SigSpec();
|
|
|
|
}
|
2013-03-31 04:51:12 -05:00
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
current_module->ast = ast_before_simplify;
|
|
|
|
current_module->nolatches = flag_nolatches;
|
|
|
|
current_module->nomem2reg = flag_nomem2reg;
|
2013-03-24 05:13:32 -05:00
|
|
|
current_module->mem2reg = flag_mem2reg;
|
2013-03-28 03:20:10 -05:00
|
|
|
current_module->lib = flag_lib;
|
2013-06-10 06:19:04 -05:00
|
|
|
current_module->noopt = flag_noopt;
|
2014-01-28 17:59:28 -06:00
|
|
|
current_module->icells = flag_icells;
|
2014-02-17 07:28:52 -06:00
|
|
|
current_module->autowire = flag_autowire;
|
2014-08-14 09:13:42 -05:00
|
|
|
current_module->fixup_ports();
|
2013-01-05 04:13:26 -06:00
|
|
|
return current_module;
|
|
|
|
}
|
|
|
|
|
|
|
|
// create AstModule instances for all modules in the AST tree and add them to 'design'
|
2014-02-17 07:28:52 -06:00
|
|
|
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
|
|
|
current_ast = ast;
|
2013-08-19 12:49:14 -05:00
|
|
|
flag_dump_ast1 = dump_ast1;
|
|
|
|
flag_dump_ast2 = dump_ast2;
|
2013-01-05 04:13:26 -06:00
|
|
|
flag_dump_vlog = dump_vlog;
|
|
|
|
flag_nolatches = nolatches;
|
|
|
|
flag_nomem2reg = nomem2reg;
|
2013-03-24 05:13:32 -05:00
|
|
|
flag_mem2reg = mem2reg;
|
2013-03-28 03:20:10 -05:00
|
|
|
flag_lib = lib;
|
2013-06-10 06:19:04 -05:00
|
|
|
flag_noopt = noopt;
|
2014-01-28 17:59:28 -06:00
|
|
|
flag_icells = icells;
|
2014-02-17 07:28:52 -06:00
|
|
|
flag_autowire = autowire;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-08-21 05:42:28 -05:00
|
|
|
std::vector<AstNode*> global_decls;
|
|
|
|
|
2014-07-28 04:08:55 -05:00
|
|
|
log_assert(current_ast->type == AST_DESIGN);
|
2014-08-21 05:42:28 -05:00
|
|
|
for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++)
|
|
|
|
{
|
|
|
|
if ((*it)->type == AST_MODULE)
|
|
|
|
{
|
|
|
|
for (auto n : global_decls)
|
|
|
|
(*it)->children.push_back(n->clone());
|
|
|
|
|
|
|
|
if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
|
|
|
|
(*it)->str = (*it)->str.substr(1);
|
|
|
|
|
|
|
|
if (defer)
|
|
|
|
(*it)->str = "$abstract" + (*it)->str;
|
|
|
|
|
|
|
|
if (design->has((*it)->str)) {
|
|
|
|
if (!ignore_redef)
|
|
|
|
log_error("Re-definition of module `%s' at %s:%d!\n",
|
|
|
|
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
|
|
|
|
log("Ignoring re-definition of module `%s' at %s:%d!\n",
|
2013-11-24 12:57:42 -06:00
|
|
|
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
|
2014-08-21 05:42:28 -05:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
design->add(process_module(*it, defer));
|
2013-11-24 12:57:42 -06:00
|
|
|
}
|
2014-08-21 05:42:28 -05:00
|
|
|
else
|
|
|
|
global_decls.push_back(*it);
|
2013-01-05 04:13:26 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// AstModule destructor
|
|
|
|
AstModule::~AstModule()
|
|
|
|
{
|
|
|
|
if (ast != NULL)
|
|
|
|
delete ast;
|
|
|
|
}
|
|
|
|
|
|
|
|
// create a new parametric module (when needed) and return the name of the generated module
|
2014-12-26 03:53:21 -06:00
|
|
|
RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters)
|
2013-01-05 04:13:26 -06:00
|
|
|
{
|
2014-08-01 17:45:25 -05:00
|
|
|
std::string stripped_name = name.str();
|
2014-02-13 06:59:13 -06:00
|
|
|
|
|
|
|
if (stripped_name.substr(0, 9) == "$abstract")
|
|
|
|
stripped_name = stripped_name.substr(9);
|
|
|
|
|
|
|
|
log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
|
|
|
|
current_ast = NULL;
|
2013-08-19 12:49:14 -05:00
|
|
|
flag_dump_ast1 = false;
|
|
|
|
flag_dump_ast2 = false;
|
2013-01-05 04:13:26 -06:00
|
|
|
flag_dump_vlog = false;
|
|
|
|
flag_nolatches = nolatches;
|
|
|
|
flag_nomem2reg = nomem2reg;
|
2013-03-24 05:13:32 -05:00
|
|
|
flag_mem2reg = mem2reg;
|
2013-03-28 03:20:10 -05:00
|
|
|
flag_lib = lib;
|
2013-06-10 06:19:04 -05:00
|
|
|
flag_noopt = noopt;
|
2014-01-28 17:59:28 -06:00
|
|
|
flag_icells = icells;
|
2014-02-17 07:28:52 -06:00
|
|
|
flag_autowire = autowire;
|
2013-01-05 04:13:26 -06:00
|
|
|
use_internal_line_num();
|
|
|
|
|
2013-04-26 06:13:58 -05:00
|
|
|
std::string para_info;
|
2013-01-05 04:13:26 -06:00
|
|
|
AstNode *new_ast = ast->clone();
|
|
|
|
|
|
|
|
int para_counter = 0;
|
2014-02-13 06:59:13 -06:00
|
|
|
int orig_parameters_n = parameters.size();
|
2013-01-05 04:13:26 -06:00
|
|
|
for (auto it = new_ast->children.begin(); it != new_ast->children.end(); it++) {
|
|
|
|
AstNode *child = *it;
|
|
|
|
if (child->type != AST_PARAMETER)
|
|
|
|
continue;
|
|
|
|
para_counter++;
|
|
|
|
std::string para_id = child->str;
|
2013-04-26 07:40:25 -05:00
|
|
|
if (parameters.count(para_id) > 0) {
|
2013-01-05 04:13:26 -06:00
|
|
|
log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
|
|
|
|
rewrite_parameter:
|
2013-04-26 07:40:25 -05:00
|
|
|
para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
|
2013-11-07 02:58:15 -06:00
|
|
|
delete child->children.at(0);
|
2013-12-04 07:24:44 -06:00
|
|
|
child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0);
|
2013-01-05 04:13:26 -06:00
|
|
|
parameters.erase(para_id);
|
|
|
|
continue;
|
|
|
|
}
|
2013-04-26 07:40:25 -05:00
|
|
|
para_id = stringf("$%d", para_counter);
|
|
|
|
if (parameters.count(para_id) > 0) {
|
2013-01-05 04:13:26 -06:00
|
|
|
log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
|
|
|
|
goto rewrite_parameter;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (parameters.size() > 0)
|
2014-02-13 06:59:13 -06:00
|
|
|
log_error("Requested parameter `%s' does not exist in module `%s'!\n", parameters.begin()->first.c_str(), stripped_name.c_str());
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2013-04-26 06:13:58 -05:00
|
|
|
std::string modname;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-02-13 06:59:13 -06:00
|
|
|
if (orig_parameters_n == 0)
|
|
|
|
modname = stripped_name;
|
2014-08-01 12:01:10 -05:00
|
|
|
else if (para_info.size() > 60)
|
|
|
|
modname = "$paramod$" + sha1(para_info) + stripped_name;
|
2013-04-26 06:13:58 -05:00
|
|
|
else
|
2014-02-13 06:59:13 -06:00
|
|
|
modname = "$paramod" + stripped_name + para_info;
|
2013-01-05 04:13:26 -06:00
|
|
|
|
2014-07-31 07:11:39 -05:00
|
|
|
if (!design->has(modname)) {
|
2013-01-05 04:13:26 -06:00
|
|
|
new_ast->str = modname;
|
2014-07-31 07:11:39 -05:00
|
|
|
design->add(process_module(new_ast, false));
|
|
|
|
design->module(modname)->check();
|
2013-01-05 04:13:26 -06:00
|
|
|
} else {
|
|
|
|
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
|
|
|
|
}
|
|
|
|
|
|
|
|
delete new_ast;
|
|
|
|
return modname;
|
|
|
|
}
|
|
|
|
|
2013-07-27 07:27:51 -05:00
|
|
|
RTLIL::Module *AstModule::clone() const
|
|
|
|
{
|
|
|
|
AstModule *new_mod = new AstModule;
|
2014-07-27 14:12:09 -05:00
|
|
|
new_mod->name = name;
|
2013-07-27 07:27:51 -05:00
|
|
|
cloneInto(new_mod);
|
|
|
|
|
|
|
|
new_mod->ast = ast->clone();
|
|
|
|
new_mod->nolatches = nolatches;
|
|
|
|
new_mod->nomem2reg = nomem2reg;
|
|
|
|
new_mod->mem2reg = mem2reg;
|
|
|
|
new_mod->lib = lib;
|
|
|
|
new_mod->noopt = noopt;
|
2014-01-28 17:59:28 -06:00
|
|
|
new_mod->icells = icells;
|
2014-02-17 07:28:52 -06:00
|
|
|
new_mod->autowire = autowire;
|
2013-07-27 07:27:51 -05:00
|
|
|
|
|
|
|
return new_mod;
|
|
|
|
}
|
|
|
|
|
2013-01-05 04:13:26 -06:00
|
|
|
// internal dummy line number callbacks
|
|
|
|
namespace {
|
|
|
|
int internal_line_num;
|
|
|
|
void internal_set_line_num(int n) {
|
|
|
|
internal_line_num = n;
|
|
|
|
}
|
|
|
|
int internal_get_line_num() {
|
|
|
|
return internal_line_num;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// use internal dummy line number callbacks
|
|
|
|
void AST::use_internal_line_num()
|
|
|
|
{
|
|
|
|
set_line_num = &internal_set_line_num;
|
|
|
|
get_line_num = &internal_get_line_num;
|
|
|
|
}
|
|
|
|
|
2014-07-31 06:19:47 -05:00
|
|
|
YOSYS_NAMESPACE_END
|
|
|
|
|