* New: Python/C++ API level:
* Write a new C++/template wrapper to get rid of boost::python
* The int & long Python type are now merged. So a C/C++ level,
it became "PyLong_X" (remove "PyInt_X") and at Python code
level, it became "int" (remove "long").
* Change: VLSISAPD finally defunct.
* Configuration is now integrated as a Hurricane component,
makes use of the new C++/template wrapper.
* vlsisapd is now defunct. Keep it in the source for now as
some remaining non essential code may have to be ported in
the future.
* Note: Python code (copy of the migration howto):
* New print function syntax print().
* Changed "dict.has_key(k)" for "k" in dict.
* Changed "except Exception, e" for "except Exception as e".
* The division "/" is now the floating point division, even if
both operand are integers. So 3/2 now gives 1.5 and no longer 1.
The integer division is now "//" : 1 = 3//2. So have to carefully
review the code to update. Most of the time we want to use "//".
We must never change to float for long that, in fact, represents
DbU (exposed as Python int type).
* execfile() must be replaced by exec(open("file").read()).
* iter().__next__() becomes iter(x).__next__().
* __getslice__() has been removed, integrated to __getitem__().
* The formating used for str(type(o)) has changed, so In Stratus,
have to update them ("<class 'MyClass'>" instead of "MyClass").
* the "types" module no longer supply values for default types
like str (types.StringType) or list (types.StringType).
Must use "isinstance()" where they were occuring.
* Remove the 'L' to indicate "long integer" (like "12L"), now
all Python integer are long.
* Change in bootstrap:
* Ported Coriolis builder (ccb) to Python3.
* Ported Coriolis socInstaller.py to Python3.
* Note: In PyQt4+Python3, QVariant no longer exists. Use None or
directly convert using the python syntax: bool(x), int(x), ...
By default, it is a string (str).
* Note: PyQt4 bindings & Python3 under SL7.
* In order to compile user's must upgrade to my own rebuild of
PyQt 4 & 5 bindings 4.19.21-1.el7.soc.
* Bug: In cumulus/plugins.block.htree.HTree.splitNet(), set the root
buffer of the H-Tree to the original signal (mainly: top clock).
Strangely, it was only done when working in full chip mode.
In the LS180, probably due to the implementation of a small RAM
with DFFs, some leaf of the clock tree (H-Tree) got heavily
loaded (around 80 DFFs sinks). Implement an option that allow
the leaf of the QuadTree to use three buffers instead of one.
The sinks are partitionned using their angle from the center
of the leaf (trigonometric direction). CChoose the bigger angle
gaps to perform the split.
* Change: In Cumulus/plugins.block.configuration.GaugeConf, in
getNearestHorizontalTrack() and getNearestVerticalTrack() add an
offset argument to shift the position of the requested track
by a certain amount.
* Change: In Cumulus/plugins.block.configuration.GaugeConf, in
createHorizontal(), add a flag to make the source end of the
segment to "stick out". Useful when connecting to a stacked
VIA top, but using a lower layer that can be shifted.
* New: In Cumulus/plugins.block.spares.Spares, BufferPool & QuadTree,
add support for selection and management of multiple buffers at
the same time. Basically returns a list of selected buffer
instances instead of just one instance.
Added HEAVY_LEAF_LOAD flag to Spares. To be used by all tools
classes that makes use of it.
Added QuadTree.runselect(), be sure to call it between different
H-Tree operations, otherwise results will be strange.
* New: In Cumulus/plugins.block.htree.HTree, in case of heavy leaf
load, in the leaf of the tree, allocate three buffers instead
of one. Select them to form a triangle around the main one.
That is, use (i,j), (i+1,j) and (i,j+1).
Added a HTree._connectLeaf() to share the handling of the child
buffer connexions. Whether they are leaf of not and heavy or not.
* Change: Cumulus/plugins.block.Block, expand HTree support to
manage the HEAVY_LEAF_LOAD flag.
* In Cumulus/plugins/block/macro.py, the METAL3 blokage was too narrow
on the left side, allowing use of METAL3 track too close from
internal components.
The METAL5 blockages around jumpers where also too narrow.
Thoses problems where seen with the density filler which put
wires everywhere.
* Change: In Etesian::Slice::fillHole(), instead of cramming the home
with tix_x0 only, put one tie at both ends and fill the rest
with fill_x0. This should help the vendor density filler to
equalze.
* New: In Etesian::Configuration, add the parameter:
"etesian.tieName" (for tix_x0) as it now separate from the simple
filler cells.
* Bug: In cumulus/plugins.chip.libresocio, the ioPadInfos where inverting
"d" and "s" terminals on IOPadInOut. This was indirectly detected by
the DRC complaining about floating gates on the "d" connected nets!
* New: cumulus/plugins.checks, plugin providing a oneDriver() function
to check that each net has one and only one driver. This is for
Cell that are not P&R (in which it is also checked). So, typically
the chip level.
* New: In cumulus/plugins.chip.core2chip, add a call to oneDriver().
* Bug: In cumulus/plugins.chip.core2chip, clear Spice extensions after
save. Otherwise we may use an outdated Spice extension after the
P&R. This is were Net missing Spice::Bit may occur.
The structure of the driver is copied from the Vhdl one. It is not
integrated as a an AllianceFramework one but as a standalone like
GDS. For now use numerical indexes for electrical nodes but also
support strings. The nets are ordereds in reverse alphabetical
order, but a custom order can be defined, if we read the model
from an external SPICE subckt (to be done).
SPICE saving has also been added to the cumulus/rsave plugin
and the block/chip P&R one.
* Change: In cumulus/plugins.chip.chip.doConnectCore(), do not use the
feature of the HTree to connect the root buffer straight to the
corona pin. It prevents the router to insert a diode when those
wires are too long. So let the standard router manage them.
Should add diode insertions in HTree.connectHTrees() later.
* Bug: In cumulus/plugins.chip.powerplane.Builder._connectHTree(),
when building the stacked VIAs over the corona Pin and the
root buffer RoutingPad, pass the GaugeConf.HAccess flag so the
stack stops at METAL4 (top horizontal layer).
Before we where also adding a VIA up to METAL5 which was unused
and caused a minimal area violation.
* Change: In cumulus/plugins.block.macro, the METAL2 blockage was
allowing horizontal tracks to be used but the METAL3 blockage
was conflicting with the end of the perpandiculars.
The router was not able to manage that, so we slightly expand
the METAL2 blockage to encompass the unreachable track.
For the same reason, add a METAL4 blockage over METAL2.
* New: In cumulus/plugins.chip.pads, add METAL5 jumpers on all wires
going to/from the I/O pads on the East & West side. This is a
quick hack as:
1. We should put it also on North/South, but no violation
happens here.
2. We should put it on *ouput* wire only (for only those are
connected to transistors gates).
* New: In cumulus/plugins.chip.macro, put jumpers on the East side
connectors for the SRAM block. Also a quick hack, not robust for
anything else than the SRAM.
* Change: In cumulus/plugins.Block.getLeafUnder(): formerly, we where
using the cut-lines (x/y) to locate which leaf a point is under.
But in case of incomplete tree, it is difficult to manage.
Now we chosse the leaf according to the distance to the center
of the leaf area. Choose the shorter, of course.
This solve the H-Tree DFF bad assignment around the PLL (top
right corner) in LS180.
* Bug: In Cumulus/plugins.block.Block, re-order Etesian tool creation
and virtual net flattening. Must investigate later why it is so
sensitive to at least warn/stop cleanly.
* Bug: In Cumulus/plugins.chip.powerplane.Builder._connectHTree(), is was
previously assumed that a net manged by a H-Tree was always coming from
the outside (i.e. a clock or a reset signal).
It is no longer the case, for example with the PLL internally generated
clock.
So prune internal signals in this method.
The H-Tree support is now allowed for any net, not only the clocks and
not only top-level nets. This allow to better management of the LS180
internal clock signal.
* New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
of the function to allow the user to select nets that will *not*
be flattened. This makes the NoClockFlatten flag effectively obsolete,
we keep it for backward compatibility.
The net names can be of non top level ones. In that case, they must
use the name an HyperNet will get (the Occurrence name). For example:
"instance1.instance2.deep_net_name".
* New: In PyCell, update the wrapper for the new parameter of flattenNets(),
new utility function pyListToStringSet() to translate a Python list into
a C++ set of names.
* New: In EtesianEngine, add support for a list of nets to be excluded
from the flattening procedure. Those excluded nets will also be
excludeds from the Coloquinte nets *and* HFNS synthesis, as they
are likely to be manageds by a H-Tree.
* Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
flagged as manually detailed route.
* New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
on nets that are already fixed or detaled route. This replace the
clock exclusion.
* New: In cumulus/plugins.{block,htree,chip}, replace the concept
of clock-tree by the more generic H-Tree. That is, we can ask the P&R
to create H-Tree on any net of the design, not only the ones matcheds
as clock. The net does not even need to be top-level.
This is to manage the PLL internal clock generated by the PLL in
the LS180 chip.
Start to change all reference to "clock" into "H-Tree".
* Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
there was an inversion of the H & V routing gauges to compute the
track into which put the H-Tree center to corona edge wiring.
This was causing tracks to be used twice, seen in the ao68000 test
bench.
* Bug: In cumulus/plugins.macro.Macro.__init__(), stick out the rigth number
of pitches on North & East sides (never tested before).
* New: In cumulus/plugins.macro.Macro.__init__(), manage layer change
if the terminal is not in the preferred routing direction. Use BigVia
and put at least two cuts.
* Bug: In cumulus/plugins.chip.Chip.save(), now completely delegate the
saving procedure to the base class (i.e. Block.save() which is
BlockConf.save()).
* Bug/Change: In cumulus/plugins.block.configuration.BlockConf.save(),
Now manage all the configutation, whether it is a simple block or
a whole chip.
In the case of a whole chip we must force the saving on both
chip and corona as the later, being P&R will be seen as a terminal
block and not recursively saved.
* In cumulus/plugins.block.Block.{place,doPnr}(), reorder the
feed insertion and spare buffer deletion call. Formerly, we
were :
1. Creating spare buffersa (Python).
2. Placing (C++)
3. Adding feeds (EtesianEngine::toHurricane() call) (C++).
4. Removing unused spare buffers (Python).
So, step 4 was *not* informing the C++ placement data-structure
created at step 3 of the change. Resulting in occurrences using
deleted Entities (Instance).
Now we swap step 3. and 4. so toHurricane() is called *after*
any Python managed change is done.
Ideally, what we should implement is a way for Python to inform
the C++ data-structure. No real problem here, but time...
* Change: In cumulus/plugins.block.configuration.Configuration.save()
and cumulus/plugins.chip.Chip.save(), according to the kind of
routing gauge we are using (symbolic or real), either recursively
save all the layouts (AP symbolic files) or only the top-level
GDSII (which embed all the hierarchy) one.
* Bug: In cumulus/plugins.chip.pads, we were connecting the ground and
power supplies to all the horizontal wires in the corona ring.
But, when there are more than one and especially at the outer
border of the pad, the vertical connecting wire will create
various shorts over the pad.
Now we connect only to the innermost horizontal wire only.
Had to chech if the core side of the pad is north or south.
* Bug: In cumulus/plugins.chip.powerplane, while building the connexion
from the corona border to the root of the HTree, the horizontal
wire at the top was too close from the border causing a minimal
spacing error in the DRC. Now put two tracks of distance.
* Bug: In cumulus/plugins.block.block.py, always import Python modules
using the exact same path. Otherwise the module may get imported
twice and static variables are duplicated, generating a big mess.
This was causing problem for the LUT in macro.py, and got SRAMs
blocks encapsulated twice.
* New: In cumulus/plugins.block.block.Block.addPlaceHolder(), create
a "place holder" instance over a given area to prevent the placer
from using it. Allow to make space reservation.
* New: In cumulus/plugins.block.configuration.BlockConf, copy the
toXPitch() and toYSlice() methods from spare in order to share
them between modules. Still have to remove some other local copies.
* New: In cumulus/plugins.block.spare.QuadTree, keep a list of all
the X centers of the partitionned areas. For yse by the power lines.
* New: In cumulus/plugins.chip.chip, move doPowerLayout() call from
doChipFloorplan() to doConnectCore(), this is to delay the call
until *after* the spare QuadTree has been created and we can
align the power lines to the centers of the QuadTree.
* New: In cumulus/plugins.chip.pads.Corona.doPowerLayout(), if a
spare QuadTree has been created, align the power lines on the
X center of the leaf areas. This is a cheap way to avoid DRC
errors between the power BigVias and the wires from the various
clock trees (on METAL5).
* New: In cumulus/plugins.block.macro, add an ad-hoc patch for Staf's
SRAMs. The blockage areas are slightly too narrow. We enlarge
them by one pitch.
* Change: In Cumulus/plupins.chip.pads.Side, in some case (LibreSOCIOPads),
when not put side by side, the I/O pads must be separated by a
minimal distance.
Introduce the new configuration parameter:
cfg.chip.minPadSpacing
Disabled if zero or non-defined.
Fix NWELL DRC errors for TSMC.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
the external status of the former Net. When a Net::merge() is
performed, we must keep track of whether the merged (destroyed)
one was external and keep that information.
Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
search of the net name in *internal* aliases. Otherwise only the
aliases tagged as *external* will be searched.
It was a bug that, when looking for a Plug master net by name
we got an homonymous internal net. In that case we must only
look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
unvectorize it, like when it is non-contiguous (we use the
isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
a flag UniquifyUpperCase to uniquify the names in uppercases.
In case of a clash with the same name in lowercase.
Prepend 'u' before all previously uppercased letter. For
example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
The Catalog flags is exported to Python for use by the blif2vst
script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
a new gate each time it is called instead of making just one for
each Model. This way, if two outside nets are connected to one
or zero they do not get merged (should work, but will be less
clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
master net in the instances models (by name), limit the search
to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
(i.e. components) with 'cmpt_' to avoid clash names with signals
in VHDL.
* Bug: In Cumulus/plugins.block.configuration.GaugeConf.rpAcces(), start
building the stack of contacts + short segments straps from the
layer of the RoutingPad and *not* from the first layer of the
RoutinhGauge.
* Bug: In Cumulus/plugins.block.configuration.GaugeConf.setStackPosition(),
Only align in the RoutingLayer gauge direction of the top layer of
the stack. For example, METAL2(H) will be y aligned or METAL3(V)
will be x aligned.
* Bug: In Cumulus/plugins.chip.powerplane.Builder._connectClock(),
forgot to call expandMinArea() on the pinRp contact stack.
* Change: In Cumulus/plugins.block.spares, allow the QuadTree to have
only *some* of it's four childs (BL, TL, TR, BR).
Modify QuandTree.getLeafUnder() so when there is no leaf under
the point, due to an incomplete tree, we get the closer leaf.
Leaf are suppressed when their center points (where the buffers
are to be put) are under a FIXED Instance (that is, an opaque block).
Those opaque blocks (or macro blocks) must be put *on the periphery*
of the design, because the closer they got to the center, the larger
the chunks of QuadTree that are removeds.
* Change: In Cumulus/plugins.block.clocktree, based on the spare
QuadTree changes, can now build a clock-tree with some of the
leaf missing. Should find a way to compensate for the missing
leaf wires & buffer (dummies).
* New: In Cumulus/plugins.block.matrix.RegisterMatrix, based on pattern
matching the output of DFF, allow to rebuild and place a matrix of
DFF constituting a RAM.
It finally proven not useful because it is a too naive approach.
Intermediate gates (buf_x2) must be found too. Most of the control
signals have more than 20 sinks so gets splitted by HFNS and lastly,
we would want the decoder to be integrated too, but they are not
regulars.
The right way to do it is to create a generator that build it
then expose it in a way nMigen can understand (not the other way
around, nMigen -> Yosys).
* New: CRL::restoreNetsdirection() (in ToolBox) that checks the coherency
of all Nets direction through a complete hierarchy of cells.
Stops at Cells flagged "TerminalNetlist".
Directions are rebuilt for all the Cells part of the hierarchy
in a bottom up fashion. It is also checked that Nets have only one
driver (we assume there is no three-state busses).
To sort cells in hierarchical order (bottom up according to their
depth), copy the DepthOrder class from the GDSII driver. Will unify
them later.
exported to the Python interface.
* New: In cumulus/tools/blif2vst.py, add a call to restoreNetsdirection()
before saving.
* Change: In NetBuilder::getPositions(), ordering of source/target points
is now integrated to this function instead of left to the caller.
In case of real (non-symbolic) routing gauge, skrink the ends of
half the wire width.
* Change: In NetBuilderHV::doRp_AutoContacts(), in case of non-METAL1
RoutingPad, put the axis of the segment on the nearest track.
Issue a warning if we have to shift, as it may be a potential
source of routing problems.
* New: Anabatic::Session::getNearestTrackaAxis(), proxy to compute
track positions, knowing the design abutment box.
* Bug: In Katana::PreProcess::propagateCagedConstraints(), when
looking at all the slave components anchoreds on a RoutingPad,
if they do not have an AutoSegment lookup, skip them instead
of crashing.
* New: In cumulus/plugins.block.Block.placeMacro(), new method to
place a macro cell, partly delegating to the Macro block wrapper.
Must be called *after* both core and corona abutment boxes have
been set.
Adjust the macro block position so the METAL2 & METAL3 pins
are exactly on pitch regarding the full routing grid. The reference
being the corona.
A shift, less than one pitch may be applied, leading in some
cases of overlapping abutment boxes. But this shouldn't be a
problem.
The macro to place is designated through a path of instances
names, rooted at the *core* (not the corona). Meaning that the
head instance must be one of the core.
* Change: In cumulus/plugins.chip.Chip, the complete chip I/O pads
plus corona and core placement is moved out from doPnR() and
put into doChipFloorplan(). It is now mandatory to call this
method *before* doPnR().
Those methods are now cleanly separated so we can perform macro
block placement or any inner core floorplaning operations between
them.
* Change: In cumulus/plugins.macro.Macro, instead of creating large
pads for the I/O pins so whatever the block position, they will
be under a grid point, create a simple dogleg to put them on
grid.
To ensure that they are "on grid", the block pins must be
in METAL2 (horizontal E/W) or METAL3 (vertical N/S) and the block
is assumed to be placed so the bottom left corner of it's
abutment box is exactly on one grid point for M2/M3.
This should be done by Block.placeMacro().
* New: In cumulus/plugins.chip.powerplane, build the overall power
grid when there is a dedicated supply layer. Makes vertical
supply stripes and connect them the *horizontal* power rails
inside the blocks (could be in *any* layer).
Stripes positions are determined by the pins createds by
the pads module.
* New: In cumulus/plugins.chip.chip, use the powerplane builder
if the RoutingGauge provides a PowerSupply kind.
* New: In cumulus/plugins.block.configuration, add support for
PowerSupply gauges.
* New: In cumulus/plugins.block.pads, if the gauge provides a
PowerSupply, create north/south border pins for power & ground
to direct the corona to make vertical power strips.
This assume that we are using LibreSOC like I/O pads that
can be connected straight from everywhere in the corona.
First and last 2 stripes are "cap end" and narrower.
Positions and width of the sripes are set through the
configuration parameters:
* "chip.supplyRailWidth"
* "chip.supplyRailPitch"
* Change: In cumulus/plugins.block.spares, now take into account
the "placeArea" parameter.
* Change: In cumulus/plugins.block.bigvia, now have a per metal layer
area that *may* be expanded if it is too narrow to put at least
one cut. Add flags to allow controlled expansion of the metal
plates.
As a security, now raise an exception if no cut can be created.
* New: In cumulus/plugins.macro.macro.Macro() to encapsulate foreign blocks.
Round their size to an exact number of GCells and a guard of one GCell.
External terminal must be on the periphery and will be made to stick out
in the guard ring. This is sub-optimal for now but provide a workaround
some Katana bad assumptions.
A "perpandicular padding" is also added to terminals to limit the
offgrid related problems. Have to optimize that in conjuction with
Katana.
* Change: In cumulus/plugins.block.Block.__init__(), assume that a block
is already built only if *all* it's instances are placed. Not some
of them.
* New: In cumulus/plugins/block/configuration, added support for a
placeArea parameter to restrict the placement area further than the
abutment box (see Etesian for the new feature).
* Change: In cumulus/plugins/CoreToChip, no longer adds I/O pads for
core signals that lacks one. Only issue an error message and
continue. More useful for debugging block support.
* New: In Etesian::Configuration add new parameters for antenna
effect management:
* "etesian.diodeName" : the name of the diode cell.
* "etesian.antennaMaxwl" : maximum length above which antenna
effect can occur. Must be the maximum for all the normal
routing layers.
* "etesian.antennaInsertThreshold" : during the placement steps,
threshold for linear disruption at which we will look for
the RSMT and insert diodes.
* New: In EtesianEngine::antennaProtect(), at a designated point
in the placement iteratives step, when the spreading starts to
be significant enough estimate the RSMT length and add a diode
if need be. The diode will be put side by side with the driver
cell. This is done by enlarging the driver cell of the diode
width.
* New: In EtesianEngine::_updatePlacement(), in the final stage,
modify the netlist to connect the diode. The diode will be
put on the side of the cell closest to the driver. This may
alow to make the connexion directly in METAL1 in the future.
* Change: In etesian/Placement.cpp, make the whole placement
structure a persistent attribute of the EtesianEngine so
it can be used afterwards.
Add a post-placement diode insertion feature. Finally
unused as they are added on the fly during placement.
In the Area, add data about the diode tie in the TieLut.
* Change: Add EtesianEnginea::clearColoquinte(), to keep the
post-placement structure while purging the Coloquinte one.
* Change: In cumulus/plugins.block.block, keep the Etesian engine
until the whole P&R is done, so we potentially can exploit
the post-placement datas.
* Bug: In cumulus/plugins.chip.power.GoCb(), for the METAL1 power
and ground wires coming from the standard cell, it was assumed
they where made of Horizontal segments, this is not the case
in FlexLib... So force to consider the plane as Horizontal when
we are processing that plane.
Better solution should be to use Horizontals...
height is a multiple of sliceHeight. Otherwise, in some situations,
fixed cell may peek out of the placement area, triggering
Coloquinte assert (which says that the top of the cell is *above*
the top row).
* New: In cumulus/plugins.block.hfns4.py, perform simple HFNS by breaking
the net into sub-nets of at most 10 sinks (hard-coded for now).
As this method is called *after* the netlist as been virtually
flattened, we have to create the RoutingPad at the top level
ourselves. Sub-nets are created at the Cell top-level (same
approach as for clock synthesis, because there is no smart way
to guess where they should be).
* New: In cumulus/plugins.block.block.py, perform HFNS (#4) *before*
doing placement. To see the real sink count on each net, we must
perform the virtual net flattening first (Cell::flattenNets()).
* Change: In cumulus/plugins.block.configuration, allow the creation
of spare buffer in any cell (instead of only "self.cellPnR").
* Change: In cumulus/plugins.block.spares.Spares.raddTransNet(),
Check if intermediate masterNet exists in Cells before trying
to blindly re-create it.
* New: In Etesian::Configuration, added "etesian.lacthUpDistance" to
control tie cells insertion (for polarization contacts).
* New: Etesian/Placement as a complete replacement for FeedCells.
Rebuild the complete slicing structure of the placement to
serve as a building block for post-placement changes under
Coriolis. Currently used to regularly insert body ties.
This is not optimal as we displace cells in each slice in
a non-coordinated manner.
* New: In cumulus/plugins/block.configuration.FeedsConf, register
the "etesian.latchUpDistance" parameter. Provides the tie width.
* New: In cumulus/plugins.block.spares, add ties around the buffer
pool block and "cap ties" at both end of each slice.
* New: In cumulus/plugins.block.spares, added creation of vertical
stacks of feed cells, for their N/P tie contacts, to ensure
correct bulk polarization. Fail, because the placer cannot
cope with such massive obstacles, the vertical columns are
too close to manage.
* New: In cumulus/plugins.block.configuration, add support to
FeedsConf so lone instances can be created (for the first
bulk trial).
* New: In CRL/hepers, new function onFGrid() to ensure a DbU is on the
foundry grid. Rounding is always done to the inferior integer.
* New: In CRL/GdsDriver, added a set of isOnGrid() functions to check
that all coordinates of various objects are on the foundry grid.
Use isOnGrid() in most objects processed in
GdsStream::operator<<(Cell*).
* Bug: In cumulus/plugins.chip.pads.Corner, correctly round the
coordinates of the 45 degree segments so they are still on the
foundry grid.
* New: In cumulus/plugins.core2chip.libresocio.CoreToChip, use new
configuration variable "chip.useAbstractpads" to select between the
abstract version (GPIO, VDD, ...) and the full version (IOPadInOut,
IOPadVdd, ...) layout.
* New: In cumulus/plugins.chip.pads.Corona._createCorewire(), add an
hard-coded limitation for LibreSOCIO I/O pad to corona wires to
always be below the maximal threshold.
* Change: In cumulus/plugins.block.configuration.BlockConf.save(),
cumulus/plugins.block.Block.save(),
cumulus/plugins.chip.Chip.save(),
cumulus/plugins.core2chip.core2chip.CoreToChip.buildChip(),
Add a "flags" parameter to control the way logical views (aka "vst")
are saved. Mainly allowing to pass on the VstUseConcat option in
order for Alliance tools to be able to read them back (lvx, asimut).
* Change: In cumulus/plugins.core2chip.core2chip.CoreToChip.buildChip(),
don't stop at the first I/O pad signal missing on the core, but
display all the missing ones (LKCL proposal).
* In cumulus/block.configuration, the rsave method was buggy. It did stop
it did not save "terminal" master cells (i.e. a cell without instance)
instead of "netlistTerminal" (explicitely flagged for standard cells).
The result was that some "empty netlist" in the complete "ls180"
from LibreSOC went missing. Causing cougar to complain.
* New: In cumulus/plugins.blocks.iospecs.IoSpecs, new class to manage
I/O pads placement. Support for reading the JSON pinmux format
(courtesy of LKCL & StackOverflow).
* Change: In cumulus/plugins.block.bigvia.BigVia, center the VIA cut
matrix. Issue a BIG warning when no one cut could be drawn
(temporarily disabled until I fix the corona).
Integrate new features and bug fixes so the Arlet 6502 benchs successfully
passes real DRC with reference industrial tools. Short summary:
* Manage minimum area for VIAs in Katana::Tracks.
* Allow different wire width for wires perpandicular to the prefered
routing direction.
* StackedVIAs used in the clock tree no longer assume an uniform
routing grid (same offset & pitch all the way up).
* Some hard-coded patches in PowerRails for FlexLib.
* New: In CRL/symbolic/cmos/kite.py & cmos45/kite.py, update the
RoutingLayerGauges by adding the new PWireWidth parameter.
Always zero in case of symbolic layout (too fine tuning).
* New: In CRL::RoutingGauge, add accessor to PWireWidth parameter.
Modify the clone method.
* New: In CRL::RoutingLayerGauge, add new parameter "PWireWidth"
to give the width of a wire when it not drawn in the prefered
routing direction. If it is set to zero, the normal width is
used.
* New: In CRL::PyRoutingGauge, export the updated constructor
interface. It is *not* backward compatible, one must add the
PWireWidth parameter in the various kite.py configuration
files (in etc/).
* Change: In AnabaticEngine::_gutAnabatic(), disable the minimum
area detection mechanism, replaced by a more complete one in
Katana::Track. Left commented out for now, but will be removed
in the future.
* Change: In Anabatic::AutoContact::updateLayer(), now systematically
calls setLayerAndWidth() to potentially resize the VIAs. This is
needed in real mode as VIAs are *not* macro-generated but have
their real final size.
* Change: In Anabatic::AutoContact::setLayerAndWidth(), select the
width and height of the contact using the gauge wire width *and*
perpandicular *wire width*.
* Change: In Anabatic::AutoSegment::_initialize(), the "VIA to same cap"
to PWireWidth/2, this will be the size of the VIA in the
non-preferred direction at the end cap (non-square in real mode).
* Change: In Anabatic::AutoSegment::getExtensionCap(), makes different
cases for symbolic and real. Use raw length in real, add half the
wire width in symbolic.
Add a flag to get the extension cap *only*, not increased of
half the minimal spacing.
* Change: In Anabatic::AutoSegment::bloatStackedStrap(), enhanced,
but finally unused...
* New: In Anabatic::AutoSegment::create(), use the PWireWidth when
the segment is not in the preferred routing direction (and of
minimal width).
* New: In Anabatic::Configuration, add new getPWirewidth(),
DPHorizontalWidth() and DPVerticalWidth() accessors.
* Change: In AnabaticEngine::setupPreRouteds(), skip components in
in "cut" material. We are only interested in objects containing
some metal (happens in real mode when VIAs cuts are really there).
* New: In Katana::PowerRailsPlanes::Rail::doLayout(), add an hard-coded
patch that artificially enlarge the *wide wire* so the spacing for
wide wire is enforced. For now, two pitches on each side for
"FlexLib" gauge.
* New: In Katana::Track, add support to find and correct small wire
chunks so they respect the minimum area rules.
Two helper functions:
* ::hasSameLayerTurn(), to find if a a TrackElement as non-zero length
perpandicular is same layer connected to it.
* ::toFoundryGrid(), to ensure that all coordinates will be on the
foundry grid (may move in a more shared location).
* ::expandToMinArea(), try to expand, *in the routing direction*
the too small wire so it respect the minimal area. Check for the
free space in the track.
Track::minExpandArea() go through all the TrackElements in the track
to look for too small ones and correct them.
* Change: In Katana::RoutingPlane, add an accessor to get the tracks.
* New: In KatanaEngine::finalizeLayout(), add a post-treatment to find
for minimal area violations.
* Change: In cumulus/plugins.block.configuration.GaugeConf, add a
routingBb attribute that will serve as a common reference to all
the functions calculation track positions. We must not have two
different reference for the core and the corona. The reference
is always the corona when we working on a complete chip.
* New: In cumulus/plugins.block.configuration.GaugeConf.getTrack(),
Simplified and more reliable way of getting tracks positions.
Use the routingBb.
* New: In cumulus/plugins.block.configuration.GaugeConf.rpAccess(),
Make use of getTrack() to get every metal strap on the right
X/Y position.
* New: In cumulus/plugins.block.configuration.GaugeConf.expandMinArea(),
As those wires are left alone by the router, it is our responsability
to abide by the minimal area rule here. Hence the code duplication
from the router (bad).
Mainly wires made for the clock tree, I mean.
* Bug: In cumulus/plugins.chip.configuration.ChipConf.setupICore(),
the core instance must be placed on the GCell grid, defined by the
slice height (X *and* Y).
* Bug: In cumulus/plugins.chip.corona.Builder(), forgot to use bigvia
for the corners of the inner ring.
* Bug: In cumulus/plugins.chip.pads.corona._createCoreWire(), hard-coded
patch for LibreSOCIO, the power/ground connectors toward the core
are too wide and can create DRC errors when put side by side.
Shrink them by the minimal distance.
* New: In cumulus/plugins/chip.corona.HorizontalRail & VerticalRail,
use the new BigVia instead of StackVia to generate a matrix of
cut when in real mode. Stick to the one massive VIA when in
symbolic.
* New: In cumulus/plugins/block.bigvia.BigVia to generate matrixes
of cut VIA.
* New: In cumulus/plugins.block.configuration, added class ConstantsConf
to store information and create instances of "zero" and "one" cells.
Added attribute in BlockConf class.
* Change: In cumulus/plugins.block.configuration, moved the cell cloning
and saving from block.spares.Spares to configuration.BlockConf as
it is a service that can be used by other modules than just spares.
Other modules may modificate the netlists also, like in XXXX.
* Change: In cumulus/plugins.chip.configuration, in various methods,
manage both cases when the layer is symbolic or real (difference
in accessing the underlying BasicLayers).
* Change: In cumulus/plugins.chip.configuration, less clutered display
of lambda length in trace mode (and use of 'L' as 'l' was too close
to '1').
* Bug: In cumulus/plugins.chip.corona.VerticalSide.addBlockages(),
as the clock are now on the *inner* rail(s), blockage must be on
the *outer* rails (power lines).
* New: In cumulus/plugins.chip.pads.Corner, add support for 45 degree
corners (cfg setting "chip.use45corners").
* New: In cumulus/plugins.chip.pads.Side.check(), correct computation
of the side's length. Was using the ioPadStep instead of the pad
cell width!
* Change: In cumulus/plugins.chip.pads.Corona._padAnalysis(), LibreSOCIO
pads uses Verticals for their ring wires (common sense would want
them *Horizontal*). So they must be included in the physical pin
detection, but in turn this cause havoc in pxlib... So create a
filtering according to the library name. This is *not* robust
but will do for now.
* New: In cumulus/plugins.chip.pad.core2chip.CoreToChip, rename
self.state into self.conf for clarity.
New method newEnableForNet(), to create "enable" nets on the
fly for emulated In/Out pads.
As it can edit the netlist (new "enable" nets) call the
BlockConf.rsave() method instead of direct saving through
AllianceFramework.
Raise NotImplementederror instead of ErrorMessage.
* New: In cumulus/plugins.chip.pad.core2chip.IoPad.createPad(),
on emulated In/Out I/O pad like for LibreSOC, generate on the fly
the right enable signal.
If an enable signal is given, it will be used (backward
compatible with the previous behavior).
* New: In cumulus/plugins.chip.pad.core2chip, support for real
LibreSOCIO pads in libresocio.py module.
* New: In cumulus/plugins/core2chip/, support for the FlexLib I/O cells
symbolic abstracts ("niolib"). More flexible way of specifying the
number and positions of the various power pads, both I/O power and
core power.
For niolib (FlexLib I/O abstract), support for multiple clocks,
that is, clock become ordinary pad (with signals typed as CLOCK).
* New: In cumulus/plugins/chip/, added support for niolib and final
integration of multiple clocks (only for niolib).
Note: The previous strategy was not fully coherent in chip mode.
Everything added, net and components must be added at
corona level and not separated between corona and core.
* New: In cumulus/plugins/block.configuration, new FeedsConf object
to handle the feeds and provide a filling area helper.
* New: In cumulus/plugins/block.spares.removeUnusedbuffers() to
remove unused buffers in the pools and replace them by feedthrough.
* Change: In cumulus/plugins.block.spares, unify coordinate/slice
computation. If we are in chip mode, the coordinates are
expressed in the corona *but* aligned on the slices of the
*core* model.
* Change: In cumulus/plugins.block.Block.rsave(), add the '_r' suffix
to the routed cells.
* Change: In cumulus/plugins.clocktree.ClockTree, when in chip mode
create everything at corona level. Also forgot to set type of
clock subnet as clock.
* Change: In Cumulus/plugins/block/spares, check that "block.spareSide"
is not below 7*sliceHeight and issue a warning instead of a later
divide by zero...
Note: The port is not complete. Integration of LKCL patches will
follow shortly.
* Change: In cumulus/plugins/alpha/block, more simple inheritance
scheme. Use classic inheritance instead of @classdecorator.
BlockConf (renamed from BlockState) now inherit from GaugeConf,
Double inheritance tree, for Block/Chip and BlockConf/ChipConf.
Allow an uniform syntax for configuration parameters.
* New: In cumulus/plugins/alpha/chip, port of the chip plugin and
integrate with the block plugin. It is now a derived class of
Block. ChipConf is also a derived from BlockConf.
Obsolete "./coriolis2/ioring.py", all informations are given
though the ChipConf state class.
* New: In cumulus/plugins/alpha/core2chip, only Alliance/pxlib is
ported yet.
* New: In CRL/helpers/utils.py, create a Python "class decorator".
Works like a decorator but without the need of implementing
the Concrete/Abstract classes structure Design Pattern.
Create proxies in the derived class for the base class
attributes & methods.
* Change: In cumulus/plugins/alpha/block/configuration.py, enrich
the BlockState object to support core2chip parameters. Make it
even more autonomous from the Block class.
* New: In cumulus/plugins/alpha/core2chip, port of the core2chip plugin
and integration with the alphs/block plugin. At "constant features"
as a first. Only ported "cmos", phlib will be later.
Note: Keep the various hfnsX.py as toolboxes for future experiments.
* New: cumulus/plugins/block/hfns3.py, build the trunk of the
net as a RMST. First with the "Iterative One Steiner Point"
(terribly slow above 100 points) then with FLUTE.
For the global routing trunk, must be very cautious to
check that the cluster "graph point" is the one of the
it's buffer RoutingPad so both end up in the same GCell.
* New: cumulus/plugins/block/timing.py, stub for basic
timing computation and conversion between sink and
capacitance. Currently based on the fake 350nm given as
example in SxLib ("man sxlib"...).
To perform HFNS, recursively makes clusters of closest sinks, less than
30 sinks and with a control of the half-perimeter at all the clusters
levels. Clearly needs lots of improvements but the backbone of the
feature works. Make use of the pool buffers as do the clock tree.
Clustering is done with a degenerated Kruskal algorithm.
This is rougly based on the article:
Buffered Steiner Trees for Difficult Instances
Charles J. Alpert, Member, IEEE
IEEE TCAD, Vol. 21, No. 1, January 2002
0278–0070/02$17.00 (c) 2002 IEEE
* Bug: In cumulus/plugins/alpha/block/clocktree.ClockTree.splitClock(),
forgot to wrap inside an UpdateSession.
* Bug: In cumulus/plugins/alpha/block/clocktree.spares.raddTransNet(),
forgot to set the masterNet for recursive call when the plug already
exists.
* New: Added multiple clock support in H-Tree generation in alpha/block.
* New: In CRL/etc/<NODE>/<TECH>/plugins.py, added three new parameters
for block plugin config:
"block.spareSide" : The size of the minimum side of a buffered area.
(quad-tree leaf).
"spare.buffer" : The model of the cell buffer to be used.
"spare.maxSinks" : max number of sinks on a buffer before issuing
a warning (non-blocking).
* Bug: In Etesian::BloatCell::getAb(), never apply the bloat profile to
fixed cells. In case of buffers from the spare maxtrix it was leading
Coloquinte to detect an overlap of fixed cells, which it do not
support (rightly so).
Jean-Paul Chaput
Luke Kenneth Casson Leighton