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Use wide pads (1 P-Pitch) for METAL3 in the cumulus/Macro block wrapper

This commit is contained in:
Jean-Paul Chaput 2021-03-09 10:58:49 +01:00
parent 1205505cf2
commit 7e6250d460
4 changed files with 39 additions and 22 deletions
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21
cumulus/src/plugins/alpha/block/configuration.py
View File

@ -609,11 +609,11 @@ class IoPadConf ( object ):
def isBidir ( self ): return self.flags & IoPadConf.BIDIR
def __repr__ ( self ):
s = '<IoPadConf {} pad:{} from:{}'.format(self.instanceName,self.padNetName,self.fromCoreNetName)
s = '<IoPadConf {} iopad="{}" from="{}"'.format(self.instanceName,self.padNetName,self.fromCoreNetName)
if self.isBidir():
s += ' to:{} en:{}'.format(self.toCoreNetName,self.enableNetName)
s += ' to="{}" en="{}"'.format(self.toCoreNetName,self.enableNetName)
if self.isTristate():
s += ' en:{}'.format(self.enableNetName)
s += ' en="{}"'.format(self.enableNetName)
s += '>'
return s
@ -892,13 +892,14 @@ class IoPin ( object ):
Create an I/O Pin on a side of a block for one net or a vector of nets.
"""
SOUTH = 0x0001
NORTH = 0x0002
EAST = 0x0004
WEST = 0x0008
A_BEGIN = 0x0010
A_END = 0x0020
A_MASK = A_BEGIN|A_END
SOUTH = 0x0001
NORTH = 0x0002
EAST = 0x0004
WEST = 0x0008
A_BEGIN = 0x0010
A_END = 0x0020
A_MASK = A_BEGIN|A_END
SIDE_MASK = EAST|WEST|NORTH|SOUTH
@staticmethod
def toStr ( value ):

3
cumulus/src/plugins/alpha/block/iospecs.py
View File

@ -103,12 +103,14 @@ class IoSpecs ( object ):
spec = IoPadSpec( instance, side )
self._ioPadsLUT[ instance ] = spec
self._ioPadsSpec.append( spec )
trace( 560, '\tIoSpecs.addIoPadSpec() side={} spec={}\n'.format(side,spec) )
return spec
def loadFromPinmux ( self, fileName ):
"""
Load ioPadsSpec from a LibreSOC generated pinmux file in JSON format.
"""
print( ' o Loading I/O pad specifications from "{}".'.format(fileName) )
if not os.path.isfile(fileName):
raise ErrorMessage( 2, [ 'IoSpecs.loadFromPinmux(): JSON pinmux file not found.'
, '("{}")'.format(fileName) ] )
@ -128,6 +130,7 @@ class IoSpecs ( object ):
end = None
if padDatas[-1] in '+-*': end = -1
self._ioPadsLUT[padName].addNets( padDatas[1:end] )
trace( 560, '-' )
@property
def ioPadsSpec ( self ):

7
cumulus/src/plugins/alpha/core2chip/core2chip.py
View File

@ -209,7 +209,6 @@ class IoNet ( object ):
# Class : "IoPad".
class IoPad ( object ):
"""
Manage I/O pad instanciation. Gather between one and three IoNet.
The number of IoNet implies the kind of I/O pad to be used.
@ -263,6 +262,7 @@ class IoPad ( object ):
respectively to simple input/output pad, tristate output pad and
bidirectional pad. See the class definition.
"""
trace( 550, '\tIoPad.addNet() net={} iopad={}\n'.format(ioNet,self))
self.nets.append( ioNet )
if len(self.nets) == 1:
if self.nets[0].coreNet.getDirection() == Net.Direction.IN: self.direction = IoPad.IN
@ -306,6 +306,11 @@ class IoPad ( object ):
"""
padInfo = self.coreToChip.getPadInfo( self.direction )
if padInfo is None:
if len(self.nets) == 0:
raise ErrorMessage( 1, [ 'IoPad.createPad(): Cannot find net(s) connected(s) to pad "{}".' \
.format( self.padInstanceName )
, '({})'.format( self.ioPadConf ) ] )
raise ErrorMessage( 1, 'IoPad.createPad(): Unsupported direction {} ({}) for pad "{}".' \
.format( self.direction
, IoPad.directionToStr(self.direction)

30
cumulus/src/plugins/alpha/macro/macro.py
View File

@ -53,6 +53,10 @@ class Macro ( object ):
else: pdepth = depth - 1
return rg.getLayerPitch( pdepth )
@staticmethod
def getWireWidth ( rg, metal ):
return rg.getWireWidth( metal )
@staticmethod
def place ( instance, transf, status ):
ab = instance.getMasterCell().getAbutmentBox()
@ -121,6 +125,7 @@ class Macro ( object ):
NetExternalComponents.setInternal( component )
pitch = rg.getPitch( component.getLayer() )
ppitch = Macro.getPPitch( rg, component.getLayer() )
wwidth = Macro.getWireWidth( rg, component.getLayer() )
bb = component.getBoundingBox()
yAxis = bb.getYCenter()
xMax = bb.getXMin()
@ -136,7 +141,7 @@ class Macro ( object ):
horizontal = Horizontal.create( component.getNet()
, component.getLayer()
, yAxis
, pitch
, pitch + wwidth
, xMin
, xMax - (hMargin-1) * ppitch
)
@ -145,6 +150,7 @@ class Macro ( object ):
NetExternalComponents.setInternal( component )
pitch = rg.getPitch( component.getLayer() )
ppitch = Macro.getPPitch( rg, component.getLayer() )
wwidth = Macro.getWireWidth( rg, component.getLayer() )
bb = component.getBoundingBox()
yAxis = bb.getYCenter()
xMin = innerAb.getXMax()
@ -160,20 +166,21 @@ class Macro ( object ):
horizontal = Horizontal.create( component.getNet()
, component.getLayer()
, yAxis
, pitch
, pitch + wwidth
, xMin + (hMargin-1) * ppitch
, xMax
)
NetExternalComponents.setExternal( horizontal )
for component in southPins:
NetExternalComponents.setInternal( component )
pitch = rg.getPitch( component.getLayer() )
ppitch = Macro.getPPitch( rg, component.getLayer() )
bb = component.getBoundingBox()
xAxis = bb.getXCenter()
yMax = bb.getYMin()
yMin = xMax - vMargin*ppitch
width = bb.getWidth()
pitch = rg.getPitch( component.getLayer() )
ppitch = Macro.getPPitch( rg, component.getLayer() )
wwidth = Macro.getWireWidth( rg, component.getLayer() )
bb = component.getBoundingBox()
xAxis = bb.getXCenter()
yMax = bb.getYMin()
yMin = xMax - vMargin*ppitch
width = bb.getWidth()
vertical = Vertical.create( component.getNet()
, component.getLayer()
, xAxis
@ -184,7 +191,7 @@ class Macro ( object ):
vertical = Vertical.create( component.getNet()
, component.getLayer()
, xAxis
, width
, pitch + wwidth
, yMin
, yMax - (vMargin-1) * ppitch
)
@ -193,6 +200,7 @@ class Macro ( object ):
NetExternalComponents.setInternal( component )
pitch = rg.getPitch( component.getLayer() )
ppitch = Macro.getPPitch( rg, component.getLayer() )
wwidth = Macro.getWireWidth( rg, component.getLayer() )
bb = component.getBoundingBox()
xAxis = bb.getXCenter()
yMin = innerAb.getYMax()
@ -208,7 +216,7 @@ class Macro ( object ):
vertical = Vertical.create( component.getNet()
, component.getLayer()
, xAxis
, width
, pitch + wwidth
, yMin + (vMargin-1) * ppitch
, yMax
)