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coriolis
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Modify the chain of "save()" calls in chip/block to pass on flags. 

* Change: In cumulus/plugins.block.configuration.BlockConf.save(),
             cumulus/plugins.block.Block.save(),
             cumulus/plugins.chip.Chip.save(),
             cumulus/plugins.core2chip.core2chip.CoreToChip.buildChip(),
    Add a "flags" parameter to control the way logical views (aka "vst")
    are saved. Mainly allowing to pass on the VstUseConcat option in
    order for Alliance tools to be able to read them back (lvx, asimut).
* Change: In cumulus/plugins.core2chip.core2chip.CoreToChip.buildChip(),
    don't stop at the first I/O pad signal missing on the core, but
    display all the missing ones (LKCL proposal).
This commit is contained in:
Jean-Paul Chaput 2020-12-05 11:59:48 +01:00
parent 1411739c0b
commit 51028980c9
4 changed files with 11 additions and 10 deletions
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4
cumulus/src/plugins/alpha/block/block.py
View File

@ -619,10 +619,10 @@ class Block ( object ):
blockIns = BlockInstance( tailInstance, transf )
self.blockInstances.append( blockIns )
def save ( self ):
def save ( self, flags=0 ):
if not self.conf.validated:
raise ErrorMessage( 1, 'block.save(): Chip is not valid, aborting.' )
self.conf.save()
self.conf.save( flags )
# ----------------------------------------------------------------------------

4
cumulus/src/plugins/alpha/block/configuration.py
View File

@ -1182,7 +1182,7 @@ class BlockConf ( GaugeConf ):
# if not masterCell.isTerminalNetlist():
# self.rsave( masterCell, depth+1 )
def save ( self ):
def save ( self, flags ):
"""
Frontend to BlockConf.rsave(). Append the "_cts" suffix to the cloned
cells, then call rsave().
@ -1193,5 +1193,5 @@ class BlockConf ( GaugeConf ):
cell.setName( cell.getName()+'_cts' )
if self.chip is None:
self.cell.setName( self.cell.getName()+'_r' )
rsave( self.cell )
rsave( self.cell, CRL.Catalog.State.Physical|flags )
return

8
cumulus/src/plugins/alpha/chip/chip.py
View File

@ -145,12 +145,12 @@ class Chip ( Block ):
self.conf.refresh( self.conf.chip )
return self.conf.validated
def save ( self ):
def save ( self, flags=0 ):
if not self.conf.validated:
raise ErrorMessage( 1, 'chip.save(): Chip is not valid, aborting.' )
super(Chip,self).save()
super(Chip,self).save( flags )
self.conf.corona.setName( self.conf.corona.getName()+'_r' )
self.conf.chip .setName( self.conf.chip .getName()+'_r' )
af = CRL.AllianceFramework.get()
af.saveCell( self.conf.corona, CRL.Catalog.State.Views )
af.saveCell( self.conf.chip , CRL.Catalog.State.Views )
af.saveCell( self.conf.corona, CRL.Catalog.State.Views|flags )
af.saveCell( self.conf.chip , CRL.Catalog.State.Views|flags )

5
cumulus/src/plugins/alpha/core2chip/core2chip.py
View File

@ -630,8 +630,9 @@ class CoreToChip ( object ):
if netName is None: continue
coreNet = self.core.getNet( netName )
if not coreNet:
raise ErrorMessage( 1, 'CoreToChip.buildChip(): Pad "{}" refer net "{}" which do not exist in core "{}".' \
.format(ioPadConf.instanceName,netName,self.core.getName()) )
print( ErrorMessage( 1, 'CoreToChip.buildChip(): Pad "{}" refer net "{}" which do not exist in core "{}".' \
.format(ioPadConf.instanceName,netName,self.core.getName()) ))
continue
ioNet = self.getIoNet( coreNet )
if ioPadConf.isBidir() or ioPadConf.isTristate():
if coreNet.getName() == ioPadConf.enableNetName: