cells are replaced with the base cells. Routing to pins
is instead done in the "gpio_connects" cells while
improving on the original routing (fewer cross-overs,
multiple vias per contact, wider buses for the analog
signals). Made small adjustments to many of the openframe
wrapper pins to keep them all on a 10nm grid. Moved the
connections previously from the "wrapped" GPIO cell back
from the openframe project border, so that the border can
be clear of all blockages. Added the DEF file of the
wrapper (previously only in the openframe example repo)
to the def/ directory. Note: The modified LVS scripts
depend on the gate-level netlists of the frame, which
have been committed in a prior pull request. This pull
request does not conflict with those files.
This file indicates which verilog files to include for openframe
simulations. Noted that there were references in the file to
GL versions of user_id_programming.v, chip_io_openframe.v, and
caravel_openframe.v. All three of these are already structural
verilog and do not have versions in the gl/ directory.
function for clock routing to include GPIO[30] and GPIO[31], for
use with the caravan chip, which does not have GPIO in locations
14 and 15. This restores the clock monitoring capability for
caravan. Eventually, the housekeeping_alt module should become
the only housekeeping module, extending the clock monitoring
function for caravel and allowing the same module to be used for
both caravel and caravan.
+ add `mprj_io_buffer` module that is used to guide the router and buffer signals going to the IOs far from the housekeeping
+ add `caravel_core` rtl that includes all the macros of caravel
~ restructure caravel to `caravel_core` and `chip_io` that includes the padframe
~ update `caravel_clocking` rtl to include `porb` input reset signal from power-on-reset
~ update `gpio_control_block` rtl to buffer `serial_clock` and `serial_load` siganls
+ add sky130_ef_sc_hd__decap_12 decaps in the rtl of gpio_signal_buffering
+ add sky130_ef_sc_hd__decap_12 stub file for openlane; there is no
yosys-parseable verilog model for sky130_ef_sc_hd__decap_12
~ change config of gpio_signal_buffering* to add sky130_ef_sc_hd__decap_12
~ regenerate the gl netlist based on the above changes
* Corrected missing part of porb_h route in the caravan chip_io_alt
layout. Correcting the indexing of the "mprj_io_one" connections
to "mgmt_io_oeb" on the left-hand side of caravan, as they were
connecting back to the right side and making a mess of wiring,
instead of being wired locally directly to the nearest I/O.
* Apply automatic changes to Manifest and README.rst
* Corrected the unconnected mgmt_io_in inputs to housekeeping on
the caravan chip (which correspond to the GPIOs that do not exist
in caravan) by connecting them to the "zero" outputs of the
closest GPIO control blocks.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
mo-hosni
M0stafaRady
Jeff DiCorpo
Tim Edwards
M0stafaRady
Passant
Anton Blanchard
D. Mitch Bailey
Kareem Farid