fix a typo in caravel_core RTL

2024-03-17 12:09:49 +02:00 · 2024-03-17 12:09:49 +02:00 · efc0304e1e
parent 0dbdb4df96
commit efc0304e1e
1 changed files with 1 additions and 1 deletions
--- a/verilog/rtl/caravel_core.v
+++ b/verilog/rtl/caravel_core.v
@ -1429,7 +1429,7 @@ module caravel_core (
    );
    /* Section 2 GPIOs (GPIO 32 to 34) */

-    gpio_control_block_mgmt gpio_control_in_2_3 [2:0] (
+    gpio_control_block gpio_control_in_2_3 [2:0] (
 `ifdef USE_POWER_PINS
    .vccd(vccd),
    .vssd(vssd),