diff --git a/verilog/rtl/caravel_core.v b/verilog/rtl/caravel_core.v
index 14944e6d..fc26a906 100644
--- a/verilog/rtl/caravel_core.v
+++ b/verilog/rtl/caravel_core.v
@@ -1429,7 +1429,7 @@ module caravel_core (
     );
     /* Section 2 GPIOs (GPIO 32 to 34) */
 
-    gpio_control_block_mgmt gpio_control_in_2_3 [2:0] (
+    gpio_control_block gpio_control_in_2_3 [2:0] (
 `ifdef USE_POWER_PINS
     .vccd(vccd),
     .vssd(vssd),