3fbc52ecbf
Merge pull request #276 from efabless/caravel_redesign-digital_pll-fanout
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reharden!: digital_pll
2022-10-17 20:50:01 +02:00
2d147966b9
Update housekeeping views and openlane configuration
2022-10-17 11:37:24 -07:00
e5d9788a43
reharden!: digital_pll
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~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys
!need to verify that the oscillator remains untouched
2022-10-17 10:56:01 -07:00
c524106fed
Merge pull request #263 from efabless/caravel_redesign-pdn-again
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update caravel pdn
2022-10-17 16:12:01 +02:00
d416d222b2
sync mag and lef with gds
2022-10-17 06:15:52 -07:00
a8794dff4b
reharden: caravel
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~ reharden with updated pdn
~ add stubs for non functional blocks
2022-10-17 03:59:28 -07:00
394546731f
update caravel pdn
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~ change pr boundary to origin to (0,0)
~ sync lef and mag with gds
2022-10-17 03:51:21 -07:00
69d353f65c
Corrected the verilog and the layout for the caravan version of the
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signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
2022-10-16 21:06:27 -04:00
41775aedfd
Changed the LEF views to restrict the pins to the route endpoints
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using the (accidentally undocumented) "-pinonly" option.
2022-10-16 14:40:50 -04:00
48ae31205c
Another change to the pin endpoint positions to make sure that they
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have at least 0.28um spacing to the next wire. Not sure that this
is going to solve the router errors, though.
2022-10-16 14:15:12 -04:00
c5e7c67d60
Once again. . . Rewrote the RTL verilog so that only signals
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being buffered pass through the buffer macros. Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
2022-10-16 12:49:44 -04:00
589f351dcb
Additional modification to move pins up into an uncongested area
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above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections. Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
2022-10-16 10:52:53 -04:00
43b8f9d4fe
Merge branch 'caravel_redesign' into fix_top_buffers_again
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Updating to the most recent caravel_redesign branch version.
2022-10-16 10:05:36 -04:00
dcc3c56b83
Some additional corrections to the gpio_signal_buffering cells.
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Corrected one instance where a buffer had incorrectly been replaced
with a decap cell. Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side. Corrected a small
DRC error in a route position at the bottom.
2022-10-16 09:50:20 -04:00
6c6fa6b502
Merge pull request #255 from efabless/caravel_power_routing-sync-views
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caravel_power_routing updates
2022-10-16 14:15:19 +02:00
914971d253
+ add pr boundary for caravel_power_routing
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based on feedback from tim in order to generate a lef view
with a zero origin and avoid any hacks
+ add caravel_power_routing lef
+ sync caravel_power_routing gds and mag
2022-10-16 04:41:29 -07:00
22dde425ac
add mgmt_protect views and openlane files
2022-10-16 03:14:55 -07:00
a77a45babe
Adjustments to the top level buffering cells to do various things
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like avoid obstructions in the padframe and power routing, add
decap, and separate coupling wires to reduce capacitance.
2022-10-15 17:35:17 -04:00
5d5d019ea1
Revert "add buff_flash_clkrst"
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This reverts commit 2675487322
2022-10-15 08:47:02 -07:00
3db846b119
Fixes issues with the GPIO signal buffering by applying a bounding
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box to the layout, so that LEF and DEF positions are correct.
2022-10-15 10:31:35 -04:00
2675487322
add buff_flash_clkrst
2022-10-15 06:38:42 -07:00
316f2dbb58
Merge pull request #238 from mo-hosni/update_mgmt_protect
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Update mgmt protect
2022-10-15 11:27:59 +02:00
3361c8787d
Add mgmt_protect views and openlane files
2022-10-15 01:46:22 -07:00
8c0e4f7403
Merge branch 'caravel_redesign' into add_top_level_buffers
2022-10-15 00:28:14 +02:00
65573a64a6
Revised the LEF view of mgmt_protect_hv, since it has changed due
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to the increase of the horizontal m3 buses (pins) to 0.5um.
2022-10-14 17:06:45 -04:00
92e2f5e8a4
Added layout views (.mag, GDS, DEF, and LEF) for the caravan
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variant of the top level GPIO signal buffering (module
gpio_signal_buffering_alt).
2022-10-14 16:06:11 -04:00
0e01725608
add housekeeping views
2022-10-14 09:26:34 -07:00
aadfb57609
reharden: caravel_clocking
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~ align pdn with top level
~ move spefs and sdfs output corners to signoff/*/openlane-signoff
2022-10-14 05:24:49 -07:00
46d44793e2
Added layout for the gpio_signal_buffering module, including GDS,
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LEF, DEF, and magic views.
2022-10-13 21:59:10 -04:00
f7299933ee
Merge pull request #217 from mo-hosni/buff_flash_clkrst
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Buff flash clkrst
2022-10-13 20:53:18 +02:00
14856fea6d
Merge pull request #216 from mo-hosni/housekeeping_final_views
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Housekeeping final views
2022-10-13 20:47:09 +02:00
e72f819020
Merge pull request #210 from mo-hosni/final_views
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mgmt_protect final views
2022-10-13 20:33:57 +02:00
08ac55bed8
Merge pull request #214 from efabless/caravel_clocking-buffering
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Caravel clocking reharden
2022-10-13 20:13:45 +02:00
c922241c3f
reharden: caravel_clocking
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+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
2022-10-13 10:54:04 -07:00
889aa7e308
add buff_flash_clkrst
2022-10-13 10:35:51 -07:00
0389423ea6
add housekeeping
2022-10-13 10:15:05 -07:00
1aaebf5cbb
add mgmt_protect
2022-10-13 10:11:45 -07:00
59743f4832
change buf16 to clkbuf16 and reimplement
2022-10-13 06:54:55 -07:00
0eed96f33f
reharden: digital_pll
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~ reimplement digital_pll using updated RTL
~ changes in config to generate same PDN
~ change deprecated variables
2022-10-13 06:21:08 -07:00
98951388d0
Merge pull request #179 from efabless/chip_io_fix_ports
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Fixes the .mag, LEF, DEF, and GDS views of chip_io and chip_io_alt
2022-10-12 11:37:24 +02:00
76f8d37496
Rehardened housekeeping to fix Antenna violations.
2022-10-11 16:41:50 -07:00
a2feddf714
Corrected the layout views of chip_io and chip_io_alt, which were
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missing some of the labels for the power supplies (they were
accidentally erased during layout re-work).
2022-10-11 11:39:03 -04:00
ee17bcf177
Merge branch 'efabless:caravel_redesign' into caravel_redesign
2022-10-11 01:47:06 -07:00
df05079b6f
update houskeepong powere netlst and fixed some antenna violations
2022-10-11 01:46:23 -07:00
4f1ee965a9
Merge pull request #170 from efabless/update_por_lef
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Updated the LEF of simple_por
2022-10-11 10:40:11 +02:00
344f806980
Merge pull request #166 from efabless/gpio_control_block-sparecell
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gpio_control_block sparecell
2022-10-11 10:39:50 +02:00
67a12304fa
Updated the LEF of simple_por, which was generated without the
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"-hide" option, but was also missing the metals 2 and 3 over the
substrate contact, allowing routes on those layers to short to
the actual layout. The new LEF properly reflects the current
version of the POR layout.
2022-10-10 20:58:07 -04:00
f4218ddde9
reharden!: gpio_control_block
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- reimplement using a sparecell
- reimplement using newest open_pdks
!important using openlane pre odb with some local patches which
most if not all are merged in the current head of openlane however
still takes effort to update the interactive script to be latest
openlane compatible
!important override abstract lef generated by openlane. openlane
generates lef and mag that contain def BLOCKAGE layers that cause
congestions during top level routing
2022-10-10 05:42:29 -07:00
40098f693e
Merge branch 'efabless:caravel_redesign' into caravel_redesign
2022-10-10 05:08:33 -07:00
fa441babea
Merge branch 'efabless:caravel_redesign' into caravel_redesign
2022-10-10 01:24:24 -07:00
Mohamed Shalan
mo-hosni
kareem
Marwan Abbas
Tim Edwards
passant5
Mohamed Hosni