Commit Graph

668 Commits

Author SHA1 Message Date
Tim Edwards 624317bc3f Corrected the missing port designation on porb_h in chip_io.mag
and chip_io_alt.mag.
2021-12-07 12:38:18 -05:00
Tim Edwards 79828c00b3 Revised the LVS run scripts to use $PDK_ROOT instead of a hard-
coded path.
2021-12-07 10:32:22 -05:00
Tim Edwards c3fc004072 Corrected an error in verilog/gl/chip_io_alt.v, which was missing
connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.
2021-12-07 10:06:35 -05:00
Tim Edwards a6d9dbf535 Corrected an inadvertant error in caravel_netlists.v that prevents
gate-level simulations from running.  Corrected caravan_netlists.v,
which did not have the same change made yesterday to caravel_netlists.v
for the DLL.
2021-12-07 09:14:59 -05:00
manarabdelaty db8cc0580b [DATA] Update GDS views for the chip_io/chip_io_alt/mgmt_protect_hv/mgmt_protect to match the mag view 2021-12-07 14:28:29 +02:00
manarabdelaty 45f20e3a24 Fix mgmt_protect_hv gate-level netlist 2021-12-07 13:38:30 +02:00
manarabdelaty bd88221d17 [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
manarabdelaty 966b1f22bb [DATA] Update digital_pll 2021-12-07 13:19:02 +02:00
manarabdelaty c178372fea Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-07 13:01:52 +02:00
manarabdelaty 95b30f6eca Update caravel_timing target 2021-12-07 13:01:40 +02:00
Tim Edwards d4b4b7abb8 Fixed one bad error in clock_div which had been done without my
knowledge and which went undetected since before MPW-one.  Modified
the "pll" and "sysctrl" testbenches so that they run and measure
something useful.  Both exercise the clock monitoring on GPIO
outputs functions.  The PLL test also runs the digital locked
loop (behavioral verilog).  The PLL test overlaps sysctrl, but
"pll" cannot be run on gate level verilog, whereas "sysctrl" can.
2021-12-06 21:37:51 -05:00
Tim Edwards a9bb8bcd0a A handful of changes/corrections: (1) Housekeeping signal "user_clock"
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be).  This is
functionally the same.  Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good).  Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change.  This
was the only change affecting layout.  Also:  Revised the "pll"
testbench.  This is still ongoing work.  Also:  Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre.  Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
2021-12-06 19:38:24 -05:00
Jeff DiCorpo b6e4d5de4d
Updated Makefile
added 'mkdir -p ./verilog/gl' in __gpio_defaults target
2021-12-06 08:39:58 -08:00
jeffdi 7854056b0c Merge remote-tracking branch 'origin/main' into main 2021-12-05 10:12:07 -08:00
jeffdi 619163aec1 fixes for RTL testbenches with mgmt core wrapper 2021-12-05 10:11:10 -08:00
manarabdelaty 00c845525a Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-05 19:50:01 +02:00
manarabdelaty 3fa797bbf8 [DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks 2021-12-05 19:48:02 +02:00
manarabdelaty aa766f9144 [DATA] Update caravel_clocking module 2021-12-05 19:44:28 +02:00
Tim Edwards 3246e64407 Correction to the gen_gpio_defaults.py file, which was accidentally
overwriting the top-level gate-level verilog netlist with the
modified layout file contents.
2021-12-04 12:41:06 -05:00
Tim Edwards 9da6bab4a8 Corrected DRC errors on the non-Manhattan edges of the caravel
and open source logos.  Modified the gpio_defaults_block layout
so that open holes are not created in the metal1 when the vias
are moved by the defaults block configuration script.
2021-12-03 22:21:06 -05:00
Tim Edwards bd6af6dddc Modified all of the Makefiles to better handle the GL netlist simulations,
which is now done through setting an environment variable to point to the
location of the management SoC wrapper.  Added the missing user project
wrappers to the GL directory (copied from the original caravel repository),
and also the GL version of chip_io_alt.  Modified the caravan_netlists and
caravel_netlists files to import the correct list of gate level netlists,
which has been reduced by moving "include" statements for components of the
management SoC into the management SoC repository (e.g., caravel_pico).
2021-12-03 17:13:53 -05:00
Tim Edwards b23ec956f3 Corrected the mprj_bitbang testbench verilog (it had not been corrected for
the change in the implementation of the serial loader, which split the load
signal out as a separate bit, and therefore had a separate bit-bang entry).
2021-12-03 15:06:15 -05:00
Tim Edwards 2691903104 Reworked part of the layouts of both caravel and caravan to move
the clocking subcircuit from inside the pad area near the "clock"
pin to under the DLL.  This prevents the DLL from having its
outputs travel all the way across the chip to reach the clocking
cell and then have the multiplexed clock travel all the way back,
especially as the DLL outputs are high-speed signals (up to 150
MHz).
2021-12-02 20:45:39 -05:00
Tim Edwards 024801ab56 Extended the gen_gpio_defaults.py script to handle modifying the
verilog gate-level netlists to match the correct GPIO default
value assignments, and modify the top level gate-level caravel.v
and caravan.v netlists to match.
2021-12-02 16:04:51 -05:00
manarabdelaty ef1019b62a [DATA] Update caravel_clocking 2021-12-02 22:50:20 +02:00
Tim Edwards 07db7f0599 Merge branch 'main' of github.com:efabless/caravel_openframe into main
Pull before push.
2021-12-02 14:28:00 -05:00
Tim Edwards 4cf7aa2983 Changed the synchronized reset to occur on the clock falling edge
to give more timing margin when reset is released (note to self:
shouldn't the ext_reset also be synchronized?).
2021-12-02 14:26:59 -05:00
manarabdelaty 85ad4b0e0f Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-02 21:20:59 +02:00
manarabdelaty c09e510017 Add target for top level sta 2021-12-02 21:20:40 +02:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
jeffdi 78278f30d4 update make truck tcl 2021-12-02 09:28:08 -08:00
jeffdi a8730cb8ef update commit id for open_pdks 2021-12-02 08:40:05 -08:00
Tim Edwards 6482c1e011 Corrected the set_user_id.py script to (1) reverse the position of
characters in the user_id_textblock layout, which was backwards,
and (2) add a path reference to "hexdigits" for each new character
layout encountered in the file, so that the text block layouts
are found even if "addpath hexdigits" has not been specified.
There were some other corrections to handling gzipped files that
probably does not apply in practice, where "make uncompress" has
been run prior to the set_user_id.py script.
2021-12-02 09:35:13 -05:00
jeffdi 5896df50a8 add files for seal ring 2021-12-01 22:35:39 -08:00
jeffdi cecf6acd85 correcting magicrc file and pdkpath issues 2021-12-01 22:00:31 -08:00
jeffdi 73343aed18 correcting magicrc file and pdkpath issues 2021-12-01 21:59:03 -08:00
jeffdi aa64579d63 fix pdkpath in generate_fill.py and compositor.py 2021-12-01 21:45:48 -08:00
jeffdi 2a5589379c fix rcfile reference in generate_fill.py and compositor.py 2021-12-01 21:13:41 -08:00
jeffdi b7a4cc1d7d Merge remote-tracking branch 'origin/main' into main 2021-12-01 21:06:09 -08:00
jeffdi 547709b619 fix rcfile reference in generate_fill.py and compositor.py 2021-12-01 21:05:46 -08:00
Jeff DiCorpo de041996a6 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-01 17:27:24 -08:00
Jeff DiCorpo a2d5967b67 updating caravel.gds to final with mgmt core wrapper 2021-12-01 17:15:02 -08:00
jeffdi 2b43163b19 Merge remote-tracking branch 'origin/main' into main 2021-12-01 11:04:10 -08:00
jeffdi 0a09f3b5ac added missing scripts 2021-12-01 11:03:45 -08:00
manarabdelaty 83863fe16e Add timing log for caravel 2021-12-01 19:28:33 +02:00
Tim Edwards 0f90c813ed Added a missing route that was not completed in the previous layout
update.  Also changed the defaults block types in the layout so that
they match the gate-level netlist.  This does not change the behavior
after assembly but lets LVS run correctly on the layout prior to final
assembly.
2021-11-30 14:38:25 -05:00
Tim Edwards e0a318d2bf Fixed the GL verilog for caravel and caravan to add the two changes
just made to the RTL verilog and layout, to separate out hk_cyc_o
and to hook up the housekeeping user_clock input.
2021-11-30 12:31:07 -05:00
Tim Edwards 1035e8b469 Updated caravel and caravan layouts to reflect the simple change
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core.  Also:  Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
2021-11-30 10:05:43 -05:00
manarabdelaty c4efcec989 [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
Tim Edwards 4c0a2303b1 Modified the GL netlists to match the layout for the GPIO defaults
blocks;  that is, there are special versions of the block for the
first 6 GPIO pins.  That should allow the GL netlists to simulate,
although the end goal is to have the gen_gpio_defaults.py script
modify the GL netlists to exactly match the configuration, as is
done for the .mag layouts.
2021-11-29 20:17:11 -05:00