riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'main' of https://github.com/efabless/caravel_openframe into main

This commit is contained in:
manarabdelaty 2021-12-07 13:01:52 +02:00
parent 95b30f6eca d4b4b7abb8
commit c178372fea
17 changed files with 959 additions and 1034 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Makefile
View File

@ -796,6 +796,7 @@ endif
__gpio_defaults:
mkdir -p ./signoff/build
mkdir -p ./verilog/gl
python3 $(CARAVEL_ROOT)/scripts/gen_gpio_defaults.py $(shell pwd) 2>&1 | tee ./signoff/build/gpio_defaults.out
.PHONY: update_caravel

612
mag/caravan.mag
View File

File diff suppressed because it is too large Load Diff

771
mag/caravel.mag
View File

File diff suppressed because it is too large Load Diff

127
verilog/dv/caravel/mgmt_soc/pll/pll.c
View File

@ -21,12 +21,9 @@
/*
* PLL Test (self-switching)
* - Enables SPI master
* - Uses SPI master to internally access the housekeeping SPI
* - Switches PLL bypass
* - Changes PLL divider
* - Switches PLL bypass in housekeeping
* - Changes PLL divider in housekeeping
*
* Tesbench mostly copied from sysctrl
*/
void main()
{
@ -54,67 +51,89 @@ void main()
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Monitor pins must be set to output */
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
// Start test
/*
*-------------------------------------------------------------
* Register 2610_000c reg_hkspi_pll_ena
* SPI address 0x08 = PLL enables
* bit 0 = PLL enable, bit 1 = DCO enable
*
* Register 2610_0010 reg_hkspi_pll_bypass
* SPI address 0x09 = PLL bypass
* bit 0 = PLL bypass
*
* Register 2610_0020 reg_hkspi_pll_source
* SPI address 0x11 = PLL source
* bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
*
* Register 2610_0024 reg_hkspi_pll_divider
* SPI address 0x12 = PLL divider
* bits 0-4 = feedback divider
*
* Register 2620_0004 reg_clk_out_dest
* SPI address 0x1b = Output redirect
* bit 0 = trap to mprj_io[13]
* bit 1 = clk to mprj_io[14]
* bit 2 = clk2 to mprj_io[15]
*-------------------------------------------------------------
*/
// Monitor the core clock and user clock on mprj_io[14] and mprj_io[15]
// reg_clk_out_dest = 0x6 to turn on, 0x0 to turn off
// Write checkpoint for clock counting (PLL bypassed)
reg_mprj_datal = 0xA0400000;
// Enable SPI master
// SPI master configuration bits:
// bits 7-0: Clock prescaler value (default 2)
// bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
// bit 9: CSB sense (0 = inverted, 1 = noninverted)
// bit 10: SCK sense (0 = noninverted, 1 = inverted)
// bit 11: mode (0 = read/write opposite edges, 1 = same edges)
// bit 12: stream (1 = CSB ends transmission)
// bit 13: enable (1 = enabled)
// bit 14: IRQ enable (1 = enabled)
// bit 15: Connect to housekeeping SPI (1 = connected)
reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
// Apply stream read (0x40 + 0x03) and read back one byte
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x08; // Write 0x18 (start address)
reg_spimaster_data = 0x01; // Write 0x01 to PLL enable, no DCO mode
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x11; // Write 0x11 (start address)
reg_spimaster_data = 0x03; // Write 0x03 to PLL output divider
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x09; // Write 0x09 (start address)
reg_spimaster_data = 0x00; // Write 0x00 to clock from PLL (no bypass)
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
// Write checkpoint
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_mprj_datal = 0xA0410000;
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x12; // Write 0x12 (start address)
reg_spimaster_data = 0x03; // Write 0x03 to feedback divider (was 0x04)
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
// Set PLL enable, no DCO mode
reg_hkspi_pll_ena = 0x1;
// Set PLL output divider to 0x03
reg_hkspi_pll_source = 0x3;
// Write checkpoint for clock counting (PLL bypassed)
reg_mprj_datal = 0xA0420000;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_mprj_datal = 0xA0430000;
// Disable PLL bypass
reg_hkspi_pll_bypass = 0x0;
// Write checkpoint for clock counting
reg_mprj_datal = 0xA0440000;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_mprj_datal = 0xA0450000;
// Write 0x03 to feedback divider (was 0x04)
reg_hkspi_pll_divider = 0x3;
// Write checkpoint
reg_mprj_datal = 0xA0420000;
reg_mprj_datal = 0xA0460000;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_mprj_datal = 0xA0470000;
reg_spimaster_config = 0xb002; // Apply stream mode
reg_spimaster_data = 0x80; // Write 0x80 (write mode)
reg_spimaster_data = 0x11; // Write 0x11 (start address)
reg_spimaster_data = 0x04; // Write 0x04 to PLL output divider
reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
// Write 0x04 to PLL output divider
reg_hkspi_pll_source = 0x4;
reg_spimaster_config = 0x2102; // Release housekeeping SPI
// Write checkpoint
reg_mprj_datal = 0xA0480000;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_mprj_datal = 0xA0490000;
// End test
reg_mprj_datal = 0xA0900000;

81
verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
View File

@ -37,6 +37,9 @@ module pll_tb;
wire flash_io1;
wire SDO;
integer ccount;
integer ucount;
assign checkbits = mprj_io[31:16];
assign spivalue = mprj_io[15:8];
@ -46,6 +49,16 @@ module pll_tb;
always #10 clock <= (clock === 1'b0);
// User clock monitoring
always @(posedge mprj_io[15]) begin
ucount = ucount + 1;
end
// Core clock monitoring
always @(posedge mprj_io[14]) begin
ccount = ccount + 1;
end
initial begin
clock = 0;
end
@ -66,26 +79,64 @@ module pll_tb;
// Monitor
initial begin
wait(checkbits == 16'hA040);
$display("Monitor: Test PLL (RTL) Started");
$display("Monitor: Test 1 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA041);
// $display(" SPI value = 0x%x (should be 0x04)", spivalue);
// if(spivalue !== 32'h04) begin
// $display("Monitor: Test PLL (RTL) Failed");
// $finish;
// end
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 129 || ccount != 129) begin
$display("Monitor: Test PLL Failed");
$finish;
end
wait(checkbits == 16'hA042);
// $display(" SPI value = 0x%x (should be 0x56)", spivalue);
// if(spivalue !== 32'h56) begin
// $display("Monitor: Test PLL (RTL) Failed");
// $finish;
// end
$display("Monitor: Test 2 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA043);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 193 || ccount != 193) begin
$display("Monitor: Test PLL Failed");
$finish;
end
wait(checkbits == 16'hA044);
$display("Monitor: Test 3 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA045);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 385 || ccount != 129) begin
$display("Monitor: Test PLL Failed");
$finish;
end
wait(checkbits == 16'hA046);
$display("Monitor: Test 4 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA047);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 385 || ccount != 129) begin
$display("Monitor: Test PLL Failed");
$finish;
end
wait(checkbits == 16'hA048);
$display("Monitor: Test 5 PLL (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA049);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 513 || ccount != 129) begin
$display("Monitor: Test PLL Failed");
$finish;
end
wait(checkbits == 16'hA090);
$display("Monitor: Test PLL (RTL) Passed");
$finish;
$display("Monitor: Test PLL (RTL) Passed");
$finish;
end
initial begin

111
verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
View File

@ -20,39 +20,23 @@
// --------------------------------------------------------
/*
* System Control Test
* - Enables SPI master
* - Uses SPI master to internally access the housekeeping SPI
* - Reads default value of SPI-Controlled registers
* - Flags failure/success using mprj_io
* System control test
* - Sets GPIO to monitor the core and user clocks
*
* This test is basically just the first part of the
* PLL test, with the PLL bypassed. Unlike the PLL
* test, it can be run on a gate-level netlist.
*
*/
void main()
{
int i;
uint32_t value;
// Force housekeeping SPI into a disabled state so that the CSB
// pin can be used as an output without the system failing
reg_hkspi_disable = 1;
reg_mprj_datal = 0;
// Configure upper 6 bits of user GPIO for generating testbench
// Configure upper 16 bits of user GPIO for generating testbench
// checkpoints.
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
// Configure all lower 32 bits for writing the SPI value read on GPIO
// NOTE: Converting reg_mprj_io_3 (CSB) to output will disable the
// SPI. But that should not disable the back-door access to the SPI
// register values!
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
@ -70,71 +54,48 @@ void main()
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Monitor pins must be set to output */
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
// Start test
reg_mprj_datah = 0x04;
// Read manufacturer and product ID
value = reg_hkspi_chip_id;
reg_mprj_datal = value; // Mfgr + product ID
reg_mprj_datah = 0x05;
/*
*-------------------------------------------------------------
* Register 2620_0004 reg_clk_out_dest
* SPI address 0x1b = Output redirect
* bit 0 = trap to mprj_io[13]
* bit 1 = clk to mprj_io[14]
* bit 2 = clk2 to mprj_io[15]
*-------------------------------------------------------------
*/
// Read user ID
value = reg_hkspi_user_id;
reg_mprj_datal = value; // User ID
reg_mprj_datah = 0x06;
// Monitor the core clock and user clock on mprj_io[14] and mprj_io[15]
// reg_clk_out_dest = 0x6 to turn on, 0x0 to turn off
// Read PLL enables
value = reg_hkspi_pll_ena;
reg_mprj_datal = value; // DLL enables
reg_mprj_datah = 0x07;
// Write checkpoint for making sure nothing is counted when monitoring is off
reg_mprj_datal = 0xA0400000;
reg_clk_out_dest = 0x0;
reg_clk_out_dest = 0x0;
reg_mprj_datal = 0xA0410000;
// Read PLL bypass state
value = reg_hkspi_pll_bypass;
reg_mprj_datal = value; // DLL bypass state
reg_mprj_datah = 0x08;
// Write checkpoint for core clock counting (PLL bypassed)
reg_mprj_datal = 0xA0420000;
reg_clk_out_dest = 0x2;
reg_clk_out_dest = 0x0;
reg_mprj_datal = 0xA0430000;
// Read PLL trim
value = reg_hkspi_pll_trim;
reg_mprj_datal = value; // DLL trim
reg_mprj_datah = 0x09;
// Read PLL source
value = reg_hkspi_pll_source;
reg_mprj_datal = value; // DLL source
reg_mprj_datah = 0x0a;
// Read PLL divider
value = reg_hkspi_pll_divider;
reg_mprj_datal = value; // DLL divider
reg_mprj_datah = 0x0b;
// Read a GPIO configuration word
value = reg_mprj_io_6;
reg_mprj_datal = value; // DLL divider
reg_mprj_datah = 0x0c;
// Write checkpoint for user clock counting (PLL bypassed)
reg_mprj_datal = 0xA0440000;
reg_clk_out_dest = 0x4;
reg_clk_out_dest = 0x0;
reg_mprj_datal = 0xA0450000;
// End test
reg_mprj_datah = 0x0d;
reg_mprj_datal = 0xA0900000;
}

124
verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
View File

@ -23,13 +23,13 @@
module sysctrl_tb;
reg clock;
reg power1;
reg power2;
reg RSTB;
reg csb_set;
reg power1, power2;
wire gpio;
wire [5:0] checkbits;
wire [31:0] spivalue;
wire [15:0] checkbits;
wire [7:0] spivalue;
wire [37:0] mprj_io;
wire flash_csb;
wire flash_clk;
@ -37,11 +37,11 @@ module sysctrl_tb;
wire flash_io1;
wire SDO;
assign checkbits = mprj_io[37:32];
assign spivalue = mprj_io[31:0];
integer ccount;
integer ucount;
// mrpj_io[3] = CSB needs to be set until the program disables the SPI.
assign mprj_io[3] = (csb_set) ? 1'b1 : 1'bz;
assign checkbits = mprj_io[31:16];
assign spivalue = mprj_io[15:8];
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@ -49,6 +49,16 @@ module sysctrl_tb;
always #10 clock <= (clock === 1'b0);
// User clock monitoring
always @(posedge mprj_io[15]) begin
ucount = ucount + 1;
end
// Core clock monitoring
always @(posedge mprj_io[14]) begin
ccount = ccount + 1;
end
initial begin
clock = 0;
end
@ -61,80 +71,50 @@ module sysctrl_tb;
$display("+1000 cycles");
end
$display("%c[1;31m",27);
`ifdef GL
$display ("Monitor: Timeout, Test Sysctrl (GL) Failed");
`else
$display ("Monitor: Timeout, Test Sysctrl (RTL) Failed");
`endif
$display("%c[0m",27);
$display ("Monitor: Timeout, Test Sysctrl (RTL) Failed");
$display("%c[0m",27);
$finish;
end
// Monitor
initial begin
wait(checkbits == 6'h04);
`ifdef GL
$display("Monitor: Test Sysctrl (GL) Started");
`else
$display("Monitor: Test Sysctrl (RTL) Started");
`endif
wait(checkbits == 6'h05);
$display(" Chip ID value = 0x%x (should be 0x00045611)", spivalue);
if(spivalue !== 32'h00045611) begin
wait(checkbits == 16'hA040);
$display("Monitor: Test 1 Sysctrl (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA041);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 0 || ccount != 0) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 6'h06);
$display(" User ID value = 0x%x (should be 0x00000000)", spivalue);
if(spivalue !== 32'h00000000) begin
wait(checkbits == 16'hA042);
$display("Monitor: Test 1 Sysctrl (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA043);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 129 || ccount != 0) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 6'h07);
$display(" PLL enables value = 0x%x (should be 0x00000002)", spivalue);
if(spivalue !== 32'h00000002) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 6'h08);
$display(" PLL bypass value = 0x%x (should be 0x00000001)", spivalue);
if(spivalue !== 32'h00000001) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 6'h09);
$display(" PLL trim value = 0x%x (should be 0x03ffefff)", spivalue);
if(spivalue !== 32'h03ffefff) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 6'h0a);
$display(" PLL divider value = 0x%x (should be 0x00000012)", spivalue);
if(spivalue !== 32'h00000012) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 6'h0b);
$display(" PLL source value = 0x%x (should be 0x00000004)", spivalue);
if(spivalue !== 32'h00000004) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 6'h0c);
$display(" GPIO config value = 0x%x (should be 0x00001809)", spivalue);
if(spivalue !== 32'h00001809) begin
wait(checkbits == 16'hA044);
$display("Monitor: Test 2 Sysctrl (RTL) Started");
ucount = 0;
ccount = 0;
wait(checkbits == 16'hA045);
$display("Monitor: ucount = %d ccount = %d", ucount, ccount);
if (ucount !== 0 || ccount != 129) begin
$display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA090);
wait(checkbits == 6'h0d);
`ifdef GL
$display("Monitor: Test Sysctrl (GL) Passed");
`else
$display("Monitor: Test Sysctrl (RTL) Passed");
`endif
$finish;
$display("Monitor: Test Sysctrl (RTL) Passed");
$finish;
end
initial begin
@ -144,16 +124,13 @@ module sysctrl_tb;
#2000;
end
initial begin // Power-up sequence
initial begin
power1 <= 1'b0;
power2 <= 1'b0;
csb_set <= 1'b1;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
#200000;
csb_set <= 1'b0; // Release CSB after SPI is disabled
end
always @(checkbits) begin
@ -168,21 +145,18 @@ module sysctrl_tb;
assign VDD1V8 = power2;
assign VSS = 1'b0;
assign mprj_io[3] = 1'b1; // Force CSB high.
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),

2
verilog/gl/caravan.v
View File

@ -3841,7 +3841,7 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
.sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }),
.trap(trap),
.uart_enabled(uart_enabled),
.user_clock(mprj_clock2),
.user_clock(caravel_clk2),
.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),

2
verilog/gl/caravel.v
View File

@ -4579,7 +4579,7 @@ module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
.sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }),
.trap(trap),
.uart_enabled(uart_enabled),
.user_clock(mprj_clock2),
.user_clock(caravel_clk2),
.usr1_vcc_pwrgood(mprj_vcc_pwrgood),
.usr1_vdd_pwrgood(mprj_vdd_pwrgood),
.usr2_vcc_pwrgood(mprj2_vcc_pwrgood),

2
verilog/rtl/caravan.v
View File

@ -767,7 +767,7 @@ module caravan (
.trap(trap),
.user_clock(mprj_clock2),
.user_clock(caravel_clk2),
.mask_rev_in(mask_rev),

6
verilog/rtl/caravel.v
View File

@ -1,4 +1,6 @@
// `default_nettype none
`ifdef SIM
`default_nettype wire
`endif
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
@ -710,7 +712,7 @@ module caravel (
.trap(trap),
.user_clock(mprj_clock2),
.user_clock(caravel_clk2),
.mask_rev_in(mask_rev),

4
verilog/rtl/caravel_netlists.v
View File

@ -48,6 +48,8 @@
`ifdef GL
`include "gl/digital_pll.v"
`include "gl/digital_pll_controller.v"
`include "gl/ring_osc2x13.v"
`include "gl/caravel_clocking.v"
`include "gl/user_id_programming.v"
`include "gl/chip_io.v"
@ -67,6 +69,8 @@
`include "gl/caravel.v"
`else
`include "digital_pll.v"
`include "digital_pll_controller.v"
`include "ring_osc2x13.v"
`include "caravel_clocking.v"
`include "user_id_programming.v"
`include "clock_div.v"

121
verilog/rtl/chip_io.v
View File

@ -126,74 +126,58 @@ module chip_io(
sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDIO(vddio)
`else
,.VDDIO_PAD(vddio_pad)
`ifndef TOP_ROUTING
.VDDIO_PAD(vddio_pad)
`endif
);
// lies in user area 2
sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDIO(vddio)
`else
,.VDDIO_PAD(vddio_pad2)
`ifndef TOP_ROUTING
.VDDIO_PAD(vddio_pad2)
`endif
);
sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDA(vdda)
`else
,.VDDA_PAD(vdda_pad)
`ifndef TOP_ROUTING
.VDDA_PAD(vdda_pad)
`endif
);
sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD(vccd)
`else
,.VCCD_PAD(vccd_pad)
`ifndef TOP_ROUTING
.VCCD_PAD(vccd_pad)
`endif
);
sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSIO(vssio)
`else
,.VSSIO_PAD(vssio_pad)
`ifndef TOP_ROUTING
.VSSIO_PAD(vssio_pad)
`endif
);
sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSIO(vssio)
`else
,.VSSIO_PAD(vssio_pad2)
`ifndef TOP_ROUTING
.VSSIO_PAD(vssio_pad2)
`endif
);
sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSA(vssa)
`else
,.VSSA_PAD(vssa_pad)
`ifndef TOP_ROUTING
.VSSA_PAD(vssa_pad)
`endif
);
sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
`MGMT_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSD(vssd)
`else
,.VSSD_PAD(vssd_pad)
`ifndef TOP_ROUTING
.VSSD_PAD(vssd_pad)
`endif
);
@ -202,58 +186,48 @@ module chip_io(
sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDA(vdda1)
`else
,.VDDA_PAD(vdda1_pad)
`ifndef TOP_ROUTING
.VDDA_PAD(vdda1_pad)
`endif
);
sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDA(vdda1)
`else
,.VDDA_PAD(vdda1_pad2)
`ifndef TOP_ROUTING
.VDDA_PAD(vdda1_pad2)
`endif
);
sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD1(vccd1),
.VSSD1(vssd1)
`else
,.VCCD_PAD(vccd1_pad)
.VSSD1(vssd1),
`ifndef TOP_ROUTING
.VCCD_PAD(vccd1_pad)
`endif
);
sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSA(vssa1)
`else
,.VSSA_PAD(vssa1_pad)
`ifndef TOP_ROUTING
.VSSA_PAD(vssa1_pad)
`endif
);
sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSA(vssa1)
`else
,.VSSA_PAD(vssa1_pad2)
`ifndef TOP_ROUTING
.VSSA_PAD(vssa1_pad2)
`endif
);
sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
`USER1_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD1(vccd1),
.VSSD1(vssd1)
`else
,.VSSD_PAD(vssd1_pad)
.VSSD1(vssd1),
`ifndef TOP_ROUTING
.VSSD_PAD(vssd1_pad)
`endif
);
@ -262,39 +236,33 @@ module chip_io(
sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VDDA(vdda2)
`else
,.VDDA_PAD(vdda2_pad)
`ifndef TOP_ROUTING
.VDDA_PAD(vdda2_pad)
`endif
);
sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD1(vccd2),
.VSSD1(vssd2)
`else
,.VCCD_PAD(vccd2_pad)
.VSSD1(vssd2),
`ifndef TOP_ROUTING
.VCCD_PAD(vccd2_pad)
`endif
);
sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VSSA(vssa2)
`else
,.VSSA_PAD(vssa2_pad)
`ifndef TOP_ROUTING
.VSSA_PAD(vssa2_pad)
`endif
);
sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
`USER2_ABUTMENT_PINS
`ifdef TOP_ROUTING
.VCCD1(vccd2),
.VSSD1(vssd2)
`else
,.VSSD_PAD(vssd2_pad)
.VSSD1(vssd2),
`ifndef TOP_ROUTING
.VSSD_PAD(vssd2_pad)
`endif
);
@ -328,7 +296,7 @@ module chip_io(
sky130_fd_io__top_xres4v2 resetb_pad (
`MGMT_ABUTMENT_PINS
`ifndef TOP_ROUTING
,.PAD(resetb),
.PAD(resetb),
`endif
.TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
.TIE_HI_ESD(),
@ -361,10 +329,7 @@ module chip_io(
.VDDA(vdda),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()
`endif
);
sky130_ef_io__corner_pad user1_corner (
`ifndef TOP_ROUTING
@ -380,8 +345,6 @@ module chip_io(
.VDDA(vdda1),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()
`endif
);
sky130_ef_io__corner_pad user2_corner (
@ -398,8 +361,6 @@ module chip_io(
.VDDA(vdda2),
.VCCD(vccd),
.VCCHIB(vccd)
`else
.VCCHIB()
`endif
);

9
verilog/rtl/clock_div.v
View File

@ -102,9 +102,10 @@ module odd #(
end
reg [SIZE-1:0] initial_begin; // this is used to offset the negative edge counter
// wire [SIZE:0] interm_3; // from the positive edge counter in order to
// assign interm_3 = {1'b0,N} + 2'b11; // guarante 50% duty cycle.
localparam [SIZE:0] interm_3 = {1'b0,`CLK_DIV} + 2'b11;
wire [SIZE:0] interm_3; // from the positive edge counter in order to
assign interm_3 = {1'b0, N} + 2'b11; // guarantee 50% duty cycle.
localparam [SIZE:0] interm_init = {1'b0,`CLK_DIV} + 2'b11;
// Counter driven by negative edge of clock.
@ -112,7 +113,7 @@ module odd #(
if (resetb == 1'b0) begin
// reset the counter at system reset
counter2 <= `CLK_DIV;
initial_begin <= interm_3[SIZE:1];
initial_begin <= interm_init[SIZE:1];
out_counter2 <= 1;
end else if (rst_pulse) begin
// reset the counter at change of N.

2
verilog/rtl/digital_pll.v
View File

@ -17,8 +17,10 @@
// Digital PLL (ring oscillator + controller)
// Technically this is a frequency locked loop, not a phase locked loop.
`ifndef SIM
`include "digital_pll_controller.v"
`include "ring_osc2x13.v"
`endif
module digital_pll(
`ifdef USE_POWER_PINS

4
verilog/rtl/mprj_io.v
View File

@ -71,7 +71,7 @@ module mprj_io #(
sky130_ef_io__gpiov2_pad_wrapped area1_io_pad [AREA1PADS - 1:0] (
`USER1_ABUTMENT_PINS
`ifndef TOP_ROUTING
,.PAD(io[AREA1PADS - 1:0]),
.PAD(io[AREA1PADS - 1:0]),
`endif
.OUT(io_out[AREA1PADS - 1:0]),
.OE_N(oeb[AREA1PADS - 1:0]),
@ -102,7 +102,7 @@ module mprj_io #(
sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [TOTAL_PADS - AREA1PADS - 1:0] (
`USER2_ABUTMENT_PINS
`ifndef TOP_ROUTING
,.PAD(io[TOTAL_PADS - 1:AREA1PADS]),
.PAD(io[TOTAL_PADS - 1:AREA1PADS]),
`endif
.OUT(io_out[TOTAL_PADS - 1:AREA1PADS]),
.OE_N(oeb[TOTAL_PADS - 1:AREA1PADS]),

14
verilog/rtl/pads.v
View File

@ -27,7 +27,7 @@
.VCCD(vccd),\
.VSSIO(vssio),\
.VSSD(vssd),\
.VSSIO_Q(vssio_q)
.VSSIO_Q(vssio_q),
`define USER2_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
@ -41,7 +41,7 @@
.VCCD(vccd),\
.VSSIO(vssio),\
.VSSD(vssd),\
.VSSIO_Q(vssio_q)
.VSSIO_Q(vssio_q),
`define MGMT_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
@ -55,7 +55,7 @@
.VCCD(vccd),\
.VSSIO(vssio),\
.VSSD(vssd),\
.VSSIO_Q(vssio_q)
.VSSIO_Q(vssio_q),
`else
`define USER1_ABUTMENT_PINS
`define USER2_ABUTMENT_PINS
@ -78,7 +78,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
,.PAD(X), \
.PAD(X), \
`endif \
.OUT(vssd), \
.OE_N(vccd), \
@ -110,7 +110,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
,.PAD(X), \
.PAD(X), \
`endif \
.OUT(Y), \
.OE_N(OUT_EN_N), \
@ -142,7 +142,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
,.PAD(X), \
.PAD(X), \
`endif \
.OUT(Y), \
.OE_N(OUT_EN_N), \
@ -174,7 +174,7 @@
sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
`MGMT_ABUTMENT_PINS \
`ifndef TOP_ROUTING \
,.PAD(X), \
.PAD(X), \
`endif \
.OUT(Y_OUT), \
.OE_N(OUT_EN_N), \