diff --git a/Makefile b/Makefile index 84aa6e19..a1841d61 100644 --- a/Makefile +++ b/Makefile @@ -796,6 +796,7 @@ endif __gpio_defaults: mkdir -p ./signoff/build + mkdir -p ./verilog/gl python3 $(CARAVEL_ROOT)/scripts/gen_gpio_defaults.py $(shell pwd) 2>&1 | tee ./signoff/build/gpio_defaults.out .PHONY: update_caravel diff --git a/mag/caravan.mag b/mag/caravan.mag index 14d72c4f..8619bcc6 100644 --- a/mag/caravan.mag +++ b/mag/caravan.mag @@ -1,7 +1,9 @@ magic tech sky130A magscale 1 2 -timestamp 1638495418 +timestamp 1638836243 +<< checkpaint >> +rect -1260 -1260 718860 1038860 << isosubstrate >> rect 707553 886338 709093 889314 rect 8741 806938 10281 809914 @@ -8698,13 +8700,6 @@ rect 20772 245840 30104 245868 rect 20772 245828 20778 245840 rect 30098 245828 30104 245840 rect 30156 245828 30162 245880 -rect 52178 245760 52184 245812 -rect 52236 245800 52242 245812 -rect 184934 245800 184940 245812 -rect 52236 245772 184940 245800 -rect 52236 245760 52242 245772 -rect 184934 245760 184940 245772 -rect 184992 245760 184998 245812 rect 41506 245692 41512 245744 rect 41564 245732 41570 245744 rect 56686 245732 56692 245744 @@ -13983,6 +13978,7 @@ rect 346360 219320 416228 219348 rect 346360 219308 346366 219320 rect 416222 219308 416228 219320 rect 416280 219308 416286 219360 +rect 597138 219294 597144 219306 rect 343450 219240 343456 219292 rect 343508 219280 343514 219292 rect 409506 219280 409512 219292 @@ -13990,6 +13986,19 @@ rect 343508 219252 409512 219280 rect 343508 219240 343514 219252 rect 409506 219240 409512 219252 rect 409564 219240 409570 219292 +rect 416720 219266 597144 219294 +rect 191080 218896 191086 218948 +rect 191138 218936 191144 218948 +rect 416720 218936 416748 219266 +rect 597138 219254 597144 219266 +rect 597196 219294 597202 219306 +rect 639198 219294 639204 219306 +rect 597196 219266 639204 219294 +rect 597196 219254 597202 219266 +rect 639198 219254 639204 219266 +rect 639256 219254 639262 219306 +rect 191138 218908 416748 218936 +rect 191138 218896 191144 218908 rect 525794 218424 525800 218476 rect 525852 218464 525858 218476 rect 613102 218464 613108 218476 @@ -16722,11 +16731,11 @@ rect 640160 76292 640166 76304 rect 627360 76264 640166 76292 rect 640160 76252 640166 76264 rect 640218 76252 640224 76304 -rect 621244 75760 621250 75812 -rect 621302 75800 621308 75812 +rect 597138 75774 597144 75826 +rect 597196 75800 597202 75826 rect 631634 75800 631640 75812 -rect 621302 75772 631640 75800 -rect 621302 75760 621308 75772 +rect 597196 75774 631640 75800 +rect 597138 75772 631640 75774 rect 631634 75760 631640 75772 rect 631692 75760 631698 75812 rect 621322 75624 621328 75676 @@ -16945,15 +16954,6 @@ rect 310480 43812 311900 43840 rect 310480 43800 310486 43812 rect 311894 43800 311900 43812 rect 311952 43800 311958 43852 -rect 622302 43092 622308 43104 -rect 223818 43064 622308 43092 -rect 52178 42712 52184 42764 -rect 52236 42752 52242 42764 -rect 223818 42752 223846 43064 -rect 622302 43052 622308 43064 -rect 622360 43052 622366 43104 -rect 52236 42724 223846 42752 -rect 52236 42712 52242 42724 rect 529658 42712 529664 42764 rect 529716 42752 529722 42764 rect 542998 42752 543004 42764 @@ -19482,8 +19482,6 @@ rect 674656 246032 674708 246084 rect 675392 246032 675444 246084 rect 20720 245828 20772 245880 rect 30104 245828 30156 245880 -rect 52184 245760 52236 245812 -rect 184940 245760 184992 245812 rect 41512 245692 41564 245744 rect 56692 245692 56744 245744 rect 41420 245624 41472 245676 @@ -20960,6 +20958,9 @@ rect 346308 219308 346360 219360 rect 416228 219308 416280 219360 rect 343456 219240 343508 219292 rect 409512 219240 409564 219292 +rect 191086 218896 191138 218948 +rect 597144 219254 597196 219306 +rect 639204 219254 639256 219306 rect 525800 218424 525852 218476 rect 613108 218424 613160 218476 rect 523408 218356 523460 218408 @@ -21734,7 +21735,7 @@ rect 621012 76266 621064 76318 rect 623120 76266 623172 76318 rect 627308 76264 627360 76316 rect 640166 76252 640218 76304 -rect 621250 75760 621302 75812 +rect 597144 75774 597196 75826 rect 631640 75760 631692 75812 rect 621328 75624 621380 75676 rect 625950 75624 626002 75676 @@ -21798,8 +21799,6 @@ rect 365168 43868 365220 43920 rect 367100 43868 367152 43920 rect 310428 43800 310480 43852 rect 311900 43800 311952 43852 -rect 52184 42712 52236 42764 -rect 622308 43052 622360 43104 rect 529664 42712 529716 42764 rect 543004 42712 543056 42764 rect 475476 42576 475528 42628 @@ -25201,8 +25200,6 @@ rect 51080 257984 51132 257990 rect 51080 257926 51132 257932 rect 52276 256760 52328 256766 rect 52276 256702 52328 256708 -rect 52184 245812 52236 245818 -rect 52184 245754 52236 245760 rect 52092 230848 52144 230854 rect 52092 230790 52144 230796 rect 50988 219700 51040 219706 @@ -25222,7 +25219,6 @@ rect 42168 181900 42196 182106 rect 52104 51134 52132 230790 rect 52092 51128 52144 51134 rect 52092 51070 52144 51076 -rect 52196 42770 52224 245754 rect 52288 47122 52316 256702 rect 52736 227724 52788 227730 rect 52736 227666 52788 227672 @@ -29291,13 +29287,35 @@ rect 639142 274680 639198 274689 rect 639142 274615 639198 274624 rect 637946 274544 638002 274553 rect 637946 274479 638002 274488 -rect 639202 271959 639262 271968 rect 636752 271924 636804 271930 -rect 639202 271890 639262 271899 rect 636752 271866 636804 271872 rect 618996 269214 619048 269220 rect 633254 269240 633310 269249 +rect 640352 269210 640380 278052 +rect 641456 274650 641484 278052 +rect 641444 274644 641496 274650 +rect 641444 274586 641496 274592 +rect 642652 272134 642680 278052 +rect 642640 272128 642692 272134 +rect 642640 272070 642692 272076 +rect 643848 271833 643876 278052 +rect 645044 271969 645072 278052 +rect 645030 271960 645086 271969 +rect 645030 271895 645086 271904 +rect 643834 271824 643890 271833 +rect 643834 271759 643890 271768 rect 633254 269175 633310 269184 +rect 640340 269204 640392 269210 +rect 640340 269146 640392 269152 +rect 646240 269113 646268 278052 +rect 647436 271862 647464 278052 +rect 648646 278038 648752 278066 +rect 648620 277636 648672 277642 +rect 648620 277578 648672 277584 +rect 647424 271856 647476 271862 +rect 647424 271798 647476 271804 +rect 646226 269104 646282 269113 +rect 646226 269039 646282 269048 rect 602434 266520 602490 266529 rect 602434 266455 602490 266464 rect 596548 266348 596600 266354 @@ -29333,18 +29351,8 @@ rect 416780 248464 416832 248470 rect 416780 248406 416832 248412 rect 564348 248464 564400 248470 rect 564348 248406 564400 248412 -rect 184938 248024 184994 248033 -rect 184938 247959 184994 247968 -rect 184952 245818 184980 247959 -rect 416778 246392 416834 246401 -rect 416778 246327 416834 246336 -rect 184940 245812 184992 245818 -rect 184940 245754 184992 245760 -rect 416792 245682 416820 246327 -rect 416780 245676 416832 245682 -rect 416780 245618 416832 245624 -rect 418066 243128 418122 243137 -rect 418066 243063 418122 243072 +rect 191082 248032 191142 248041 +rect 191082 247963 191142 247972 rect 184940 237448 184992 237454 rect 184938 237416 184940 237425 rect 184992 237416 184994 237425 @@ -29857,6 +29865,14 @@ rect 188988 221002 189040 221008 rect 189000 217410 189028 221002 rect 189828 217410 189856 221138 rect 190380 217410 190408 226850 +rect 191098 218954 191126 247963 +rect 416778 246392 416834 246401 +rect 416778 246327 416834 246336 +rect 416792 245682 416820 246327 +rect 416780 245676 416832 245682 +rect 416780 245618 416832 245624 +rect 418066 243128 418122 243137 +rect 418066 243063 418122 243072 rect 192312 226370 192340 231676 rect 192300 226364 192352 226370 rect 192300 226306 192352 226312 @@ -29880,6 +29896,8 @@ rect 192668 224936 192720 224942 rect 192668 224878 192720 224884 rect 191472 223780 191524 223786 rect 191472 223722 191524 223728 +rect 191086 218948 191138 218954 +rect 191086 218890 191138 218896 rect 191484 217410 191512 223722 rect 193048 221406 193076 226578 rect 193324 222193 193352 231676 @@ -34610,6 +34628,13 @@ rect 566832 222284 566884 222290 rect 566832 222226 566884 222232 rect 566844 217410 566872 222226 rect 567120 221649 567148 251194 +rect 648632 231334 648660 277578 +rect 648724 269142 648752 278038 +rect 654140 277568 654192 277574 +rect 654140 277510 654192 277516 +rect 648712 269136 648764 269142 +rect 648712 269078 648764 269084 +rect 648632 231306 650380 231334 rect 570236 227724 570288 227730 rect 570236 227666 570288 227672 rect 569314 227624 569370 227633 @@ -34660,10 +34685,8 @@ rect 574388 217410 574416 221575 rect 575202 221504 575258 221513 rect 575202 221439 575258 221448 rect 575216 217410 575244 221439 -rect 607128 218136 607180 218142 -rect 607128 218078 607180 218084 -rect 606668 218068 606720 218074 -rect 606668 218010 606720 218016 +rect 597144 219306 597196 219312 +rect 597144 219248 597196 219254 rect 582660 217764 582712 217770 rect 582660 217706 582712 217712 rect 573560 217382 573896 217410 @@ -35065,8 +35088,6 @@ rect 218072 46852 218100 46854 rect 141804 46702 142370 46730 rect 85120 45756 85172 45762 rect 85120 45698 85172 45704 -rect 52184 42764 52236 42770 -rect 52184 42706 52236 42712 rect 141804 40202 141832 46702 rect 460664 46028 460716 46034 rect 460664 45970 460716 45976 @@ -35381,6 +35402,112 @@ rect 582010 128919 582066 128928 rect 582208 127497 582236 146338 rect 582300 133481 582328 151914 rect 582820 146970 582848 215494 +rect 582804 146961 582864 146970 +rect 582804 146892 582864 146901 +rect 582286 133472 582342 133481 +rect 582286 133407 582342 133416 +rect 582194 127488 582250 127497 +rect 582194 127423 582250 127432 +rect 582288 124364 582340 124370 +rect 582288 124306 582340 124312 +rect 581918 122088 581974 122097 +rect 581918 122023 581974 122032 +rect 582196 121644 582248 121650 +rect 582196 121586 582248 121592 +rect 582012 121576 582064 121582 +rect 582012 121518 582064 121524 +rect 581920 118788 581972 118794 +rect 581920 118730 581972 118736 +rect 581826 89844 581882 89853 +rect 581826 89779 581882 89788 +rect 581828 84448 581880 84454 +rect 581828 84390 581880 84396 +rect 581734 77864 581790 77873 +rect 581734 77799 581790 77808 +rect 581642 75032 581698 75041 +rect 581642 74967 581698 74976 +rect 581550 71760 581606 71769 +rect 581550 71695 581606 71704 +rect 581182 67256 581238 67265 +rect 581182 67191 581238 67200 +rect 581090 64264 581146 64273 +rect 581090 64199 581146 64208 +rect 581840 56777 581868 84390 +rect 581932 84153 581960 118730 +rect 582024 86845 582052 121518 +rect 582104 121508 582156 121514 +rect 582104 121450 582156 121456 +rect 582116 88341 582144 121450 +rect 582102 88332 582158 88341 +rect 582102 88267 582158 88276 +rect 582010 86836 582066 86845 +rect 582010 86771 582066 86780 +rect 582208 85349 582236 121586 +rect 582300 92825 582328 124306 +rect 583668 118856 583720 118862 +rect 583668 118798 583720 118804 +rect 582286 92816 582342 92825 +rect 582286 92751 582342 92760 +rect 582194 85340 582250 85349 +rect 582194 85275 582250 85284 +rect 582196 84584 582248 84590 +rect 582196 84526 582248 84532 +rect 582012 84380 582064 84386 +rect 582012 84322 582064 84328 +rect 581918 84144 581974 84153 +rect 581918 84079 581974 84088 +rect 581826 56768 581882 56777 +rect 581826 56703 581882 56712 +rect 582024 55281 582052 84322 +rect 582104 84312 582156 84318 +rect 582104 84254 582156 84260 +rect 582116 59769 582144 84254 +rect 582208 61265 582236 84526 +rect 582288 84516 582340 84522 +rect 582288 84458 582340 84464 +rect 582194 61256 582250 61265 +rect 582194 61191 582250 61200 +rect 582102 59760 582158 59769 +rect 582102 59695 582158 59704 +rect 582300 58273 582328 84458 +rect 583680 82686 583708 118798 +rect 591948 95396 592000 95402 +rect 591948 95338 592000 95344 +rect 589188 95328 589240 95334 +rect 589188 95270 589240 95276 +rect 583760 84652 583812 84658 +rect 583760 84594 583812 84600 +rect 583668 82680 583720 82686 +rect 583668 82622 583720 82628 +rect 583668 73160 583720 73166 +rect 583668 73102 583720 73108 +rect 582286 58264 582342 58273 +rect 582286 58199 582342 58208 +rect 582010 55272 582066 55281 +rect 582010 55207 582066 55216 +rect 580906 53776 580962 53785 +rect 580906 53711 580962 53720 +rect 581644 53236 581696 53242 +rect 581644 53178 581696 53184 +rect 581656 48414 581684 53178 +rect 581644 48408 581696 48414 +rect 581644 48350 581696 48356 +rect 583680 47122 583708 73102 +rect 583772 66230 583800 84594 +rect 589200 75002 589228 95270 +rect 589188 74996 589240 75002 +rect 589188 74938 589240 74944 +rect 591960 72690 591988 95338 +rect 596916 83156 596968 83162 +rect 596916 83098 596968 83104 +rect 596928 78674 596956 83098 +rect 596916 78668 596968 78674 +rect 596916 78610 596968 78616 +rect 597156 75832 597184 219248 +rect 607128 218136 607180 218142 +rect 607128 218078 607180 218084 +rect 606668 218068 606720 218074 +rect 606668 218010 606720 218016 rect 600044 215348 600096 215354 rect 600044 215290 600096 215296 rect 599952 212628 600004 212634 @@ -35586,6 +35713,10 @@ rect 637396 215756 637448 215762 rect 637396 215698 637448 215704 rect 637408 210202 637436 215698 rect 637868 210202 637896 221031 +rect 650352 220346 650380 231306 +rect 649552 220318 650380 220346 +rect 639204 219306 639256 219312 +rect 639204 219248 639256 219254 rect 638316 215620 638368 215626 rect 638316 215562 638368 215568 rect 638328 210202 638356 215562 @@ -35662,40 +35793,7 @@ rect 637376 210174 637436 210202 rect 637836 210174 637896 210202 rect 638296 210174 638356 210202 rect 638756 210174 638816 210202 -rect 639218 210154 639246 271890 -rect 640352 269210 640380 278052 -rect 641456 274650 641484 278052 -rect 641444 274644 641496 274650 -rect 641444 274586 641496 274592 -rect 642652 272134 642680 278052 -rect 642640 272128 642692 272134 -rect 642640 272070 642692 272076 -rect 643848 271833 643876 278052 -rect 645044 271969 645072 278052 -rect 645030 271960 645086 271969 -rect 645030 271895 645086 271904 -rect 643834 271824 643890 271833 -rect 643834 271759 643890 271768 -rect 640340 269204 640392 269210 -rect 640340 269146 640392 269152 -rect 646240 269113 646268 278052 -rect 647436 271862 647464 278052 -rect 648646 278038 648752 278066 -rect 648620 277636 648672 277642 -rect 648620 277578 648672 277584 -rect 647424 271856 647476 271862 -rect 647424 271798 647476 271804 -rect 646226 269104 646282 269113 -rect 646226 269039 646282 269048 -rect 648632 231334 648660 277578 -rect 648724 269142 648752 278038 -rect 654140 277568 654192 277574 -rect 654140 277510 654192 277516 -rect 648712 269136 648764 269142 -rect 648712 269078 648764 269084 -rect 648632 231306 650380 231334 -rect 650352 220346 650380 231306 -rect 649552 220318 650380 220346 +rect 639216 210122 639244 219248 rect 639696 217048 639748 217054 rect 639696 216990 639748 216996 rect 639708 210202 639736 216990 @@ -36258,8 +36356,6 @@ rect 599952 149116 600004 149122 rect 599952 149058 600004 149064 rect 599858 148336 599914 148345 rect 599858 148271 599914 148280 -rect 582804 146961 582864 146970 -rect 582804 146892 582864 146901 rect 599872 146402 599900 148271 rect 599950 147384 600006 147393 rect 599950 147319 600006 147328 @@ -36326,8 +36422,6 @@ rect 600042 135144 600098 135153 rect 600042 135079 600098 135088 rect 599858 134056 599914 134065 rect 599858 133991 599914 134000 -rect 582286 133472 582342 133481 -rect 582286 133407 582342 133416 rect 599872 132598 599900 133991 rect 599950 133104 600006 133113 rect 599950 133039 600006 133048 @@ -36356,8 +36450,6 @@ rect 599952 129804 600004 129810 rect 599952 129746 600004 129752 rect 599858 129024 599914 129033 rect 599858 128959 599914 128968 -rect 582194 127488 582250 127497 -rect 582194 127423 582250 127432 rect 599872 127090 599900 128959 rect 599950 127936 600006 127945 rect 599950 127871 600006 127880 @@ -36370,42 +36462,6 @@ rect 599952 126958 600004 126964 rect 599858 126919 599914 126928 rect 599766 124944 599822 124953 rect 599766 124879 599822 124888 -rect 582288 124364 582340 124370 -rect 582288 124306 582340 124312 -rect 581918 122088 581974 122097 -rect 581918 122023 581974 122032 -rect 582196 121644 582248 121650 -rect 582196 121586 582248 121592 -rect 582012 121576 582064 121582 -rect 582012 121518 582064 121524 -rect 581920 118788 581972 118794 -rect 581920 118730 581972 118736 -rect 581826 89844 581882 89853 -rect 581826 89779 581882 89788 -rect 581828 84448 581880 84454 -rect 581828 84390 581880 84396 -rect 581734 77864 581790 77873 -rect 581734 77799 581790 77808 -rect 581642 75032 581698 75041 -rect 581642 74967 581698 74976 -rect 581550 71760 581606 71769 -rect 581550 71695 581606 71704 -rect 581182 67256 581238 67265 -rect 581182 67191 581238 67200 -rect 581090 64264 581146 64273 -rect 581090 64199 581146 64208 -rect 581840 56777 581868 84390 -rect 581932 84153 581960 118730 -rect 582024 86845 582052 121518 -rect 582104 121508 582156 121514 -rect 582104 121450 582156 121456 -rect 582116 88341 582144 121450 -rect 582102 88332 582158 88341 -rect 582102 88267 582158 88276 -rect 582010 86836 582066 86845 -rect 582010 86771 582066 86780 -rect 582208 85349 582236 121586 -rect 582300 92825 582328 124306 rect 599780 124302 599808 124879 rect 599872 124370 599900 126919 rect 599950 125896 600006 125905 @@ -36437,35 +36493,8 @@ rect 600042 120799 600098 120808 rect 599950 119776 600006 119785 rect 599950 119711 600006 119720 rect 599964 118862 599992 119711 -rect 583668 118856 583720 118862 rect 599952 118856 600004 118862 -rect 583668 118798 583720 118804 rect 599858 118824 599914 118833 -rect 582286 92816 582342 92825 -rect 582286 92751 582342 92760 -rect 582194 85340 582250 85349 -rect 582194 85275 582250 85284 -rect 582196 84584 582248 84590 -rect 582196 84526 582248 84532 -rect 582012 84380 582064 84386 -rect 582012 84322 582064 84328 -rect 581918 84144 581974 84153 -rect 581918 84079 581974 84088 -rect 581826 56768 581882 56777 -rect 581826 56703 581882 56712 -rect 582024 55281 582052 84322 -rect 582104 84312 582156 84318 -rect 582104 84254 582156 84260 -rect 582116 59769 582144 84254 -rect 582208 61265 582236 84526 -rect 582288 84516 582340 84522 -rect 582288 84458 582340 84464 -rect 582194 61256 582250 61265 -rect 582194 61191 582250 61200 -rect 582102 59760 582158 59769 -rect 582102 59695 582158 59704 -rect 582300 58273 582328 84458 -rect 583680 82686 583708 118798 rect 599952 118798 600004 118804 rect 600056 118794 600084 120799 rect 599858 118759 599914 118768 @@ -36521,33 +36550,6 @@ rect 599950 100399 600006 100408 rect 599964 99414 599992 100399 rect 599952 99408 600004 99414 rect 599952 99350 600004 99356 -rect 591948 95396 592000 95402 -rect 591948 95338 592000 95344 -rect 589188 95328 589240 95334 -rect 589188 95270 589240 95276 -rect 583760 84652 583812 84658 -rect 583760 84594 583812 84600 -rect 583668 82680 583720 82686 -rect 583668 82622 583720 82628 -rect 583668 73160 583720 73166 -rect 583668 73102 583720 73108 -rect 582286 58264 582342 58273 -rect 582286 58199 582342 58208 -rect 582010 55272 582066 55281 -rect 582010 55207 582066 55216 -rect 580906 53776 580962 53785 -rect 580906 53711 580962 53720 -rect 581644 53236 581696 53242 -rect 581644 53178 581696 53184 -rect 581656 48414 581684 53178 -rect 581644 48408 581696 48414 -rect 581644 48350 581696 48356 -rect 583680 47122 583708 73102 -rect 583772 66230 583800 84594 -rect 589200 75002 589228 95270 -rect 589188 74996 589240 75002 -rect 589188 74938 589240 74944 -rect 591960 72690 591988 95338 rect 600240 84250 600268 110599 rect 600318 108624 600374 108633 rect 600318 108559 600374 108568 @@ -36598,9 +36600,6 @@ rect 600872 84312 600924 84318 rect 600872 84254 600924 84260 rect 600596 84176 600648 84182 rect 600596 84118 600648 84124 -rect 596916 83156 596968 83162 -rect 596916 83098 596968 83104 -rect 596928 78674 596956 83098 rect 604472 82890 604500 95542 rect 607220 93900 607272 93906 rect 607220 93842 607272 93848 @@ -36611,8 +36610,8 @@ rect 597468 82884 597520 82890 rect 597468 82826 597520 82832 rect 604460 82884 604512 82890 rect 604460 82826 604512 82832 -rect 596916 78668 596968 78674 -rect 596916 78610 596968 78616 +rect 597144 75826 597196 75832 +rect 597144 75768 597196 75774 rect 586428 72684 586480 72690 rect 586428 72626 586480 72632 rect 591948 72684 592000 72690 @@ -36996,15 +36995,8 @@ rect 623120 76260 623172 76266 rect 610348 66292 610400 66298 rect 610348 66234 610400 66240 rect 621024 62689 621052 76260 -rect 621248 75818 621276 75822 -rect 621248 75812 621302 75818 -rect 621248 75760 621250 75812 -rect 621248 75754 621302 75760 -rect 621248 62825 621276 75754 rect 621328 75676 621380 75682 rect 621328 75618 621380 75624 -rect 621232 62816 621292 62825 -rect 621232 62747 621292 62756 rect 621008 62680 621068 62689 rect 621008 62611 621068 62620 rect 610256 46028 610308 46034 @@ -37102,11 +37094,6 @@ rect 641498 67298 641526 67305 rect 641354 65880 641414 65889 rect 641354 65811 641414 65820 rect 641370 65810 641398 65811 -rect 622310 62814 622366 62823 -rect 622310 62749 622366 62758 -rect 621328 45564 621380 45570 -rect 621328 45506 621380 45512 -rect 622320 43110 622348 62749 rect 631872 62674 631932 62683 rect 631872 62605 631932 62614 rect 631888 51066 631916 62605 @@ -37440,6 +37427,8 @@ rect 661130 47560 661186 47569 rect 661130 47495 661186 47504 rect 642640 46912 642692 46918 rect 642640 46854 642692 46860 +rect 621328 45564 621380 45570 +rect 621328 45506 621380 45512 rect 661144 44130 661172 47495 rect 665192 47433 665220 95134 rect 666572 48521 666600 170054 @@ -41575,8 +41564,6 @@ rect 665178 47424 665234 47433 rect 665178 47359 665234 47368 rect 661132 44124 661184 44130 rect 661132 44066 661184 44072 -rect 622308 43104 622360 43110 -rect 622308 43046 622360 43052 rect 607496 41472 607548 41478 rect 607496 41414 607548 41420 rect 602988 41404 603040 41410 @@ -42447,15 +42434,15 @@ rect 629666 272040 629722 272096 rect 626078 269320 626134 269376 rect 639142 274624 639198 274680 rect 637946 274488 638002 274544 -rect 639202 271899 639262 271959 rect 633254 269184 633310 269240 +rect 645030 271904 645086 271960 +rect 643834 271768 643890 271824 +rect 646226 269048 646282 269104 rect 602434 266464 602490 266520 rect 184938 258576 184994 258632 rect 416778 252728 416834 252784 rect 416778 249464 416834 249520 -rect 184938 247968 184994 248024 -rect 416778 246336 416834 246392 -rect 418066 243072 418122 243128 +rect 191082 247972 191142 248032 rect 184938 237396 184940 237416 rect 184940 237396 184992 237416 rect 184992 237396 184994 237416 @@ -42502,6 +42489,8 @@ rect 119986 221584 120042 221640 rect 121366 221448 121422 221504 rect 160098 224168 160154 224224 rect 172426 224032 172482 224088 +rect 416778 246336 416834 246392 +rect 418066 243072 418122 243128 rect 194782 227704 194838 227760 rect 194414 227568 194470 227624 rect 194046 224984 194102 225040 @@ -42810,13 +42799,31 @@ rect 582286 153000 582342 153056 rect 582194 151504 582250 151560 rect 582102 139416 582158 139472 rect 582010 128928 582066 128984 +rect 582804 146901 582864 146961 +rect 582286 133416 582342 133472 +rect 582194 127432 582250 127488 +rect 581918 122032 581974 122088 +rect 581826 89788 581882 89844 +rect 581734 77808 581790 77864 +rect 581642 74976 581698 75032 +rect 581550 71704 581606 71760 +rect 581182 67200 581238 67256 +rect 581090 64208 581146 64264 +rect 582102 88276 582158 88332 +rect 582010 86780 582066 86836 +rect 582286 92760 582342 92816 +rect 582194 85284 582250 85340 +rect 581918 84088 581974 84144 +rect 581826 56712 581882 56768 +rect 582194 61200 582250 61256 +rect 582102 59704 582158 59760 +rect 582286 58208 582342 58264 +rect 582010 55216 582066 55272 +rect 580906 53720 580962 53776 rect 622490 221176 622546 221232 rect 624330 221312 624386 221368 rect 637854 221040 637910 221096 rect 636934 220904 636990 220960 -rect 645030 271904 645086 271960 -rect 643834 271768 643890 271824 -rect 646226 269048 646282 269104 rect 652758 217232 652814 217288 rect 655518 291488 655574 291544 rect 655702 290400 655758 290456 @@ -42904,7 +42911,6 @@ rect 600042 151408 600098 151464 rect 599858 150320 599914 150376 rect 599950 149368 600006 149424 rect 599858 148280 599914 148336 -rect 582804 146901 582864 146961 rect 599950 147328 600006 147384 rect 599858 146240 599914 146296 rect 600042 145288 600098 145344 @@ -42922,37 +42928,20 @@ rect 599858 137128 599914 137184 rect 599950 136040 600006 136096 rect 600042 135088 600098 135144 rect 599858 134000 599914 134056 -rect 582286 133416 582342 133472 rect 599950 133048 600006 133104 rect 600042 131960 600098 132016 rect 599858 131008 599914 131064 rect 599950 129920 600006 129976 rect 599858 128968 599914 129024 -rect 582194 127432 582250 127488 rect 599950 127880 600006 127936 rect 599858 126928 599914 126984 rect 599766 124888 599822 124944 -rect 581918 122032 581974 122088 -rect 581826 89788 581882 89844 -rect 581734 77808 581790 77864 -rect 581642 74976 581698 75032 -rect 581550 71704 581606 71760 -rect 581182 67200 581238 67256 -rect 581090 64208 581146 64264 -rect 582102 88276 582158 88332 -rect 582010 86780 582066 86836 rect 599950 125840 600006 125896 rect 600042 123800 600098 123856 rect 599858 122848 599914 122904 rect 599950 121760 600006 121816 rect 600042 120808 600098 120864 rect 599950 119720 600006 119776 -rect 582286 92760 582342 92816 -rect 582194 85284 582250 85340 -rect 581918 84088 581974 84144 -rect 581826 56712 581882 56768 -rect 582194 61200 582250 61256 -rect 582102 59704 582158 59760 rect 599858 118768 599914 118824 rect 600042 117680 600098 117736 rect 599950 116728 600006 116784 @@ -42964,9 +42953,6 @@ rect 600226 110608 600282 110664 rect 599306 109520 599362 109576 rect 599950 107480 600006 107536 rect 599950 100408 600006 100464 -rect 582286 58208 582342 58264 -rect 582010 55216 582066 55272 -rect 580906 53720 580962 53776 rect 600318 108568 600374 108624 rect 600594 106528 600650 106584 rect 600410 105440 600466 105496 @@ -42998,7 +42984,6 @@ rect 623134 84088 623190 84144 rect 622122 83136 622178 83192 rect 627490 82208 627546 82264 rect 627304 81400 627364 81460 -rect 621232 62756 621292 62816 rect 621008 62620 621068 62680 rect 642730 92656 642786 92712 rect 641162 74812 641222 74872 @@ -43008,7 +42993,6 @@ rect 641940 71794 642000 71854 rect 641832 68812 641892 68872 rect 641482 67314 641542 67374 rect 641354 65820 641414 65880 -rect 622310 62758 622366 62814 rect 631872 62614 631932 62674 rect 645858 89664 645914 89720 rect 646042 87080 646098 87136 @@ -49317,21 +49301,14 @@ rect 70577 271902 194199 271904 rect 70577 271899 70643 271902 rect 194133 271899 194199 271902 rect 410517 271962 410583 271965 -rect 639197 271962 639267 271967 rect 645025 271962 645091 271965 rect 410517 271960 645091 271962 rect 410517 271904 410522 271960 -rect 410578 271959 645030 271960 -rect 410578 271904 639202 271959 -rect 410517 271902 639202 271904 -rect 410517 271899 410583 271902 -rect 639197 271899 639202 271902 -rect 639262 271904 645030 271959 +rect 410578 271904 645030 271960 rect 645086 271904 645091 271960 -rect 639262 271902 645091 271904 -rect 639262 271899 639267 271902 +rect 410517 271902 645091 271904 +rect 410517 271899 410583 271902 rect 645025 271899 645091 271902 -rect 639197 271894 639267 271899 rect 69381 271826 69447 271829 rect 193673 271826 193739 271829 rect 69381 271824 193739 271826 @@ -50179,12 +50156,12 @@ rect 41462 248104 41510 248160 rect 41566 248104 41571 248160 rect 41462 248102 41571 248104 rect 41505 248099 41571 248102 -rect 184933 248026 184999 248029 -rect 184933 248024 191820 248026 -rect 184933 247968 184938 248024 -rect 184994 247968 191820 248024 -rect 184933 247966 191820 247968 -rect 184933 247963 184999 247966 +rect 191077 248032 191147 248037 +rect 191077 248026 191082 248032 +rect 191076 247972 191082 248026 +rect 191142 248026 191147 248032 +rect 191142 247972 191820 248026 +rect 191076 247966 191820 247972 rect 41462 247757 41522 247860 rect 41413 247752 41522 247757 rect 41413 247696 41418 247752 @@ -53926,19 +53903,10 @@ rect 576380 64208 581090 64264 rect 581146 64208 581151 64264 rect 576380 64206 581151 64208 rect 581085 64203 581151 64206 -rect 621227 62816 621297 62821 -rect 622305 62816 622371 62819 rect 580809 62770 580875 62773 rect 576380 62768 580875 62770 rect 576380 62712 580814 62768 rect 580870 62712 580875 62768 -rect 621227 62756 621232 62816 -rect 621292 62814 622371 62816 -rect 621292 62758 622310 62814 -rect 622366 62758 622371 62814 -rect 621292 62756 622371 62758 -rect 621227 62751 621297 62756 -rect 622305 62753 622371 62756 rect 576380 62710 580875 62712 rect 580809 62707 580875 62710 rect 621003 62680 621073 62685 @@ -55357,9 +55325,13 @@ rect 515440 6598 527960 19088 rect 570422 6811 582590 18975 rect 624222 6811 636390 18975 use xres_buf rstb_level -timestamp 1638495418 +timestamp 1638030917 transform -1 0 145710 0 -1 50488 box 414 -400 3522 3800 +use open_source open_source_0 hexdigits +timestamp 1638586442 +transform 1 0 206074 0 1 2336 +box 752 5164 29030 16242 use caravan_motto caravan_motto_0 timestamp 1637698689 transform 1 0 -54560 0 1 -52 @@ -55368,10 +55340,6 @@ use caravan_logo caravan_logo_0 timestamp 1636751500 transform 1 0 255300 0 1 6032 box 2240 2560 37000 11520 -use open_source open_source_0 hexdigits -timestamp 1635801696 -transform 1 0 206074 0 1 2336 -box 752 5164 29030 16242 use copyright_block_a copyright_block_a_0 timestamp 1636248774 transform 1 0 149582 0 1 16298 @@ -55381,27 +55349,27 @@ timestamp 1608324878 transform 1 0 96272 0 1 6890 box -656 1508 33720 10344 use caravel_clocking clocking -timestamp 1638495418 +timestamp 1638662845 transform 1 0 621684 0 1 63608 box -38 -48 20000 12000 use housekeeping housekeeping -timestamp 1638495418 +timestamp 1638464048 transform 1 0 606434 0 1 100002 box 0 0 60046 110190 use digital_pll pll -timestamp 1638495418 +timestamp 1638470892 transform 1 0 628146 0 1 80944 box 0 0 15000 15000 use user_id_programming user_id_value -timestamp 1638495418 +timestamp 1638030917 transform 1 0 656624 0 1 88126 box 0 0 7109 7077 use gpio_defaults_block_1803 gpio_defaults_block_0 -timestamp 1638495418 +timestamp 1636219436 transform -1 0 709467 0 1 134000 box -38 0 6018 2224 use gpio_control_block gpio_control_bidir_1\[0\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 121000 box 882 167 34000 13000 use simple_por por ../maglef @@ -55413,235 +55381,235 @@ timestamp 1638280046 transform 1 0 52034 0 1 53002 box 382 -400 524400 164400 use gpio_control_block gpio_control_bidir_2\[2\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 202600 box 882 167 34000 13000 use gpio_defaults_block_1803 gpio_defaults_block_1 -timestamp 1638495418 +timestamp 1636219436 transform -1 0 709467 0 1 179200 box -38 0 6018 2224 use gpio_control_block gpio_control_bidir_1\[1\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 166200 box 882 167 34000 13000 use gpio_control_block gpio_control_bidir_2\[1\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 245800 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_37 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 215600 box -38 0 6018 2224 use mgmt_protect mgmt_buffers -timestamp 1638495418 +timestamp 1638030917 transform 1 0 192180 0 1 232036 box -400 -400 220400 32400 use spare_logic_block spare_logic_block_3 -timestamp 1638495418 +timestamp 1638030917 transform 1 0 88632 0 1 232528 box 0 0 9000 9000 use spare_logic_block spare_logic_block_1 -timestamp 1638495418 +timestamp 1638030917 transform 1 0 168632 0 1 232528 box 0 0 9000 9000 use spare_logic_block spare_logic_block_2 -timestamp 1638495418 +timestamp 1638030917 transform 1 0 428632 0 1 232528 box 0 0 9000 9000 use spare_logic_block spare_logic_block_0 -timestamp 1638495418 +timestamp 1638030917 transform 1 0 640874 0 1 220592 box 0 0 9000 9000 use gpio_control_block gpio_control_in_1a\[0\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 211200 box 882 167 34000 13000 use gpio_defaults_block_0403 gpio_defaults_block_2 -timestamp 1638495418 +timestamp 1638299091 transform -1 0 709467 0 1 224200 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_36 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 258800 box -38 0 6018 2224 use gpio_control_block gpio_control_in_1a\[1\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 256400 box 882 167 34000 13000 use gpio_defaults_block_0403 gpio_defaults_block_3 -timestamp 1638495418 +timestamp 1638299091 transform -1 0 709467 0 1 269400 box -38 0 6018 2224 use gpio_control_block gpio_control_bidir_2\[0\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 289000 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_35 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 302000 box -38 0 6018 2224 use gpio_control_block gpio_control_in_1a\[2\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 301400 box 882 167 34000 13000 use gpio_defaults_block_0403 gpio_defaults_block_4 -timestamp 1638495418 +timestamp 1638299091 transform -1 0 709467 0 1 314400 box -38 0 6018 2224 use gpio_control_block gpio_control_in_2\[7\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 418600 box 882 167 34000 13000 use gpio_control_block gpio_control_in_2\[8\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 375400 box 882 167 34000 13000 use gpio_control_block gpio_control_in_2\[9\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 332200 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_32 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 431600 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_33 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 388400 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_34 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 345200 box -38 0 6018 2224 use gpio_control_block gpio_control_in_1a\[3\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 346400 box 882 167 34000 13000 use gpio_control_block gpio_control_in_1a\[4\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 391600 box 882 167 34000 13000 use gpio_control_block gpio_control_in_1a\[5\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 479800 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_5 -timestamp 1638495418 +timestamp 1638587925 transform -1 0 709467 0 1 359400 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_6 -timestamp 1638495418 +timestamp 1638587925 transform -1 0 709467 0 1 404600 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_7 -timestamp 1638495418 +timestamp 1638587925 transform -1 0 709467 0 1 492800 box -38 0 6018 2224 use gpio_control_block gpio_control_in_2\[4\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 632600 box 882 167 34000 13000 use gpio_control_block gpio_control_in_2\[5\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 589400 box 882 167 34000 13000 use gpio_control_block gpio_control_in_2\[6\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 546200 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_30 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 602400 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_31 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 559200 box -38 0 6018 2224 use gpio_control_block gpio_control_in_1\[0\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 523800 box 882 167 34000 13000 use gpio_control_block gpio_control_in_1\[1\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 568800 box 882 167 34000 13000 use gpio_control_block gpio_control_in_1\[2\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 614000 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_10 -timestamp 1638495418 +timestamp 1638587925 transform -1 0 709467 0 1 627000 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_8 -timestamp 1638495418 +timestamp 1638587925 transform -1 0 709467 0 1 536800 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_9 -timestamp 1638495418 +timestamp 1638587925 transform -1 0 709467 0 1 581800 box -38 0 6018 2224 use gpio_control_block gpio_control_in_2\[2\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 719000 box 882 167 34000 13000 use gpio_control_block gpio_control_in_2\[3\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 675800 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_27 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 732000 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_28 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 688800 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_29 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 645600 box -38 0 6018 2224 use gpio_control_block gpio_control_in_1\[3\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 659000 box 882 167 34000 13000 use gpio_control_block gpio_control_in_1\[4\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 704200 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_11 -timestamp 1638495418 +timestamp 1638587925 transform -1 0 709467 0 1 672000 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_12 -timestamp 1638495418 +timestamp 1638587925 transform -1 0 709467 0 1 717200 box -38 0 6018 2224 use gpio_control_block gpio_control_in_2\[0\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 805400 box 882 167 34000 13000 use gpio_control_block gpio_control_in_2\[1\] -timestamp 1638495418 +timestamp 1638030917 transform 1 0 7631 0 1 762200 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_14 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 818400 box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_26 -timestamp 1638495418 +timestamp 1638587925 transform 1 0 8367 0 1 775200 box -38 0 6018 2224 use gpio_control_block gpio_control_in_1\[5\] -timestamp 1638495418 +timestamp 1638030917 transform -1 0 710203 0 1 884800 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_13 -timestamp 1638495418 +timestamp 1638587925 transform -1 0 709467 0 1 897800 box -38 0 6018 2224 use chip_io_alt padframe -timestamp 1638495418 +timestamp 1638031010 transform 1 0 0 0 1 0 box 0 0 717600 1037600 use caravan_power_routing caravan_power_routing_0 diff --git a/mag/caravel.mag b/mag/caravel.mag index 72d4eb4c..6f6bdb42 100644 --- a/mag/caravel.mag +++ b/mag/caravel.mag @@ -1,7 +1,9 @@ magic tech sky130A magscale 1 2 -timestamp 1638492834 +timestamp 1638835791 +<< checkpaint >> +rect -1260 -1260 718860 1038860 << isosubstrate >> rect 98738 1027427 101714 1028967 rect 150138 1027427 153114 1028967 @@ -11805,13 +11807,6 @@ rect 675168 246044 675392 246072 rect 675168 246032 675174 246044 rect 675386 246032 675392 246044 rect 675444 246032 675450 246084 -rect 52178 245624 52184 245676 -rect 52236 245664 52242 245676 -rect 184934 245664 184940 245676 -rect 52236 245636 184940 245664 -rect 52236 245624 52242 245636 -rect 184934 245624 184940 245636 -rect 184992 245624 184998 245676 rect 416774 245624 416780 245676 rect 416832 245664 416838 245676 rect 571610 245664 571616 245676 @@ -17138,14 +17133,7 @@ rect 349212 219308 349218 219320 rect 423030 219308 423036 219320 rect 423088 219308 423094 219360 rect 674834 219348 674840 219360 -rect 674832 219320 674840 219348 -rect 674834 219308 674840 219320 -rect 674892 219348 674898 219360 -rect 676030 219348 676036 219360 -rect 674892 219320 676036 219348 -rect 674892 219308 674898 219320 -rect 676030 219308 676036 219320 -rect 676088 219308 676094 219360 +rect 597348 219312 597354 219324 rect 350534 219240 350540 219292 rect 350592 219280 350598 219292 rect 426342 219280 426348 219292 @@ -17153,6 +17141,7 @@ rect 350592 219252 426348 219280 rect 350592 219240 350598 219252 rect 426342 219240 426348 219252 rect 426400 219240 426406 219292 +rect 426796 219284 597354 219312 rect 344830 219172 344836 219224 rect 344888 219212 344894 219224 rect 412910 219212 412916 219224 @@ -17167,6 +17156,30 @@ rect 346360 219116 416228 219144 rect 346360 219104 346366 219116 rect 416222 219104 416228 219116 rect 416280 219104 416286 219156 +rect 426796 219104 426824 219284 +rect 597348 219272 597354 219284 +rect 597406 219312 597412 219324 +rect 639194 219312 639200 219324 +rect 597406 219284 639200 219312 +rect 597406 219272 597412 219284 +rect 639194 219272 639200 219284 +rect 639252 219272 639258 219324 +rect 674832 219320 674840 219348 +rect 674834 219308 674840 219320 +rect 674892 219348 674898 219360 +rect 676030 219348 676036 219360 +rect 674892 219320 676036 219348 +rect 674892 219308 674898 219320 +rect 676030 219308 676036 219320 +rect 676088 219308 676094 219360 +rect 416602 219076 426824 219104 +rect 191210 219008 191216 219020 +rect 48252 218980 191216 219008 +rect 191210 218968 191216 218980 +rect 191268 219008 191274 219020 +rect 416602 219008 416630 219076 +rect 191268 218980 416630 219008 +rect 191268 218968 191274 218980 rect 523402 218492 523408 218544 rect 523460 218532 523466 218544 rect 612642 218532 612648 218544 @@ -19824,11 +19837,11 @@ rect 613068 76782 646018 76810 rect 613068 76770 613074 76782 rect 646012 76770 646018 76782 rect 646070 76770 646076 76822 -rect 622302 76620 622308 76672 -rect 622360 76660 622366 76672 +rect 597348 76620 597354 76672 +rect 597406 76660 597412 76672 rect 636712 76660 636718 76672 -rect 622360 76632 636718 76660 -rect 622360 76620 622366 76632 +rect 597406 76632 636718 76660 +rect 597406 76620 597412 76632 rect 636712 76620 636718 76632 rect 636770 76620 636776 76672 rect 622870 76436 622876 76488 @@ -20160,13 +20173,6 @@ rect 405608 43948 607220 43976 rect 405608 43936 405614 43948 rect 607214 43936 607220 43948 rect 607272 43936 607278 43988 -rect 214828 43324 214834 43376 -rect 214886 43364 214892 43376 -rect 622302 43364 622308 43376 -rect 214886 43336 622308 43364 -rect 214886 43324 214892 43336 -rect 622302 43324 622308 43336 -rect 622360 43324 622366 43376 rect 209682 43256 209688 43308 rect 209740 43296 209746 43308 rect 622870 43296 622876 43308 @@ -20174,13 +20180,6 @@ rect 209740 43268 622876 43296 rect 209740 43256 209746 43268 rect 622870 43256 622876 43268 rect 622928 43256 622934 43308 -rect 52178 42848 52184 42900 -rect 52236 42888 52242 42900 -rect 214828 42888 214834 42906 -rect 52236 42860 214834 42888 -rect 52236 42848 52242 42860 -rect 214828 42854 214834 42860 -rect 214886 42854 214892 42906 rect 530670 42344 530676 42356 rect 525720 42316 530676 42344 rect 455414 42236 455420 42288 @@ -23579,8 +23578,6 @@ rect 41512 246440 41564 246492 rect 45744 246440 45796 246492 rect 675116 246032 675168 246084 rect 675392 246032 675444 246084 -rect 52184 245624 52236 245676 -rect 184940 245624 184992 245676 rect 416780 245624 416832 245676 rect 571616 245624 571668 245676 rect 42708 244468 42760 244520 @@ -25067,14 +25064,17 @@ rect 48780 219376 48832 219428 rect 654140 219376 654192 219428 rect 349160 219308 349212 219360 rect 423036 219308 423088 219360 -rect 674840 219308 674892 219360 -rect 676036 219308 676088 219360 rect 350540 219240 350592 219292 rect 426348 219240 426400 219292 rect 344836 219172 344888 219224 rect 412916 219172 412968 219224 rect 346308 219104 346360 219156 rect 416228 219104 416280 219156 +rect 597354 219272 597406 219324 +rect 639200 219272 639252 219324 +rect 674840 219308 674892 219360 +rect 676036 219308 676088 219360 +rect 191216 218968 191268 219020 rect 523408 218492 523460 218544 rect 612648 218492 612700 218544 rect 525800 218424 525852 218476 @@ -25825,7 +25825,7 @@ rect 618260 76938 618312 76990 rect 646124 76938 646176 76990 rect 613016 76770 613068 76822 rect 646018 76770 646070 76822 -rect 622308 76620 622360 76672 +rect 597354 76620 597406 76672 rect 636718 76620 636770 76672 rect 622876 76436 622928 76488 rect 628156 76436 628208 76488 @@ -25920,12 +25920,8 @@ rect 419724 44004 419776 44056 rect 540888 44004 540940 44056 rect 405556 43936 405608 43988 rect 607220 43936 607272 43988 -rect 214834 43324 214886 43376 -rect 622308 43324 622360 43376 rect 209688 43256 209740 43308 rect 622876 43256 622928 43308 -rect 52184 42848 52236 42900 -rect 214834 42854 214886 42906 rect 455420 42236 455472 42288 rect 530676 42304 530728 42356 rect 531044 42304 531096 42356 @@ -32175,8 +32171,6 @@ rect 50988 257576 51040 257582 rect 50988 257518 51040 257524 rect 52276 256760 52328 256766 rect 52276 256702 52328 256708 -rect 52184 245676 52236 245682 -rect 52184 245618 52236 245624 rect 52092 231247 52144 231253 rect 52092 231189 52144 231195 rect 48964 231056 49016 231062 @@ -32291,7 +32285,6 @@ rect 41800 182477 41828 182679 rect 52104 51066 52132 231189 rect 52092 51060 52144 51066 rect 52092 51002 52144 51008 -rect 52196 42906 52224 245618 rect 52288 47122 52316 256702 rect 57610 227760 57666 227769 rect 52736 227724 52788 227730 @@ -35763,10 +35756,26 @@ rect 641628 274644 641680 274650 rect 641628 274586 641680 274592 rect 640430 272096 640486 272105 rect 640430 272031 640486 272040 -rect 639196 271970 639256 271979 -rect 639196 271901 639256 271910 rect 636842 269376 636898 269385 rect 636842 269311 636898 269320 +rect 642744 269249 642772 277780 +rect 642730 269240 642786 269249 +rect 642730 269175 642786 269184 +rect 643940 269113 643968 277780 +rect 645136 271969 645164 277780 +rect 645122 271960 645178 271969 +rect 645122 271895 645178 271904 +rect 646332 271833 646360 277780 +rect 646318 271824 646374 271833 +rect 646318 271759 646374 271768 +rect 647528 269210 647556 277780 +rect 647516 269204 647568 269210 +rect 647516 269146 647568 269152 +rect 648724 269142 648752 277780 +rect 648712 269136 648764 269142 +rect 643926 269104 643982 269113 +rect 648712 269078 648764 269084 +rect 643926 269039 643982 269048 rect 616786 266384 616842 266393 rect 603724 266348 603776 266354 rect 616786 266319 616842 266328 @@ -35814,18 +35823,8 @@ rect 416778 249455 416834 249464 rect 416792 248470 416820 249455 rect 416780 248464 416832 248470 rect 416780 248406 416832 248412 -rect 184938 248024 184994 248033 -rect 184938 247959 184994 247968 -rect 184952 245682 184980 247959 -rect 416778 246392 416834 246401 -rect 416778 246327 416834 246336 -rect 416792 245682 416820 246327 -rect 184940 245676 184992 245682 -rect 184940 245618 184992 245624 -rect 416780 245676 416832 245682 -rect 416780 245618 416832 245624 -rect 418066 243128 418122 243137 -rect 418066 243063 418122 243072 +rect 191212 248028 191272 248037 +rect 191212 247959 191272 247968 rect 184940 237448 184992 237454 rect 184938 237416 184940 237425 rect 184992 237416 184994 237425 @@ -36455,8 +36454,18 @@ rect 189816 221196 189868 221202 rect 189816 221138 189868 221144 rect 189828 217410 189856 221138 rect 190380 217410 190408 226850 +rect 191228 219026 191256 247959 +rect 416778 246392 416834 246401 +rect 416778 246327 416834 246336 +rect 416792 245682 416820 246327 +rect 416780 245676 416832 245682 +rect 416780 245618 416832 245624 +rect 418066 243128 418122 243137 +rect 418066 243063 418122 243072 rect 191472 224188 191524 224194 rect 191472 224130 191524 224136 +rect 191216 219020 191268 219026 +rect 191216 218962 191268 218968 rect 191484 217410 191512 224130 rect 192312 223650 192340 231676 rect 192588 225049 192616 231676 @@ -41153,10 +41162,8 @@ rect 607588 223450 607640 223456 rect 575204 220788 575256 220794 rect 575204 220730 575256 220736 rect 575216 217410 575244 220730 -rect 607128 218204 607180 218210 -rect 607128 218146 607180 218152 -rect 606668 218136 606720 218142 -rect 606668 218078 606720 218084 +rect 597354 219324 597406 219330 +rect 597354 219266 597406 219272 rect 583128 217912 583180 217918 rect 583128 217854 583180 217860 rect 582962 217808 583014 217814 @@ -41534,8 +41541,6 @@ rect 145102 50064 145616 50092 rect 141804 46702 142370 46730 rect 85120 45688 85172 45694 rect 85120 45630 85172 45636 -rect 52184 42900 52236 42906 -rect 52184 42842 52236 42848 rect 141804 40202 141832 46702 rect 145588 41546 145616 50064 rect 150268 48414 150296 52426 @@ -41615,11 +41620,6 @@ rect 310428 44124 310480 44130 rect 310428 44066 310480 44072 rect 365168 44124 365220 44130 rect 365168 44066 365220 44072 -rect 214834 43376 214886 43382 -rect 214834 43318 214886 43324 -rect 214846 42912 214874 43318 -rect 214834 42906 214886 42912 -rect 214834 42848 214886 42854 rect 310440 42106 310468 44066 rect 365180 42106 365208 44066 rect 419724 44056 419776 44062 @@ -41889,14 +41889,153 @@ rect 582638 146831 582666 215902 rect 582850 213614 582878 217652 rect 582974 213768 583002 217750 rect 583140 213894 583168 217854 -rect 599768 215620 599820 215626 -rect 599768 215562 599820 215568 rect 583128 213888 583180 213894 rect 583128 213830 583180 213836 rect 582962 213762 583014 213768 rect 582962 213704 583014 213710 rect 582838 213608 582890 213614 rect 582838 213550 582890 213556 +rect 582622 146822 582682 146831 +rect 582622 146753 582682 146762 +rect 582286 131976 582342 131985 +rect 582286 131911 582342 131920 +rect 581918 128984 581974 128993 +rect 581918 128919 581974 128928 +rect 582288 124364 582340 124370 +rect 582288 124306 582340 124312 +rect 582012 124296 582064 124302 +rect 582012 124238 582064 124244 +rect 581920 121576 581972 121582 +rect 581920 121518 581972 121524 +rect 581828 118788 581880 118794 +rect 581828 118730 581880 118736 +rect 581734 118376 581790 118385 +rect 581734 118311 581790 118320 +rect 581642 116880 581698 116889 +rect 581642 116815 581698 116824 +rect 581736 116068 581788 116074 +rect 581736 116010 581788 116016 +rect 581644 113280 581696 113286 +rect 581644 113222 581696 113228 +rect 581550 80792 581606 80801 +rect 581550 80727 581606 80736 +rect 581458 76208 581514 76217 +rect 581458 76143 581514 76152 +rect 581656 74721 581684 113222 +rect 581748 79369 581776 116010 +rect 581840 83793 581868 118730 +rect 581932 85289 581960 121518 +rect 582024 89833 582052 124238 +rect 582104 121644 582156 121650 +rect 582104 121586 582156 121592 +rect 582010 89824 582066 89833 +rect 582010 89759 582066 89768 +rect 582116 86785 582144 121586 +rect 582196 121508 582248 121514 +rect 582196 121450 582248 121456 +rect 582208 88281 582236 121450 +rect 582300 91369 582328 124306 +rect 583668 118856 583720 118862 +rect 583668 118798 583720 118804 +rect 582286 91360 582342 91369 +rect 582286 91295 582342 91304 +rect 582194 88272 582250 88281 +rect 582194 88207 582250 88216 +rect 582102 86776 582158 86785 +rect 582102 86711 582158 86720 +rect 581918 85280 581974 85289 +rect 581918 85215 581974 85224 +rect 582288 84448 582340 84454 +rect 582288 84390 582340 84396 +rect 582196 84380 582248 84386 +rect 582196 84322 582248 84328 +rect 582012 84312 582064 84318 +rect 582012 84254 582064 84260 +rect 581920 84176 581972 84182 +rect 581920 84118 581972 84124 +rect 581826 83784 581882 83793 +rect 581826 83719 581882 83728 +rect 581734 79360 581790 79369 +rect 581734 79295 581790 79304 +rect 581642 74712 581698 74721 +rect 581642 74647 581698 74656 +rect 581366 71720 581422 71729 +rect 581366 71655 581422 71664 +rect 581182 67196 581238 67205 +rect 581182 67131 581238 67140 +rect 581090 64244 581146 64253 +rect 581090 64179 581146 64188 +rect 581932 56817 581960 84118 +rect 582024 62777 582052 84254 +rect 582104 84244 582156 84250 +rect 582104 84186 582156 84192 +rect 582010 62768 582066 62777 +rect 582010 62703 582066 62712 +rect 581918 56808 581974 56817 +rect 581918 56743 581974 56752 +rect 582116 55321 582144 84186 +rect 582208 61305 582236 84322 +rect 582300 68701 582328 84390 +rect 583680 82326 583708 118798 +rect 596180 95396 596232 95402 +rect 596180 95338 596232 95344 +rect 586428 84652 586480 84658 +rect 586428 84594 586480 84600 +rect 583852 84584 583904 84590 +rect 583852 84526 583904 84532 +rect 583760 84516 583812 84522 +rect 583760 84458 583812 84464 +rect 583668 82320 583720 82326 +rect 583668 82262 583720 82268 +rect 582286 68692 582342 68701 +rect 582286 68627 582342 68636 +rect 583668 66292 583720 66298 +rect 583668 66234 583720 66240 +rect 582194 61296 582250 61305 +rect 582194 61231 582250 61240 +rect 583680 60790 583708 66234 +rect 583668 60784 583720 60790 +rect 583668 60726 583720 60732 +rect 583772 60518 583800 84458 +rect 583760 60512 583812 60518 +rect 583760 60454 583812 60460 +rect 583864 58682 583892 84526 +rect 586440 66230 586468 84594 +rect 596192 80850 596220 95338 +rect 591948 80844 592000 80850 +rect 591948 80786 592000 80792 +rect 596180 80844 596232 80850 +rect 596180 80786 596232 80792 +rect 590660 73160 590712 73166 +rect 590660 73102 590712 73108 +rect 590672 66298 590700 73102 +rect 590660 66292 590712 66298 +rect 590660 66234 590712 66240 +rect 586428 66224 586480 66230 +rect 586428 66166 586480 66172 +rect 590660 64864 590712 64870 +rect 590660 64806 590712 64812 +rect 583852 58676 583904 58682 +rect 583852 58618 583904 58624 +rect 582564 58132 582616 58138 +rect 582564 58074 582616 58080 +rect 582102 55312 582158 55321 +rect 582102 55247 582158 55256 +rect 580906 53816 580962 53825 +rect 580906 53751 580962 53760 +rect 582576 53650 582604 58074 +rect 590672 58002 590700 64806 +rect 590752 62144 590804 62150 +rect 590752 62086 590804 62092 +rect 590764 58002 590792 62086 +rect 591960 58138 591988 80786 +rect 597366 76678 597394 219266 +rect 607128 218204 607180 218210 +rect 607128 218146 607180 218152 +rect 606668 218136 606720 218142 +rect 606668 218078 606720 218084 +rect 599768 215620 599820 215626 +rect 599768 215562 599820 215568 rect 599124 209840 599176 209846 rect 599124 209782 599176 209788 rect 599136 205465 599164 209782 @@ -42104,6 +42243,12 @@ rect 636384 216038 636436 216044 rect 636396 210202 636424 216038 rect 636948 210202 636976 220895 rect 637408 210202 637436 221031 +rect 648528 219768 648580 219774 +rect 648528 219710 648580 219716 +rect 647148 219700 647200 219706 +rect 647148 219642 647200 219648 +rect 639200 219324 639252 219330 +rect 639200 219266 639252 219272 rect 637856 216164 637908 216170 rect 637856 216106 637908 216112 rect 637868 210202 637896 216106 @@ -42183,29 +42328,7 @@ rect 637376 210174 637436 210202 rect 637836 210174 637896 210202 rect 638296 210174 638356 210202 rect 638756 210174 638816 210202 -rect 639212 210090 639240 271901 -rect 642744 269249 642772 277780 -rect 642730 269240 642786 269249 -rect 642730 269175 642786 269184 -rect 643940 269113 643968 277780 -rect 645136 271969 645164 277780 -rect 645122 271960 645178 271969 -rect 645122 271895 645178 271904 -rect 646332 271833 646360 277780 -rect 646318 271824 646374 271833 -rect 646318 271759 646374 271768 -rect 647528 269210 647556 277780 -rect 647516 269204 647568 269210 -rect 647516 269146 647568 269152 -rect 648724 269142 648752 277780 -rect 648712 269136 648764 269142 -rect 643926 269104 643982 269113 -rect 648712 269078 648764 269084 -rect 643926 269039 643982 269048 -rect 648528 219768 648580 219774 -rect 648528 219710 648580 219716 -rect 647148 219700 647200 219706 -rect 647148 219642 647200 219648 +rect 639212 210090 639240 219266 rect 646964 218000 647016 218006 rect 646964 217942 647016 217948 rect 642732 217932 642784 217938 @@ -43113,8 +43236,6 @@ rect 599952 149116 600004 149122 rect 599952 149058 600004 149064 rect 599858 148336 599914 148345 rect 599858 148271 599914 148280 -rect 582622 146822 582682 146831 -rect 582622 146753 582682 146762 rect 599872 146334 599900 148271 rect 599950 147384 600006 147393 rect 599950 147319 600006 147328 @@ -43193,9 +43314,7 @@ rect 600056 132530 600084 135079 rect 600044 132524 600096 132530 rect 600044 132466 600096 132472 rect 599858 132016 599914 132025 -rect 582286 131976 582342 131985 rect 599858 131951 599914 131960 -rect 582286 131911 582342 131920 rect 599766 131064 599822 131073 rect 599766 130999 599822 131008 rect 599780 129946 599808 130999 @@ -43210,9 +43329,7 @@ rect 599964 129810 599992 129911 rect 599952 129804 600004 129810 rect 599952 129746 600004 129752 rect 599858 129024 599914 129033 -rect 581918 128984 581974 128993 rect 599858 128959 599914 128968 -rect 581918 128919 581974 128928 rect 599872 127022 599900 128959 rect 599950 127936 600006 127945 rect 599950 127871 600006 127880 @@ -43223,40 +43340,6 @@ rect 599860 127016 599912 127022 rect 599766 126984 599822 126993 rect 599860 126958 599912 126964 rect 599766 126919 599822 126928 -rect 582288 124364 582340 124370 -rect 582288 124306 582340 124312 -rect 582012 124296 582064 124302 -rect 582012 124238 582064 124244 -rect 581920 121576 581972 121582 -rect 581920 121518 581972 121524 -rect 581828 118788 581880 118794 -rect 581828 118730 581880 118736 -rect 581734 118376 581790 118385 -rect 581734 118311 581790 118320 -rect 581642 116880 581698 116889 -rect 581642 116815 581698 116824 -rect 581736 116068 581788 116074 -rect 581736 116010 581788 116016 -rect 581644 113280 581696 113286 -rect 581644 113222 581696 113228 -rect 581550 80792 581606 80801 -rect 581550 80727 581606 80736 -rect 581458 76208 581514 76217 -rect 581458 76143 581514 76152 -rect 581656 74721 581684 113222 -rect 581748 79369 581776 116010 -rect 581840 83793 581868 118730 -rect 581932 85289 581960 121518 -rect 582024 89833 582052 124238 -rect 582104 121644 582156 121650 -rect 582104 121586 582156 121592 -rect 582010 89824 582066 89833 -rect 582010 89759 582066 89768 -rect 582116 86785 582144 121586 -rect 582196 121508 582248 121514 -rect 582196 121450 582248 121456 -rect 582208 88281 582236 121450 -rect 582300 91369 582328 124306 rect 599780 124234 599808 126919 rect 600042 125896 600098 125905 rect 600042 125831 600098 125840 @@ -43290,50 +43373,8 @@ rect 600042 120799 600098 120808 rect 599950 119776 600006 119785 rect 599950 119711 600006 119720 rect 599964 118862 599992 119711 -rect 583668 118856 583720 118862 rect 599952 118856 600004 118862 -rect 583668 118798 583720 118804 rect 599858 118824 599914 118833 -rect 582286 91360 582342 91369 -rect 582286 91295 582342 91304 -rect 582194 88272 582250 88281 -rect 582194 88207 582250 88216 -rect 582102 86776 582158 86785 -rect 582102 86711 582158 86720 -rect 581918 85280 581974 85289 -rect 581918 85215 581974 85224 -rect 582288 84448 582340 84454 -rect 582288 84390 582340 84396 -rect 582196 84380 582248 84386 -rect 582196 84322 582248 84328 -rect 582012 84312 582064 84318 -rect 582012 84254 582064 84260 -rect 581920 84176 581972 84182 -rect 581920 84118 581972 84124 -rect 581826 83784 581882 83793 -rect 581826 83719 581882 83728 -rect 581734 79360 581790 79369 -rect 581734 79295 581790 79304 -rect 581642 74712 581698 74721 -rect 581642 74647 581698 74656 -rect 581366 71720 581422 71729 -rect 581366 71655 581422 71664 -rect 581182 67196 581238 67205 -rect 581182 67131 581238 67140 -rect 581090 64244 581146 64253 -rect 581090 64179 581146 64188 -rect 581932 56817 581960 84118 -rect 582024 62777 582052 84254 -rect 582104 84244 582156 84250 -rect 582104 84186 582156 84192 -rect 582010 62768 582066 62777 -rect 582010 62703 582066 62712 -rect 581918 56808 581974 56817 -rect 581918 56743 581974 56752 -rect 582116 55321 582144 84186 -rect 582208 61305 582236 84322 -rect 582300 68701 582328 84390 -rect 583680 82326 583708 118798 rect 599952 118798 600004 118804 rect 600056 118794 600084 120799 rect 599858 118759 599914 118768 @@ -43389,31 +43430,6 @@ rect 599950 100399 600006 100408 rect 599964 99414 599992 100399 rect 599952 99408 600004 99414 rect 599952 99350 600004 99356 -rect 596180 95396 596232 95402 -rect 596180 95338 596232 95344 -rect 586428 84652 586480 84658 -rect 586428 84594 586480 84600 -rect 583852 84584 583904 84590 -rect 583852 84526 583904 84532 -rect 583760 84516 583812 84522 -rect 583760 84458 583812 84464 -rect 583668 82320 583720 82326 -rect 583668 82262 583720 82268 -rect 582286 68692 582342 68701 -rect 582286 68627 582342 68636 -rect 583668 66292 583720 66298 -rect 583668 66234 583720 66240 -rect 582194 61296 582250 61305 -rect 582194 61231 582250 61240 -rect 583680 60790 583708 66234 -rect 583668 60784 583720 60790 -rect 583668 60726 583720 60732 -rect 583772 60518 583800 84458 -rect 583760 60512 583812 60518 -rect 583760 60454 583812 60460 -rect 583864 58682 583892 84526 -rect 586440 66230 586468 84594 -rect 596192 80850 596220 95338 rect 600240 84454 600268 110599 rect 600318 108624 600374 108633 rect 600318 108559 600374 108568 @@ -43463,37 +43479,13 @@ rect 601700 91044 601752 91050 rect 601700 90986 601752 90992 rect 600872 84176 600924 84182 rect 600872 84118 600924 84124 -rect 591948 80844 592000 80850 -rect 591948 80786 592000 80792 -rect 596180 80844 596232 80850 -rect 596180 80786 596232 80792 -rect 590660 73160 590712 73166 -rect 590660 73102 590712 73108 -rect 590672 66298 590700 73102 -rect 590660 66292 590712 66298 -rect 590660 66234 590712 66240 -rect 586428 66224 586480 66230 -rect 586428 66166 586480 66172 -rect 590660 64864 590712 64870 -rect 590660 64806 590712 64812 -rect 583852 58676 583904 58682 -rect 583852 58618 583904 58624 -rect 582564 58132 582616 58138 -rect 582564 58074 582616 58080 -rect 582102 55312 582158 55321 -rect 582102 55247 582158 55256 -rect 580906 53816 580962 53825 -rect 580906 53751 580962 53760 -rect 582576 53650 582604 58074 -rect 590672 58002 590700 64806 -rect 590752 62144 590804 62150 -rect 590752 62086 590804 62092 -rect 590764 58002 590792 62086 -rect 591960 58138 591988 80786 rect 601712 80186 601740 90986 rect 601620 80158 601740 80186 rect 600228 78532 600280 78538 rect 600228 78474 600280 78480 +rect 597354 76672 597406 76678 +rect 597354 76614 597406 76620 +rect 597366 76610 597394 76614 rect 600044 74520 600096 74526 rect 600044 74462 600096 74468 rect 598940 69080 598992 69086 @@ -43922,22 +43914,17 @@ rect 618260 76990 618312 76996 rect 618260 76932 618312 76938 rect 613016 76822 613068 76828 rect 613016 76764 613068 76770 -rect 622308 76672 622360 76678 -rect 622308 76614 622360 76620 +rect 628168 76494 628196 77692 +rect 622876 76488 622928 76494 +rect 622876 76430 622928 76436 +rect 628156 76488 628208 76494 +rect 628156 76430 628208 76436 rect 610256 45892 610308 45898 rect 610256 45834 610308 45840 rect 607588 45756 607640 45762 rect 607588 45698 607640 45704 rect 607220 43988 607272 43994 rect 607220 43930 607272 43936 -rect 622320 43382 622348 76614 -rect 628168 76494 628196 77692 -rect 622876 76488 622928 76494 -rect 622876 76430 622928 76436 -rect 628156 76488 628208 76494 -rect 628156 76430 628208 76436 -rect 622308 43376 622360 43382 -rect 622308 43318 622360 43324 rect 622888 43314 622916 76430 rect 623734 75430 623786 75436 rect 623734 75372 623786 75378 @@ -49898,8 +49885,11 @@ rect 635646 274624 635702 274680 rect 629758 269456 629814 269512 rect 638038 274488 638094 274544 rect 640430 272040 640486 272096 -rect 639196 271910 639256 271970 rect 636842 269320 636898 269376 +rect 642730 269184 642786 269240 +rect 645122 271904 645178 271960 +rect 646318 271768 646374 271824 +rect 643926 269048 643982 269104 rect 616786 266328 616842 266384 rect 581274 266192 581330 266248 rect 577778 266056 577834 266112 @@ -49912,9 +49902,7 @@ rect 184938 258576 184994 258632 rect 416778 255856 416834 255912 rect 416778 252728 416834 252784 rect 416778 249464 416834 249520 -rect 184938 247968 184994 248024 -rect 416778 246336 416834 246392 -rect 418066 243072 418122 243128 +rect 191212 247968 191272 248028 rect 184938 237396 184940 237416 rect 184940 237396 184992 237416 rect 184992 237396 184994 237416 @@ -49964,6 +49952,8 @@ rect 115754 224304 115810 224360 rect 118330 221448 118386 221504 rect 120814 224032 120870 224088 rect 121366 221584 121422 221640 +rect 416778 246336 416834 246392 +rect 418066 243072 418122 243128 rect 192574 224984 192630 225040 rect 193678 224848 193734 224904 rect 193310 222128 193366 222184 @@ -50256,6 +50246,30 @@ rect 582102 155968 582158 156024 rect 582010 136424 582066 136480 rect 582194 134928 582250 134984 rect 582102 133416 582158 133472 +rect 582622 146762 582682 146822 +rect 582286 131920 582342 131976 +rect 581918 128928 581974 128984 +rect 581734 118320 581790 118376 +rect 581642 116824 581698 116880 +rect 581550 80736 581606 80792 +rect 581458 76152 581514 76208 +rect 582010 89768 582066 89824 +rect 582286 91304 582342 91360 +rect 582194 88216 582250 88272 +rect 582102 86720 582158 86776 +rect 581918 85224 581974 85280 +rect 581826 83728 581882 83784 +rect 581734 79304 581790 79360 +rect 581642 74656 581698 74712 +rect 581366 71664 581422 71720 +rect 581182 67140 581238 67196 +rect 581090 64188 581146 64244 +rect 582010 62712 582066 62768 +rect 581918 56752 581974 56808 +rect 582286 68636 582342 68692 +rect 582194 61240 582250 61296 +rect 582102 55256 582158 55312 +rect 580906 53760 580962 53816 rect 599766 209480 599822 209536 rect 627090 221856 627146 221912 rect 625250 221720 625306 221776 @@ -50265,10 +50279,6 @@ rect 621478 221176 621534 221232 rect 624330 221448 624386 221504 rect 637394 221040 637450 221096 rect 636934 220904 636990 220960 -rect 642730 269184 642786 269240 -rect 645122 271904 645178 271960 -rect 646318 271768 646374 271824 -rect 643926 269048 643982 269104 rect 655518 975840 655574 975896 rect 655702 962512 655758 962568 rect 655794 949320 655850 949376 @@ -50409,7 +50419,6 @@ rect 598938 151408 598994 151464 rect 599858 150320 599914 150376 rect 599950 149368 600006 149424 rect 599858 148280 599914 148336 -rect 582622 146762 582682 146822 rect 599950 147328 600006 147384 rect 600042 146240 600098 146296 rect 599858 145288 599914 145344 @@ -50428,19 +50437,12 @@ rect 599950 136040 600006 136096 rect 600042 135088 600098 135144 rect 599858 134000 599914 134056 rect 599950 133048 600006 133104 -rect 582286 131920 582342 131976 rect 599858 131960 599914 132016 rect 599766 131008 599822 131064 rect 599950 129920 600006 129976 -rect 581918 128928 581974 128984 rect 599858 128968 599914 129024 rect 599950 127880 600006 127936 rect 599766 126928 599822 126984 -rect 581734 118320 581790 118376 -rect 581642 116824 581698 116880 -rect 581550 80736 581606 80792 -rect 581458 76152 581514 76208 -rect 582010 89768 582066 89824 rect 600042 125840 600098 125896 rect 599950 124888 600006 124944 rect 600042 123800 600098 123856 @@ -50448,18 +50450,6 @@ rect 599858 122848 599914 122904 rect 599950 121760 600006 121816 rect 600042 120808 600098 120864 rect 599950 119720 600006 119776 -rect 582286 91304 582342 91360 -rect 582194 88216 582250 88272 -rect 582102 86720 582158 86776 -rect 581918 85224 581974 85280 -rect 581826 83728 581882 83784 -rect 581734 79304 581790 79360 -rect 581642 74656 581698 74712 -rect 581366 71664 581422 71720 -rect 581182 67140 581238 67196 -rect 581090 64188 581146 64244 -rect 582010 62712 582066 62768 -rect 581918 56752 581974 56808 rect 599858 118768 599914 118824 rect 599858 117680 599914 117736 rect 599950 116728 600006 116784 @@ -50471,8 +50461,6 @@ rect 600226 110608 600282 110664 rect 599950 109520 600006 109576 rect 599950 107480 600006 107536 rect 599950 100408 600006 100464 -rect 582286 68636 582342 68692 -rect 582194 61240 582250 61296 rect 600318 108568 600374 108624 rect 600594 106528 600650 106584 rect 600410 105440 600466 105496 @@ -50480,8 +50468,6 @@ rect 600502 103400 600558 103456 rect 600686 104488 600742 104544 rect 600870 102448 600926 102504 rect 600778 101360 600834 101416 -rect 582102 55256 582158 55312 -rect 580906 53760 580962 53816 rect 571338 41928 571394 41984 rect 563610 41656 563666 41712 rect 622122 85992 622178 86048 @@ -58358,7 +58344,6 @@ rect 640486 272040 640491 272096 rect 408769 272038 640491 272040 rect 408769 272035 408835 272038 rect 640425 272035 640491 272038 -rect 639191 271970 639261 271975 rect 76465 271962 76531 271965 rect 196341 271962 196407 271965 rect 76465 271960 196407 271962 @@ -58369,15 +58354,10 @@ rect 76465 271902 196407 271904 rect 76465 271899 76531 271902 rect 196341 271899 196407 271902 rect 410517 271962 410583 271965 -rect 639191 271962 639196 271970 -rect 410517 271960 639196 271962 -rect 410517 271904 410522 271960 -rect 410578 271910 639196 271960 -rect 639256 271962 639261 271970 rect 645117 271962 645183 271965 -rect 639256 271960 645183 271962 -rect 639256 271910 645122 271960 -rect 410578 271904 645122 271910 +rect 410517 271960 645183 271962 +rect 410517 271904 410522 271960 +rect 410578 271904 645122 271960 rect 645178 271904 645183 271960 rect 410517 271902 645183 271904 rect 410517 271899 410583 271902 @@ -59269,12 +59249,13 @@ rect 38285 248104 38290 248160 rect 38346 248104 38394 248160 rect 38285 248102 38394 248104 rect 38285 248099 38351 248102 -rect 184933 248026 184999 248029 -rect 184933 248024 191820 248026 -rect 184933 247968 184938 248024 -rect 184994 247968 191820 248024 -rect 184933 247966 191820 247968 -rect 184933 247963 184999 247966 +rect 191207 248028 191277 248033 +rect 191207 248026 191212 248028 +rect 191190 247968 191212 248026 +rect 191272 248026 191277 248028 +rect 191272 247968 191820 248026 +rect 191190 247966 191820 247968 +rect 191207 247963 191277 247966 rect 41462 247757 41522 247860 rect 41462 247752 41571 247757 rect 41462 247696 41510 247752 @@ -64836,11 +64817,11 @@ timestamp 1636248654 transform 1 0 149582 0 1 16298 box -262 -9464 35048 2764 use caravel_clocking clocking -timestamp 1638492834 +timestamp 1638662845 transform 1 0 626764 0 1 63284 box -38 -48 20000 12000 use housekeeping housekeeping -timestamp 1638492834 +timestamp 1638835791 transform 1 0 606434 0 1 100002 box 0 0 60046 110190 use digital_pll pll @@ -64879,6 +64860,10 @@ use gpio_defaults_block_1803 gpio_defaults_block_1 timestamp 1638492834 transform -1 0 709467 0 1 179200 box -38 0 6018 2224 +use mgmt_protect mgmt_buffers +timestamp 1638030917 +transform 1 0 192180 0 1 232036 +box -400 -400 220400 32400 use gpio_control_block gpio_control_bidir_2\[1\] timestamp 1638492834 transform 1 0 7631 0 1 245800 @@ -64895,10 +64880,6 @@ use spare_logic_block spare_logic_block_1 timestamp 1638492834 transform 1 0 168632 0 1 232528 box 0 0 9000 9000 -use mgmt_protect mgmt_buffers -timestamp 1638492834 -transform 1 0 192180 0 1 232036 -box -400 -400 220400 32400 use spare_logic_block spare_logic_block_2 timestamp 1638492834 transform 1 0 428632 0 1 232528 @@ -64991,200 +64972,200 @@ use gpio_defaults_block gpio_defaults_block_7 timestamp 1638492834 transform -1 0 709467 0 1 492800 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_2\[11\] -timestamp 1638492834 -transform 1 0 7631 0 1 589400 -box 882 167 34000 13000 -use gpio_control_block gpio_control_in_2\[12\] -timestamp 1638492834 -transform 1 0 7631 0 1 546200 -box 882 167 34000 13000 -use gpio_defaults_block gpio_defaults_block_31 -timestamp 1638492834 -transform 1 0 8367 0 1 559200 -box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_30 timestamp 1638492834 transform 1 0 8367 0 1 602400 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_1\[0\] +use gpio_defaults_block gpio_defaults_block_31 timestamp 1638492834 -transform -1 0 710203 0 1 523800 -box 882 167 34000 13000 -use gpio_control_block gpio_control_in_1\[1\] -timestamp 1638492834 -transform -1 0 710203 0 1 568800 -box 882 167 34000 13000 -use gpio_defaults_block gpio_defaults_block_8 -timestamp 1638492834 -transform -1 0 709467 0 1 536800 +transform 1 0 8367 0 1 559200 box -38 0 6018 2224 +use gpio_control_block gpio_control_in_2\[12\] +timestamp 1638492834 +transform 1 0 7631 0 1 546200 +box 882 167 34000 13000 +use gpio_control_block gpio_control_in_2\[11\] +timestamp 1638492834 +transform 1 0 7631 0 1 589400 +box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_9 timestamp 1638492834 transform -1 0 709467 0 1 581800 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_2\[10\] +use gpio_defaults_block gpio_defaults_block_8 timestamp 1638492834 -transform 1 0 7631 0 1 632600 -box 882 167 34000 13000 -use gpio_control_block gpio_control_in_2\[9\] -timestamp 1638492834 -transform 1 0 7631 0 1 675800 -box 882 167 34000 13000 -use gpio_defaults_block gpio_defaults_block_29 -timestamp 1638492834 -transform 1 0 8367 0 1 645600 +transform -1 0 709467 0 1 536800 box -38 0 6018 2224 +use gpio_control_block gpio_control_in_1\[1\] +timestamp 1638492834 +transform -1 0 710203 0 1 568800 +box 882 167 34000 13000 +use gpio_control_block gpio_control_in_1\[0\] +timestamp 1638492834 +transform -1 0 710203 0 1 523800 +box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_28 timestamp 1638492834 transform 1 0 8367 0 1 688800 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_1\[2\] +use gpio_defaults_block gpio_defaults_block_29 timestamp 1638492834 -transform -1 0 710203 0 1 614000 -box 882 167 34000 13000 -use gpio_control_block gpio_control_in_1\[3\] -timestamp 1638492834 -transform -1 0 710203 0 1 659000 -box 882 167 34000 13000 -use gpio_defaults_block gpio_defaults_block_10 -timestamp 1638492834 -transform -1 0 709467 0 1 627000 +transform 1 0 8367 0 1 645600 box -38 0 6018 2224 +use gpio_control_block gpio_control_in_2\[9\] +timestamp 1638492834 +transform 1 0 7631 0 1 675800 +box 882 167 34000 13000 +use gpio_control_block gpio_control_in_2\[10\] +timestamp 1638492834 +transform 1 0 7631 0 1 632600 +box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_11 timestamp 1638492834 transform -1 0 709467 0 1 672000 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_2\[7\] +use gpio_defaults_block gpio_defaults_block_10 timestamp 1638492834 -transform 1 0 7631 0 1 762200 -box 882 167 34000 13000 -use gpio_control_block gpio_control_in_2\[8\] -timestamp 1638492834 -transform 1 0 7631 0 1 719000 -box 882 167 34000 13000 -use gpio_defaults_block gpio_defaults_block_27 -timestamp 1638492834 -transform 1 0 8367 0 1 732000 +transform -1 0 709467 0 1 627000 box -38 0 6018 2224 +use gpio_control_block gpio_control_in_1\[3\] +timestamp 1638492834 +transform -1 0 710203 0 1 659000 +box 882 167 34000 13000 +use gpio_control_block gpio_control_in_1\[2\] +timestamp 1638492834 +transform -1 0 710203 0 1 614000 +box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_26 timestamp 1638492834 transform 1 0 8367 0 1 775200 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_1\[4\] +use gpio_defaults_block gpio_defaults_block_27 timestamp 1638492834 -transform -1 0 710203 0 1 704200 -box 882 167 34000 13000 -use gpio_control_block gpio_control_in_1\[5\] -timestamp 1638492834 -transform -1 0 710203 0 1 749200 -box 882 167 34000 13000 -use gpio_defaults_block gpio_defaults_block_12 -timestamp 1638492834 -transform -1 0 709467 0 1 717200 +transform 1 0 8367 0 1 732000 box -38 0 6018 2224 +use gpio_control_block gpio_control_in_2\[8\] +timestamp 1638492834 +transform 1 0 7631 0 1 719000 +box 882 167 34000 13000 +use gpio_control_block gpio_control_in_2\[7\] +timestamp 1638492834 +transform 1 0 7631 0 1 762200 +box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_13 timestamp 1638492834 transform -1 0 709467 0 1 762200 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_2\[6\] +use gpio_defaults_block gpio_defaults_block_12 timestamp 1638492834 -transform 1 0 7631 0 1 805400 +transform -1 0 709467 0 1 717200 +box -38 0 6018 2224 +use gpio_control_block gpio_control_in_1\[5\] +timestamp 1638492834 +transform -1 0 710203 0 1 749200 +box 882 167 34000 13000 +use gpio_control_block gpio_control_in_1\[4\] +timestamp 1638492834 +transform -1 0 710203 0 1 704200 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_25 timestamp 1638492834 transform 1 0 8367 0 1 818400 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_2\[5\] +use gpio_control_block gpio_control_in_2\[6\] timestamp 1638492834 -transform 1 0 7631 0 1 931200 +transform 1 0 7631 0 1 805400 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_24 timestamp 1638492834 transform 1 0 8367 0 1 944200 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_1\[6\] +use gpio_control_block gpio_control_in_2\[5\] timestamp 1638492834 -transform -1 0 710203 0 1 927600 +transform 1 0 7631 0 1 931200 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_14 timestamp 1638492834 transform -1 0 709467 0 1 940600 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_2\[3\] +use gpio_control_block gpio_control_in_1\[6\] timestamp 1638492834 -transform 0 1 148600 -1 0 1030077 +transform -1 0 710203 0 1 927600 box 882 167 34000 13000 -use gpio_control_block gpio_control_in_2\[4\] -timestamp 1638492834 -transform 0 1 97200 -1 0 1030077 -box 882 167 34000 13000 -use gpio_defaults_block gpio_defaults_block_23 -timestamp 1638492834 -transform 0 1 110194 -1 0 1029341 -box -38 0 6018 2224 use gpio_defaults_block gpio_defaults_block_22 timestamp 1638492834 transform 0 1 161594 -1 0 1029341 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_2\[1\] +use gpio_defaults_block gpio_defaults_block_23 timestamp 1638492834 -transform 0 1 251400 -1 0 1030077 +transform 0 1 110194 -1 0 1029341 +box -38 0 6018 2224 +use gpio_control_block gpio_control_in_2\[4\] +timestamp 1638492834 +transform 0 1 97200 -1 0 1030077 box 882 167 34000 13000 -use gpio_control_block gpio_control_in_2\[2\] +use gpio_control_block gpio_control_in_2\[3\] timestamp 1638492834 -transform 0 1 200000 -1 0 1030077 +transform 0 1 148600 -1 0 1030077 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_21 timestamp 1638492834 transform 0 1 212994 -1 0 1029341 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_2\[0\] +use gpio_control_block gpio_control_in_2\[2\] timestamp 1638492834 -transform 0 1 303000 -1 0 1030077 +transform 0 1 200000 -1 0 1030077 box 882 167 34000 13000 -use gpio_defaults_block gpio_defaults_block_20 +use gpio_control_block gpio_control_in_2\[1\] timestamp 1638492834 -transform 0 1 264394 -1 0 1029341 -box -38 0 6018 2224 +transform 0 1 251400 -1 0 1030077 +box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_19 timestamp 1638492834 transform 0 1 315994 -1 0 1029341 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_1\[10\] +use gpio_defaults_block gpio_defaults_block_20 timestamp 1638492834 -transform 0 1 353400 -1 0 1030077 -box 882 167 34000 13000 -use gpio_control_block gpio_control_in_1\[9\] -timestamp 1638492834 -transform 0 1 420800 -1 0 1030077 -box 882 167 34000 13000 -use gpio_defaults_block gpio_defaults_block_18 -timestamp 1638492834 -transform 0 1 366394 -1 0 1029341 +transform 0 1 264394 -1 0 1029341 box -38 0 6018 2224 +use gpio_control_block gpio_control_in_2\[0\] +timestamp 1638492834 +transform 0 1 303000 -1 0 1030077 +box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_17 timestamp 1638492834 transform 0 1 433794 -1 0 1029341 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_1\[8\] +use gpio_defaults_block gpio_defaults_block_18 timestamp 1638492834 -transform 0 1 497800 -1 0 1030077 +transform 0 1 366394 -1 0 1029341 +box -38 0 6018 2224 +use gpio_control_block gpio_control_in_1\[9\] +timestamp 1638492834 +transform 0 1 420800 -1 0 1030077 +box 882 167 34000 13000 +use gpio_control_block gpio_control_in_1\[10\] +timestamp 1638492834 +transform 0 1 353400 -1 0 1030077 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_16 timestamp 1638492834 transform 0 1 510794 -1 0 1029341 box -38 0 6018 2224 -use gpio_control_block gpio_control_in_1\[7\] +use gpio_control_block gpio_control_in_1\[8\] timestamp 1638492834 -transform 0 1 549200 -1 0 1030077 +transform 0 1 497800 -1 0 1030077 box 882 167 34000 13000 use gpio_defaults_block gpio_defaults_block_15 timestamp 1638492834 transform 0 1 562194 -1 0 1029341 box -38 0 6018 2224 -use chip_io padframe +use gpio_control_block gpio_control_in_1\[7\] timestamp 1638492834 +transform 0 1 549200 -1 0 1030077 +box 882 167 34000 13000 +use chip_io padframe +timestamp 1638030917 transform 1 0 0 0 1 0 box 0 0 717600 1037600 use caravel_power_routing caravel_power_routing_0 diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll.c b/verilog/dv/caravel/mgmt_soc/pll/pll.c index 81a1fc66..978b53e3 100644 --- a/verilog/dv/caravel/mgmt_soc/pll/pll.c +++ b/verilog/dv/caravel/mgmt_soc/pll/pll.c @@ -21,12 +21,9 @@ /* * PLL Test (self-switching) - * - Enables SPI master - * - Uses SPI master to internally access the housekeeping SPI - * - Switches PLL bypass - * - Changes PLL divider + * - Switches PLL bypass in housekeeping + * - Changes PLL divider in housekeeping * - * Tesbench mostly copied from sysctrl */ void main() { @@ -54,67 +51,89 @@ void main() reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + /* Monitor pins must be set to output */ + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + /* Apply configuration */ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); // Start test + + /* + *------------------------------------------------------------- + * Register 2610_000c reg_hkspi_pll_ena + * SPI address 0x08 = PLL enables + * bit 0 = PLL enable, bit 1 = DCO enable + * + * Register 2610_0010 reg_hkspi_pll_bypass + * SPI address 0x09 = PLL bypass + * bit 0 = PLL bypass + * + * Register 2610_0020 reg_hkspi_pll_source + * SPI address 0x11 = PLL source + * bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider + * + * Register 2610_0024 reg_hkspi_pll_divider + * SPI address 0x12 = PLL divider + * bits 0-4 = feedback divider + * + * Register 2620_0004 reg_clk_out_dest + * SPI address 0x1b = Output redirect + * bit 0 = trap to mprj_io[13] + * bit 1 = clk to mprj_io[14] + * bit 2 = clk2 to mprj_io[15] + *------------------------------------------------------------- + */ + + // Monitor the core clock and user clock on mprj_io[14] and mprj_io[15] + // reg_clk_out_dest = 0x6 to turn on, 0x0 to turn off + + // Write checkpoint for clock counting (PLL bypassed) reg_mprj_datal = 0xA0400000; - - // Enable SPI master - // SPI master configuration bits: - // bits 7-0: Clock prescaler value (default 2) - // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first) - // bit 9: CSB sense (0 = inverted, 1 = noninverted) - // bit 10: SCK sense (0 = noninverted, 1 = inverted) - // bit 11: mode (0 = read/write opposite edges, 1 = same edges) - // bit 12: stream (1 = CSB ends transmission) - // bit 13: enable (1 = enabled) - // bit 14: IRQ enable (1 = enabled) - // bit 15: Connect to housekeeping SPI (1 = connected) - - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, - // connect to housekeeping SPI - - // Apply stream read (0x40 + 0x03) and read back one byte - - reg_spimaster_config = 0xb002; // Apply stream mode - reg_spimaster_data = 0x80; // Write 0x80 (write mode) - reg_spimaster_data = 0x08; // Write 0x18 (start address) - reg_spimaster_data = 0x01; // Write 0x01 to PLL enable, no DCO mode - reg_spimaster_config = 0xa102; // Release CSB (ends stream mode) - - reg_spimaster_config = 0xb002; // Apply stream mode - reg_spimaster_data = 0x80; // Write 0x80 (write mode) - reg_spimaster_data = 0x11; // Write 0x11 (start address) - reg_spimaster_data = 0x03; // Write 0x03 to PLL output divider - reg_spimaster_config = 0xa102; // Release CSB (ends stream mode) - - reg_spimaster_config = 0xb002; // Apply stream mode - reg_spimaster_data = 0x80; // Write 0x80 (write mode) - reg_spimaster_data = 0x09; // Write 0x09 (start address) - reg_spimaster_data = 0x00; // Write 0x00 to clock from PLL (no bypass) - reg_spimaster_config = 0xa102; // Release CSB (ends stream mode) - - // Write checkpoint + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; reg_mprj_datal = 0xA0410000; - reg_spimaster_config = 0xb002; // Apply stream mode - reg_spimaster_data = 0x80; // Write 0x80 (write mode) - reg_spimaster_data = 0x12; // Write 0x12 (start address) - reg_spimaster_data = 0x03; // Write 0x03 to feedback divider (was 0x04) - reg_spimaster_config = 0xa102; // Release CSB (ends stream mode) + // Set PLL enable, no DCO mode + reg_hkspi_pll_ena = 0x1; + + // Set PLL output divider to 0x03 + reg_hkspi_pll_source = 0x3; + + // Write checkpoint for clock counting (PLL bypassed) + reg_mprj_datal = 0xA0420000; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; + reg_mprj_datal = 0xA0430000; + + // Disable PLL bypass + reg_hkspi_pll_bypass = 0x0; + + // Write checkpoint for clock counting + reg_mprj_datal = 0xA0440000; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; + reg_mprj_datal = 0xA0450000; + + // Write 0x03 to feedback divider (was 0x04) + reg_hkspi_pll_divider = 0x3; // Write checkpoint - reg_mprj_datal = 0xA0420000; + reg_mprj_datal = 0xA0460000; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; + reg_mprj_datal = 0xA0470000; - reg_spimaster_config = 0xb002; // Apply stream mode - reg_spimaster_data = 0x80; // Write 0x80 (write mode) - reg_spimaster_data = 0x11; // Write 0x11 (start address) - reg_spimaster_data = 0x04; // Write 0x04 to PLL output divider - reg_spimaster_config = 0xa102; // Release CSB (ends stream mode) + // Write 0x04 to PLL output divider + reg_hkspi_pll_source = 0x4; - reg_spimaster_config = 0x2102; // Release housekeeping SPI + // Write checkpoint + reg_mprj_datal = 0xA0480000; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; + reg_mprj_datal = 0xA0490000; // End test reg_mprj_datal = 0xA0900000; diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v index 5c037b06..6d662c34 100644 --- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v +++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v @@ -37,6 +37,9 @@ module pll_tb; wire flash_io1; wire SDO; + integer ccount; + integer ucount; + assign checkbits = mprj_io[31:16]; assign spivalue = mprj_io[15:8]; @@ -46,6 +49,16 @@ module pll_tb; always #10 clock <= (clock === 1'b0); + // User clock monitoring + always @(posedge mprj_io[15]) begin + ucount = ucount + 1; + end + + // Core clock monitoring + always @(posedge mprj_io[14]) begin + ccount = ccount + 1; + end + initial begin clock = 0; end @@ -66,26 +79,64 @@ module pll_tb; // Monitor initial begin wait(checkbits == 16'hA040); - - $display("Monitor: Test PLL (RTL) Started"); - + $display("Monitor: Test 1 PLL (RTL) Started"); + ucount = 0; + ccount = 0; wait(checkbits == 16'hA041); - // $display(" SPI value = 0x%x (should be 0x04)", spivalue); - // if(spivalue !== 32'h04) begin - // $display("Monitor: Test PLL (RTL) Failed"); - // $finish; - // end + $display("Monitor: ucount = %d ccount = %d", ucount, ccount); + if (ucount !== 129 || ccount != 129) begin + $display("Monitor: Test PLL Failed"); + $finish; + end + wait(checkbits == 16'hA042); - // $display(" SPI value = 0x%x (should be 0x56)", spivalue); - // if(spivalue !== 32'h56) begin - // $display("Monitor: Test PLL (RTL) Failed"); - // $finish; - // end + $display("Monitor: Test 2 PLL (RTL) Started"); + ucount = 0; + ccount = 0; + wait(checkbits == 16'hA043); + $display("Monitor: ucount = %d ccount = %d", ucount, ccount); + if (ucount !== 193 || ccount != 193) begin + $display("Monitor: Test PLL Failed"); + $finish; + end + + wait(checkbits == 16'hA044); + $display("Monitor: Test 3 PLL (RTL) Started"); + ucount = 0; + ccount = 0; + wait(checkbits == 16'hA045); + $display("Monitor: ucount = %d ccount = %d", ucount, ccount); + if (ucount !== 385 || ccount != 129) begin + $display("Monitor: Test PLL Failed"); + $finish; + end + + wait(checkbits == 16'hA046); + $display("Monitor: Test 4 PLL (RTL) Started"); + ucount = 0; + ccount = 0; + wait(checkbits == 16'hA047); + $display("Monitor: ucount = %d ccount = %d", ucount, ccount); + if (ucount !== 385 || ccount != 129) begin + $display("Monitor: Test PLL Failed"); + $finish; + end + + wait(checkbits == 16'hA048); + $display("Monitor: Test 5 PLL (RTL) Started"); + ucount = 0; + ccount = 0; + wait(checkbits == 16'hA049); + $display("Monitor: ucount = %d ccount = %d", ucount, ccount); + if (ucount !== 513 || ccount != 129) begin + $display("Monitor: Test PLL Failed"); + $finish; + end wait(checkbits == 16'hA090); - $display("Monitor: Test PLL (RTL) Passed"); - $finish; + $display("Monitor: Test PLL (RTL) Passed"); + $finish; end initial begin diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c index a104729e..f55bc3f9 100644 --- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c +++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c @@ -20,39 +20,23 @@ // -------------------------------------------------------- /* - * System Control Test - * - Enables SPI master - * - Uses SPI master to internally access the housekeeping SPI - * - Reads default value of SPI-Controlled registers - * - Flags failure/success using mprj_io + * System control test + * - Sets GPIO to monitor the core and user clocks + * + * This test is basically just the first part of the + * PLL test, with the PLL bypassed. Unlike the PLL + * test, it can be run on a gate-level netlist. + * */ void main() { int i; - uint32_t value; - - // Force housekeeping SPI into a disabled state so that the CSB - // pin can be used as an output without the system failing - - reg_hkspi_disable = 1; reg_mprj_datal = 0; - // Configure upper 6 bits of user GPIO for generating testbench + // Configure upper 16 bits of user GPIO for generating testbench // checkpoints. - reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; - - // Configure all lower 32 bits for writing the SPI value read on GPIO - // NOTE: Converting reg_mprj_io_3 (CSB) to output will disable the - // SPI. But that should not disable the back-door access to the SPI - // register values! - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; @@ -70,71 +54,48 @@ void main() reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + /* Monitor pins must be set to output */ reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; /* Apply configuration */ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); // Start test - reg_mprj_datah = 0x04; - // Read manufacturer and product ID - value = reg_hkspi_chip_id; - reg_mprj_datal = value; // Mfgr + product ID - reg_mprj_datah = 0x05; + /* + *------------------------------------------------------------- + * Register 2620_0004 reg_clk_out_dest + * SPI address 0x1b = Output redirect + * bit 0 = trap to mprj_io[13] + * bit 1 = clk to mprj_io[14] + * bit 2 = clk2 to mprj_io[15] + *------------------------------------------------------------- + */ - // Read user ID - value = reg_hkspi_user_id; - reg_mprj_datal = value; // User ID - reg_mprj_datah = 0x06; + // Monitor the core clock and user clock on mprj_io[14] and mprj_io[15] + // reg_clk_out_dest = 0x6 to turn on, 0x0 to turn off - // Read PLL enables - value = reg_hkspi_pll_ena; - reg_mprj_datal = value; // DLL enables - reg_mprj_datah = 0x07; + // Write checkpoint for making sure nothing is counted when monitoring is off + reg_mprj_datal = 0xA0400000; + reg_clk_out_dest = 0x0; + reg_clk_out_dest = 0x0; + reg_mprj_datal = 0xA0410000; - // Read PLL bypass state - value = reg_hkspi_pll_bypass; - reg_mprj_datal = value; // DLL bypass state - reg_mprj_datah = 0x08; + // Write checkpoint for core clock counting (PLL bypassed) + reg_mprj_datal = 0xA0420000; + reg_clk_out_dest = 0x2; + reg_clk_out_dest = 0x0; + reg_mprj_datal = 0xA0430000; - // Read PLL trim - value = reg_hkspi_pll_trim; - reg_mprj_datal = value; // DLL trim - reg_mprj_datah = 0x09; - - // Read PLL source - value = reg_hkspi_pll_source; - reg_mprj_datal = value; // DLL source - reg_mprj_datah = 0x0a; - - // Read PLL divider - value = reg_hkspi_pll_divider; - reg_mprj_datal = value; // DLL divider - reg_mprj_datah = 0x0b; - - // Read a GPIO configuration word - value = reg_mprj_io_6; - reg_mprj_datal = value; // DLL divider - reg_mprj_datah = 0x0c; + // Write checkpoint for user clock counting (PLL bypassed) + reg_mprj_datal = 0xA0440000; + reg_clk_out_dest = 0x4; + reg_clk_out_dest = 0x0; + reg_mprj_datal = 0xA0450000; // End test - reg_mprj_datah = 0x0d; + reg_mprj_datal = 0xA0900000; } diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v index 0ef9ba41..26d279ce 100644 --- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v +++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v @@ -23,13 +23,13 @@ module sysctrl_tb; reg clock; + reg power1; + reg power2; reg RSTB; - reg csb_set; - reg power1, power2; wire gpio; - wire [5:0] checkbits; - wire [31:0] spivalue; + wire [15:0] checkbits; + wire [7:0] spivalue; wire [37:0] mprj_io; wire flash_csb; wire flash_clk; @@ -37,11 +37,11 @@ module sysctrl_tb; wire flash_io1; wire SDO; - assign checkbits = mprj_io[37:32]; - assign spivalue = mprj_io[31:0]; + integer ccount; + integer ucount; - // mrpj_io[3] = CSB needs to be set until the program disables the SPI. - assign mprj_io[3] = (csb_set) ? 1'b1 : 1'bz; + assign checkbits = mprj_io[31:16]; + assign spivalue = mprj_io[15:8]; // External clock is used by default. Make this artificially fast for the // simulation. Normally this would be a slow clock and the digital PLL @@ -49,6 +49,16 @@ module sysctrl_tb; always #10 clock <= (clock === 1'b0); + // User clock monitoring + always @(posedge mprj_io[15]) begin + ucount = ucount + 1; + end + + // Core clock monitoring + always @(posedge mprj_io[14]) begin + ccount = ccount + 1; + end + initial begin clock = 0; end @@ -61,80 +71,50 @@ module sysctrl_tb; $display("+1000 cycles"); end $display("%c[1;31m",27); - `ifdef GL - $display ("Monitor: Timeout, Test Sysctrl (GL) Failed"); - `else - $display ("Monitor: Timeout, Test Sysctrl (RTL) Failed"); - `endif - $display("%c[0m",27); + $display ("Monitor: Timeout, Test Sysctrl (RTL) Failed"); + $display("%c[0m",27); $finish; end // Monitor initial begin - wait(checkbits == 6'h04); - `ifdef GL - $display("Monitor: Test Sysctrl (GL) Started"); - `else - $display("Monitor: Test Sysctrl (RTL) Started"); - `endif - wait(checkbits == 6'h05); - $display(" Chip ID value = 0x%x (should be 0x00045611)", spivalue); - if(spivalue !== 32'h00045611) begin + wait(checkbits == 16'hA040); + $display("Monitor: Test 1 Sysctrl (RTL) Started"); + ucount = 0; + ccount = 0; + wait(checkbits == 16'hA041); + $display("Monitor: ucount = %d ccount = %d", ucount, ccount); + if (ucount !== 0 || ccount != 0) begin $display("Monitor: Test Sysctrl Failed"); $finish; end - wait(checkbits == 6'h06); - $display(" User ID value = 0x%x (should be 0x00000000)", spivalue); - if(spivalue !== 32'h00000000) begin + + wait(checkbits == 16'hA042); + $display("Monitor: Test 1 Sysctrl (RTL) Started"); + ucount = 0; + ccount = 0; + wait(checkbits == 16'hA043); + $display("Monitor: ucount = %d ccount = %d", ucount, ccount); + if (ucount !== 129 || ccount != 0) begin $display("Monitor: Test Sysctrl Failed"); $finish; end - wait(checkbits == 6'h07); - $display(" PLL enables value = 0x%x (should be 0x00000002)", spivalue); - if(spivalue !== 32'h00000002) begin - $display("Monitor: Test Sysctrl Failed"); - $finish; - end - wait(checkbits == 6'h08); - $display(" PLL bypass value = 0x%x (should be 0x00000001)", spivalue); - if(spivalue !== 32'h00000001) begin - $display("Monitor: Test Sysctrl Failed"); - $finish; - end - wait(checkbits == 6'h09); - $display(" PLL trim value = 0x%x (should be 0x03ffefff)", spivalue); - if(spivalue !== 32'h03ffefff) begin - $display("Monitor: Test Sysctrl Failed"); - $finish; - end - wait(checkbits == 6'h0a); - $display(" PLL divider value = 0x%x (should be 0x00000012)", spivalue); - if(spivalue !== 32'h00000012) begin - $display("Monitor: Test Sysctrl Failed"); - $finish; - end - wait(checkbits == 6'h0b); - $display(" PLL source value = 0x%x (should be 0x00000004)", spivalue); - if(spivalue !== 32'h00000004) begin - $display("Monitor: Test Sysctrl Failed"); - $finish; - end - wait(checkbits == 6'h0c); - $display(" GPIO config value = 0x%x (should be 0x00001809)", spivalue); - if(spivalue !== 32'h00001809) begin + + wait(checkbits == 16'hA044); + $display("Monitor: Test 2 Sysctrl (RTL) Started"); + ucount = 0; + ccount = 0; + wait(checkbits == 16'hA045); + $display("Monitor: ucount = %d ccount = %d", ucount, ccount); + if (ucount !== 0 || ccount != 129) begin $display("Monitor: Test Sysctrl Failed"); $finish; end + wait(checkbits == 16'hA090); - wait(checkbits == 6'h0d); - `ifdef GL - $display("Monitor: Test Sysctrl (GL) Passed"); - `else - $display("Monitor: Test Sysctrl (RTL) Passed"); - `endif - $finish; + $display("Monitor: Test Sysctrl (RTL) Passed"); + $finish; end initial begin @@ -144,16 +124,13 @@ module sysctrl_tb; #2000; end - initial begin // Power-up sequence + initial begin power1 <= 1'b0; power2 <= 1'b0; - csb_set <= 1'b1; #200; power1 <= 1'b1; #200; power2 <= 1'b1; - #200000; - csb_set <= 1'b0; // Release CSB after SPI is disabled end always @(checkbits) begin @@ -168,21 +145,18 @@ module sysctrl_tb; assign VDD1V8 = power2; assign VSS = 1'b0; - + assign mprj_io[3] = 1'b1; // Force CSB high. + caravel uut ( .vddio (VDD3V3), - .vddio_2 (VDD3V3), .vssio (VSS), - .vssio_2 (VSS), .vdda (VDD3V3), .vssa (VSS), .vccd (VDD1V8), .vssd (VSS), .vdda1 (VDD3V3), - .vdda1_2 (VDD3V3), .vdda2 (VDD3V3), .vssa1 (VSS), - .vssa1_2 (VSS), .vssa2 (VSS), .vccd1 (VDD1V8), .vccd2 (VDD1V8), diff --git a/verilog/gl/caravan.v b/verilog/gl/caravan.v index 6320bd53..c037c1fc 100644 --- a/verilog/gl/caravan.v +++ b/verilog/gl/caravan.v @@ -3841,7 +3841,7 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }), .trap(trap), .uart_enabled(uart_enabled), - .user_clock(mprj_clock2), + .user_clock(caravel_clk2), .usr1_vcc_pwrgood(mprj_vcc_pwrgood), .usr1_vdd_pwrgood(mprj_vdd_pwrgood), .usr2_vcc_pwrgood(mprj2_vcc_pwrgood), diff --git a/verilog/gl/caravel.v b/verilog/gl/caravel.v index 4dfb68c3..aa90fe8e 100644 --- a/verilog/gl/caravel.v +++ b/verilog/gl/caravel.v @@ -4579,7 +4579,7 @@ module caravel(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd .sram_ro_data({ \hkspi_sram_data[31] , \hkspi_sram_data[30] , \hkspi_sram_data[29] , \hkspi_sram_data[28] , \hkspi_sram_data[27] , \hkspi_sram_data[26] , \hkspi_sram_data[25] , \hkspi_sram_data[24] , \hkspi_sram_data[23] , \hkspi_sram_data[22] , \hkspi_sram_data[21] , \hkspi_sram_data[20] , \hkspi_sram_data[19] , \hkspi_sram_data[18] , \hkspi_sram_data[17] , \hkspi_sram_data[16] , \hkspi_sram_data[15] , \hkspi_sram_data[14] , \hkspi_sram_data[13] , \hkspi_sram_data[12] , \hkspi_sram_data[11] , \hkspi_sram_data[10] , \hkspi_sram_data[9] , \hkspi_sram_data[8] , \hkspi_sram_data[7] , \hkspi_sram_data[6] , \hkspi_sram_data[5] , \hkspi_sram_data[4] , \hkspi_sram_data[3] , \hkspi_sram_data[2] , \hkspi_sram_data[1] , \hkspi_sram_data[0] }), .trap(trap), .uart_enabled(uart_enabled), - .user_clock(mprj_clock2), + .user_clock(caravel_clk2), .usr1_vcc_pwrgood(mprj_vcc_pwrgood), .usr1_vdd_pwrgood(mprj_vdd_pwrgood), .usr2_vcc_pwrgood(mprj2_vcc_pwrgood), diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v index cd13dde5..bf673a9a 100644 --- a/verilog/rtl/caravan.v +++ b/verilog/rtl/caravan.v @@ -767,7 +767,7 @@ module caravan ( .trap(trap), - .user_clock(mprj_clock2), + .user_clock(caravel_clk2), .mask_rev_in(mask_rev), diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index b14d8bb8..3b6b9bb9 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -1,4 +1,6 @@ -// `default_nettype none + `ifdef SIM + `default_nettype wire + `endif // SPDX-FileCopyrightText: 2020 Efabless Corporation // // Licensed under the Apache License, Version 2.0 (the "License"); @@ -710,7 +712,7 @@ module caravel ( .trap(trap), - .user_clock(mprj_clock2), + .user_clock(caravel_clk2), .mask_rev_in(mask_rev), diff --git a/verilog/rtl/caravel_netlists.v b/verilog/rtl/caravel_netlists.v index 5ef76286..73426536 100644 --- a/verilog/rtl/caravel_netlists.v +++ b/verilog/rtl/caravel_netlists.v @@ -48,6 +48,8 @@ `ifdef GL `include "gl/digital_pll.v" + `include "gl/digital_pll_controller.v" + `include "gl/ring_osc2x13.v" `include "gl/caravel_clocking.v" `include "gl/user_id_programming.v" `include "gl/chip_io.v" @@ -67,6 +69,8 @@ `include "gl/caravel.v" `else `include "digital_pll.v" + `include "digital_pll_controller.v" + `include "ring_osc2x13.v" `include "caravel_clocking.v" `include "user_id_programming.v" `include "clock_div.v" diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v index 21c8340c..8ae69d11 100644 --- a/verilog/rtl/chip_io.v +++ b/verilog/rtl/chip_io.v @@ -126,74 +126,58 @@ module chip_io( sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] ( `MGMT_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VDDIO(vddio) -`else - ,.VDDIO_PAD(vddio_pad) +`ifndef TOP_ROUTING + .VDDIO_PAD(vddio_pad) `endif ); // lies in user area 2 sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] ( `USER2_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VDDIO(vddio) -`else - ,.VDDIO_PAD(vddio_pad2) +`ifndef TOP_ROUTING + .VDDIO_PAD(vddio_pad2) `endif ); sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad ( `MGMT_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VDDA(vdda) -`else - ,.VDDA_PAD(vdda_pad) +`ifndef TOP_ROUTING + .VDDA_PAD(vdda_pad) `endif ); sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad ( `MGMT_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VCCD(vccd) -`else - ,.VCCD_PAD(vccd_pad) +`ifndef TOP_ROUTING + .VCCD_PAD(vccd_pad) `endif ); sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] ( `MGMT_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VSSIO(vssio) -`else - ,.VSSIO_PAD(vssio_pad) +`ifndef TOP_ROUTING + .VSSIO_PAD(vssio_pad) `endif ); sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] ( `USER2_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VSSIO(vssio) -`else - ,.VSSIO_PAD(vssio_pad2) +`ifndef TOP_ROUTING + .VSSIO_PAD(vssio_pad2) `endif ); sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad ( `MGMT_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VSSA(vssa) -`else - ,.VSSA_PAD(vssa_pad) +`ifndef TOP_ROUTING + .VSSA_PAD(vssa_pad) `endif ); sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad ( `MGMT_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VSSD(vssd) -`else - ,.VSSD_PAD(vssd_pad) +`ifndef TOP_ROUTING + .VSSD_PAD(vssd_pad) `endif ); @@ -202,58 +186,48 @@ module chip_io( sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] ( `USER1_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VDDA(vdda1) -`else - ,.VDDA_PAD(vdda1_pad) +`ifndef TOP_ROUTING + .VDDA_PAD(vdda1_pad) `endif ); sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] ( `USER1_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VDDA(vdda1) -`else - ,.VDDA_PAD(vdda1_pad2) +`ifndef TOP_ROUTING + .VDDA_PAD(vdda1_pad2) `endif ); sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad ( `USER1_ABUTMENT_PINS -`ifdef TOP_ROUTING .VCCD1(vccd1), - .VSSD1(vssd1) -`else - ,.VCCD_PAD(vccd1_pad) + .VSSD1(vssd1), +`ifndef TOP_ROUTING + .VCCD_PAD(vccd1_pad) `endif ); sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] ( `USER1_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VSSA(vssa1) -`else - ,.VSSA_PAD(vssa1_pad) +`ifndef TOP_ROUTING + .VSSA_PAD(vssa1_pad) `endif ); sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] ( `USER1_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VSSA(vssa1) -`else - ,.VSSA_PAD(vssa1_pad2) +`ifndef TOP_ROUTING + .VSSA_PAD(vssa1_pad2) `endif ); sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad ( `USER1_ABUTMENT_PINS -`ifdef TOP_ROUTING .VCCD1(vccd1), - .VSSD1(vssd1) -`else - ,.VSSD_PAD(vssd1_pad) + .VSSD1(vssd1), +`ifndef TOP_ROUTING + .VSSD_PAD(vssd1_pad) `endif ); @@ -262,39 +236,33 @@ module chip_io( sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad ( `USER2_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VDDA(vdda2) -`else - ,.VDDA_PAD(vdda2_pad) +`ifndef TOP_ROUTING + .VDDA_PAD(vdda2_pad) `endif ); sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad ( `USER2_ABUTMENT_PINS -`ifdef TOP_ROUTING .VCCD1(vccd2), - .VSSD1(vssd2) -`else - ,.VCCD_PAD(vccd2_pad) + .VSSD1(vssd2), +`ifndef TOP_ROUTING + .VCCD_PAD(vccd2_pad) `endif ); sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad ( `USER2_ABUTMENT_PINS -`ifdef TOP_ROUTING - .VSSA(vssa2) -`else - ,.VSSA_PAD(vssa2_pad) +`ifndef TOP_ROUTING + .VSSA_PAD(vssa2_pad) `endif ); sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad ( `USER2_ABUTMENT_PINS -`ifdef TOP_ROUTING .VCCD1(vccd2), - .VSSD1(vssd2) -`else - ,.VSSD_PAD(vssd2_pad) + .VSSD1(vssd2), +`ifndef TOP_ROUTING + .VSSD_PAD(vssd2_pad) `endif ); @@ -328,7 +296,7 @@ module chip_io( sky130_fd_io__top_xres4v2 resetb_pad ( `MGMT_ABUTMENT_PINS `ifndef TOP_ROUTING - ,.PAD(resetb), + .PAD(resetb), `endif .TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h .TIE_HI_ESD(), @@ -361,10 +329,7 @@ module chip_io( .VDDA(vdda), .VCCD(vccd), .VCCHIB(vccd) -`else - .VCCHIB() `endif - ); sky130_ef_io__corner_pad user1_corner ( `ifndef TOP_ROUTING @@ -380,8 +345,6 @@ module chip_io( .VDDA(vdda1), .VCCD(vccd), .VCCHIB(vccd) -`else - .VCCHIB() `endif ); sky130_ef_io__corner_pad user2_corner ( @@ -398,8 +361,6 @@ module chip_io( .VDDA(vdda2), .VCCD(vccd), .VCCHIB(vccd) -`else - .VCCHIB() `endif ); diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v index 49ff44bf..a2bbf195 100644 --- a/verilog/rtl/clock_div.v +++ b/verilog/rtl/clock_div.v @@ -102,9 +102,10 @@ module odd #( end reg [SIZE-1:0] initial_begin; // this is used to offset the negative edge counter - // wire [SIZE:0] interm_3; // from the positive edge counter in order to - // assign interm_3 = {1'b0,N} + 2'b11; // guarante 50% duty cycle. - localparam [SIZE:0] interm_3 = {1'b0,`CLK_DIV} + 2'b11; + wire [SIZE:0] interm_3; // from the positive edge counter in order to + assign interm_3 = {1'b0, N} + 2'b11; // guarantee 50% duty cycle. + + localparam [SIZE:0] interm_init = {1'b0,`CLK_DIV} + 2'b11; // Counter driven by negative edge of clock. @@ -112,7 +113,7 @@ module odd #( if (resetb == 1'b0) begin // reset the counter at system reset counter2 <= `CLK_DIV; - initial_begin <= interm_3[SIZE:1]; + initial_begin <= interm_init[SIZE:1]; out_counter2 <= 1; end else if (rst_pulse) begin // reset the counter at change of N. diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v index b8dd69e9..322c2541 100644 --- a/verilog/rtl/digital_pll.v +++ b/verilog/rtl/digital_pll.v @@ -17,8 +17,10 @@ // Digital PLL (ring oscillator + controller) // Technically this is a frequency locked loop, not a phase locked loop. +`ifndef SIM `include "digital_pll_controller.v" `include "ring_osc2x13.v" +`endif module digital_pll( `ifdef USE_POWER_PINS diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v index 6a1d98b2..ec4fdf99 100644 --- a/verilog/rtl/mprj_io.v +++ b/verilog/rtl/mprj_io.v @@ -71,7 +71,7 @@ module mprj_io #( sky130_ef_io__gpiov2_pad_wrapped area1_io_pad [AREA1PADS - 1:0] ( `USER1_ABUTMENT_PINS `ifndef TOP_ROUTING - ,.PAD(io[AREA1PADS - 1:0]), + .PAD(io[AREA1PADS - 1:0]), `endif .OUT(io_out[AREA1PADS - 1:0]), .OE_N(oeb[AREA1PADS - 1:0]), @@ -102,7 +102,7 @@ module mprj_io #( sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [TOTAL_PADS - AREA1PADS - 1:0] ( `USER2_ABUTMENT_PINS `ifndef TOP_ROUTING - ,.PAD(io[TOTAL_PADS - 1:AREA1PADS]), + .PAD(io[TOTAL_PADS - 1:AREA1PADS]), `endif .OUT(io_out[TOTAL_PADS - 1:AREA1PADS]), .OE_N(oeb[TOTAL_PADS - 1:AREA1PADS]), diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v index b691e50f..86e0be5d 100644 --- a/verilog/rtl/pads.v +++ b/verilog/rtl/pads.v @@ -27,7 +27,7 @@ .VCCD(vccd),\ .VSSIO(vssio),\ .VSSD(vssd),\ - .VSSIO_Q(vssio_q) + .VSSIO_Q(vssio_q), `define USER2_ABUTMENT_PINS \ .AMUXBUS_A(analog_a),\ @@ -41,7 +41,7 @@ .VCCD(vccd),\ .VSSIO(vssio),\ .VSSD(vssd),\ - .VSSIO_Q(vssio_q) + .VSSIO_Q(vssio_q), `define MGMT_ABUTMENT_PINS \ .AMUXBUS_A(analog_a),\ @@ -55,7 +55,7 @@ .VCCD(vccd),\ .VSSIO(vssio),\ .VSSD(vssd),\ - .VSSIO_Q(vssio_q) + .VSSIO_Q(vssio_q), `else `define USER1_ABUTMENT_PINS `define USER2_ABUTMENT_PINS @@ -78,7 +78,7 @@ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ - ,.PAD(X), \ + .PAD(X), \ `endif \ .OUT(vssd), \ .OE_N(vccd), \ @@ -110,7 +110,7 @@ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ - ,.PAD(X), \ + .PAD(X), \ `endif \ .OUT(Y), \ .OE_N(OUT_EN_N), \ @@ -142,7 +142,7 @@ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ - ,.PAD(X), \ + .PAD(X), \ `endif \ .OUT(Y), \ .OE_N(OUT_EN_N), \ @@ -174,7 +174,7 @@ sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \ `MGMT_ABUTMENT_PINS \ `ifndef TOP_ROUTING \ - ,.PAD(X), \ + .PAD(X), \ `endif \ .OUT(Y_OUT), \ .OE_N(OUT_EN_N), \