* Effectively reverted the change to add spare logic blocks near each
of the GPIO control blocks by changing the definition of
NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks)
for both caravel and caravan top level RTL verilog modules.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations
!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
* Added enough spare logic blocks to have the existing four above
the processor, plus one each per GPIO (38 for caravel, 27 for
caravan).
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
* Removed the SRAM read-only interface by wrapping all related code
in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
to caravel_netlists.v when attempting to determine if the
verification testbenches could be run from caravel referencing
caravel_mgmt_soc_litex instead of the other way around. This file
has been reverted back to its original form.
This reverts commit 577cc12fe0.
Reverting the change from issue #16. After some discussion, it has
been decided that it is up to the user to implement the pull-up and
pull-down modes correctly by setting the output enable and driving
the output to the appropriate value. Note that this should be well
documented, if by nothing else than a validation testbench that
excercises a user pull-up and pull-down input mode.
zero level outputs when the user project area is powered down.
That allows the synthesis tools to buffer these outputs. The
protection from floating inputs is left as-is, but all logic that
was unnecessary to be specified by gate instances has been changed
to RTL. This leaves only a handful of signals (logic analyzer input,
user IRQ, and wishbone data out and acknowledge out) to be handled
by explicit logic gate instances.
mo-hosni
Mohamed Hosni
R. Timothy Edwards
kareem
Jeff DiCorpo
jeffdi
RTimothyEdwards
Marwan Abbas
Mohamed Shalan
M0stafaRady
M0stafaRady