* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one
* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it
* Apply automatic changes to Manifest and README.rst
* add caravan power routing lef
* - update mag and def view of caravan
- add_macro_placement for fake cell
* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines. Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag. It may be
worth cherry-picking the files to merge and exclude those layouts.
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
Still evaluating why the layout does not pass LVS like it did
previously, although all current LVS errors appear to be related
to magic's extraction of the isolated substrates, and do not
imply functional issues. Also, LVS has only been done on the
top level.
* REVERT ME: temporarily match simple_por pin in verilog with lef
* - update configs
- add patch file for power routing def
* - update the following caravel toplevel views
- gl
- mag
- def
- add caravel power routing def
* Apply automatic changes to Manifest and README.rst
* update gl mag and def for caravel
* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"
This reverts commit b70c27c69f.
* update caravel gds
* Apply automatic changes to Manifest and README.rst
* Added text and logo cells back into the caravel top level. Put an
isolated ground marker layer on the xres_buf layout. Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v. Updated the copyright block text.
Corrected DRC errors in the top level routing.
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect
* mgmt_protect updated
* mgmt_protect updated
* remove some via3 to fix power shorts
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
getting changed by "make ship" because the build is done in a place
where the path pointer to the user_id_programming GDS still points
back to the original caravel repository, not the user project
repository. The user_id_programming GDS was removed (no longer used),
the user_id_programming.mag file was modified to remove the path
pointer to the GDS, and the set_user_id.py script was modified to
make changes directly to the user_id_programming.mag file instead of
the GDS. An additional method was added to the set_user_id.py script
to modify the gate-level verilog/gl/user_id_programming.v to make
the user ID correct for gate-level testbench simulations.
it is exactly overlapping; this resolves issues with LVS. Also:
Corrected the references to the OpenLane/ path in the .mag files
by changing them to the canonical $PDKPATH reference.
to be abstract views, and modified the LVS scripts accordingly
(they no longer need a special version of the netgen setup
script). LVS was verified on both caravel and caravan using this
setup.
connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be). This is
functionally the same. Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good). Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change. This
was the only change affecting layout. Also: Revised the "pll"
testbench. This is still ongoing work. Also: Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre. Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
and open source logos. Modified the gpio_defaults_block layout
so that open holes are not created in the metal1 when the vias
are moved by the defaults block configuration script.
the clocking subcircuit from inside the pad area near the "clock"
pin to under the DLL. This prevents the DLL from having its
outputs travel all the way across the chip to reach the clocking
cell and then have the multiplexed clock travel all the way back,
especially as the DLL outputs are high-speed signals (up to 150
MHz).
update. Also changed the defaults block types in the layout so that
they match the gate-level netlist. This does not change the behavior
after assembly but lets LVS run correctly on the layout prior to final
assembly.
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core. Also: Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
R. Timothy Edwards
Kareem Farid
Marwan Abbas
Jeff DiCorpo
D. Mitch Bailey
manarabdelaty
jeffdi