inputs that are permanently tied low or high come from either
the local "TIE" pad connections (if they are in the 3.3V
domain) or from a constant one wire in the 1.8V domain that
is generated in the gpio_control_block module and exported
to the chip_io (or chip_io_alt) module.
update gpio_control_block config for new openlane versions:
- disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size
and fit the floorplan
- change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells
- disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and
enable `GLB_RESIZER_TIMING_OPTIMIZATIONS`
- remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement
- set `DECAP_CELL` to not use ef decaps.. i think that was for simulations?
- enable some turned off `QUIT_*` variables
- replace deprecated variables such as `GLB_RT_*`
- customize `pdn.tcl` to force pdn straps to follow the old pattern
- replace `$script_dir` with `$::env(DESIGN_DIR)`
!IMPORTANT - still need to run dynamic simulations
tweak blackbox lvs scripts for very fast extract; update spi/lvs/*.spice.
The .spice (once propagated to caravel-lite AND caravel-lite embed in mpw_precheck docker)
will pass the consistency check.
Co-authored-by: Risto Bell <rb@efabless.com>
from the data and replace them with a single flop clocked on the
negative edge of the serial clock. This will completely avoid hold
violations by ensuring that the block's output data bit does not
change anywhere near the clock rising edge, so clocks do not have
to be tightly aligned among all of the GPIO blocks.
* Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds.
This commit does the following:
(1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds.
(2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds.
(3) Corrects the xschem testbench to connect to both grounds of simple_por.
(4) Corrects the simple_por layout to remove the 1.8V logic from the
3.3V ground and connect it instead to the 1.8V ground.
(5) Extends the top-level power routing of caravel and caravan to
make a better connection to the simple_por 1.8V ground.
(6) Adds an LVS script to properly check the simple_por layout against the
xschem-generated schematic netlist.
NOTE: None of these modifications change the function of any circuit. The
1.8V and 3.3V ground nets are only logically separated in the netlists but
share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds
within the simple_por, where they were previously mingled. It also ensures
that the full LVS for caravel and caravan can now include the simple_por at
the transistor level and still pass.
* Updated the GDS of simple_por (previously did not remove GDS_FILE
from the .mag file and so it just overwrote the original GDS file
with itself).
* Corrected a route to simple_por in the top level of both caravel
and caravan that was shorting to the extra metals put on top of
the substrate contact across the top (bottom, in the top level)
of the simple_por layout.
* Modified the set_user_id.py script so that mode "-report" returns
a valid value, instead of throwing an error, because the "info.yaml"
file was removed without due consideration of the side effects.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
it will recognize all block cell types in the gate level netlist
after having been run previously. The former code was only looking
for numeric digits in the cell name, but the cell name suffix is
hex, not integer, and so the script needs to add a check for the
letters A-F or a-f in the cell name suffix. This is not an
immediate issue because the two default values used are "0403" and
"1803" and happen not to have any alphabetic hex digits. But if
it were deemed necessary to change a default, then this script
should not break.
does not pass through an inverter, so that the input can remain
unconnected. Rewired the existing implementation to use an
alternative gate that has an inverting input so that the
user_gpio_out signal can be left undriven when the GPIOs are in
the management enable state. This is a simple logic refactoring
and does not change the logic function. The manual rewiring has
been confirmed by LVS, but at least one GL simulation should be
run to confirm that the logic function remains the same as before.
* Corrects four signals which were missing from the caravan top level
(management output and output enable to GPIO 0 and 1---these errors
would have prevented the houskeeping SPI from working on caravel).
Corrected RTL verilog (source of the error), GL verilog, and layout.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Create lvs-cvc.rst
* user_project_analog_wrapper -> user_analog_project_wrapper
* Added table
* Update lvs-cvc.rst
* Create lvs_cvc_mpw4.rst
Initial steps for LVS and CVC-RV for MPW-4 slot-002
* Update lvs_cvc_mpw4.rst
diode and short errors
* daily progress
`simple_por` changes to `caravel.v`
* Update lvs_cvc_mpw4.rst
* Changed int (truncate) to round to correct gpio_default error.
* Replace gpio_defaults_block for gpio 0-4 correctly.
Remove old versions of gpio_defaults_block 0403 and 1803.
* Removed local CVC-RV docs not ready for commit.
* Quick fix to a route that was hand-corrected from an Openlane
short but which is just shy of the minimum width for metal4.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Fixes an error in the gen_gpio_defaults.py script that is incompatible
with the use of indexed arrays for five of the gpio_defaults_block
instances. Previously this was handled by manually changing the names
in the layout file. This script avoids the need for manual modification
by directly handling the indexed notation. Also, this extends the
modifications made to the layout to include the first five defaults
blocks; otherwise, the first five defaults blocks are not changed and
the defaults will be wrong for the housekeeping SPI pins.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* (1) Modified the .magicrc file to set a default for PDK if not set in the
environment. (2) Fixed the user ID programming layout to not leave holes
behind when the script moves the vias around (similar to the handling of
the GPIO defaults block). (3) Added substrate isolation to gpio_control_block
and fixed the path references to the standard cells. (4) Fixed the four
missing routes on the Caravan top level. (5) Reinstated the large rendered
labels for the pads on both caravel and caravan. (6) Corrected the top
level gate-level netlist for caravan to add the missing pins to the
management core wrapper. (7) Did the same for the caravan top level RTL.
(8) Created scripts to run full LVS including extracting the management
core wrapper and reading all gate-level verilog submodules. (9) Moved all
of the LVS scripts to the scripts directory.
* Apply automatic changes to Manifest and README.rst
* Made the changes from pull request #73 as they did not get merged
successfully, and if merged now they will generate conflicts with
this pull request in scripts/set_user_id.py. So it's easier to
just manually add them to this pull request.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Create lvs-cvc.rst
* user_project_analog_wrapper -> user_analog_project_wrapper
* Added table
* Update lvs-cvc.rst
* Create lvs_cvc_mpw4.rst
Initial steps for LVS and CVC-RV for MPW-4 slot-002
* Update lvs_cvc_mpw4.rst
diode and short errors
* daily progress
`simple_por` changes to `caravel.v`
* Update lvs_cvc_mpw4.rst
* Remove old local documentation.
* Changes that correct gpio_default_block, user_id_programming, and mgmt_core references.
mgmt_core_wrapper
Use absolute path instead of relative path.
user_id_programming
Remove GDS references as GDS is no longer modified.
Corrected string concatenation.
Corrected mag data replacement.
Corrected verilog data replacement.
gpio_default_block
Rename instances for gpio_default_blocks 0-4 in caravel.mag and caravan.mag.
Change replace range in gen_gpio_defaults.py to handle gpio_default_blocks 0-4.
* Revert changes related to gpio_default_block.
* Changed mgmt_core_wrapper absolute path from UPRJ_ROOT to MCW_ROOT.
* Corrected MCW_ROOT path (includes mgmt_core_wrapper)
* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one
* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it
* Apply automatic changes to Manifest and README.rst
* add caravan power routing lef
* - update mag and def view of caravan
- add_macro_placement for fake cell
* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines. Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag. It may be
worth cherry-picking the files to merge and exclude those layouts.
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
Still evaluating why the layout does not pass LVS like it did
previously, although all current LVS errors appear to be related
to magic's extraction of the isolated substrates, and do not
imply functional issues. Also, LVS has only been done on the
top level.
* Fix syntax error in gpio_control_block
Fixed syntax error that was only visible when running iverilog for simulation
* Apply automatic changes to Manifest and README.rst
Co-authored-by: marwaneltoukhy <marwaneltoukhy@users.noreply.github.com>
* REVERT ME: temporarily match simple_por pin in verilog with lef
* - update configs
- add patch file for power routing def
* - update the following caravel toplevel views
- gl
- mag
- def
- add caravel power routing def
* Apply automatic changes to Manifest and README.rst
* update gl mag and def for caravel
* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"
This reverts commit b70c27c69f.
* update caravel gds
* Apply automatic changes to Manifest and README.rst
* Added text and logo cells back into the caravel top level. Put an
isolated ground marker layer on the xres_buf layout. Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v. Updated the copyright block text.
Corrected DRC errors in the top level routing.
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
jeffdi
jeffdi
RTimothyEdwards
Tim Edwards
kareem
sto6
Jeff DiCorpo
matt venn
Marwan Abbas
Anton Blanchard
Mitch Bailey
Ian Zhang
Kareem Farid
ef-gps