- remove unused port in chip_io
- move the rest of chip_io power ports to the USE_POWER_PINS guard
- add caravel_power_routing cell guarded by TOP_ROUTING ifdef
* Effectively reverted the change to add spare logic blocks near each
of the GPIO control blocks by changing the definition of
NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks)
for both caravel and caravan top level RTL verilog modules.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
* Added enough spare logic blocks to have the existing four above
the processor, plus one each per GPIO (38 for caravel, 27 for
caravan).
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
* Removed the SRAM read-only interface by wrapping all related code
in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
Corrected the pad constant connections to all be in the correct domain
(1.8V or 3.3V). Created a new "constant_block" module that generates
a single constant 1 and 0 value in the 1.8V domain, and used 7 of these
in the chip_io (and chip_io_alt) modules to create the 1.8V domain
constant signals for the seven pads belonging to the management (clock,
reset, flash SPI, and management GPIO).
inputs that are permanently tied low or high come from either
the local "TIE" pad connections (if they are in the 3.3V
domain) or from a constant one wire in the 1.8V domain that
is generated in the gpio_control_block module and exported
to the chip_io (or chip_io_alt) module.
* Corrected the issue reported on the github issue tracker (#34)
in which the use of "clocking" as an instance name in caravel and
caravan conflicts with the system verilog keyword of the same
name.
* Apply automatic changes to Manifest and README.rst
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
(input for monitoring) changed from being connected directly to the
user project (where it shouldn't be) to the same signal on the input
side of the management protect block (where it should be). This is
functionally the same. Checked for any other signals connected
directly from the user project to any block other than mgmt_protect,
didn't find any (good). Modified the gate-level netlists and top-level
layouts for caravel and caravan with the corresponding change. This
was the only change affecting layout. Also: Revised the "pll"
testbench. This is still ongoing work. Also: Fixed the way the
pins on I/O pads are declared in chip_io.v, mprj_io.v, and pads.v, so
that it isn't so bizarre. Most of this change is functionally
agnostic (just a change in the way the ifdefs work), but did fix an
incorrect ifdef that causes the whole user power domain to be broken.
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core. Also: Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
add a separate signal for the houskeeping wb_cyc_i wishbone signal,
instead of combining it with the user project's wb_cyc_i. This
change makes it compatible with the LiteX implementation of the
wishbone bus.
verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to
correct this; still need to correct the layouts. The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing. Will route this by hand.
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared. The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
fixed by moving from after the managment protect to before it, but
an inversion of the signal was missed, leading to an incorrect
wb_rst_i passed to housekeeping. (2) Revised the method to load
the serial GPIO data chain from a 2-pin, I2C-like method to a
more straightforward 3-pin method with separate reset, clock, and
load pins. The load pin propagates through the chaing like the
other two. Added a bit-bang signal for the load signal as well.
(3) Added an implied buffer after the data output of the GPIO
control block to ensure that the data arrives at the next control
block after the clock, to prevent hold violations.
incorrectly assigned to the clock on the user side of the managment
protect block, causing it to be undefined when the user area power
supply is down. The "hkspi_power" testbench which tests using the
housekeeping SPI while the user area power is grounded now works
correctly.
an unconnected wishbone bus (unconnected inputs). Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
via programming. The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file. For the verilog, they are
applied as parameters. For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master. Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
storage. Not all of these pass simulation checks. Added back the
bit-bang control of the GPIO programming. Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports. There is not yet a testbench for the SRAM read-only
interface.
kareem
R. Timothy Edwards
Jeff DiCorpo
jeffdi
manarabdelaty