Commit Graph

130 Commits

Author SHA1 Message Date
marwaneltoukhy 494c0d4473 added views for caravel and caravan and fixed lvs in power routing 2022-10-28 15:23:00 -07:00
marwaneltoukhy 5c9a2a1e0a added views and signoff reports for eco 2022-10-28 13:13:37 -07:00
mo-hosni b5010be8a7 Update Openlane views 2022-10-27 09:53:45 -07:00
mo-hosni 2d61e593aa Decreased distances from pins to and gates in mgmt_protect 2022-10-27 08:20:57 -07:00
Tim Edwards 0f08073876 Updated the chip_io_alt LEF, DEF, and GDS views after updating
the layout yesterday.
2022-10-22 08:46:18 -04:00
passant5 0c9e3a08fd
update caravel with tying `porb_h_in` with `por_l_in` (#326)
* update caravel with tying `porb_h_in` with `por_l_in` at the `mgmt_core_wrapper` in the top-level layout:
- `porb_h_in` shouldn't be left floating as it is an input to `clkbuf_16`

* add caravel-eco.gds (same as caravel.gds)
2022-10-21 11:52:00 -07:00
Jeff DiCorpo 4192c34f4b
Caravan redesign (#321)
* Fixed caravan top level power routing and updated views for mag, gds and lef

* caravan(rtl): updates

~ typos fix
- remove unused pin in chip_io_alt
+ add caravan_power_routing verilog

* Apply automatic changes to Manifest and README.rst

* ~ update caravan openlane configs to add extra cell references
~ correct placment and cell names of some macro in caravan interactive script

* reharden: caravan

+ add non functional blocks
+ add an initial iteration of caravan

* Apply automatic changes to Manifest and README.rst

* Revert "Fixed caravan top level power routing and updated views for mag, gds and lef"

This reverts commit 70628f748a.

* fixed caravan top level power routing

* reharden: caravan

based on new power routing
~ guard rtl chip_io power pins in the power macro guard

* Apply automatic changes to Manifest and README.rst

* fixed caravan top level power routing

* rehadren: caravan

+ add caravan signal routing to openlane run
~ change rtl to guard power and analog against routing by
openlane by ifndef TOP_ROUTING
~ add pr bounadry for caravan signal routing to fix origin issues

* Apply automatic changes to Manifest and README.rst

* fix power connection in buffering block and regenerate gl

* Apply automatic changes to Manifest and README.rst

* updated views for caravan

* Added extract unique to lvs-gds-cell target. (#313)

* This fixes errors in the top level RTL of caravan that failed to
hook up the buffers through the SoC correctly.

* Apply automatic changes to Manifest and README.rst

* reharden: caravan

~ rtl updated

* fixed caravan mag top level

* updated views for caravan + signoff

* fixed top level cell name

* fix syntax error related to signal initialization place in caravan (#319)

* fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>

* Apply automatic changes to Manifest and README.rst

Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com>
Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 07:37:41 -07:00
R. Timothy Edwards 1d26e4df32
Fixed the LEF views of caravel and caravan, which determine the (#297)
location, use, class, and name of all of the pins around the
padframe.
2022-10-20 14:34:28 -07:00
Marwan Abbas bbb6bf775c
Caravel redesign new top (#300)
* reharden: caravel

~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing

* update pdn for `caravel_clocking` & `digital_pll`

* added script to update and generate the power routing views

* ~ run update_power_routing_views from the caravel root with prboundary

* fix output message

* added power routing lef, mag and gds

* fix update_power_routing_views saving wrong cell name

* reharden: caravel

~ incorperate pdn changes
~ re-extract spefs

* fix caravel_power_routing views

* fix abs path in maglef views

* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect

* generate a new chip_io gds

* regenerate gpio_control_block due to mag and gds not in sync

* reharden: caravel

~ change config to pass clean routing
~ use updated views of macros

* lvs clean views

* add caravel top-level generated sdf for all corners

* fix absolute path for mgmt_core_wrapper

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>
2022-10-18 17:24:07 -07:00
Marwan Abbas 3334498409 added lef and gds views for caravel_power_routing 2022-10-18 18:08:31 +02:00
Marwan Abbas 20e51c8504
Merge pull request #281 from efabless/fix_buffer_cell_for_lvs
Small change to the signal buffer layouts for LVS.
2022-10-18 17:12:49 +02:00
Marwan Abbas 981f0a54ff
Merge pull request #177 from efabless/top_layout_rework
Create top-level LEF and pin generation script.
2022-10-18 17:11:02 +02:00
Marwan Abbas 38902bde45
Merge pull request #292 from efabless/caravel-redesign-digital_pll-decaps
reharden: digital_pll
2022-10-18 16:35:49 +02:00
Marwan Abbas 4cbf8ca4f6
Merge pull request #291 from efabless/caravel-redesign-clocking-decaps
reharden: caravel_clocking
2022-10-18 16:35:26 +02:00
kareem 68063ddadc reharden: digital_pll
~ increase width for more spread decaps
+ add or cells to cell exclude
~ change placement density in accordance to area
~ change padding to allow for space for decaps
2022-10-18 07:07:32 -07:00
Marwan Abbas 7c468c0be2 Fixed PDN to incorprate new changes to housekeeping and caravel clocking 2022-10-18 15:52:47 +02:00
kareem fdeb6003f3 Merge branch 'caravel_redesign-digital_pll-no-or' into caravel_redesign 2022-10-18 06:31:00 -07:00
kareem 3bd586b50c reharden: caravel_clocking
~ increase height for more spread decap insertion
+ add or cells to cell exclude
~ adjust pdn to have an offset half to pitch
~ change placement density in accordance to area
~ change padding to allow for space for decap insertion
2022-10-18 06:18:30 -07:00
mo-hosni 1110ae2fe8 update housekeeping views and openlane configuration 2022-10-18 04:07:27 -07:00
Tim Edwards 6bed433856 One additional small change to the signal buffer layouts to avoid
a collision with the lower three right-hand side I/O cells that
was discovered by LVS.
2022-10-17 15:51:43 -04:00
kareem 712b784e16 reharden!: digital_pll
~ disable or gate
+ add nosynth list file
2022-10-17 12:33:25 -07:00
Mohamed Shalan 3fbc52ecbf
Merge pull request #276 from efabless/caravel_redesign-digital_pll-fanout
reharden!: digital_pll
2022-10-17 20:50:01 +02:00
mo-hosni 2d147966b9 Update housekeeping views and openlane configuration 2022-10-17 11:37:24 -07:00
kareem e5d9788a43 reharden!: digital_pll
~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys

!need to verify that the oscillator remains untouched
2022-10-17 10:56:01 -07:00
Marwan Abbas c524106fed
Merge pull request #263 from efabless/caravel_redesign-pdn-again
update caravel pdn
2022-10-17 16:12:01 +02:00
kareem d416d222b2 sync mag and lef with gds 2022-10-17 06:15:52 -07:00
kareem a8794dff4b reharden: caravel
~ reharden with updated pdn
~ add stubs for non functional blocks
2022-10-17 03:59:28 -07:00
kareem 394546731f update caravel pdn
~ change pr boundary to origin to (0,0)
~ sync lef and mag with gds
2022-10-17 03:51:21 -07:00
Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the
signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
2022-10-16 21:06:27 -04:00
Tim Edwards 41775aedfd Changed the LEF views to restrict the pins to the route endpoints
using the (accidentally undocumented) "-pinonly" option.
2022-10-16 14:40:50 -04:00
Tim Edwards 48ae31205c Another change to the pin endpoint positions to make sure that they
have at least 0.28um spacing to the next wire.  Not sure that this
is going to solve the router errors, though.
2022-10-16 14:15:12 -04:00
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
2022-10-16 12:49:44 -04:00
Tim Edwards 589f351dcb Additional modification to move pins up into an uncongested area
above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections.  Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
2022-10-16 10:52:53 -04:00
Tim Edwards 43b8f9d4fe Merge branch 'caravel_redesign' into fix_top_buffers_again
Updating to the most recent caravel_redesign branch version.
2022-10-16 10:05:36 -04:00
Tim Edwards dcc3c56b83 Some additional corrections to the gpio_signal_buffering cells.
Corrected one instance where a buffer had incorrectly been replaced
with a decap cell.  Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side.  Corrected a small
DRC error in a route position at the bottom.
2022-10-16 09:50:20 -04:00
Marwan Abbas 6c6fa6b502
Merge pull request #255 from efabless/caravel_power_routing-sync-views
caravel_power_routing updates
2022-10-16 14:15:19 +02:00
kareem 914971d253 + add pr boundary for caravel_power_routing
based on feedback from tim in order to generate a lef view
with a zero origin and avoid any hacks

+ add caravel_power_routing lef
+ sync caravel_power_routing gds and mag
2022-10-16 04:41:29 -07:00
mo-hosni 22dde425ac add mgmt_protect views and openlane files 2022-10-16 03:14:55 -07:00
Tim Edwards a77a45babe Adjustments to the top level buffering cells to do various things
like avoid obstructions in the padframe and power routing, add
decap, and separate coupling wires to reduce capacitance.
2022-10-15 17:35:17 -04:00
kareem 5d5d019ea1 Revert "add buff_flash_clkrst"
This reverts commit 2675487322.
2022-10-15 08:47:02 -07:00
Tim Edwards 3db846b119 Fixes issues with the GPIO signal buffering by applying a bounding
box to the layout, so that LEF and DEF positions are correct.
2022-10-15 10:31:35 -04:00
mo-hosni 2675487322 add buff_flash_clkrst 2022-10-15 06:38:42 -07:00
Marwan Abbas 316f2dbb58
Merge pull request #238 from mo-hosni/update_mgmt_protect
Update mgmt protect
2022-10-15 11:27:59 +02:00
mo-hosni 3361c8787d Add mgmt_protect views and openlane files 2022-10-15 01:46:22 -07:00
passant5 8c0e4f7403
Merge branch 'caravel_redesign' into add_top_level_buffers 2022-10-15 00:28:14 +02:00
Tim Edwards 65573a64a6 Revised the LEF view of mgmt_protect_hv, since it has changed due
to the increase of the horizontal m3 buses (pins) to 0.5um.
2022-10-14 17:06:45 -04:00
Tim Edwards 92e2f5e8a4 Added layout views (.mag, GDS, DEF, and LEF) for the caravan
variant of the top level GPIO signal buffering (module
gpio_signal_buffering_alt).
2022-10-14 16:06:11 -04:00
mo-hosni 0e01725608 add housekeeping views 2022-10-14 09:26:34 -07:00
kareem aadfb57609 reharden: caravel_clocking
~ align pdn with top level
~ move spefs and sdfs output corners to signoff/*/openlane-signoff
2022-10-14 05:24:49 -07:00
Tim Edwards 46d44793e2 Added layout for the gpio_signal_buffering module, including GDS,
LEF, DEF, and magic views.
2022-10-13 21:59:10 -04:00