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arch_exploration

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k4_N8_interface

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multiple_global_clocks

ql_ap3_arch_eval

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ql_frac_lut4_arith

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1.0.0

Mono Color

• 7f9c8e2e90 [Doc] Add Readme for design compiler workspace tangxifan 2020-12-07 17:40:08 -0700
• 2f741ecc15 [MSIM] Now modelsim verification is multithreaded tangxifan 2020-12-07 15:25:48 -0700
• 0e691fe9ca [SOFA-HD] Updated reports and screenshots Ganesh Gore 2020-12-07 11:55:59 -0700
• 40f1e1fae1 Merge remote-tracking branch 'origin/master' into ganesh_dev Ganesh Gore 2020-12-07 10:14:56 -0700
• 67e0c94c66
  Merge pull request #58 from lnis-uofu/xt_dev Laboratory for Nano Integrated Systems (LNIS) 2020-12-07 09:45:43 -0700
• fd074254e9
  Merge pull request #57 from lnis-uofu/ganesh_dev tangxifan 2020-12-07 09:07:30 -0700
• 7967d1da1f [Bugfix] Solved merge conflict Ganesh Gore 2020-12-06 23:13:59 -0700
• 5474ff53c5 [Fixup] Merge conflict with master Ganesh Gore 2020-12-06 21:41:06 -0700
• b90ee124a3 Resolves merge conflict with master Ganesh Gore 2020-12-06 21:35:34 -0700
• b0098ed4b9 Merge remote-tracking branch 'origin/master' into ganesh_dev Ganesh Gore 2020-12-06 21:29:06 -0700
• 5679ee0cb4 [QLSOFA-HD] Fixed reset signal short/GDS precision to 1000 Ganesh Gore 2020-12-06 20:47:52 -0700
• 12ffaed8fa [QLSOFA-HD] Added screenshots for top level PnR Ganesh Gore 2020-12-06 20:45:31 -0700
• 7f53e0ef18 [HDL] Add HDL for custom cells tangxifan 2020-12-06 14:15:03 -0700
• aa90424ada [HDL] Add primitive include lines for digital I/O built with HD cells tangxifan 2020-12-06 11:35:35 -0700
• 21a4928002 [HDL] Bug fix in custom cell code generator tangxifan 2020-12-06 11:28:37 -0700
• da08e505b5 [MSIM] Support pre-pnr simulation in script-run verification tangxifan 2020-12-06 11:13:50 -0700
• 328594d8c5 [Action] Clean up action scripts Ganesh Gore 2020-12-06 01:53:21 -0700
• 9322afadad [Action] Added 30 min timeout ticker Ganesh Gore 2020-12-06 00:17:17 -0700
• ea7e2b248b [Action] Testing Docker action Ganesh Gore 2020-12-05 22:40:33 -0700
• 10cab93799 [Action] Integrated MPW prechecker Ganesh Gore 2020-12-05 19:31:32 -0700
• 40c131983a [FPGA1212_v1] Changed gds precision to 1000 Ganesh Gore 2020-12-05 16:24:05 -0700
• 6af001df11 Added SynRepoConfig is paths Ganesh Gore 2020-12-04 15:25:50 -0700
• 2bada6124f [Action] Changed Docker workdir Ganesh Gore 2020-12-04 11:46:30 -0700
• cfa2bb96c4 [Action] Removed nojekyll file addition Ganesh Gore 2020-12-04 11:19:51 -0700
• 51cd5d6630 [Action] Added Docker itegration Ganesh Gore 2020-12-04 09:23:46 -0700
• 60060762e5 [Action] Replaced destination repo url Ganesh Gore 2020-12-04 09:06:17 -0700
• 2ecc166e95 [Action] Added destination repo push action Ganesh Gore 2020-12-04 01:10:34 -0700
• 8105a46f07 [Actions] Alternate option to modify file Ganesh Gore 2020-12-04 00:22:48 -0700
• d63dfa00b7 [Actions] filename bugfix Ganesh Gore 2020-12-04 00:18:22 -0700
• 027f0f76a2 [bugfix] Indentation bug in actions yaml Ganesh Gore 2020-12-03 23:57:56 -0700
• 41f2844698 [Action] And modify file and push action Ganesh Gore 2020-12-03 23:50:45 -0700
• 62e0cffea1 [Actions] Disables build test in ganesh_dev branch Ganesh Gore 2020-12-03 23:48:45 -0700
• d5a5ec5b1d [Actions] Testing repository fetch option Ganesh Gore 2020-12-03 23:15:15 -0700
• 452af85e98 [Cleanup] Removed/Ignored testbench files from generated source Ganesh Gore 2020-12-02 12:03:24 -0700
• f5c1d9c0a0 [Arch] enable local encoders tangxifan 2020-12-01 20:56:53 -0700
• ad120e205b [CI] Add new arch to CI test tangxifan 2020-12-01 20:55:10 -0700
• 004f9dbcca [Arch] Bug fix in new arch tangxifan 2020-12-01 20:49:02 -0700
• c015d65a03 [Script] Add task run for custom cell FPGA architectures tangxifan 2020-12-01 20:22:16 -0700
• 4ddc6955a3 [Arch] Add architecture using custom cells tangxifan 2020-12-01 20:19:22 -0700
• 22451870dd [CI] Patch github repo path to sync with OpenFPGA repo movement tangxifan 2020-12-01 11:58:19 -0700
• 87f79d78bb [CI] Add wrapper generator examples to CI tangxifan 2020-12-01 11:32:27 -0700
• 696529b43d [Script] Increase routing chan width from 40 to 60 for version 1.2 tangxifan 2020-12-01 10:17:47 -0700
• f572be8fc2
  Merge pull request #56 from lnis-uofu/xt_dev Laboratory for Nano Integrated Systems (LNIS) 2020-12-05 22:11:36 -0700
• 443eb12710 [CI] Add test to CI tangxifan 2020-12-05 21:17:59 -0700
• 22f2b3aa90 [HDL] Add python script to adapt OpenFPGA MUX primitives to use custom cells tangxifan 2020-12-05 21:14:56 -0700
• 6039ae92ca [Arch] Bug fix for buffering two-level routing multiplexers using custom cells tangxifan 2020-12-05 19:37:34 -0700
• 52413059f6
  Merge pull request #55 from lnis-uofu/xt_dev Laboratory for Nano Integrated Systems (LNIS) 2020-12-04 14:47:52 -0700
• 3a75e079ba [Doc] Update the frontpage README tangxifan 2020-12-04 14:09:40 -0700
• f766052bf7 [Doc] Add route W to device comparison tangxifan 2020-12-04 13:41:47 -0700
• 156e1d007c [Doc] Add missing figure and bug fix tangxifan 2020-12-04 13:34:41 -0700
• 1948f000e0 [Doc] Reorganize documentation for SOFA HD device family tangxifan 2020-12-04 12:02:30 -0700
• 6fca7b9641 [Doc] Add figures about fle architecture v1.1 tangxifan 2020-12-04 09:27:11 -0700
• a09933cb75
  Merge pull request #54 from lnis-uofu/xt_dev Laboratory for Nano Integrated Systems (LNIS) 2020-12-03 17:20:02 -0700
• 51167f871e [Testbench] Patch ccff test tangxifan 2020-12-02 20:07:36 -0700
• ce058447f2 [MSIM] Bug fix in reporting errors tangxifan 2020-12-02 20:07:16 -0700
• 2db2b468fe [Script] Try auto number of simulation clock cycles tangxifan 2020-12-02 19:33:28 -0700
• 3a097b38af [CI] Remove the out-of-data tests tangxifan 2020-12-02 18:00:48 -0700
• 930f7ec486 [Script] Remove task run for redundant architectures tangxifan 2020-12-02 17:56:58 -0700
• 7b637e6676 [Testbench] Bug fix in post PnR testbench templates tangxifan 2020-12-02 17:50:49 -0700
• b966829566 [Script] Force a fixed number of clock cycles in simulation to avoid false-positive tangxifan 2020-12-02 17:50:23 -0700
• a19c9bdbda [CI] Add CCFF and SCFF testbench conversion to CI test tangxifan 2020-12-02 15:30:54 -0700
• 6814b3bb60 [Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants tangxifan 2020-12-02 15:22:19 -0700
• 4875b2de95 [HDL] Patch pin assignment names to be consistent with post-PnR netlists tangxifan 2020-12-02 14:02:18 -0700
• 06731e092e [Arch] Patch reset port name to be consistent with post-PnR netlist tangxifan 2020-12-02 13:46:40 -0700
• 20cba3f558 [Testbench] Add testbench for post-PnR verification for FPGA with reset tangxifan 2020-12-02 13:43:06 -0700
• ea3165b14d Merge branch 'master' into xt_dev tangxifan 2020-12-02 13:27:50 -0700
• b9053269e9
  Merge pull request #52 from lnis-uofu/ganesh_dev tangxifan 2020-12-02 13:10:35 -0700
• 0cc5b492d2 [Cleanup] Removed/Ignored testbench files from generated source Ganesh Gore 2020-12-02 12:03:24 -0700
• 61163de580 [Testbench] Correct path to post-pnR netlists and prepare for sign-off on FPGA with reset tangxifan 2020-12-02 12:00:28 -0700
• 361cd2d9e1 Merge remote-tracking branch 'origin/master' into ganesh_dev Ganesh Gore 2020-12-02 10:56:59 -0700
• a90528544d make further changes to VPR binding Tarachand Pagarani 2020-12-02 05:40:56 -0800
• 671f00469c make further changes to VPR binding Tarachand Pagarani 2020-12-02 05:38:51 -0800
• a6939d4a3f make further changes to VPR binding Tarachand Pagarani 2020-12-02 05:36:44 -0800
• 923a502c24 [FPGA1212_v1.1] Added PostPnR files Ganesh Gore 2020-12-02 01:43:58 -0700
• f385c0ca11 [FPGA1212_v1.1] Added OpenFPGA task and verilog netlist Ganesh Gore 2020-12-02 01:43:05 -0700
• 07d1962051
  Merge pull request #51 from lnis-uofu/xt_dev Laboratory for Nano Integrated Systems (LNIS) 2020-12-01 22:16:49 -0700
• b5abfdd994 [Arch] enable local encoders tangxifan 2020-12-01 20:56:53 -0700
• fc92dceb94 [CI] Add new arch to CI test tangxifan 2020-12-01 20:55:10 -0700
• 3b6f3b0691 [Arch] Bug fix in new arch tangxifan 2020-12-01 20:49:02 -0700
• 147dd8d606 [Script] Add task run for custom cell FPGA architectures tangxifan 2020-12-01 20:22:16 -0700
• 454ea09dc4 [Arch] Add architecture using custom cells tangxifan 2020-12-01 20:19:22 -0700
• 29a9dea3ca
  Merge pull request #50 from lnis-uofu/xt_dev Laboratory for Nano Integrated Systems (LNIS) 2020-12-01 15:45:35 -0700
• f2056a9bf9 [Git] Ignore .v as LFS files tangxifan 2020-12-01 14:50:20 -0700
• 4594be46c8 [CI] Patch github repo path to sync with OpenFPGA repo movement tangxifan 2020-12-01 11:58:19 -0700
• 83bd343f70 [CI] Add wrapper generator examples to CI tangxifan 2020-12-01 11:32:27 -0700
• fd7a65c756 Merge remote-tracking branch 'origin/master' into ganesh_dev Ganesh Gore 2020-12-01 11:29:15 -0700
• a134cffb9d Added verilog files only in testbench directory in gitLFS Ganesh Gore 2020-12-01 11:23:02 -0700
• 95cbc60cc2
  Merge pull request #49 from LNIS-Projects/xt_dev Laboratory for Nano Integrated Systems (LNIS) 2020-12-01 11:21:31 -0700
• 0eb1b68bee [Script] Increase routing chan width from 40 to 60 for version 1.2 tangxifan 2020-12-01 10:17:47 -0700
• 8713eb3c5b
  Merge pull request #48 from LNIS-Projects/xt_dev Laboratory for Nano Integrated Systems (LNIS) 2020-12-01 08:56:35 -0700
• d867dbb1bf [Testbench] Bug fix in calling sub python script tangxifan 2020-12-01 08:14:43 -0700
• 11d4b156b4 [Testbench] Bug fix in finding scripts tangxifan 2020-11-30 22:41:29 -0700
• 6d5bb2d794 [CI] Bug fix tangxifan 2020-11-30 22:38:24 -0700
• 764e5310aa [Doc] Add badges to frontpage README tangxifan 2020-11-30 21:29:15 -0700
• 2aa8f81421 [CI] Add more tests tangxifan 2020-11-30 21:25:02 -0700
• 3a6b0c18f7 [CI] Bug fix tangxifan 2020-11-30 20:35:56 -0700
• ef2d19aafa [CI] Bug fix tangxifan 2020-11-30 20:27:41 -0700
• e0d9eb9e7f [CI] Add debugging info tangxifan 2020-11-30 20:18:19 -0700
• 582b3afa6d [CI] Use native cmake build commands tangxifan 2020-11-30 20:14:43 -0700
• 27b16b3619 [CI] Bug fix tangxifan 2020-11-30 20:06:03 -0700