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Merge pull request #50 from lnis-uofu/xt_dev 

Add wrapper generator examples to CI
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Laboratory for Nano Integrated Systems (LNIS) 2020-12-01 15:45:35 -07:00 committed by GitHub
parent 95cbc60cc2 f2056a9bf9
commit 29a9dea3ca
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3 changed files with 6 additions and 2 deletions
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1
.gitattributes vendored
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@ -1,3 +1,2 @@
*.gds filter=lfs diff=lfs merge=lfs -text
*.spef filter=lfs diff=lfs merge=lfs -text
*.v filter=lfs diff=lfs merge=lfs -text

2
.github/workflows/build.yml vendored
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@ -44,7 +44,7 @@ jobs:
- name: Checkout OpenFPGA repo
uses: actions/checkout@v2
with:
repository: LNIS-Projects/OpenFPGA
repository: lnis-uofu/OpenFPGA
path: OpenFPGA
- name: Install dependency

5
.github/workflows/quick_test.sh vendored
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@ -12,6 +12,11 @@ set -e
# - Run FPGA tasks to validate netlist generations
python3 SCRIPT/repo_setup.py --openfpga_root_path ./OpenFPGA
##############################################
# Generate wrapper HDL codes to bridge Caravel I/Os and FPGA I/Os
python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.0.v
python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.1.v
##############################################
# Generate post-PnR testbenches
python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json