Merge pull request #52 from lnis-uofu/ganesh_dev

Ganesh dev

.gitattributes

@@ -1,2 +1,3 @@
 *.gds filter=lfs diff=lfs merge=lfs -text
 *.spef filter=lfs diff=lfs merge=lfs -text
+TESTBENCH/**/*.v filter=lfs diff=lfs merge=lfs -text

.gitignore

@@ -7,3 +7,4 @@
 **/*_Verilog/SRC_Skeleton
 **/*_Verilog/SRCBackup
 **/DOC/build
+**/SRC**/*_tb.v

FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/top_formal_random_top_tb.v

@@ -1,126 +0,0 @@
-//
-//
-//
-//
-//
-//
-//
-//
-`timescale 1ns / 1ps
-
-module top_top_formal_verification_random_tb;
-//
-	reg [0:0] clk;
-
-//
-	reg [0:0] a;
-	reg [0:0] b;
-
-//
-	wire [0:0] out:c_gfpga;
-
-`ifdef AUTOCHECKED_SIMULATION
-
-//
-	wire [0:0] out:c_bench;
-
-//
-	reg [0:0] out:c_flag;
-
-`endif
-
-//
-	integer nb_error= 0;
-
-//
-	top_top_formal_verification FPGA_DUT(
-		.a_fm(a),
-		.b_fm(b),
-		.out:c_fm(out:c_gfpga)	);
-//
-
-`ifdef AUTOCHECKED_SIMULATION
-//
-	top REF_DUT(
-		.a(a),
-		.b(b),
-		.c(out:c_bench)	);
-//
-
-`endif
-
-//
-	initial begin
-		clk[0] <= 1'b0;
-		while(1) begin
-			#0.5551859605
-			clk[0] <= !clk[0];
-		end
-	end
-
-//
-	initial begin
-		a <= 1'b0;
-		b <= 1'b0;
-
-		out:c_flag[0] <= 1'b0;
-	end
-
-//
-	always@(negedge clk[0]) begin
-		a <= $random;
-		b <= $random;
-	end
-
-`ifdef AUTOCHECKED_SIMULATION
-//
-//
-	reg [0:0] sim_start;
-
-	always@(negedge clk[0]) begin
-		if (1'b1 == sim_start[0]) begin
-			sim_start[0] <= ~sim_start[0];
-		end else begin
-			if(!(out:c_gfpga === out:c_bench) && !(out:c_bench === 1'bx)) begin
-				out:c_flag <= 1'b1;
-			end else begin
-				out:c_flag<= 1'b0;
-			end
-		end
-	end
-
-	always@(posedge out:c_flag) begin
-		if(out:c_flag) begin
-			nb_error = nb_error + 1;
-			$display("Mismatch on out:c_gfpga at time = %t", $realtime);
-		end
-	end
-
-`endif
-
-`ifdef ICARUS_SIMULATOR
-//
-	initial begin
-		$dumpfile("top_formal.vcd");
-		$dumpvars(1, top_top_formal_verification_random_tb);
-	end
-`endif
-//
-
-initial begin
-	sim_start[0] <= 1'b1;
-	$timeformat(-9, 2, "ns", 20);
-	$display("Simulation start");
-//
-	#444
-	if(nb_error == 0) begin
-		$display("Simulation Succeed");
-	end else begin
-		$display("Simulation Failed with %d error(s)", nb_error);
-	end
-	$finish;
-end
-
-endmodule
-//
-

FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.top_only.pt.v

@@ -0,0 +1,443 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__0_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , 
+    top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , 
+    top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , 
+    top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , 
+    top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , 
+    top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , 
+    top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , 
+    top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , 
+    top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , 
+    top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , 
+    top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , 
+    top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , 
+    top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , 
+    top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , 
+    SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , prog_clk_0_N_in , 
+    prog_clk_0_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_16_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] top_width_0_height_0__pin_0_ ;
+input  [0:0] top_width_0_height_0__pin_2_ ;
+input  [0:0] top_width_0_height_0__pin_4_ ;
+input  [0:0] top_width_0_height_0__pin_6_ ;
+input  [0:0] top_width_0_height_0__pin_8_ ;
+input  [0:0] top_width_0_height_0__pin_10_ ;
+input  [0:0] top_width_0_height_0__pin_12_ ;
+input  [0:0] top_width_0_height_0__pin_14_ ;
+input  [0:0] top_width_0_height_0__pin_16_ ;
+output [0:0] top_width_0_height_0__pin_1_upper ;
+output [0:0] top_width_0_height_0__pin_1_lower ;
+output [0:0] top_width_0_height_0__pin_3_upper ;
+output [0:0] top_width_0_height_0__pin_3_lower ;
+output [0:0] top_width_0_height_0__pin_5_upper ;
+output [0:0] top_width_0_height_0__pin_5_lower ;
+output [0:0] top_width_0_height_0__pin_7_upper ;
+output [0:0] top_width_0_height_0__pin_7_lower ;
+output [0:0] top_width_0_height_0__pin_9_upper ;
+output [0:0] top_width_0_height_0__pin_9_lower ;
+output [0:0] top_width_0_height_0__pin_11_upper ;
+output [0:0] top_width_0_height_0__pin_11_lower ;
+output [0:0] top_width_0_height_0__pin_13_upper ;
+output [0:0] top_width_0_height_0__pin_13_lower ;
+output [0:0] top_width_0_height_0__pin_15_upper ;
+output [0:0] top_width_0_height_0__pin_15_lower ;
+output [0:0] top_width_0_height_0__pin_17_upper ;
+output [0:0] top_width_0_height_0__pin_17_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
+wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_5 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_116 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_6 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_7 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_114 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_115 ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .io_outpad ( top_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( top_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , 
+    .io_outpad ( top_width_0_height_0__pin_2_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_3_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_512_ } ) ,
+    .io_outpad ( top_width_0_height_0__pin_4_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_5_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , 
+    .ZBUF_184_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , 
+    .io_outpad ( top_width_0_height_0__pin_6_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_7_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , 
+    .io_outpad ( top_width_0_height_0__pin_8_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_9_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , 
+    .io_outpad ( top_width_0_height_0__pin_10_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_11_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , 
+    .io_outpad ( top_width_0_height_0__pin_12_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_13_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , 
+    .io_outpad ( top_width_0_height_0__pin_14_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_15_lower ) , 
+    .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ) ;
+cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , 
+    .io_outpad ( top_width_0_height_0__pin_16_ ) , 
+    .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , 
+    .io_inpad ( top_width_0_height_0__pin_17_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_1117 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( top_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( 
+    .A ( top_width_0_height_0__pin_3_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( 
+    .A ( top_width_0_height_0__pin_5_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_62__61 ( 
+    .A ( top_width_0_height_0__pin_7_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_63__62 ( 
+    .A ( top_width_0_height_0__pin_9_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_64__63 ( 
+    .A ( top_width_0_height_0__pin_11_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_65__64 ( 
+    .A ( top_width_0_height_0__pin_13_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_66__65 ( 
+    .A ( top_width_0_height_0__pin_15_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_67__66 ( 
+    .A ( top_width_0_height_0__pin_17_lower[0] ) , 
+    .X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , 
+    .HI ( optlc_net_114 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , 
+    .HI ( optlc_net_115 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , 
+    .HI ( optlc_net_116 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_184_inst_121 ( .A ( aps_rename_512_ ) , 
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_3521248 ( .A ( ctsbuf_net_1117 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+

FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.top_only.pt.v

@@ -0,0 +1,472 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__1_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , 
+    REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , prog_clk_0_N_in , 
+    prog_clk_0_W_out , prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , 
+    prog_clk_1_S_out , prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , 
+    prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , 
+    prog_clk_3_W_out , clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , 
+    clk_2_E_in , clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , 
+    clk_3_E_in , clk_3_E_out , clk_3_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  REGIN_FEEDTHROUGH ;
+output REGOUT_FEEDTHROUGH ;
+input  prog_clk_0_N_in ;
+output prog_clk_0_W_out ;
+input  prog_clk_1_W_in ;
+input  prog_clk_1_E_in ;
+output prog_clk_1_N_out ;
+output prog_clk_1_S_out ;
+input  prog_clk_2_E_in ;
+input  prog_clk_2_W_in ;
+output prog_clk_2_W_out ;
+output prog_clk_2_E_out ;
+input  prog_clk_3_W_in ;
+input  prog_clk_3_E_in ;
+output prog_clk_3_E_out ;
+output prog_clk_3_W_out ;
+input  clk_1_W_in ;
+input  clk_1_E_in ;
+output clk_1_N_out ;
+output clk_1_S_out ;
+input  clk_2_E_in ;
+input  clk_2_W_in ;
+output clk_2_W_out ;
+output clk_2_E_out ;
+input  clk_3_W_in ;
+input  clk_3_E_in ;
+output clk_3_E_out ;
+output clk_3_W_out ;
+
+wire ropt_net_94 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_1_E_in = prog_clk_1_W_in ;
+assign prog_clk_2_W_in = prog_clk_2_E_in ;
+assign prog_clk_3_E_in = prog_clk_3_W_in ;
+assign clk_1_E_in = clk_1_W_in ;
+assign clk_2_W_in = clk_2_E_in ;
+assign clk_3_E_in = clk_3_W_in ;
+
+cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_4 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_8 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_12 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ropt_net_100 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_71 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_69 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[13] , chanx_left_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[17] , chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_70 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
+    .X ( ctsbuf_net_173 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , 
+    .X ( prog_clk_2_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , 
+    .X ( prog_clk_3_W_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_N_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , 
+    .X ( clk_1_S_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , 
+    .X ( clk_2_W_out ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_68 ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_E_out ) ) ;
+sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , 
+    .X ( clk_3_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_12 FTB_18__17 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( SC_IN_BOT ) , .X ( ropt_net_94 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( REGIN_FEEDTHROUGH ) , 
+    .X ( REGOUT_FEEDTHROUGH ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , 
+    .Y ( prog_clk_1_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_65 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , 
+    .Y ( prog_clk_1_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_67 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( net_net_68 ) , .X ( clk_2_E_out ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_70 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_71 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , 
+    .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1318 ( .A ( ropt_net_94 ) , 
+    .X ( ropt_net_104 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521204 ( .A ( ctsbuf_net_173 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1325 ( .A ( ropt_net_100 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1329 ( .A ( ropt_net_104 ) , 
+    .X ( SC_OUT_TOP ) ) ;
+endmodule
+
+

FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.top_only.pt.v

@@ -0,0 +1,432 @@
+//
+//
+//
+//
+//
+//
+module cbx_1__2_ ( chanx_left_in , chanx_right_in , ccff_head , 
+    chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , 
+    bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , 
+    bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , 
+    bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , 
+    bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , 
+    bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , 
+    ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , 
+    bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , 
+    SC_IN_BOT , SC_OUT_TOP , prog_clk_0_S_in , prog_clk_0_W_out ) ;
+input  [0:19] chanx_left_in ;
+input  [0:19] chanx_right_in ;
+input  [0:0] ccff_head ;
+output [0:19] chanx_left_out ;
+output [0:19] chanx_right_out ;
+output [0:0] top_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_0_ ;
+output [0:0] bottom_grid_pin_1_ ;
+output [0:0] bottom_grid_pin_2_ ;
+output [0:0] bottom_grid_pin_3_ ;
+output [0:0] bottom_grid_pin_4_ ;
+output [0:0] bottom_grid_pin_5_ ;
+output [0:0] bottom_grid_pin_6_ ;
+output [0:0] bottom_grid_pin_7_ ;
+output [0:0] bottom_grid_pin_8_ ;
+output [0:0] bottom_grid_pin_9_ ;
+output [0:0] bottom_grid_pin_10_ ;
+output [0:0] bottom_grid_pin_11_ ;
+output [0:0] bottom_grid_pin_12_ ;
+output [0:0] bottom_grid_pin_13_ ;
+output [0:0] bottom_grid_pin_14_ ;
+output [0:0] bottom_grid_pin_15_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] bottom_width_0_height_0__pin_0_ ;
+output [0:0] bottom_width_0_height_0__pin_1_upper ;
+output [0:0] bottom_width_0_height_0__pin_1_lower ;
+input  SC_IN_TOP ;
+output SC_OUT_BOT ;
+input  SC_IN_BOT ;
+output SC_OUT_TOP ;
+input  prog_clk_0_S_in ;
+output prog_clk_0_W_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[11] , chanx_left_out[11] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_3 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[8] , chanx_left_out[8] , chanx_right_out[14] , 
+        chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_4 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[5] , chanx_left_out[5] , 
+        chanx_right_out[9] , chanx_left_out[9] , chanx_right_out[15] , 
+        chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_7 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[8] , chanx_left_out[8] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , 
+        chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_8 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , 
+        chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_11 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_12 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[17] , 
+        chanx_left_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[4] , chanx_left_out[4] , 
+        chanx_right_out[10] , chanx_left_out[10] , chanx_right_out[16] , 
+        chanx_left_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_2 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_5 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_6 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_72 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_9 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[6] , chanx_left_out[6] , 
+        chanx_right_out[14] , chanx_left_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_75 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_10 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[7] , chanx_left_out[7] , 
+        chanx_right_out[15] , chanx_left_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_13 (
+    .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[2] , 
+        chanx_left_out[2] , chanx_right_out[10] , chanx_left_out[10] , 
+        chanx_right_out[18] , chanx_left_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_73 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_14 (
+    .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[3] , 
+        chanx_left_out[3] , chanx_right_out[11] , chanx_left_out[11] , 
+        chanx_right_out[19] , chanx_left_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_74 ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_14 ( .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , 
+    .X ( ctsbuf_net_176 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
+    .X ( chanx_right_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
+    .X ( chanx_right_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
+    .X ( chanx_right_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
+    .X ( chanx_right_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
+    .X ( chanx_right_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
+    .X ( chanx_right_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
+    .X ( chanx_right_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
+    .X ( chanx_right_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
+    .X ( chanx_right_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
+    .X ( chanx_right_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
+    .X ( chanx_right_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
+    .X ( chanx_right_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
+    .X ( chanx_right_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
+    .X ( chanx_right_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
+    .X ( chanx_right_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
+    .X ( chanx_right_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
+    .X ( chanx_right_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
+    .X ( chanx_right_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
+    .X ( chanx_right_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
+    .X ( chanx_right_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[0] ) , 
+    .X ( chanx_left_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[1] ) , 
+    .X ( chanx_left_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[2] ) , 
+    .X ( chanx_left_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[3] ) , 
+    .X ( chanx_left_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[4] ) , 
+    .X ( chanx_left_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[5] ) , 
+    .X ( chanx_left_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[6] ) , 
+    .X ( chanx_left_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[7] ) , 
+    .X ( chanx_left_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[8] ) , 
+    .X ( chanx_left_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[9] ) , 
+    .X ( chanx_left_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[10] ) , 
+    .X ( chanx_left_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[11] ) , 
+    .X ( chanx_left_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[12] ) , 
+    .X ( chanx_left_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[13] ) , 
+    .X ( chanx_left_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[14] ) , 
+    .X ( chanx_left_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[15] ) , 
+    .X ( chanx_left_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[16] ) , 
+    .X ( chanx_left_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[17] ) , 
+    .X ( chanx_left_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[18] ) , 
+    .X ( chanx_left_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[19] ) , 
+    .X ( chanx_left_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( bottom_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_60__59 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_72 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_73 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_74 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521207 ( .A ( ctsbuf_net_176 ) , 
+    .X ( prog_clk_0_W_out ) ) ;
+endmodule
+
+

FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v

@@ -0,0 +1,356 @@
+//
+//
+//
+//
+//
+//
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_55 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , 
+    .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_56 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , 
+    .X ( copt_net_57 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , 
+    .X ( copt_net_58 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , 
+    .X ( copt_net_59 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , 
+    .X ( copt_net_60 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_43 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_43 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_43 ( .A ( BUF_net_45 ) , .Y ( BUF_net_43 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_45 ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_54 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , 
+    .X ( copt_net_49 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , 
+    .X ( copt_net_50 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , 
+    .X ( copt_net_51 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_52 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , 
+    .X ( copt_net_53 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , 
+    .X ( copt_net_54 ) ) ;
+endmodule
+
+
+module cby_0__1__const1 ( const1 ) ;
+output [0:0] const1 ;
+
+wire [0:0] const1_0 ;
+
+assign const1_0[0] = 1'b1 ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+cby_0__1__const1 const1_0_ (
+    .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_47 ) ) ;
+endmodule
+
+
+module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
+    right_width_0_height_0__pin_1_lower , prog_clk_0_E_in ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_73 ;
+wire ropt_net_75 ;
+wire ropt_net_74 ;
+wire ropt_net_72 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_48 ) ) ;
+cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
+    .X ( ropt_net_73 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
+    .X ( ropt_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , 
+    .X ( ropt_net_74 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( ropt_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( 
+    .A ( right_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_48 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , 
+    .X ( chany_top_out[8] ) ) ;
+endmodule
+
+

FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v

@@ -0,0 +1,395 @@
+//
+//
+//
+//
+//
+//
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+wire copt_net_55 ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , 
+    .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , 
+    .X ( copt_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , 
+    .X ( copt_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , 
+    .X ( copt_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , 
+    .X ( copt_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_43 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_43 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_43 ( .A ( BUF_net_45 ) , .Y ( BUF_net_43 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail , VDD , VSS ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_54 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , 
+    .X ( copt_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , 
+    .X ( copt_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , 
+    .X ( copt_net_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , 
+    .X ( copt_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , 
+    .X ( copt_net_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_47 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
+    right_width_0_height_0__pin_1_lower , prog_clk_0_E_in , VDD , VSS ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_E_in ;
+input  VDD ;
+input  VSS ;
+
+wire ropt_net_73 ;
+wire ropt_net_75 ;
+wire ropt_net_74 ;
+wire ropt_net_72 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_48 ) ) ;
+cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
+    .X ( ropt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
+    .X ( ropt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , 
+    .X ( ropt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( ropt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( 
+    .A ( right_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , 
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , 
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , 
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , 
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+

FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v

@@ -0,0 +1,345 @@
+//
+//
+//
+//
+//
+//
+module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( prog_clk , 
+    ccff_head , ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:0] mem_out ;
+
+wire copt_net_55 ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( copt_net_55 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_59 ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1187 ( .A ( copt_net_55 ) , 
+    .X ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1188 ( .A ( mem_out[0] ) , 
+    .X ( copt_net_56 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1189 ( .A ( copt_net_60 ) , 
+    .X ( copt_net_57 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1190 ( .A ( copt_net_57 ) , 
+    .X ( copt_net_58 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1191 ( .A ( copt_net_58 ) , 
+    .X ( copt_net_59 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1192 ( .A ( copt_net_56 ) , 
+    .X ( copt_net_60 ) ) ;
+endmodule
+
+
+module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+input  SOC_IN ;
+output SOC_OUT ;
+output SOC_DIR ;
+output FPGA_IN ;
+input  FPGA_OUT ;
+input  FPGA_DIR ;
+input  IO_ISOL_N ;
+
+sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_43 ) , .Y ( SOC_DIR_N ) ) ;
+sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
+    .TE_B ( BUF_net_43 ) , .Z ( SOC_OUT ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_43 ( .A ( BUF_net_45 ) , .Y ( BUF_net_43 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_44 ( .A ( BUF_net_45 ) , .Y ( SOC_DIR ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_45 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_45 ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , iopad_outpad , ccff_head , 
+    iopad_inpad , ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] iopad_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] iopad_inpad ;
+output [0:0] ccff_tail ;
+
+wire [0:0] EMBEDDED_IO_HD_0_en ;
+
+cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
+    .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
+    .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
+    .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
+    .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfxtp_1_mem ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+endmodule
+
+
+module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , prog_clk , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
+    ccff_tail ) ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] prog_clk ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] io_outpad ;
+input  [0:0] ccff_head ;
+output [0:0] io_inpad ;
+output [0:0] ccff_tail ;
+
+cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , 
+    ccff_tail , mem_out ) ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:3] mem_out ;
+
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_0_ ( .D ( copt_net_54 ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_2_ ( .D ( mem_out[1] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) ) ;
+sky130_fd_sc_hd__dfxtp_4 sky130_fd_sc_hd__dfxtp_1_3_ ( .D ( mem_out[2] ) , 
+    .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1181 ( .A ( copt_net_51 ) , 
+    .X ( copt_net_49 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1182 ( .A ( copt_net_52 ) , 
+    .X ( copt_net_50 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1183 ( .A ( copt_net_53 ) , 
+    .X ( copt_net_51 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1184 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_52 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1185 ( .A ( copt_net_50 ) , 
+    .X ( copt_net_53 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1186 ( .A ( copt_net_49 ) , 
+    .X ( copt_net_54 ) ) ;
+endmodule
+
+
+module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+input  [0:9] in ;
+input  [0:3] sram ;
+input  [0:3] sram_inv ;
+output [0:0] out ;
+input  p0 ;
+
+wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
+wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+
+sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , 
+    .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( 
+    .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , 
+    .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , 
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_46 ( .A ( BUF_net_47 ) , .Y ( out[0] ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_47 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
+    .Y ( BUF_net_47 ) ) ;
+endmodule
+
+
+module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
+    right_width_0_height_0__pin_1_lower , prog_clk_0_E_in ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_73 ;
+wire ropt_net_75 ;
+wire ropt_net_74 ;
+wire ropt_net_72 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_48 ) ) ;
+cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
+    .X ( ropt_net_73 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
+    .X ( ropt_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , 
+    .X ( ropt_net_74 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( ropt_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( 
+    .A ( right_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_48 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , 
+    .X ( chany_top_out[8] ) ) ;
+endmodule
+
+

FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.top_only.pt.v

@@ -0,0 +1,158 @@
+//
+//
+//
+//
+//
+//
+module cby_0__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
+    right_width_0_height_0__pin_1_lower , prog_clk_0_E_in ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_0_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] right_width_0_height_0__pin_0_ ;
+output [0:0] right_width_0_height_0__pin_1_upper ;
+output [0:0] right_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_E_in ;
+
+wire ropt_net_73 ;
+wire ropt_net_75 ;
+wire ropt_net_74 ;
+wire ropt_net_72 ;
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_48 ) ) ;
+cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( right_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
+    .ccff_tail ( ccff_tail ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
+    .X ( ropt_net_73 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
+    .X ( ropt_net_75 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_24__23 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_top_in[3] ) , 
+    .X ( ropt_net_74 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_28__27 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_41__40 ( .A ( chany_top_in[18] ) , 
+    .X ( ropt_net_72 ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_43__42 ( 
+    .A ( right_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_48 ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1204 ( .A ( ropt_net_72 ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1205 ( .A ( ropt_net_73 ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1206 ( .A ( ropt_net_74 ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 ropt_mt_inst_1207 ( .A ( ropt_net_75 ) , 
+    .X ( chany_top_out[8] ) ) ;
+endmodule
+
+

FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.top_only.pt.v

@@ -0,0 +1,471 @@
+//
+//
+//
+//
+//
+//
+module cby_1__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , 
+    left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , 
+    left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , 
+    left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , 
+    left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , 
+    left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , 
+    Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , 
+    Test_en_E_out , prog_clk_0_W_in , prog_clk_0_S_out , prog_clk_0_N_out , 
+    prog_clk_2_N_in , prog_clk_2_S_in , prog_clk_2_S_out , prog_clk_2_N_out , 
+    prog_clk_3_S_in , prog_clk_3_N_in , prog_clk_3_N_out , prog_clk_3_S_out , 
+    clk_2_N_in , clk_2_S_in , clk_2_S_out , clk_2_N_out , clk_3_S_in , 
+    clk_3_N_in , clk_3_N_out , clk_3_S_out ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  Test_en_S_in ;
+input  Test_en_E_in ;
+input  Test_en_W_in ;
+output Test_en_N_out ;
+output Test_en_W_out ;
+output Test_en_E_out ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+input  prog_clk_2_N_in ;
+input  prog_clk_2_S_in ;
+output prog_clk_2_S_out ;
+output prog_clk_2_N_out ;
+input  prog_clk_3_S_in ;
+input  prog_clk_3_N_in ;
+output prog_clk_3_N_out ;
+output prog_clk_3_S_out ;
+input  clk_2_N_in ;
+input  clk_2_S_in ;
+output clk_2_S_out ;
+output clk_2_N_out ;
+input  clk_3_S_in ;
+input  clk_3_N_in ;
+output clk_3_N_out ;
+output clk_3_S_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign Test_en_E_in = Test_en_S_in ;
+assign Test_en_E_in = Test_en_W_in ;
+assign prog_clk_0 = prog_clk[0] ;
+assign prog_clk_2_S_in = prog_clk_2_N_in ;
+assign prog_clk_3_N_in = prog_clk_3_S_in ;
+assign clk_2_S_in = clk_2_N_in ;
+assign clk_3_N_in = clk_3_S_in ;
+
+cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_4 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_8 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_12 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[15] , chany_bottom_out[15] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { copt_net_87 } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[13] , chany_bottom_out[13] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[17] , chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( aps_rename_505_ ) ) ;
+sky130_fd_sc_hd__buf_4 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( ropt_net_94 ) ) ;
+sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , 
+    .X ( net_net_67 ) ) ;
+sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ropt_net_93 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , 
+    .X ( ZBUF_6_f_1 ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( prog_clk_3_N_out ) ) ;
+sky130_fd_sc_hd__buf_4 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , 
+    .X ( ropt_net_95 ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , 
+    .X ( clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_4 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , .X ( ZBUF_6_f_0 ) ) ;
+sky130_fd_sc_hd__buf_4 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( ropt_net_99 ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , 
+    .X ( aps_rename_506_ ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( Test_en_N_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( aps_rename_505_ ) , 
+    .Y ( BUF_net_66 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( net_net_67 ) , .X ( Test_en_E_out ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( clk_3_S_out ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( aps_rename_506_ ) , 
+    .Y ( BUF_net_69 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1303 ( .A ( ZBUF_6_f_0 ) , 
+    .X ( clk_2_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1304 ( .A ( ZBUF_6_f_1 ) , 
+    .X ( prog_clk_2_N_out ) ) ;
+sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1325 ( .A ( copt_net_91 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1337 ( .A ( ropt_net_99 ) , 
+    .X ( clk_3_N_out ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_87 ) , 
+    .X ( copt_net_90 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_92 ) , 
+    .X ( copt_net_91 ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_90 ) , 
+    .X ( copt_net_92 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1331 ( .A ( ropt_net_93 ) , 
+    .X ( prog_clk_2_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1332 ( .A ( ropt_net_94 ) , 
+    .X ( Test_en_W_out ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_mt_inst_1333 ( .A ( ropt_net_95 ) , 
+    .X ( prog_clk_3_S_out ) ) ;
+endmodule
+
+

FPGA1212_FLAT_HD_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.top_only.pt.v

@@ -0,0 +1,436 @@
+//
+//
+//
+//
+//
+//
+module cby_2__1_ ( chany_bottom_in , chany_top_in , ccff_head , 
+    chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , 
+    left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , 
+    left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , 
+    left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , 
+    left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , 
+    left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , 
+    IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
+    gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
+    left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , 
+    left_width_0_height_0__pin_1_lower , prog_clk_0_W_in , prog_clk_0_S_out , 
+    prog_clk_0_N_out ) ;
+input  [0:19] chany_bottom_in ;
+input  [0:19] chany_top_in ;
+input  [0:0] ccff_head ;
+output [0:19] chany_bottom_out ;
+output [0:19] chany_top_out ;
+output [0:0] right_grid_pin_0_ ;
+output [0:0] left_grid_pin_16_ ;
+output [0:0] left_grid_pin_17_ ;
+output [0:0] left_grid_pin_18_ ;
+output [0:0] left_grid_pin_19_ ;
+output [0:0] left_grid_pin_20_ ;
+output [0:0] left_grid_pin_21_ ;
+output [0:0] left_grid_pin_22_ ;
+output [0:0] left_grid_pin_23_ ;
+output [0:0] left_grid_pin_24_ ;
+output [0:0] left_grid_pin_25_ ;
+output [0:0] left_grid_pin_26_ ;
+output [0:0] left_grid_pin_27_ ;
+output [0:0] left_grid_pin_28_ ;
+output [0:0] left_grid_pin_29_ ;
+output [0:0] left_grid_pin_30_ ;
+output [0:0] left_grid_pin_31_ ;
+output [0:0] ccff_tail ;
+input  [0:0] IO_ISOL_N ;
+input  [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
+output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
+input  [0:0] left_width_0_height_0__pin_0_ ;
+output [0:0] left_width_0_height_0__pin_1_upper ;
+output [0:0] left_width_0_height_0__pin_1_lower ;
+input  prog_clk_0_W_in ;
+output prog_clk_0_S_out ;
+output prog_clk_0_N_out ;
+
+wire [0:0] prog_clk ;
+wire prog_clk_0 ;
+wire [0:3] mux_tree_tapbuf_size10_0_sram ;
+wire [0:3] mux_tree_tapbuf_size10_1_sram ;
+wire [0:3] mux_tree_tapbuf_size10_2_sram ;
+wire [0:3] mux_tree_tapbuf_size10_3_sram ;
+wire [0:3] mux_tree_tapbuf_size10_4_sram ;
+wire [0:3] mux_tree_tapbuf_size10_5_sram ;
+wire [0:3] mux_tree_tapbuf_size10_6_sram ;
+wire [0:3] mux_tree_tapbuf_size10_7_sram ;
+wire [0:3] mux_tree_tapbuf_size10_8_sram ;
+wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ;
+wire [0:3] mux_tree_tapbuf_size8_0_sram ;
+wire [0:3] mux_tree_tapbuf_size8_1_sram ;
+wire [0:3] mux_tree_tapbuf_size8_2_sram ;
+wire [0:3] mux_tree_tapbuf_size8_3_sram ;
+wire [0:3] mux_tree_tapbuf_size8_4_sram ;
+wire [0:3] mux_tree_tapbuf_size8_5_sram ;
+wire [0:3] mux_tree_tapbuf_size8_6_sram ;
+wire [0:3] mux_tree_tapbuf_size8_7_sram ;
+wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ;
+wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ;
+
+assign prog_clk_0 = prog_clk[0] ;
+
+cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
+        SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[11] , chany_bottom_out[11] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
+        SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_3 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[8] , chany_bottom_out[8] , chany_top_out[14] , 
+        chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size10_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
+        SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
+    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_4 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[5] , chany_bottom_out[5] , 
+        chany_top_out[9] , chany_bottom_out[9] , chany_top_out[15] , 
+        chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size10_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
+        SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
+    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_7 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[8] , chany_bottom_out[8] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , 
+        chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size10_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
+        SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
+    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_8 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , 
+        chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size10_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
+        SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
+    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_11 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[12] , chany_bottom_out[12] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
+        SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
+    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_12 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[13] , chany_bottom_out[13] , chany_top_out[17] , 
+        chany_bottom_out[17] } ) ,
+    .sram ( mux_tree_tapbuf_size10_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
+        SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
+    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[4] , chany_bottom_out[4] , 
+        chany_top_out[10] , chany_bottom_out[10] , chany_top_out[16] , 
+        chany_bottom_out[16] } ) ,
+    .sram ( mux_tree_tapbuf_size10_8_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
+        SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
+    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( 
+    .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_3 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_4 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_7 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_8 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_11 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_12 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) ,
+    .ccff_tail ( { ccff_tail_mid } ) ,
+    .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_0_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
+        SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
+    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_2 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_1_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
+        SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
+    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_5 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_2_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
+        SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
+    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_78 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_6 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_3_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
+        SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
+    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_9 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[6] , chany_bottom_out[6] , 
+        chany_top_out[14] , chany_bottom_out[14] } ) ,
+    .sram ( mux_tree_tapbuf_size8_4_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
+        SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
+    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_10 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[7] , chany_bottom_out[7] , 
+        chany_top_out[15] , chany_bottom_out[15] } ) ,
+    .sram ( mux_tree_tapbuf_size8_5_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
+        SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
+    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_77 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_13 (
+    .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[2] , 
+        chany_bottom_out[2] , chany_top_out[10] , chany_bottom_out[10] , 
+        chany_top_out[18] , chany_bottom_out[18] } ) ,
+    .sram ( mux_tree_tapbuf_size8_6_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
+        SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
+    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_76 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_14 (
+    .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[3] , 
+        chany_bottom_out[3] , chany_top_out[11] , chany_bottom_out[11] , 
+        chany_top_out[19] , chany_bottom_out[19] } ) ,
+    .sram ( mux_tree_tapbuf_size8_7_sram ) ,
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
+        SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
+    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_75 ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_2 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_5 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_6 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_9 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_4_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_10 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_5_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_13 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_6_sram ) ) ;
+cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_14 ( 
+    .prog_clk ( prog_clk ) , 
+    .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , 
+    .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , 
+    .mem_out ( mux_tree_tapbuf_size8_7_sram ) ) ;
+cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
+    .IO_ISOL_N ( IO_ISOL_N ) , .prog_clk ( prog_clk ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
+    .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
+    .io_outpad ( left_width_0_height_0__pin_0_ ) ,
+    .ccff_head ( { ccff_tail_mid } ) ,
+    .io_inpad ( left_width_0_height_0__pin_1_lower ) ,
+    .ccff_tail ( { ropt_net_91 } ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
+    .X ( prog_clk[0] ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_179 ) ) ;
+sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
+    .X ( ctsbuf_net_280 ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , 
+    .X ( chany_top_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , 
+    .X ( chany_top_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , 
+    .X ( chany_top_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , 
+    .X ( chany_top_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , 
+    .X ( chany_top_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , 
+    .X ( chany_top_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , 
+    .X ( chany_top_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , 
+    .X ( chany_top_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , 
+    .X ( chany_top_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , 
+    .X ( chany_top_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , 
+    .X ( chany_top_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , 
+    .X ( chany_top_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , 
+    .X ( chany_top_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , 
+    .X ( chany_top_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , 
+    .X ( chany_top_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , 
+    .X ( chany_top_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , 
+    .X ( chany_top_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , 
+    .X ( chany_top_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , 
+    .X ( chany_top_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , 
+    .X ( chany_top_out[19] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[0] ) , 
+    .X ( chany_bottom_out[0] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_top_in[1] ) , 
+    .X ( chany_bottom_out[1] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[2] ) , 
+    .X ( chany_bottom_out[2] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[3] ) , 
+    .X ( chany_bottom_out[3] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_top_in[4] ) , 
+    .X ( chany_bottom_out[4] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_top_in[5] ) , 
+    .X ( chany_bottom_out[5] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[6] ) , 
+    .X ( chany_bottom_out[6] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[7] ) , 
+    .X ( chany_bottom_out[7] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[8] ) , 
+    .X ( chany_bottom_out[8] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[9] ) , 
+    .X ( chany_bottom_out[9] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , 
+    .X ( chany_bottom_out[10] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , 
+    .X ( chany_bottom_out[11] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , 
+    .X ( chany_bottom_out[12] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[13] ) , 
+    .X ( chany_bottom_out[13] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[14] ) , 
+    .X ( chany_bottom_out[14] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[15] ) , 
+    .X ( chany_bottom_out[15] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[16] ) , 
+    .X ( chany_bottom_out[16] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[17] ) , 
+    .X ( chany_bottom_out[17] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[18] ) , 
+    .X ( chany_bottom_out[18] ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[19] ) , 
+    .X ( chany_bottom_out[19] ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_59__58 ( 
+    .A ( left_width_0_height_0__pin_1_lower[0] ) , 
+    .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
+    .HI ( optlc_net_75 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
+    .HI ( optlc_net_76 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
+    .HI ( optlc_net_77 ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
+    .HI ( optlc_net_78 ) ) ;
+sky130_fd_sc_hd__buf_6 ropt_h_inst_1313 ( .A ( ropt_net_92 ) , 
+    .X ( ccff_tail[0] ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3471205 ( .A ( ctsbuf_net_179 ) , 
+    .X ( prog_clk_0_S_out ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_3521210 ( .A ( ctsbuf_net_280 ) , 
+    .X ( prog_clk_0_N_out ) ) ;
+sky130_fd_sc_hd__buf_1 ropt_h_inst_1314 ( .A ( ropt_net_91 ) , 
+    .X ( ropt_net_92 ) ) ;
+endmodule
+
+