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[Doc] Add missing figure and bug fix

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tangxifan 2020-12-04 13:34:41 -07:00
parent 1948f000e0
commit 156e1d007c
16 changed files with 5243 additions and 30 deletions
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DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_clb_arch.svg Normal file
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<metadata> Produced by OmniGraffle 7.18\n2020-11-29 03:10:55 +0000</metadata>
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<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="10.382812" y="15">Caravel Logic Analyzer</tspan>
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<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="3.1015625" y="34">Caravel Wishbone rst_i</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.765625" y="53">Caravel Wishbone stb_i</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="0" y="72">Caravel Wishbone cyc_i</tspan>
<tspan font-family="Times" font-size="16" font-weight="400" fill="black" x="1.7734375" y="91">Caravel Wishbone we_i</tspan>
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<tspan font-family="Times" font-size="16" font-weight="400" fill="#ff2600" x="0" y="53">- When Caravel GPIO[25] is logic ‘0’, FPGA is interfacing the logic analyzer</tspan>
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After

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10
DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst
View File

@ -3,6 +3,12 @@
Architecture
-------------
.. _qlsofa_hd_fpga_arch_floorplan:
Floorplan
^^^^^^^^^
:numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`).
@ -19,7 +25,7 @@ I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RIS
.. _qlsofa_hd_fpga_arch_tiles:
Tiles
-----
^^^^^
The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built:
@ -56,7 +62,7 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
.. _qlsofa_hd_fpga_arch_scan_chain:
Scan-chain
----------
^^^^^^^^^^
There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`.

32
DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst
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@ -3,8 +3,8 @@
I/O Resources
-------------
DATA I/Os
^^^^^^^^^
Pin Assignment
^^^^^^^^^^^^^^
The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`.
@ -31,9 +31,9 @@ Among the 144 I/Os,
.. _io_resource_qlsofa_hd_external_io:
External I/Os
~~~~~~~~~~~~~
^^^^^^^^^^^^^
A SOFA HD FPGA IP contains 37 external I/O pins, including 29 data I/Os and 8 control I/Os.
A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os.
Full details are summarized in the following table.
@ -42,21 +42,25 @@ Full details are summarized in the following table.
+-----------+------------------------------------------------------------------------+-------------+
| I/O Type | Description | No. of Pins |
+===========+========================================================================+=============+
| Data I/O | Datapath I/Os of FPGA fabric | 29 |
| Data I/O | Datapath I/Os of FPGA fabric | 27 |
+-----------+------------------------------------------------------------------------+-------------+
| Clk | Operating clock of FPGA core | 1 |
| CLK | Operating clock of FPGA core | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 |
| PROG_CLK | Clock used by configuration protocol to program FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| CCin | Input of configuation protocol to load bitstream | 1 |
| RESET | Active-low reset for datapath flip-flops in the FPGA | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| CCout | Output of configuration protocol to read back bitstream | 1 |
| PROG_RESET| Active-low reset for configuration flip-flops in the FPGA | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| TestEn | Activate the test mode of FPGA fabric | 1 |
| CCFF_HEAD | Input of configuation protocol to load bitstream | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
| CCFF_TAIL | Output of configuration protocol to read back bitstream | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
| TEST_EN | Activate the test mode of FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| SC_HEAD | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| SC_TAIL | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 |
+-----------+------------------------------------------------------------------------+-------------+
@ -66,7 +70,7 @@ Full details are summarized in the following table.
.. _qlsofa_hd_io_resource_accelerator:
Accelerator Mode
~~~~~~~~~~~~~~~~
^^^^^^^^^^^^^^^^
When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
:numref:`fig_qlsofa_hd_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
@ -86,7 +90,7 @@ When the Wishbone interface is enabled, the FPGA can operate as an accelerator f
.. _qlsofa_hd_io_resource_debug:
Debug Mode
~~~~~~~~~~
^^^^^^^^^^
When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor.
:numref:`fig_qlsofa_hd_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations.

10
DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst
View File

@ -3,6 +3,12 @@
Architecture
-------------
.. _sofa_hd_fpga_arch_floorplan:
Floorplan
^^^^^^^^^
:numref:`fig_sofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric.
The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`sofa_hd_io_resource`).
@ -19,7 +25,7 @@ I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RIS
.. _sofa_hd_fpga_arch_tiles:
Tiles
-----
^^^^^
The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built:
@ -56,7 +62,7 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
.. _sofa_hd_fpga_arch_scan_chain:
Scan-chain
----------
^^^^^^^^^^
There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`sofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_sofa_hd_fabric_scan_chain`.

24
DOC/source/datasheet/sofa_hd/sofa_hd_io_resource.rst
View File

@ -3,8 +3,8 @@
I/O Resources
-------------
DATA I/Os
^^^^^^^^^
Pin Assignment
^^^^^^^^^^^^^^
The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_sofa_hd_fpga_io_switch`.
@ -31,7 +31,7 @@ Among the 144 I/Os,
.. _io_resource_sofa_hd_external_io:
External I/Os
~~~~~~~~~~~~~
^^^^^^^^^^^^^
A SOFA HD FPGA IP contains 37 external I/O pins, including 29 data I/Os and 8 control I/Os.
@ -44,19 +44,19 @@ Full details are summarized in the following table.
+===========+========================================================================+=============+
| Data I/O | Datapath I/Os of FPGA fabric | 29 |
+-----------+------------------------------------------------------------------------+-------------+
| Clk | Operating clock of FPGA core | 1 |
| CLK | Operating clock of FPGA core | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 |
| PROG_CLK | Clock used by configuration protocol to program FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| CCin | Input of configuation protocol to load bitstream | 1 |
| CCFF_HEAD | Input of configuation protocol to load bitstream | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| CCout | Output of configuration protocol to read back bitstream | 1 |
| CCFF_TAIL | Output of configuration protocol to read back bitstream | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| TestEn | Activate the test mode of FPGA fabric | 1 |
| TEST_EN | Activate the test mode of FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
| SC_HEAD | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
| SC_TAIL | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 |
+-----------+------------------------------------------------------------------------+-------------+
| IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 |
+-----------+------------------------------------------------------------------------+-------------+
@ -66,7 +66,7 @@ Full details are summarized in the following table.
.. _sofa_hd_io_resource_accelerator:
Accelerator Mode
~~~~~~~~~~~~~~~~
^^^^^^^^^^^^^^^^
When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor.
:numref:`fig_sofa_hd_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations.
@ -86,7 +86,7 @@ When the Wishbone interface is enabled, the FPGA can operate as an accelerator f
.. _sofa_hd_io_resource_debug:
Debug Mode
~~~~~~~~~~
^^^^^^^^^^
When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor.
:numref:`fig_sofa_hd_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations.