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+ + + + + Caravel + GPIO[10:4] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + + + + 5 bit + + + + + Caravel Logic Analyzer + la_data_in/out/oen[123:127] + + + + + + + + gpio[19] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + gpio[24] + + + + + gpio[121] + + + + + … + + + + + + + + + Caravel Logic Analyzer + la_data_in/out/oen[15:122] + + + + + + + + + 108 bit + + + + + + + + 4 bit + + + + + Caravel Logic Analyzer + la_data_in/out/oen[11:14] + + + + + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_map_wishbone_mode.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_map_wishbone_mode.svg new file mode 100644 index 0000000..4744bdb --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_map_wishbone_mode.svg @@ -0,0 +1,259 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-29 00:23:07 +0000 + + v1.1 + + base + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + … + + + + + gpio[12] + + + + + gpio[18] + + + + + … + + + + + gpio[136] + + + + + gpio[143] + + + + + … + + + + + … + + + + + … + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 7 bit + + + + + Caravel + GPIO[10:4] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + Caravel Wishbone clk_i + Caravel Wishbone rst_i + Caravel Wishbone ack_o + Caravel Wishbone cyc_i + + + + + + + + + + + + + + + + + 32 bit + + + + + gpio[19] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + gpio[24] + + + + + Caravel Wishbone stb_i + Caravel Wishbone we_i + Caravel Wishbone adr_i[31:0] + Caravel Wishbone dat_i[31:0] + Caravel Wishbone dat_o[31:0] + Caravel Wishbone sel_i[3:0] + + + + + + + + + 70 bit + + + + + … + + + + + gpio[30] + + + + + + + + 3 bit + + + + + + + + + 1 bit + + + + + … + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_switch.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_switch.svg new file mode 100644 index 0000000..3e91b9b --- /dev/null +++ b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_io_switch.svg @@ -0,0 +1,353 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18\n2020-11-29 03:10:55 +0000 + + v1.1 + + base + + + CCFF_TAIL -> Caravel GPIO[35] + CLK <- Caravel GPIO[36] + PROG_CLK <- Caravel GPIO[37] + + + + + + + + + + + FPGA Core + + + + + gpio[0] + + + + + gpio[11] + + + + + … + + + + + gpio[12] + + + + + gpio[18] + + + + + … + + + + + gpio[136] + + + + + gpio[143] + + + + + … + + + + + … + + + + + … + + + + + + + + + + + + + + + + + + + Caravel GPIO[24:13] + + + + + 12 bit + + + + + 7 bit + + + + + Caravel + GPIO[10:4] + + + + + + + + + + + + Caravel + GPIO[34:27] + + + + + 8 bit + + + + + + + + 5 bit + + + + + + + + 4 bit + + + + + + + + gpio[19] + + + + + gpio[23] + + + + + gpio[135] + + + + + gpio[132] + + + + + gpio[131] + + + + + gpio[24] + + + + + gpio[121] + + + + + … + + + + + Caravel Logic Analyzer + la_data_in/out/oen[11:127] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Caravel + GPIO[25] + + + + + + + + + + + + Caravel Wishbone clk_i + Caravel Wishbone rst_i + Caravel Wishbone stb_i + Caravel Wishbone cyc_i + Caravel Wishbone we_i + + + + + + + + + Mode switch truth table: + - When Caravel GPIO[25] is logic ‘1’, FPGA is interfacing the Wishbone bus + - When Caravel GPIO[25] is logic ‘0’, FPGA is interfacing the logic analyzer + + + + + + + + + CCFF_HEAD <- Caravel GPIO[12] + SC_TAIL -> Caravel GPIO[11] + + + + + + SC_HEAD <- Caravel GPIO[26] + + + + + + + + + + + + + + + + + PROG_RESET <- Caravel GPIO[3] + RESET <- Caravel GPIO[2] + IO_ISOL_N <- Caravel GPIO[1] + TEST_EN <- Caravel GPIO[0] + + + + + 106 bit + + + + + 117 bit + + + + + + + + + Caravel Wishbone sel_i[3:0] + Caravel Wishbone dat_i[31:0] + Caravel Wishbone adr_i[31:0] + Caravel Wishbone ack_o + Caravel Wishbone dat_o[31:0] + + + + + diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst index 59f9cca..f1d079d 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst @@ -3,6 +3,12 @@ Architecture ------------- +.. _qlsofa_hd_fpga_arch_floorplan: + +Floorplan +^^^^^^^^^ + + :numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric. I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`). @@ -19,7 +25,7 @@ I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RIS .. _qlsofa_hd_fpga_arch_tiles: Tiles ------ +^^^^^ The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built: @@ -56,7 +62,7 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra .. _qlsofa_hd_fpga_arch_scan_chain: Scan-chain ----------- +^^^^^^^^^^ There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`. diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst index 229295f..fc2badb 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst @@ -3,8 +3,8 @@ I/O Resources ------------- -DATA I/Os -^^^^^^^^^ +Pin Assignment +^^^^^^^^^^^^^^ The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`. @@ -31,9 +31,9 @@ Among the 144 I/Os, .. _io_resource_qlsofa_hd_external_io: External I/Os -~~~~~~~~~~~~~ +^^^^^^^^^^^^^ -A SOFA HD FPGA IP contains 37 external I/O pins, including 29 data I/Os and 8 control I/Os. +A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os. Full details are summarized in the following table. @@ -42,21 +42,25 @@ Full details are summarized in the following table. +-----------+------------------------------------------------------------------------+-------------+ | I/O Type | Description | No. of Pins | +===========+========================================================================+=============+ - | Data I/O | Datapath I/Os of FPGA fabric | 29 | + | Data I/O | Datapath I/Os of FPGA fabric | 27 | +-----------+------------------------------------------------------------------------+-------------+ - | Clk | Operating clock of FPGA core | 1 | + | CLK | Operating clock of FPGA core | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 | + | PROG_CLK | Clock used by configuration protocol to program FPGA fabric | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | CCin | Input of configuation protocol to load bitstream | 1 | + | RESET | Active-low reset for datapath flip-flops in the FPGA | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | CCout | Output of configuration protocol to read back bitstream | 1 | + | PROG_RESET| Active-low reset for configuration flip-flops in the FPGA | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | TestEn | Activate the test mode of FPGA fabric | 1 | + | CCFF_HEAD | Input of configuation protocol to load bitstream | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 | + | CCFF_TAIL | Output of configuration protocol to read back bitstream | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 | + | TEST_EN | Activate the test mode of FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | SC_HEAD | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 | + +-----------+------------------------------------------------------------------------+-------------+ + | SC_TAIL | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 | +-----------+------------------------------------------------------------------------+-------------+ | IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 | +-----------+------------------------------------------------------------------------+-------------+ @@ -66,7 +70,7 @@ Full details are summarized in the following table. .. _qlsofa_hd_io_resource_accelerator: Accelerator Mode -~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^ When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor. :numref:`fig_qlsofa_hd_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. @@ -86,7 +90,7 @@ When the Wishbone interface is enabled, the FPGA can operate as an accelerator f .. _qlsofa_hd_io_resource_debug: Debug Mode -~~~~~~~~~~ +^^^^^^^^^^ When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor. :numref:`fig_qlsofa_hd_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations. diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst index adffbf4..5f503c9 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_fpga_arch.rst @@ -3,6 +3,12 @@ Architecture ------------- + +.. _sofa_hd_fpga_arch_floorplan: + +Floorplan +^^^^^^^^^ + :numref:`fig_sofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric. I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`sofa_hd_io_resource`). @@ -19,7 +25,7 @@ I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RIS .. _sofa_hd_fpga_arch_tiles: Tiles ------ +^^^^^ The FPGA architecture follows a tile-based organization, to exploit the fine-grainularity in physical design, where three types of tiles are built: @@ -56,7 +62,7 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra .. _sofa_hd_fpga_arch_scan_chain: Scan-chain ----------- +^^^^^^^^^^ There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`sofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_sofa_hd_fabric_scan_chain`. diff --git a/DOC/source/datasheet/sofa_hd/sofa_hd_io_resource.rst b/DOC/source/datasheet/sofa_hd/sofa_hd_io_resource.rst index 516f875..48f29a3 100644 --- a/DOC/source/datasheet/sofa_hd/sofa_hd_io_resource.rst +++ b/DOC/source/datasheet/sofa_hd/sofa_hd_io_resource.rst @@ -3,8 +3,8 @@ I/O Resources ------------- -DATA I/Os -^^^^^^^^^ +Pin Assignment +^^^^^^^^^^^^^^ The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_sofa_hd_fpga_io_switch`. @@ -31,7 +31,7 @@ Among the 144 I/Os, .. _io_resource_sofa_hd_external_io: External I/Os -~~~~~~~~~~~~~ +^^^^^^^^^^^^^ A SOFA HD FPGA IP contains 37 external I/O pins, including 29 data I/Os and 8 control I/Os. @@ -44,19 +44,19 @@ Full details are summarized in the following table. +===========+========================================================================+=============+ | Data I/O | Datapath I/Os of FPGA fabric | 29 | +-----------+------------------------------------------------------------------------+-------------+ - | Clk | Operating clock of FPGA core | 1 | + | CLK | Operating clock of FPGA core | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | ProgClk | Clock used by configuration protocol to program FPGA fabric | 1 | + | PROG_CLK | Clock used by configuration protocol to program FPGA fabric | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | CCin | Input of configuation protocol to load bitstream | 1 | + | CCFF_HEAD | Input of configuation protocol to load bitstream | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | CCout | Output of configuration protocol to read back bitstream | 1 | + | CCFF_TAIL | Output of configuration protocol to read back bitstream | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | TestEn | Activate the test mode of FPGA fabric | 1 | + | TEST_EN | Activate the test mode of FPGA fabric | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | SCin | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 | + | SC_HEAD | Input of built-in scan-chain to load data to flip-flops of FPGA fabric | 1 | +-----------+------------------------------------------------------------------------+-------------+ - | SCout | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 | + | SC_TAIL | Output of built-in scan-chain to read back flip-flops from FPGA fabric | 1 | +-----------+------------------------------------------------------------------------+-------------+ | IO_ISLO_N | Active-low signal to enable I/O datapath isolation from external ports | 1 | +-----------+------------------------------------------------------------------------+-------------+ @@ -66,7 +66,7 @@ Full details are summarized in the following table. .. _sofa_hd_io_resource_accelerator: Accelerator Mode -~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^ When the Wishbone interface is enabled, the FPGA can operate as an accelerator for the RISC-V processor. :numref:`fig_sofa_hd_fpga_io_map_wishbone_mode` illustrates the detailed I/O arrangement for the FPGA, where the wishbone bus signals are connected to fixed FPGA I/O locations. @@ -86,7 +86,7 @@ When the Wishbone interface is enabled, the FPGA can operate as an accelerator f .. _sofa_hd_io_resource_debug: Debug Mode -~~~~~~~~~~ +^^^^^^^^^^ When the logic analyzer interface is enabled, the FPGA can operate in debug mode, whose internal signals can be readback through the registers of the RISC-V processor. :numref:`fig_sofa_hd_fpga_io_map_logic_analyzer_mode` illustrates the detailed I/O arrangement for the FPGA, where the logic analyzer signals are connected to fixed FPGA I/O locations.