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398 Commits 16 Branches 1 Tag 1.8 GiB
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398 Commits

Author SHA1 Message Date
tangxifan da08e505b5 [MSIM] Support pre-pnr simulation in script-run verification 2020-12-06 11:13:50 -07:00
tangxifan 443eb12710 [CI] Add test to CI 2020-12-05 21:17:59 -07:00
tangxifan 22f2b3aa90 [HDL] Add python script to adapt OpenFPGA MUX primitives to use custom cells 2020-12-05 21:14:56 -07:00
tangxifan 6039ae92ca [Arch] Bug fix for buffering two-level routing multiplexers using custom cells 2020-12-05 19:37:34 -07:00
tangxifan 3a75e079ba [Doc] Update the frontpage README 2020-12-04 14:09:40 -07:00
tangxifan f766052bf7 [Doc] Add route W to device comparison 2020-12-04 13:41:47 -07:00
tangxifan 156e1d007c [Doc] Add missing figure and bug fix 2020-12-04 13:34:41 -07:00
tangxifan 1948f000e0 [Doc] Reorganize documentation for SOFA HD device family 2020-12-04 12:02:30 -07:00
tangxifan 6fca7b9641 [Doc] Add figures about fle architecture v1.1 2020-12-04 09:27:11 -07:00
tangxifan 51167f871e [Testbench] Patch ccff test 2020-12-02 20:07:36 -07:00
tangxifan ce058447f2 [MSIM] Bug fix in reporting errors 2020-12-02 20:07:16 -07:00
tangxifan 2db2b468fe [Script] Try auto number of simulation clock cycles 2020-12-02 19:33:28 -07:00
tangxifan 3a097b38af [CI] Remove the out-of-data tests 2020-12-02 18:00:48 -07:00
tangxifan 930f7ec486 [Script] Remove task run for redundant architectures 2020-12-02 17:56:58 -07:00
tangxifan 7b637e6676 [Testbench] Bug fix in post PnR testbench templates 2020-12-02 17:50:49 -07:00
tangxifan b966829566 [Script] Force a fixed number of clock cycles in simulation to avoid false-positive 2020-12-02 17:50:23 -07:00
tangxifan a19c9bdbda [CI] Add CCFF and SCFF testbench conversion to CI test 2020-12-02 15:30:54 -07:00
tangxifan 6814b3bb60 [Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants 2020-12-02 15:22:19 -07:00
tangxifan 4875b2de95 [HDL] Patch pin assignment names to be consistent with post-PnR netlists 2020-12-02 14:02:18 -07:00
tangxifan 06731e092e [Arch] Patch reset port name to be consistent with post-PnR netlist 2020-12-02 13:46:40 -07:00
tangxifan 20cba3f558 [Testbench] Add testbench for post-PnR verification for FPGA with reset 2020-12-02 13:43:06 -07:00
tangxifan ea3165b14d Merge branch 'master' into xt_dev 2020-12-02 13:27:50 -07:00
tangxifan b9053269e9
Merge pull request #52 from lnis-uofu/ganesh_dev 
Ganesh dev
 2020-12-02 13:10:35 -07:00
Ganesh Gore 0cc5b492d2 [Cleanup] Removed/Ignored testbench files from generated source 2020-12-02 12:03:24 -07:00
tangxifan 61163de580 [Testbench] Correct path to post-pnR netlists and prepare for sign-off on FPGA with reset 2020-12-02 12:00:28 -07:00
Ganesh Gore 361cd2d9e1 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-02 10:56:59 -07:00
Ganesh Gore 923a502c24 [FPGA1212_v1.1] Added PostPnR files 2020-12-02 01:43:58 -07:00
Ganesh Gore f385c0ca11 [FPGA1212_v1.1] Added OpenFPGA task and verilog netlist 2020-12-02 01:43:05 -07:00
Laboratory for Nano Integrated Systems (LNIS) 07d1962051
Merge pull request #51 from lnis-uofu/xt_dev 
Add new architecture files which use custom cells based on Skywater HD library
 2020-12-01 22:16:49 -07:00
tangxifan b5abfdd994 [Arch] enable local encoders 2020-12-01 20:56:53 -07:00
tangxifan fc92dceb94 [CI] Add new arch to CI test 2020-12-01 20:55:10 -07:00
tangxifan 3b6f3b0691 [Arch] Bug fix in new arch 2020-12-01 20:49:02 -07:00
tangxifan 147dd8d606 [Script] Add task run for custom cell FPGA architectures 2020-12-01 20:22:16 -07:00
tangxifan 454ea09dc4 [Arch] Add architecture using custom cells 2020-12-01 20:19:22 -07:00
Laboratory for Nano Integrated Systems (LNIS) 29a9dea3ca
Merge pull request #50 from lnis-uofu/xt_dev 
Add wrapper generator examples to CI
 2020-12-01 15:45:35 -07:00
tangxifan f2056a9bf9 [Git] Ignore .v as LFS files 2020-12-01 14:50:20 -07:00
tangxifan 4594be46c8 [CI] Patch github repo path to sync with OpenFPGA repo movement 2020-12-01 11:58:19 -07:00
tangxifan 83bd343f70 [CI] Add wrapper generator examples to CI 2020-12-01 11:32:27 -07:00
Ganesh Gore fd7a65c756 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-01 11:29:15 -07:00
Ganesh Gore a134cffb9d Added verilog files only in testbench directory in gitLFS 2020-12-01 11:23:02 -07:00
Laboratory for Nano Integrated Systems (LNIS) 95cbc60cc2
Merge pull request #49 from LNIS-Projects/xt_dev 
Increase routing chan width from 40 to 60 for the architecture using reset and soft adders
 2020-12-01 11:21:31 -07:00
tangxifan 0eb1b68bee [Script] Increase routing chan width from 40 to 60 for version 1.2 2020-12-01 10:17:47 -07:00
Laboratory for Nano Integrated Systems (LNIS) 8713eb3c5b
Merge pull request #48 from LNIS-Projects/xt_dev 
Add Continuous Integration
 2020-12-01 08:56:35 -07:00
tangxifan d867dbb1bf [Testbench] Bug fix in calling sub python script 2020-12-01 08:14:43 -07:00
tangxifan 11d4b156b4 [Testbench] Bug fix in finding scripts 2020-11-30 22:41:29 -07:00
tangxifan 6d5bb2d794 [CI] Bug fix 2020-11-30 22:38:24 -07:00
tangxifan 764e5310aa [Doc] Add badges to frontpage README 2020-11-30 21:29:15 -07:00
tangxifan 2aa8f81421 [CI] Add more tests 2020-11-30 21:25:02 -07:00
tangxifan 3a6b0c18f7 [CI] Bug fix 2020-11-30 20:35:56 -07:00
tangxifan ef2d19aafa [CI] Bug fix 2020-11-30 20:27:41 -07:00