tangxifan
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0e964534bc
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[HDL] bug fix in wrapper line generator
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2020-11-29 12:01:15 -07:00 |
tangxifan
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9622b44554
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[HDL] Bug fix in JSON file syntax
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2020-11-29 11:59:56 -07:00 |
tangxifan
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27da78fe29
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[HDL] Update wrapper line generator to parse json data
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2020-11-29 11:57:34 -07:00 |
tangxifan
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329b6644f3
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[Script] Bug fix in creating directories for verification task
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2020-11-29 11:02:23 -07:00 |
Ganesh Gore
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20dc203b31
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[FPGA1212_v1] Module level results
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2020-11-29 11:02:17 -07:00 |
Ganesh Gore
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225feaef3c
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[FPGA1212_v1] Added top-level pnr screenshots
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2020-11-29 10:59:15 -07:00 |
tangxifan
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4ec490645d
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Merge branch 'master' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev
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2020-11-29 10:35:40 -07:00 |
tangxifan
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bc3d839e5b
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[HDL] Upgrading code generator for wrapper
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2020-11-29 10:35:10 -07:00 |
tangxifan
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a50dfc09b5
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Merge pull request #43 from LNIS-Projects/ganesh_dev
[FPGA1212_V1] Updated design
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2020-11-29 10:34:29 -07:00 |
Ganesh Gore
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7db7c240e3
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[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed
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2020-11-29 10:24:03 -07:00 |
tangxifan
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aac8ddc3ec
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[HDL] update json to ease parsing
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2020-11-28 21:10:46 -07:00 |
tangxifan
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47389a483e
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[HDL] Add json description for pin assignment v1.0
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2020-11-28 20:55:41 -07:00 |
tangxifan
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54eb5b469b
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[Doc] Fix pin direction typo in I/O resource map
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2020-11-28 20:13:05 -07:00 |
tangxifan
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aff43bf473
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[Doc] Add README to HDL common files
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2020-11-28 17:37:36 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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90f4e3fa70
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Merge pull request #42 from LNIS-Projects/xt_dev
Push-button Modelsim Verification for Specific FPGA fabric
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2020-11-28 16:44:21 -07:00 |
tangxifan
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969ef7976f
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[Testbench] Remove those with problems in convergence
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2020-11-28 15:24:54 -07:00 |
tangxifan
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3c685311e9
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[Testbench] Bug fix for the ccff testbench to sync with latest netlist
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2020-11-28 15:22:50 -07:00 |
tangxifan
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4e9b07125e
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[Script] Bug fix
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2020-11-28 15:01:09 -07:00 |
tangxifan
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d70bcbb7ca
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[Doc] Add README for Modelsim workspace
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2020-11-28 14:59:26 -07:00 |
tangxifan
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d3b1562fa2
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[Testbench] Rename top-level module to be compatible to Modelsim task run scripts
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2020-11-28 14:55:17 -07:00 |
tangxifan
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ee92b15f0e
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[Script] Bug fix in modelsim task-run script
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2020-11-28 14:50:39 -07:00 |
tangxifan
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2380783808
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[Testbench] Remove post pnr testbenches that can be auto-generated
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2020-11-28 14:46:27 -07:00 |
tangxifan
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8374fcfd4e
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[Script] Rectify output messages
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2020-11-28 14:41:48 -07:00 |
tangxifan
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396988b1b6
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[Script] Now testbench generator requires a specific dir name
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2020-11-28 14:39:18 -07:00 |
tangxifan
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e88a33831c
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[Testbench] Update scripts to rename top-level module for post-PnR testbenches
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2020-11-28 14:29:56 -07:00 |
tangxifan
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1b7b247097
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[Testbench] Rename to be compatible with Modelsim run scripts
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2020-11-28 14:25:55 -07:00 |
tangxifan
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8c44532e4e
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[Script] Add python script to run all the testbenches in a given repo
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2020-11-28 14:24:27 -07:00 |
tangxifan
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56cbe48ad6
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[Script] Disable debugging log in single Modelsim verification task
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2020-11-28 13:53:14 -07:00 |
tangxifan
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9c7ec9bd61
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[Script] Now python script for post-pnr Modelsim simulation works
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2020-11-28 13:00:21 -07:00 |
tangxifan
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a9b94d4303
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[Testbench] Update top-level module name for post PnR testbenches
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2020-11-28 12:59:59 -07:00 |
tangxifan
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b2ebac3b23
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[Testbench] Rename post-PnR testbenches to ease modelsim batch jobs
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2020-11-28 11:14:34 -07:00 |
tangxifan
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0c9953a26e
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[Testbench] Update post-PnR testbenches to synchornize with latest netlist
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2020-11-28 11:09:55 -07:00 |
tangxifan
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0f0133951c
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[Script] Update modelsim script for post-PnR verification
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2020-11-28 11:07:39 -07:00 |
tangxifan
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f435d80dcc
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Merge pull request #41 from LNIS-Projects/ganesh_dev
Ganesh dev
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2020-11-27 22:55:45 -07:00 |
Ganesh Gore
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66d09da857
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[FPGA1212_v1] Updated the PostPnR Netlist and PnR Files
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2020-11-27 22:11:51 -07:00 |
Ganesh Gore
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ce4a6f72f5
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[FPGA1212_v1] Updated the task and PrePNR Verilog netlist
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2020-11-27 22:08:16 -07:00 |
Ganesh Gore
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da097413b0
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[Cleanup] Removed buggy hierarchical flow files
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2020-11-27 22:00:43 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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4c8e94722c
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Merge pull request #40 from LNIS-Projects/xt_dev
New Architecture: Support both Reset pins in FFs and Soft Adders
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2020-11-27 20:00:05 -07:00 |
tangxifan
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c7ea3f3936
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[Arch] Bug fix in the arch with reset and soft adder
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2020-11-27 19:54:31 -07:00 |
tangxifan
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6a12cdbad1
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[Script] Add task run for the architecture with both reset and soft adders
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2020-11-27 18:15:05 -07:00 |
tangxifan
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14c21378b8
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[Arch] Add new architecture using reset and softadder
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2020-11-27 18:12:06 -07:00 |
Ganesh Gore
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5be185e7a5
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Merge remote-tracking branch 'origin/master' into ganesh_dev
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2020-11-27 17:51:51 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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9102b7ec5e
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Merge pull request #39 from LNIS-Projects/xt_dev
New Architecture: Support Carry Adders which are Implemented by LUTs
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2020-11-27 16:41:57 -07:00 |
tangxifan
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efab96d2dd
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[Arch] Bug fix in softadder architecture
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2020-11-27 16:36:31 -07:00 |
tangxifan
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e5a66dd47f
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[Script] Add task run for softadder architecture
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2020-11-27 16:14:14 -07:00 |
tangxifan
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31dcd4a17f
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[HDL] Add a wrapper for HD MUX2 cell required by carry logic
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2020-11-27 16:01:27 -07:00 |
tangxifan
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295df663bb
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[Arch] Add arch variant with soft adders
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2020-11-27 15:57:05 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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5bbb3959ca
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Merge pull request #38 from LNIS-Projects/xt_dev
Misc Updates: New Architecture and Verification Scripts
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2020-11-27 15:22:48 -07:00 |
tangxifan
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28c8dba87b
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[Script] Bug fix in task configuration files
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2020-11-27 15:05:35 -07:00 |
tangxifan
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f27424c803
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[Arch] Bug fix in the architecture using reset
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2020-11-27 15:04:19 -07:00 |