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[Arch] Bug fix in the arch with reset and soft adder

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tangxifan 2020-11-27 19:54:31 -07:00
parent 6a12cdbad1
commit c7ea3f3936
1 changed files with 1 additions and 0 deletions
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ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -432,6 +432,7 @@
<clock name="clk" num_pins="1"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/>
<T_setup value="66e-12" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>