mirror of https://github.com/lnis-uofu/SOFA.git
[FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed
This commit is contained in:
Ganesh Gore
parent
66d09da857
commit
7db7c240e3
|
|
@ -48,6 +48,7 @@ Untracked files:
|
|||
openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA1212_FLAT_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task
|
||||
openfpga_flow/tasks/FPGA1212_RESET_HD_SKY_task
|
||||
openfpga_flow/tasks/FPGA128128_FLAT_task
|
||||
openfpga_flow/tasks/FPGA1616_FLAT_task
|
||||
openfpga_flow/tasks/FPGA22_FLAT_SKY_task
|
||||
|
|
|
|||
|
|
@ -0,0 +1,144 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Connection Block cby_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configurable memory outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable configuration outputs of all the programmable cells for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram_inv
|
||||
set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
|
||||
set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
|
||||
set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
|
||||
set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable routing multiplexer outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out
|
||||
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Disable Switch Block outputs for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out
|
||||
|
||||
set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Clock contraints for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
##################################################
|
||||
# Create programmable clock
|
||||
##################################################
|
||||
create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}]
|
||||
##################################################
|
||||
# Create clock
|
||||
##################################################
|
||||
create_clock -name clk[0] -period 1.110371906e-09 -waveform {0 5.551859528e-10} [get_ports {clk[0]}]
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10
|
||||
set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11
|
||||
set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11
|
||||
set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_0__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_12__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__0_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__12_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11
|
||||
|
|
@ -0,0 +1,322 @@
|
|||
#############################################
|
||||
# Synopsys Design Constraints (SDC)
|
||||
# For FPGA fabric
|
||||
# Description: Constrain timing of Switch Block sb_1__1_ for PnR
|
||||
# Author: Xifan TANG
|
||||
# Organization: University of Utah
|
||||
# Date: Sun Nov 29 02:09:07 2020
|
||||
#############################################
|
||||
|
||||
#############################################
|
||||
# Define time unit
|
||||
#############################################
|
||||
set_units -time s
|
||||
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
- Fabric bitstream
|
||||
- Author: Xifan TANG
|
||||
- Organization: University of Utah
|
||||
- Date: Fri Nov 27 20:48:28 2020
|
||||
- Date: Sun Nov 29 02:09:06 2020
|
||||
-->
|
||||
|
||||
<fabric_bitstream>
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
- Architecture independent bitstream
|
||||
- Author: Xifan TANG
|
||||
- Organization: University of Utah
|
||||
- Date: Fri Nov 27 20:48:28 2020
|
||||
- Date: Sun Nov 29 02:09:06 2020
|
||||
-->
|
||||
|
||||
<bitstream_block name="fpga_top" hierarchy_level="0">
|
||||
|
|
|
|||
|
|
@ -329,10 +329,10 @@ Warning 60: in check_rr_node: RR node: 1389 type: OPIN location: (11,1) pin: 50
|
|||
Warning 61: in check_rr_node: RR node: 1390 type: OPIN location: (11,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||||
Warning 62: in check_rr_node: RR node: 1479 type: OPIN location: (12,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
|
||||
Warning 63: in check_rr_node: RR node: 1480 type: OPIN location: (12,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
|
||||
## Build tileable routing resource graph took 0.17 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB)
|
||||
## Build tileable routing resource graph took 0.16 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB)
|
||||
RR Graph Nodes: 18580
|
||||
RR Graph Edges: 96524
|
||||
# Create Device took 0.17 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB)
|
||||
# Create Device took 0.16 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB)
|
||||
|
||||
# Placement
|
||||
## Computing placement delta delay look-up
|
||||
|
|
@ -654,7 +654,7 @@ Setup slack histogram:
|
|||
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||||
[ -9.3e-10: -9.3e-10) 0 ( 0.0%) |
|
||||
|
||||
Timing analysis took 0.000513075 seconds (0.000459398 STA, 5.3677e-05 slack) (67 full updates: 48 setup, 0 hold, 19 combined).
|
||||
Timing analysis took 0.000524223 seconds (0.00046474 STA, 5.9483e-05 slack) (67 full updates: 48 setup, 0 hold, 19 combined).
|
||||
VPR suceeded
|
||||
The entire flow of VPR took 0.50 seconds (max_rss 19.5 MiB)
|
||||
|
||||
|
|
@ -886,7 +886,7 @@ Done with 19 nodes mapping
|
|||
[99%] Backannotated GSB[12][11]
|
||||
[100%] Backannotated GSB[12][12]
|
||||
Backannotated 169 General Switch Blocks (GSBs).
|
||||
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.01 seconds (max_rss 19.8 MiB, delta_rss +0.0 MiB)
|
||||
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 19.8 MiB, delta_rss +0.0 MiB)
|
||||
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
|
||||
[0%] Sorted edges for GSB[0][0]
|
||||
[1%] Sorted edges for GSB[0][1]
|
||||
|
|
@ -1127,7 +1127,7 @@ Building physical tiles...Done
|
|||
## Add connection block instances to top module
|
||||
## Add connection block instances to top module took 0.00 seconds (max_rss 27.1 MiB, delta_rss +0.5 MiB)
|
||||
## Add module nets between grids and GSBs
|
||||
## Add module nets between grids and GSBs took 0.14 seconds (max_rss 42.8 MiB, delta_rss +15.7 MiB)
|
||||
## Add module nets between grids and GSBs took 0.13 seconds (max_rss 42.8 MiB, delta_rss +15.7 MiB)
|
||||
## Add module nets for inter-tile connections
|
||||
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 43.3 MiB, delta_rss +0.5 MiB)
|
||||
## Add module nets for configuration buses
|
||||
|
|
@ -1168,10 +1168,10 @@ Generating bitstream for X-direction Connection blocks ...Done
|
|||
Generating bitstream for Y-direction Connection blocks ...Done
|
||||
|
||||
Build fabric-independent bitstream for implementation 'top'
|
||||
took 0.16 seconds (max_rss 49.7 MiB, delta_rss +5.1 MiB)
|
||||
took 0.13 seconds (max_rss 49.7 MiB, delta_rss +5.1 MiB)
|
||||
Warning 116: Directory path is empty and nothing will be created.
|
||||
Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
|
||||
Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.52 seconds (max_rss 49.7 MiB, delta_rss +0.0 MiB)
|
||||
Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.45 seconds (max_rss 49.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: build_fabric_bitstream
|
||||
|
||||
|
|
@ -1182,7 +1182,7 @@ Build fabric dependent bitstream
|
|||
|
||||
|
||||
Build fabric dependent bitstream
|
||||
took 0.03 seconds (max_rss 53.6 MiB, delta_rss +3.9 MiB)
|
||||
took 0.07 seconds (max_rss 53.6 MiB, delta_rss +3.9 MiB)
|
||||
|
||||
Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
|
||||
|
||||
|
|
@ -1202,7 +1202,7 @@ Confirm selected options when call command 'write_fabric_bitstream':
|
|||
--verbose: off
|
||||
Warning 118: Directory path is empty and nothing will be created.
|
||||
Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml'
|
||||
Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.09 seconds (max_rss 53.6 MiB, delta_rss +0.0 MiB)
|
||||
Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.12 seconds (max_rss 53.6 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
|
||||
|
||||
|
|
@ -1264,7 +1264,7 @@ Building physical tiles...Done
|
|||
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
|
||||
Written 71 Verilog modules in total
|
||||
Write Verilog netlists for FPGA fabric
|
||||
took 0.34 seconds (max_rss 56.4 MiB, delta_rss +2.8 MiB)
|
||||
took 0.44 seconds (max_rss 56.4 MiB, delta_rss +2.8 MiB)
|
||||
|
||||
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
|
||||
|
||||
|
|
@ -1284,17 +1284,72 @@ Write Verilog testbenches for FPGA fabric
|
|||
|
||||
Warning 120: Directory './SRC' already exists. Will overwrite contents
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top'
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.11 seconds (max_rss 56.4 MiB, delta_rss +0.0 MiB)
|
||||
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.14 seconds (max_rss 56.5 MiB, delta_rss +0.2 MiB)
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 56.4 MiB, delta_rss +0.0 MiB)
|
||||
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 56.5 MiB, delta_rss +0.0 MiB)
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
|
||||
Will use 67961 configuration clock cycles to top testbench
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.12 seconds (max_rss 56.6 MiB, delta_rss +0.2 MiB)
|
||||
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.13 seconds (max_rss 56.6 MiB, delta_rss +0.1 MiB)
|
||||
Succeed to create directory './SimulationDeck'
|
||||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
|
||||
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 56.6 MiB, delta_rss +0.0 MiB)
|
||||
Write Verilog testbenches for FPGA fabric
|
||||
took 0.24 seconds (max_rss 56.7 MiB, delta_rss +0.3 MiB)
|
||||
took 0.29 seconds (max_rss 56.6 MiB, delta_rss +0.2 MiB)
|
||||
|
||||
Command line to execute: write_pnr_sdc --file ./SDC
|
||||
|
||||
Confirm selected options when call command 'write_pnr_sdc':
|
||||
--file, -f: ./SDC
|
||||
--flatten_names: off
|
||||
--hierarchical: off
|
||||
--output_hierarchy: off
|
||||
--time_unit: off
|
||||
--constrain_global_port: off
|
||||
--constrain_non_clock_global_port: off
|
||||
--constrain_grid: off
|
||||
--constrain_sb: off
|
||||
--constrain_cb: off
|
||||
--constrain_configurable_memory_outputs: off
|
||||
--constrain_routing_multiplexer_outputs: off
|
||||
--constrain_switch_block_outputs: off
|
||||
--constrain_zero_delay_paths: off
|
||||
--verbose: off
|
||||
Succeed to create directory './SDC'
|
||||
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc'
|
||||
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc'
|
||||
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc'
|
||||
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.05 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc'
|
||||
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constrain Switch Block timing for P&R flow
|
||||
Write SDC for constrain Switch Block timing for P&R flow took 0.05 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constrain Connection Block timing for P&R flow
|
||||
Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||||
Write SDC for constraining grid timing for P&R flow
|
||||
Write SDC for constraining grid timing for P&R flow took 0.02 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||||
|
||||
Confirm selected options when call command 'write_sdc_disable_timing_configure_ports':
|
||||
--file, -f: ./SDC/disable_configure_ports.sdc
|
||||
--flatten_names: off
|
||||
--verbose: off
|
||||
Warning 121: Directory './SDC' already exists. Will overwrite contents
|
||||
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc'
|
||||
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.12 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: write_analysis_sdc --file ./SDC_analysis
|
||||
|
||||
Confirm selected options when call command 'write_analysis_sdc':
|
||||
--file, -f: ./SDC_analysis
|
||||
--verbose: off
|
||||
--flatten_names: off
|
||||
--time_unit: off
|
||||
Succeed to create directory './SDC_analysis'
|
||||
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc'
|
||||
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 0.76 seconds (max_rss 56.8 MiB, delta_rss +0.0 MiB)
|
||||
|
||||
Command line to execute: exit
|
||||
|
||||
|
|
@ -1302,6 +1357,6 @@ Confirm selected options when call command 'exit':
|
|||
|
||||
Finish execution with 0 errors
|
||||
|
||||
The entire OpenFPGA flow took 2.06 seconds
|
||||
The entire OpenFPGA flow took 3.11 seconds
|
||||
|
||||
Thank you for using OpenFPGA!
|
||||
|
|
|
|||
|
|
@ -39,6 +39,17 @@ write_fabric_bitstream --format xml --file fabric_bitstream.xml
|
|||
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
|
||||
|
||||
write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
|
||||
|
||||
# Write the SDC files for PnR backend
|
||||
# - Turn on every options here
|
||||
write_pnr_sdc --file ./SDC
|
||||
|
||||
# Write SDC to disable timing for configure ports
|
||||
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||||
|
||||
# Write the SDC to run timing analysis for a mapped FPGA fabric
|
||||
write_analysis_sdc --file ./SDC_analysis
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
BIN
FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef (Stored with Git LFS)
BIN
FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef (Stored with Git LFS)
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue