From 7db7c240e3b6e913c0b49110198978914f3fab94 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sun, 29 Nov 2020 10:24:03 -0700 Subject: [PATCH] [FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed --- .../OpenFPGAEngine.info | 1 + .../SDC/cbx_1__0_.sdc | 144 + .../SDC/cbx_1__12_.sdc | 208 + .../SDC/cbx_1__1_.sdc | 198 + .../SDC/cby_0__1_.sdc | 64 + .../SDC/cby_12__1_.sdc | 208 + .../SDC/cby_1__1_.sdc | 198 + .../disable_configurable_memory_outputs.sdc | 127 + .../SDC/disable_configure_ports.sdc | 243 + .../disable_routing_multiplexer_outputs.sdc | 122 + .../SDC/disable_sb_outputs.sdc | 75 + .../SDC/global_ports.sdc | 17 + .../SDC/logical_tile_clb_mode_clb_.sdc | 16 + .../logical_tile_clb_mode_default__fle.sdc | 14 + ...ode_default__fle_mode_physical__fabric.sdc | 22 + ...mode_physical__fabric_mode_default__ff.sdc | 14 + ...sical__fabric_mode_default__frac_logic.sdc | 14 + .../SDC/logical_tile_io_mode_io_.sdc | 16 + .../SDC/sb_0__0_.sdc | 94 + .../SDC/sb_0__12_.sdc | 94 + .../SDC/sb_0__1_.sdc | 158 + .../SDC/sb_12__0_.sdc | 120 + .../SDC/sb_12__12_.sdc | 120 + .../SDC/sb_12__1_.sdc | 206 + .../SDC/sb_1__0_.sdc | 200 + .../SDC/sb_1__12_.sdc | 200 + .../SDC/sb_1__1_.sdc | 322 + .../TESTBENCH/top/fabric_bitstream.xml | 2 +- .../top/fabric_indepenent_bitstream.xml | 2 +- .../openfpgashell.log | 85 +- .../generate_fabric.openfpga | 11 + .../fpga_top/fpga_top_icv_in_design.fm.v | 31382 +++++++++------ .../fpga_top/fpga_top_icv_in_design.gds.gz | Bin 3980417 -> 4325458 bytes .../fpga_top/fpga_top_icv_in_design.lvs.v | 31455 ++++++++++------ .../fpga_top_icv_in_design.nominal_25.spef | 4 +- .../fpga_top/fpga_top_icv_in_design.pt.v | 31382 +++++++++------ .../fpga_top_icv_in_design.top_only.pt.v | 8842 ++++- 37 files changed, 74080 insertions(+), 32300 deletions(-) create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__0_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__12_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__1_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_0__1_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_12__1_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_1__1_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configure_ports.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/global_ports.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__0_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__12_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__1_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__0_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__12_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__1_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__0_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__12_.sdc create mode 100644 FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__1_.sdc diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/OpenFPGAEngine.info b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/OpenFPGAEngine.info index 07b3b6c..e241c01 100644 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/OpenFPGAEngine.info +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/OpenFPGAEngine.info @@ -48,6 +48,7 @@ Untracked files: openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task openfpga_flow/tasks/FPGA1212_FLAT_HD_SKY_task openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task + openfpga_flow/tasks/FPGA1212_RESET_HD_SKY_task openfpga_flow/tasks/FPGA128128_FLAT_task openfpga_flow/tasks/FPGA1616_FLAT_task openfpga_flow/tasks/FPGA22_FLAT_SKY_task diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__0_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__0_.sdc new file mode 100644 index 0000000..fc31f23 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__0_.sdc @@ -0,0 +1,144 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cbx_1__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/chanx_left_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/chanx_right_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/chanx_left_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/chanx_right_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/chanx_left_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/chanx_right_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/chanx_left_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/chanx_right_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/chanx_left_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/chanx_right_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/chanx_left_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/chanx_right_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/chanx_left_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/chanx_right_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/chanx_left_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/chanx_right_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/chanx_left_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/chanx_right_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/chanx_left_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/chanx_right_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[13] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[19] -to fpga_top/cbx_1__0_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[14] -to fpga_top/cbx_1__0_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[15] -to fpga_top/cbx_1__0_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[10] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[16] -to fpga_top/cbx_1__0_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[11] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[17] -to fpga_top/cbx_1__0_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[12] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_left_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__0_/chanx_right_in[18] -to fpga_top/cbx_1__0_/bottom_grid_pin_16_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__12_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__12_.sdc new file mode 100644 index 0000000..c6fbd27 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__12_.sdc @@ -0,0 +1,208 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cbx_1__12_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/chanx_left_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/chanx_right_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/chanx_left_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/chanx_right_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/chanx_left_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/chanx_right_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/chanx_left_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/chanx_right_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/chanx_left_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/chanx_right_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/chanx_left_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/chanx_right_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/chanx_left_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/chanx_right_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/chanx_left_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/chanx_right_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/chanx_left_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/chanx_right_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/chanx_left_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/chanx_right_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/chanx_left_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/chanx_right_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/chanx_left_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/chanx_right_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/chanx_left_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/chanx_right_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/chanx_left_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/chanx_right_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/chanx_left_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/chanx_right_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/chanx_left_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/chanx_right_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/chanx_left_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/chanx_right_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/chanx_left_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/chanx_right_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/chanx_left_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/chanx_right_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/chanx_left_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/chanx_right_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/top_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[5] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[8] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[9] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[14] -to fpga_top/cbx_1__12_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[15] -to fpga_top/cbx_1__12_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[6] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[12] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[7] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[13] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[17] -to fpga_top/cbx_1__12_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[18] -to fpga_top/cbx_1__12_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[1] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[3] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[11] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[19] -to fpga_top/cbx_1__12_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[0] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[2] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[4] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[10] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_left_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__12_/chanx_right_in[16] -to fpga_top/cbx_1__12_/bottom_grid_pin_15_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__1_.sdc new file mode 100644 index 0000000..493377e --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cbx_1__1_.sdc @@ -0,0 +1,198 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cbx_1__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/chanx_left_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/chanx_right_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/chanx_left_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/chanx_right_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/chanx_left_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/chanx_right_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/chanx_left_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/chanx_right_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/chanx_left_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/chanx_right_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/chanx_left_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/chanx_right_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/chanx_left_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/chanx_right_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/chanx_left_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/chanx_right_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/chanx_left_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/chanx_right_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/chanx_left_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/chanx_right_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_1_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_2_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_3_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_4_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_5_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_6_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_7_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_8_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[13] -to fpga_top/cbx_1__1_/bottom_grid_pin_9_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[14] -to fpga_top/cbx_1__1_/bottom_grid_pin_10_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[11] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_11_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[12] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[16] -to fpga_top/cbx_1__1_/bottom_grid_pin_12_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[17] -to fpga_top/cbx_1__1_/bottom_grid_pin_13_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[10] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[18] -to fpga_top/cbx_1__1_/bottom_grid_pin_14_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[15] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_left_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cbx_1__1_/chanx_right_in[19] -to fpga_top/cbx_1__1_/bottom_grid_pin_15_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_0__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_0__1_.sdc new file mode 100644 index 0000000..6eb012e --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_0__1_.sdc @@ -0,0 +1,64 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cby_0__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/chany_bottom_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/chany_top_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[11] -to fpga_top/cby_0__1_/chany_bottom_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[11] -to fpga_top/cby_0__1_/chany_top_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[12] -to fpga_top/cby_0__1_/chany_bottom_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[12] -to fpga_top/cby_0__1_/chany_top_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[13] -to fpga_top/cby_0__1_/chany_bottom_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[13] -to fpga_top/cby_0__1_/chany_top_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[14] -to fpga_top/cby_0__1_/chany_bottom_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[14] -to fpga_top/cby_0__1_/chany_top_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[15] -to fpga_top/cby_0__1_/chany_bottom_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[15] -to fpga_top/cby_0__1_/chany_top_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/chany_bottom_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/chany_top_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[17] -to fpga_top/cby_0__1_/chany_bottom_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[17] -to fpga_top/cby_0__1_/chany_top_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[18] -to fpga_top/cby_0__1_/chany_bottom_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[18] -to fpga_top/cby_0__1_/chany_top_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[19] -to fpga_top/cby_0__1_/chany_bottom_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[19] -to fpga_top/cby_0__1_/chany_top_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[10] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_bottom_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_0__1_/chany_top_in[16] -to fpga_top/cby_0__1_/left_grid_pin_0_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_12__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_12__1_.sdc new file mode 100644 index 0000000..9263af3 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_12__1_.sdc @@ -0,0 +1,208 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cby_12__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/chany_bottom_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/chany_top_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/chany_bottom_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/chany_top_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/chany_bottom_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/chany_top_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/chany_bottom_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/chany_top_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/chany_bottom_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/chany_top_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/chany_bottom_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/chany_top_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/chany_bottom_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/chany_top_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/chany_bottom_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/chany_top_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/chany_bottom_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/chany_top_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/chany_bottom_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/chany_top_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/chany_bottom_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/chany_top_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/chany_bottom_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/chany_top_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/chany_bottom_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/chany_top_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/chany_bottom_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/chany_top_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/chany_bottom_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/chany_top_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/chany_bottom_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/chany_top_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/chany_bottom_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/chany_top_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/chany_bottom_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/chany_top_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/chany_bottom_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/chany_top_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/chany_bottom_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/chany_top_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/right_grid_pin_0_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[5] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[8] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[9] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[14] -to fpga_top/cby_12__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[15] -to fpga_top/cby_12__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[6] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[12] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[7] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[13] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[17] -to fpga_top/cby_12__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[18] -to fpga_top/cby_12__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[1] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[3] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[11] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[19] -to fpga_top/cby_12__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[0] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[2] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[4] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[10] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_bottom_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_12__1_/chany_top_in[16] -to fpga_top/cby_12__1_/left_grid_pin_31_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_1__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_1__1_.sdc new file mode 100644 index 0000000..facf484 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/cby_1__1_.sdc @@ -0,0 +1,198 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Connection Block cby_1__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/chany_bottom_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/chany_top_out[0] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/chany_bottom_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/chany_top_out[1] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/chany_bottom_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/chany_top_out[2] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/chany_bottom_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/chany_top_out[3] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/chany_bottom_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/chany_top_out[4] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/chany_bottom_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/chany_top_out[5] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/chany_bottom_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/chany_top_out[6] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/chany_bottom_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/chany_top_out[7] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/chany_bottom_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/chany_top_out[8] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/chany_bottom_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/chany_top_out[9] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/chany_bottom_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/chany_top_out[10] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/chany_bottom_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/chany_top_out[11] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/chany_bottom_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/chany_top_out[12] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/chany_bottom_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/chany_top_out[13] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/chany_bottom_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/chany_top_out[14] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/chany_bottom_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/chany_top_out[15] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/chany_bottom_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/chany_top_out[16] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/chany_bottom_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/chany_top_out[17] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/chany_bottom_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/chany_top_out[18] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/chany_bottom_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/chany_top_out[19] 2.272500113e-12 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_16_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_17_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_18_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_19_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[4] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_20_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_21_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_22_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[7] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_23_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[8] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_24_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[13] -to fpga_top/cby_1__1_/left_grid_pin_25_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[14] -to fpga_top/cby_1__1_/left_grid_pin_26_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[5] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[11] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_27_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[6] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[12] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[16] -to fpga_top/cby_1__1_/left_grid_pin_28_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[17] -to fpga_top/cby_1__1_/left_grid_pin_29_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[0] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[2] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[10] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[18] -to fpga_top/cby_1__1_/left_grid_pin_30_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[1] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[3] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[9] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[15] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_bottom_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 +set_max_delay -from fpga_core_uut/cby_1__1_/chany_top_in[19] -to fpga_top/cby_1__1_/left_grid_pin_31_[0] 7.247000222e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc new file mode 100644 index 0000000..8da07fe --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configurable_memory_outputs.sdc @@ -0,0 +1,127 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable configurable memory outputs for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cbx_*__*_/mem_bottom_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mem_frac_logic_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_fabric_out_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mem_ff_*_D_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cby_*__*_/mem_left_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cby_*__*_/mem_right_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_bottom_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/cbx_*__*_/mem_top_ipin_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_sky*_fd_sc_hd__dfxtp_*_mem/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_left_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_top_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q +set_disable_timing fpga_core_uut/sb_*__*_/mem_right_track_*/sky*_fd_sc_hd__dfxtp_*_*_/Q diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configure_ports.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configure_ports.sdc new file mode 100644 index 0000000..2231d34 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_configure_ports.sdc @@ -0,0 +1,243 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable configuration outputs of all the programmable cells for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram_inv +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/mode_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram +set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/sram +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram +set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/sram +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/sram_inv +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/sram_inv +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/sram_inv +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/sram_inv +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/sram_inv +set_disable_timing fpga_core_uut/grid_io_top_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR +set_disable_timing fpga_core_uut/grid_io_right_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR +set_disable_timing fpga_core_uut/grid_io_bottom_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR +set_disable_timing fpga_core_uut/grid_io_left_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/EMBEDDED_IO_HD_*_/FPGA_DIR diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc new file mode 100644 index 0000000..f785ffc --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_routing_multiplexer_outputs.sdc @@ -0,0 +1,122 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable routing multiplexer outputs for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out +set_disable_timing fpga_core_uut/cbx_*__*_/mux_bottom_ipin_*/out +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out +set_disable_timing fpga_core_uut/cby_*__*_/mux_left_ipin_*/out +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out +set_disable_timing fpga_core_uut/cbx_*__*_/mux_top_ipin_*/out +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out +set_disable_timing fpga_core_uut/cby_*__*_/mux_right_ipin_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_right_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_top_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_bottom_track_*/out +set_disable_timing fpga_core_uut/sb_*__*_/mux_left_track_*/out +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/mux_frac_logic_out_*/out +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_fabric_out_*/out +set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/mux_ff_*_D_*/out diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc new file mode 100644 index 0000000..13c97d4 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/disable_sb_outputs.sdc @@ -0,0 +1,75 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Disable Switch Block outputs for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out + +set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail + +set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out + +set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out + +set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail + +set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out + +set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail + +set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out + +set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out + +set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_right_out + +set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out + +set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail + +set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out + +set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail + +set_disable_timing fpga_core_uut/sb_*__*_/chany_top_out + +set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out + +set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail + +set_disable_timing fpga_core_uut/sb_*__*_/chany_bottom_out + +set_disable_timing fpga_core_uut/sb_*__*_/chanx_left_out + +set_disable_timing fpga_core_uut/sb_*__*_/ccff_tail + diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/global_ports.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/global_ports.sdc new file mode 100644 index 0000000..990109f --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/global_ports.sdc @@ -0,0 +1,17 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Clock contraints for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +################################################## +# Create programmable clock +################################################## +create_clock -name prog_clk[0] -period 9.999999939e-09 -waveform {0 4.99999997e-09} [get_ports {prog_clk[0]}] +################################################## +# Create clock +################################################## +create_clock -name clk[0] -period 1.110371906e-09 -waveform {0 5.551859528e-10} [get_ports {clk[0]}] diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc new file mode 100644 index 0000000..92d66d1 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_clb_.sdc @@ -0,0 +1,16 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_clb_ in PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_reg_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_reg_in[0] 1.599999994e-10 +set_max_delay -from fpga_core_uut/grid_clb/logical_tile_clb_mode_clb__0_/clb_sc_in[0] -to fpga_top/grid_clb/logical_tile_clb_mode_default__fle_0/fle_sc_in[0] 1.599999994e-10 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc new file mode 100644 index 0000000..77bc245 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle.sdc @@ -0,0 +1,14 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle in PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc new file mode 100644 index 0000000..207d32a --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric.sdc @@ -0,0 +1,22 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric in PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 4.500000025e-11 +set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[0] 2.500000033e-11 +set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 4.500000025e-11 +set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_out[1] 2.500000033e-11 +set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 2.500000033e-11 +set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_0_/fabric_reg_in[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_D[0] 4.500000025e-11 +set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/frac_logic_out[1] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 2.500000033e-11 +set_max_delay -from fpga_core_uut/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/ff_Q[0] -to fpga_top/grid_clb/fle/fabric/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/ff_D[0] 4.500000025e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc new file mode 100644 index 0000000..d681f4c --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.sdc @@ -0,0 +1,14 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff in PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc new file mode 100644 index 0000000..993d28b --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.sdc @@ -0,0 +1,14 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic in PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc new file mode 100644 index 0000000..cdd5327 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/logical_tile_io_mode_io_.sdc @@ -0,0 +1,16 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Timing constraints for Grid logical_tile_io_mode_io_ in PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_io__0_/io_inpad[0] 4.243000049e-11 +set_max_delay -from fpga_core_uut/grid_io_left_left/logical_tile_io_mode_io__0_/io_outpad[0] -to fpga_top/grid_io_left_left/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] 1.39400002e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__0_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__0_.sdc new file mode 100644 index 0000000..3b4882a --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__0_.sdc @@ -0,0 +1,94 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_0__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[1] -to fpga_top/sb_0__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[2] -to fpga_top/sb_0__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[3] -to fpga_top/sb_0__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[4] -to fpga_top/sb_0__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[5] -to fpga_top/sb_0__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[6] -to fpga_top/sb_0__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[7] -to fpga_top/sb_0__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[8] -to fpga_top/sb_0__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[9] -to fpga_top/sb_0__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[10] -to fpga_top/sb_0__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[11] -to fpga_top/sb_0__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[12] -to fpga_top/sb_0__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[13] -to fpga_top/sb_0__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[14] -to fpga_top/sb_0__0_/chany_top_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[15] -to fpga_top/sb_0__0_/chany_top_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[16] -to fpga_top/sb_0__0_/chany_top_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[17] -to fpga_top/sb_0__0_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[18] -to fpga_top/sb_0__0_/chany_top_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[19] -to fpga_top/sb_0__0_/chany_top_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chanx_right_in[0] -to fpga_top/sb_0__0_/chany_top_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[19] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[1] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[2] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[3] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[4] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[5] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[6] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[7] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[8] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[9] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[10] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[11] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_0__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[12] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_0__0_/chanx_right_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[13] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_0__0_/chanx_right_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[14] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_0__0_/chanx_right_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[15] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_0__0_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[16] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_0__0_/chanx_right_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[17] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_0__0_/chanx_right_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/chany_top_in[18] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_0__0_/chanx_right_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__12_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__12_.sdc new file mode 100644 index 0000000..acc213d --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__12_.sdc @@ -0,0 +1,94 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_0__12_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[18] -to fpga_top/sb_0__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[17] -to fpga_top/sb_0__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[16] -to fpga_top/sb_0__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[15] -to fpga_top/sb_0__12_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[14] -to fpga_top/sb_0__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[13] -to fpga_top/sb_0__12_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[12] -to fpga_top/sb_0__12_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[11] -to fpga_top/sb_0__12_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[10] -to fpga_top/sb_0__12_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[9] -to fpga_top/sb_0__12_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[8] -to fpga_top/sb_0__12_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[7] -to fpga_top/sb_0__12_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[6] -to fpga_top/sb_0__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[5] -to fpga_top/sb_0__12_/chanx_right_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[4] -to fpga_top/sb_0__12_/chanx_right_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[3] -to fpga_top/sb_0__12_/chanx_right_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[2] -to fpga_top/sb_0__12_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[1] -to fpga_top/sb_0__12_/chanx_right_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[0] -to fpga_top/sb_0__12_/chanx_right_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chany_bottom_in[19] -to fpga_top/sb_0__12_/chanx_right_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[18] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[17] -to fpga_top/sb_0__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[16] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[15] -to fpga_top/sb_0__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[14] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[13] -to fpga_top/sb_0__12_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[12] -to fpga_top/sb_0__12_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[11] -to fpga_top/sb_0__12_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[10] -to fpga_top/sb_0__12_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[9] -to fpga_top/sb_0__12_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[8] -to fpga_top/sb_0__12_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[7] -to fpga_top/sb_0__12_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[6] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__12_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[5] -to fpga_top/sb_0__12_/chany_bottom_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[4] -to fpga_top/sb_0__12_/chany_bottom_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[3] -to fpga_top/sb_0__12_/chany_bottom_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[2] -to fpga_top/sb_0__12_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[1] -to fpga_top/sb_0__12_/chany_bottom_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[0] -to fpga_top/sb_0__12_/chany_bottom_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__12_/chanx_right_in[19] -to fpga_top/sb_0__12_/chany_bottom_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__1_.sdc new file mode 100644 index 0000000..5bcfcf7 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_0__1_.sdc @@ -0,0 +1,158 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_0__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/top_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[2] -to fpga_top/sb_0__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[4] -to fpga_top/sb_0__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[1] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[5] -to fpga_top/sb_0__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[3] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[6] -to fpga_top/sb_0__1_/chanx_right_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[7] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[8] -to fpga_top/sb_0__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[11] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[9] -to fpga_top/sb_0__1_/chanx_right_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[15] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[10] -to fpga_top/sb_0__1_/chanx_right_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[19] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[12] -to fpga_top/sb_0__1_/chanx_right_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[13] -to fpga_top/sb_0__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[14] -to fpga_top/sb_0__1_/chanx_right_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[16] -to fpga_top/sb_0__1_/chanx_right_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[17] -to fpga_top/sb_0__1_/chanx_right_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[18] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[19] -to fpga_top/sb_0__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[15] -to fpga_top/sb_0__1_/chanx_right_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[11] -to fpga_top/sb_0__1_/chanx_right_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[7] -to fpga_top/sb_0__1_/chanx_right_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[3] -to fpga_top/sb_0__1_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[1] -to fpga_top/sb_0__1_/chanx_right_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_bottom_in[0] -to fpga_top/sb_0__1_/chanx_right_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_0__1_/chanx_right_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[12] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[19] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[4] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[11] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[5] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[3] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[2] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[16] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/bottom_left_grid_pin_1_[0] -to fpga_top/sb_0__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[17] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[1] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[8] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[15] -to fpga_top/sb_0__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[9] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[18] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[0] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[7] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[14] -to fpga_top/sb_0__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chany_top_in[10] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[6] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_0__1_/chanx_right_in[13] -to fpga_top/sb_0__1_/chany_bottom_out[16] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__0_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__0_.sdc new file mode 100644 index 0000000..10ea317 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__0_.sdc @@ -0,0 +1,120 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_12__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[0] -to fpga_top/sb_12__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[19] -to fpga_top/sb_12__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[18] -to fpga_top/sb_12__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[17] -to fpga_top/sb_12__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[16] -to fpga_top/sb_12__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[15] -to fpga_top/sb_12__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[14] -to fpga_top/sb_12__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[13] -to fpga_top/sb_12__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[12] -to fpga_top/sb_12__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[11] -to fpga_top/sb_12__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[10] -to fpga_top/sb_12__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[9] -to fpga_top/sb_12__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[8] -to fpga_top/sb_12__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[7] -to fpga_top/sb_12__0_/chany_top_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[6] -to fpga_top/sb_12__0_/chany_top_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[5] -to fpga_top/sb_12__0_/chany_top_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[4] -to fpga_top/sb_12__0_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[3] -to fpga_top/sb_12__0_/chany_top_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[2] -to fpga_top/sb_12__0_/chany_top_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chanx_left_in[1] -to fpga_top/sb_12__0_/chany_top_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[19] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[18] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[17] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[16] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[15] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[14] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[13] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[12] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[11] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[10] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[9] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[8] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_12__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[7] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_12__0_/chanx_left_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[6] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_12__0_/chanx_left_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[5] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_12__0_/chanx_left_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[4] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_12__0_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[3] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_12__0_/chanx_left_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[2] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_12__0_/chanx_left_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/chany_top_in[1] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_12__0_/chanx_left_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__12_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__12_.sdc new file mode 100644 index 0000000..6419e35 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__12_.sdc @@ -0,0 +1,120 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_12__12_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[1] -to fpga_top/sb_12__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[2] -to fpga_top/sb_12__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[3] -to fpga_top/sb_12__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[4] -to fpga_top/sb_12__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[5] -to fpga_top/sb_12__12_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[6] -to fpga_top/sb_12__12_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[7] -to fpga_top/sb_12__12_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[8] -to fpga_top/sb_12__12_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[9] -to fpga_top/sb_12__12_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[10] -to fpga_top/sb_12__12_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[11] -to fpga_top/sb_12__12_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[12] -to fpga_top/sb_12__12_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[13] -to fpga_top/sb_12__12_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[14] -to fpga_top/sb_12__12_/chany_bottom_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[15] -to fpga_top/sb_12__12_/chany_bottom_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[16] -to fpga_top/sb_12__12_/chany_bottom_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[17] -to fpga_top/sb_12__12_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[18] -to fpga_top/sb_12__12_/chany_bottom_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[19] -to fpga_top/sb_12__12_/chany_bottom_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chanx_left_in[0] -to fpga_top/sb_12__12_/chany_bottom_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[19] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[1] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[2] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[3] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[4] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[5] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[6] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[7] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[8] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[9] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[10] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[11] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[12] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__12_/chanx_left_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[13] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__12_/chanx_left_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[14] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__12_/chanx_left_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[15] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__12_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[16] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__12_/chanx_left_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[17] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__12_/chanx_left_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/chany_bottom_in[18] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__12_/chanx_left_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__1_.sdc new file mode 100644 index 0000000..2dd7ba7 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_12__1_.sdc @@ -0,0 +1,206 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_12__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[1] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[15] -to fpga_top/sb_12__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[2] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[3] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_right_grid_pin_1_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[4] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[11] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[5] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[12] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[19] -to fpga_top/sb_12__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[6] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[13] -to fpga_top/sb_12__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[0] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[7] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chanx_left_in[14] -to fpga_top/sb_12__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[2] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[4] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[1] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[5] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[3] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[6] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[7] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[8] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[9] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[11] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[10] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[15] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[12] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[19] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[13] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[14] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[16] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[17] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_bottom_in[18] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_12__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_12__1_/chanx_left_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[19] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_12__1_/chanx_left_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[15] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_12__1_/chanx_left_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[11] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_12__1_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[7] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_12__1_/chanx_left_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[3] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_12__1_/chanx_left_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/chany_top_in[1] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_12__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_12__1_/chanx_left_out[19] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__0_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__0_.sdc new file mode 100644 index 0000000..a0e1859 --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__0_.sdc @@ -0,0 +1,200 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_1__0_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[1] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[0] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[3] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[7] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[11] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chany_top_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[15] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[19] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chany_top_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chany_top_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chany_top_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chany_top_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chany_top_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chany_top_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__0_/chany_top_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[19] -to fpga_top/sb_1__0_/chany_top_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[15] -to fpga_top/sb_1__0_/chany_top_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[11] -to fpga_top/sb_1__0_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[7] -to fpga_top/sb_1__0_/chany_top_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[3] -to fpga_top/sb_1__0_/chany_top_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[0] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[1] -to fpga_top/sb_1__0_/chany_top_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[2] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[12] -to fpga_top/sb_1__0_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[4] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[13] -to fpga_top/sb_1__0_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[5] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[14] -to fpga_top/sb_1__0_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[6] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[16] -to fpga_top/sb_1__0_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[8] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[17] -to fpga_top/sb_1__0_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[9] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[18] -to fpga_top/sb_1__0_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/right_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_left_in[10] -to fpga_top/sb_1__0_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[7] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[14] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[2] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[12] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[6] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[4] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[13] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[12] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[19] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[5] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[14] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[4] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[11] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[18] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[6] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[16] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_1_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_9_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_17_[0] -to fpga_top/sb_1__0_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[3] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[10] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[8] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[17] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_3_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_11_[0] -to fpga_top/sb_1__0_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[2] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[16] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[9] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[18] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_5_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_13_[0] -to fpga_top/sb_1__0_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[1] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[8] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chany_top_in[15] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/chanx_right_in[10] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_7_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__0_/left_bottom_grid_pin_15_[0] -to fpga_top/sb_1__0_/chanx_left_out[16] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__12_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__12_.sdc new file mode 100644 index 0000000..17cb8de --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__12_.sdc @@ -0,0 +1,200 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_1__12_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[2] -to fpga_top/sb_1__12_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[4] -to fpga_top/sb_1__12_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[5] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[6] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[3] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[8] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[9] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[5] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[10] -to fpga_top/sb_1__12_/chany_bottom_out[6] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[12] -to fpga_top/sb_1__12_/chany_bottom_out[7] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[13] -to fpga_top/sb_1__12_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[14] -to fpga_top/sb_1__12_/chany_bottom_out[9] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[16] -to fpga_top/sb_1__12_/chany_bottom_out[10] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[17] -to fpga_top/sb_1__12_/chany_bottom_out[11] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[19] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[18] -to fpga_top/sb_1__12_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[15] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__12_/chany_bottom_out[13] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[11] -to fpga_top/sb_1__12_/chany_bottom_out[14] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[7] -to fpga_top/sb_1__12_/chany_bottom_out[15] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[3] -to fpga_top/sb_1__12_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[1] -to fpga_top/sb_1__12_/chany_bottom_out[17] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[18] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_left_in[0] -to fpga_top/sb_1__12_/chany_bottom_out[19] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[2] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[12] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[6] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[13] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[4] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[13] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[7] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[14] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[5] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[14] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[1] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[8] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[15] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[6] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[2] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[9] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[16] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_top_grid_pin_1_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__12_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[8] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[3] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[10] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[17] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__12_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[9] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[4] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[11] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[18] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__12_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chanx_right_in[10] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[5] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[12] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/chany_bottom_in[19] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__12_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__12_/chanx_left_out[16] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__1_.sdc b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__1_.sdc new file mode 100644 index 0000000..5490fea --- /dev/null +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SDC/sb_1__1_.sdc @@ -0,0 +1,322 @@ +############################################# +# Synopsys Design Constraints (SDC) +# For FPGA fabric +# Description: Constrain timing of Switch Block sb_1__1_ for PnR +# Author: Xifan TANG +# Organization: University of Utah +# Date: Sun Nov 29 02:09:07 2020 +############################################# + +############################################# +# Define time unit +############################################# +set_units -time s + +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_top_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_top_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_top_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_top_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_top_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_top_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/top_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_top_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chanx_right_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chanx_right_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chanx_right_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chanx_right_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chanx_right_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chanx_right_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/right_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chanx_right_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[2] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[12] -to fpga_top/sb_1__1_/chany_bottom_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[4] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[13] -to fpga_top/sb_1__1_/chany_bottom_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[5] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[7] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[14] -to fpga_top/sb_1__1_/chany_bottom_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[3] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_42_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_46_[0] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[6] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[11] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[16] -to fpga_top/sb_1__1_/chany_bottom_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[1] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_43_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_47_[0] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[8] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[15] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[17] -to fpga_top/sb_1__1_/chany_bottom_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_44_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_48_[0] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[9] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[18] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[19] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_45_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/bottom_left_grid_pin_49_[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[0] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_left_in[10] -to fpga_top/sb_1__1_/chany_bottom_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[2] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[12] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[19] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[0] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[19] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[4] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[13] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[1] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[15] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[1] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[5] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[14] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[2] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[11] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[3] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[6] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[16] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_34_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_38_[0] -to fpga_top/sb_1__1_/chanx_left_out[4] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[7] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[8] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[17] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_35_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_39_[0] -to fpga_top/sb_1__1_/chanx_left_out[8] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[3] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[9] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[11] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[18] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_36_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_40_[0] -to fpga_top/sb_1__1_/chanx_left_out[12] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[1] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_top_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chanx_right_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[10] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/chany_bottom_in[15] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_37_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 +set_max_delay -from fpga_core_uut/sb_1__1_/left_bottom_grid_pin_41_[0] -to fpga_top/sb_1__1_/chanx_left_out[16] 6.020400151e-11 diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml index a14a23c..3484569 100644 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml @@ -2,7 +2,7 @@ - Fabric bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Fri Nov 27 20:48:28 2020 + - Date: Sun Nov 29 02:09:06 2020 --> diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml index 7f52d9c..daf3c8d 100644 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Fri Nov 27 20:48:28 2020 + - Date: Sun Nov 29 02:09:06 2020 --> diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/openfpgashell.log b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/openfpgashell.log index 714039d..d5c45e0 100644 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/openfpgashell.log +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/openfpgashell.log @@ -329,10 +329,10 @@ Warning 60: in check_rr_node: RR node: 1389 type: OPIN location: (11,1) pin: 50 Warning 61: in check_rr_node: RR node: 1390 type: OPIN location: (11,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. Warning 62: in check_rr_node: RR node: 1479 type: OPIN location: (12,1) pin: 50 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. Warning 63: in check_rr_node: RR node: 1480 type: OPIN location: (12,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -## Build tileable routing resource graph took 0.17 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB) +## Build tileable routing resource graph took 0.16 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB) RR Graph Nodes: 18580 RR Graph Edges: 96524 -# Create Device took 0.17 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB) +# Create Device took 0.16 seconds (max_rss 18.1 MiB, delta_rss +7.3 MiB) # Placement ## Computing placement delta delay look-up @@ -654,7 +654,7 @@ Setup slack histogram: [ -9.3e-10: -9.3e-10) 0 ( 0.0%) | [ -9.3e-10: -9.3e-10) 0 ( 0.0%) | -Timing analysis took 0.000513075 seconds (0.000459398 STA, 5.3677e-05 slack) (67 full updates: 48 setup, 0 hold, 19 combined). +Timing analysis took 0.000524223 seconds (0.00046474 STA, 5.9483e-05 slack) (67 full updates: 48 setup, 0 hold, 19 combined). VPR suceeded The entire flow of VPR took 0.50 seconds (max_rss 19.5 MiB) @@ -886,7 +886,7 @@ Done with 19 nodes mapping [99%] Backannotated GSB[12][11] [100%] Backannotated GSB[12][12] Backannotated 169 General Switch Blocks (GSBs). -# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.01 seconds (max_rss 19.8 MiB, delta_rss +0.0 MiB) +# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 19.8 MiB, delta_rss +0.0 MiB) # Sort incoming edges for each routing track output node of General Switch Block(GSB) [0%] Sorted edges for GSB[0][0] [1%] Sorted edges for GSB[0][1] @@ -1127,7 +1127,7 @@ Building physical tiles...Done ## Add connection block instances to top module ## Add connection block instances to top module took 0.00 seconds (max_rss 27.1 MiB, delta_rss +0.5 MiB) ## Add module nets between grids and GSBs -## Add module nets between grids and GSBs took 0.14 seconds (max_rss 42.8 MiB, delta_rss +15.7 MiB) +## Add module nets between grids and GSBs took 0.13 seconds (max_rss 42.8 MiB, delta_rss +15.7 MiB) ## Add module nets for inter-tile connections ## Add module nets for inter-tile connections took 0.00 seconds (max_rss 43.3 MiB, delta_rss +0.5 MiB) ## Add module nets for configuration buses @@ -1168,10 +1168,10 @@ Generating bitstream for X-direction Connection blocks ...Done Generating bitstream for Y-direction Connection blocks ...Done Build fabric-independent bitstream for implementation 'top' - took 0.16 seconds (max_rss 49.7 MiB, delta_rss +5.1 MiB) + took 0.13 seconds (max_rss 49.7 MiB, delta_rss +5.1 MiB) Warning 116: Directory path is empty and nothing will be created. Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' -Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.52 seconds (max_rss 49.7 MiB, delta_rss +0.0 MiB) +Write 67960 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.45 seconds (max_rss 49.7 MiB, delta_rss +0.0 MiB) Command line to execute: build_fabric_bitstream @@ -1182,7 +1182,7 @@ Build fabric dependent bitstream Build fabric dependent bitstream - took 0.03 seconds (max_rss 53.6 MiB, delta_rss +3.9 MiB) + took 0.07 seconds (max_rss 53.6 MiB, delta_rss +3.9 MiB) Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit @@ -1202,7 +1202,7 @@ Confirm selected options when call command 'write_fabric_bitstream': --verbose: off Warning 118: Directory path is empty and nothing will be created. Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml' -Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.09 seconds (max_rss 53.6 MiB, delta_rss +0.0 MiB) +Write 67960 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.12 seconds (max_rss 53.6 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose @@ -1264,7 +1264,7 @@ Building physical tiles...Done Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done Written 71 Verilog modules in total Write Verilog netlists for FPGA fabric - took 0.34 seconds (max_rss 56.4 MiB, delta_rss +2.8 MiB) + took 0.44 seconds (max_rss 56.4 MiB, delta_rss +2.8 MiB) Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping @@ -1284,17 +1284,72 @@ Write Verilog testbenches for FPGA fabric Warning 120: Directory './SRC' already exists. Will overwrite contents # Write pre-configured FPGA top-level Verilog netlist for design 'top' -# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.11 seconds (max_rss 56.4 MiB, delta_rss +0.0 MiB) +# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.14 seconds (max_rss 56.5 MiB, delta_rss +0.2 MiB) # Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' -# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 56.4 MiB, delta_rss +0.0 MiB) +# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 56.5 MiB, delta_rss +0.0 MiB) # Write autocheck testbench for FPGA top-level Verilog netlist for 'top' Will use 67961 configuration clock cycles to top testbench -# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.12 seconds (max_rss 56.6 MiB, delta_rss +0.2 MiB) +# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.13 seconds (max_rss 56.6 MiB, delta_rss +0.1 MiB) Succeed to create directory './SimulationDeck' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 56.6 MiB, delta_rss +0.0 MiB) Write Verilog testbenches for FPGA fabric - took 0.24 seconds (max_rss 56.7 MiB, delta_rss +0.3 MiB) + took 0.29 seconds (max_rss 56.6 MiB, delta_rss +0.2 MiB) + +Command line to execute: write_pnr_sdc --file ./SDC + +Confirm selected options when call command 'write_pnr_sdc': +--file, -f: ./SDC +--flatten_names: off +--hierarchical: off +--output_hierarchy: off +--time_unit: off +--constrain_global_port: off +--constrain_non_clock_global_port: off +--constrain_grid: off +--constrain_sb: off +--constrain_cb: off +--constrain_configurable_memory_outputs: off +--constrain_routing_multiplexer_outputs: off +--constrain_switch_block_outputs: off +--constrain_zero_delay_paths: off +--verbose: off +Succeed to create directory './SDC' +Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' +Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB) +Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' +Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB) +Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' +Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.05 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB) +Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' +Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB) +Write SDC for constrain Switch Block timing for P&R flow +Write SDC for constrain Switch Block timing for P&R flow took 0.05 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB) +Write SDC for constrain Connection Block timing for P&R flow +Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB) +Write SDC for constraining grid timing for P&R flow +Write SDC for constraining grid timing for P&R flow took 0.02 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB) + +Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +Confirm selected options when call command 'write_sdc_disable_timing_configure_ports': +--file, -f: ./SDC/disable_configure_ports.sdc +--flatten_names: off +--verbose: off +Warning 121: Directory './SDC' already exists. Will overwrite contents +Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' +Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.12 seconds (max_rss 56.7 MiB, delta_rss +0.0 MiB) + +Command line to execute: write_analysis_sdc --file ./SDC_analysis + +Confirm selected options when call command 'write_analysis_sdc': +--file, -f: ./SDC_analysis +--verbose: off +--flatten_names: off +--time_unit: off +Succeed to create directory './SDC_analysis' +Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' +Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 0.76 seconds (max_rss 56.8 MiB, delta_rss +0.0 MiB) Command line to execute: exit @@ -1302,6 +1357,6 @@ Confirm selected options when call command 'exit': Finish execution with 0 errors -The entire OpenFPGA flow took 2.06 seconds +The entire OpenFPGA flow took 3.11 seconds Thank you for using OpenFPGA! diff --git a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/generate_fabric.openfpga b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/generate_fabric.openfpga index 2c8e5b5..4131cae 100644 --- a/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/generate_fabric.openfpga +++ b/FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/generate_fabric.openfpga @@ -39,6 +39,17 @@ write_fabric_bitstream --format xml --file fabric_bitstream.xml write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + # Finish and exit OpenFPGA exit diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.fm.v b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.fm.v index 9923502..53318a3 100644 --- a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.fm.v +++ b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.fm.v @@ -34269,7 +34269,385 @@ endmodule module fpga_core ( prog_clk , Test_en , IO_ISOL_N , clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , ccff_head , ccff_tail , sc_head , - sc_tail ) ; + sc_tail , h_incr0 , p0 , p1 , p2 , p3 , p4 , p5 , p6 , p7 , p8 , p9 , + p10 , p11 , p12 , p13 , p14 , p15 , p16 , p17 , p18 , p19 , p20 , p21 , + p22 , p23 , p24 , p25 , p26 , p27 , p28 , p29 , p30 , p31 , p32 , p33 , + p34 , p35 , p36 , p37 , p38 , p39 , p40 , p41 , p42 , p43 , p44 , p45 , + p46 , p47 , p48 , p49 , p50 , p51 , p52 , p53 , p54 , p55 , p56 , p57 , + p58 , p59 , p60 , p61 , p62 , p63 , p64 , p65 , p66 , p67 , p68 , p69 , + p70 , p71 , p72 , p73 , p74 , p75 , p76 , p77 , p78 , p79 , p80 , p81 , + p82 , p83 , p84 , p85 , p86 , p87 , p88 , p89 , p90 , p91 , p92 , p93 , + p94 , p95 , p96 , p97 , p98 , p99 , p100 , p101 , p102 , p103 , p104 , + p105 , p106 , p107 , p108 , p109 , p110 , p111 , p112 , p113 , p114 , + p115 , p116 , p117 , p118 , p119 , p120 , p121 , p122 , p123 , p124 , + p125 , p126 , p127 , p128 , p129 , p130 , p131 , p132 , p133 , p134 , + p135 , p136 , p137 , p138 , p139 , p140 , p141 , p142 , p143 , p144 , + p145 , p146 , p147 , p148 , p149 , p150 , p151 , p152 , p153 , p154 , + p155 , p156 , p157 , p158 , p159 , p160 , p161 , p162 , p163 , p164 , + p165 , p166 , p167 , p168 , p169 , p170 , p171 , p172 , p173 , p174 , + p175 , p176 , p177 , p178 , p179 , p180 , p181 , p182 , p183 , p184 , + p185 , p186 , p187 , p188 , p189 , p190 , p191 , p192 , p193 , p194 , + p195 , p196 , p197 , p198 , p199 , p200 , p201 , p202 , p203 , p204 , + p205 , p206 , p207 , p208 , p209 , p210 , p211 , p212 , p213 , p214 , + p215 , p216 , p217 , p218 , p219 , p220 , p221 , p222 , p223 , p224 , + p225 , p226 , p227 , p228 , p229 , p230 , p231 , p232 , p233 , p234 , + p235 , p236 , p237 , p238 , p239 , p240 , p241 , p242 , p243 , p244 , + p245 , p246 , p247 , p248 , p249 , p250 , p251 , p252 , p253 , p254 , + p255 , p256 , p257 , p258 , p259 , p260 , p261 , p262 , p263 , p264 , + p265 , p266 , p267 , p268 , p269 , p270 , p271 , p272 , p273 , p274 , + p275 , p276 , p277 , p278 , p279 , p280 , p281 , p282 , p283 , p284 , + p285 , p286 , p287 , p288 , p289 , p290 , p291 , p292 , p293 , p294 , + p295 , p296 , p297 , p298 , p299 , p300 , p301 , p302 , p303 , p304 , + p305 , p306 , p307 , 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p2581 , p2582 , p2583 , p2584 , p2585 , p2586 , p2587 , p2588 , + p2589 , p2590 , p2591 , p2592 , p2593 , p2594 , p2595 , p2596 , p2597 , + p2598 , p2599 , p2600 , p2601 , p2602 , p2603 , p2604 , p2605 , p2606 , + p2607 , p2608 , p2609 , p2610 , p2611 , p2612 , p2613 , p2614 , p2615 , + p2616 , p2617 , p2618 , p2619 , p2620 , p2621 , p2622 , p2623 , p2624 , + p2625 , p2626 , p2627 , p2628 , p2629 , p2630 , p2631 , p2632 , p2633 , + p2634 , p2635 , p2636 , p2637 , p2638 , p2639 , p2640 , p2641 , p2642 , + p2643 , p2644 , p2645 , p2646 , p2647 , p2648 , p2649 , p2650 , p2651 , + p2652 , p2653 , p2654 , p2655 , p2656 , p2657 , p2658 , p2659 , p2660 , + p2661 , p2662 , p2663 , p2664 , p2665 , p2666 , p2667 , p2668 , p2669 , + p2670 , p2671 , p2672 , p2673 , p2674 , p2675 , p2676 , p2677 , p2678 , + p2679 , p2680 , p2681 , p2682 , p2683 , p2684 , p2685 , p2686 , p2687 , + p2688 , p2689 , p2690 , p2691 , p2692 , p2693 , p2694 , p2695 , p2696 , + p2697 , p2698 , p2699 , p2700 , p2701 , p2702 , p2703 , p2704 , p2705 , + p2706 , p2707 , p2708 , p2709 , p2710 , p2711 , p2712 , p2713 , p2714 , + p2715 , p2716 , p2717 , p2718 , p2719 , p2720 , p2721 , p2722 , p2723 , + p2724 , p2725 , p2726 , p2727 , p2728 , p2729 , p2730 , p2731 , p2732 , + p2733 , p2734 , p2735 , p2736 , p2737 , p2738 , p2739 , p2740 , p2741 , + p2742 , p2743 , p2744 , p2745 , p2746 , p2747 , p2748 , p2749 , p2750 , + p2751 , p2752 , p2753 , p2754 , p2755 , p2756 , p2757 , p2758 , p2759 , + p2760 , p2761 , p2762 , p2763 , p2764 , p2765 , p2766 , p2767 , p2768 , + p2769 , p2770 , p2771 , p2772 , p2773 , p2774 , p2775 , p2776 , p2777 , + p2778 , p2779 , p2780 , p2781 , p2782 , p2783 , p2784 , p2785 , p2786 , + p2787 , p2788 , p2789 , p2790 , p2791 , p2792 , p2793 , p2794 , p2795 , + p2796 , p2797 , p2798 , p2799 , p2800 , p2801 , p2802 , p2803 , p2804 , + p2805 , p2806 , p2807 , p2808 , p2809 , p2810 , p2811 , p2812 , p2813 , + p2814 , p2815 , p2816 , p2817 , p2818 , p2819 , p2820 , p2821 , p2822 , + p2823 , p2824 , p2825 , p2826 , p2827 , p2828 , p2829 , p2830 , p2831 , + p2832 , p2833 , p2834 , p2835 , p2836 , p2837 , p2838 , p2839 , p2840 , + p2841 , p2842 , p2843 , p2844 , p2845 , p2846 , p2847 , p2848 , p2849 , + p2850 , p2851 , p2852 , p2853 , p2854 , p2855 , p2856 , p2857 , p2858 , + p2859 , p2860 , p2861 , p2862 , p2863 , p2864 , p2865 , p2866 , p2867 , + p2868 , p2869 , p2870 , p2871 , p2872 , p2873 , p2874 , p2875 , p2876 , + p2877 , p2878 , p2879 , p2880 , p2881 , p2882 , p2883 , p2884 , p2885 , + p2886 , p2887 , p2888 , p2889 , p2890 , p2891 , p2892 , p2893 , p2894 , + p2895 , p2896 , p2897 , p2898 , p2899 , p2900 , p2901 , p2902 , p2903 , + p2904 , p2905 , p2906 , p2907 , p2908 , p2909 , p2910 , p2911 , p2912 , + p2913 , p2914 , p2915 , p2916 , p2917 , p2918 , p2919 , p2920 , p2921 , + p2922 , p2923 , p2924 , p2925 , p2926 , p2927 , p2928 , p2929 , p2930 , + p2931 , p2932 , p2933 , p2934 , p2935 , p2936 , p2937 , p2938 , p2939 , + p2940 , p2941 , p2942 , p2943 , p2944 , p2945 , p2946 , p2947 , p2948 , + p2949 , p2950 , p2951 , p2952 , p2953 , p2954 , p2955 , p2956 , p2957 , + p2958 , p2959 , p2960 , p2961 , p2962 , p2963 , p2964 , p2965 , p2966 , + p2967 , p2968 , p2969 , p2970 , p2971 , p2972 , p2973 , p2974 , p2975 , + p2976 , p2977 , p2978 , p2979 , p2980 , p2981 , p2982 , p2983 , p2984 , + p2985 , p2986 , p2987 , p2988 , p2989 , p2990 , p2991 , p2992 , p2993 , + p2994 , p2995 , p2996 , p2997 , p2998 , p2999 , p3000 , p3001 , p3002 , + p3003 , p3004 , p3005 , p3006 , p3007 , p3008 , p3009 , p3010 , p3011 , + p3012 , p3013 , p3014 , p3015 , p3016 , p3017 , p3018 , p3019 , p3020 , + p3021 , p3022 , p3023 , p3024 , p3025 , p3026 , p3027 , p3028 , p3029 , + p3030 , p3031 , p3032 , p3033 , p3034 , p3035 , p3036 , p3037 , p3038 , + p3039 , p3040 , p3041 , p3042 , p3043 , p3044 , p3045 , p3046 , p3047 , + p3048 , p3049 , p3050 , p3051 , p3052 , p3053 , p3054 , p3055 , p3056 , + p3057 , p3058 , p3059 , p3060 , p3061 , p3062 , p3063 , p3064 , p3065 , + p3066 , p3067 , p3068 , p3069 , p3070 , p3071 , p3072 , p3073 , p3074 , + p3075 , p3076 , p3077 , p3078 , p3079 , p3080 , p3081 , p3082 , p3083 , + p3084 , p3085 , p3086 , p3087 , p3088 , p3089 , p3090 , p3091 , p3092 , + p3093 , p3094 , p3095 , p3096 , p3097 , p3098 , p3099 , p3100 , p3101 , + p3102 , p3103 , p3104 , p3105 , p3106 , p3107 , p3108 , p3109 , p3110 , + p3111 , p3112 , p3113 , p3114 , p3115 , p3116 , p3117 , p3118 , p3119 , + p3120 , p3121 , p3122 , p3123 , p3124 , p3125 , p3126 , p3127 , p3128 , + p3129 , p3130 , p3131 , p3132 , p3133 , p3134 , p3135 , p3136 , p3137 , + p3138 , p3139 , p3140 , p3141 , p3142 , p3143 , p3144 , p3145 , p3146 , + p3147 , p3148 , p3149 , p3150 , p3151 , p3152 , p3153 , p3154 , p3155 , + p3156 , p3157 , p3158 , p3159 , p3160 , p3161 , p3162 , p3163 , p3164 , + p3165 , p3166 , p3167 , p3168 , p3169 , p3170 , p3171 , p3172 , p3173 , + p3174 , p3175 , p3176 , p3177 , p3178 , p3179 , p3180 , p3181 , p3182 , + p3183 , p3184 , p3185 , p3186 , p3187 , p3188 , p3189 , p3190 , p3191 , + p3192 , p3193 , p3194 , p3195 , p3196 , p3197 , p3198 , p3199 , p3200 , + p3201 , p3202 , p3203 , p3204 , p3205 , p3206 , p3207 , p3208 , p3209 , + p3210 , p3211 , p3212 , p3213 , p3214 , p3215 , p3216 , p3217 , p3218 , + p3219 , p3220 , p3221 , p3222 , p3223 , p3224 , p3225 , p3226 , p3227 , + p3228 , p3229 , p3230 , p3231 , p3232 , p3233 , p3234 , p3235 , p3236 , + p3237 , p3238 , p3239 , p3240 , p3241 , p3242 , p3243 , p3244 , p3245 , + p3246 , p3247 , p3248 , p3249 , p3250 , p3251 , p3252 , p3253 , p3254 , + p3255 , p3256 , p3257 , p3258 , p3259 , p3260 , p3261 , p3262 , p3263 , + p3264 , p3265 , p3266 , p3267 , p3268 , p3269 , p3270 , p3271 , p3272 , + p3273 , p3274 , p3275 , p3276 , p3277 , p3278 , p3279 , p3280 , p3281 , + p3282 , p3283 , p3284 , p3285 , p3286 , p3287 , p3288 , p3289 , p3290 , + p3291 , p3292 , p3293 , p3294 , p3295 , p3296 , p3297 , p3298 , p3299 , + p3300 , p3301 , p3302 , p3303 , p3304 , p3305 , p3306 , p3307 , p3308 , + p3309 , p3310 , p3311 , p3312 , p3313 , p3314 , p3315 , p3316 , p3317 , + p3318 , p3319 , p3320 , p3321 , p3322 , p3323 , p3324 , p3325 , p3326 , + p3327 , p3328 , p3329 , p3330 , p3331 , p3332 , p3333 , p3334 , p3335 , + p3336 , p3337 , p3338 , p3339 , p3340 , p3341 , p3342 , p3343 , p3344 , + p3345 , p3346 , p3347 , p3348 , p3349 , p3350 , p3351 , p3352 , p3353 , + p3354 , p3355 , p3356 , p3357 , p3358 , p3359 , p3360 , p3361 , p3362 , + p3363 , p3364 , p3365 , p3366 , p3367 , p3368 , p3369 , p3370 , p3371 , + p3372 , p3373 , p3374 , p3375 , p3376 , p3377 , p3378 , p3379 , p3380 , + p3381 , p3382 , p3383 , p3384 , p3385 , p3386 , p3387 , p3388 , p3389 , + p3390 , p3391 , p3392 , p3393 , p3394 , p3395 , p3396 , p3397 , p3398 , + p3399 , p3400 , p3401 , p3402 , p3403 , p3404 , p3405 , p3406 , p3407 , + p3408 , p3409 , p3410 , p3411 , p3412 , p3413 , p3414 , p3415 , p3416 , + p3417 , p3418 , p3419 , p3420 , p3421 , p3422 , p3423 , p3424 , p3425 , + p3426 , p3427 , p3428 , p3429 , p3430 , p3431 , p3432 , p3433 , p3434 , + p3435 , p3436 , p3437 , p3438 , p3439 , p3440 , p3441 , p3442 , p3443 , + p3444 , p3445 , p3446 , p3447 , p3448 , p3449 , p3450 , p3451 , p3452 , + p3453 , p3454 , p3455 , p3456 , p3457 , p3458 , p3459 , p3460 , p3461 , + p3462 , p3463 , p3464 , p3465 , p3466 , p3467 , p3468 , p3469 , p3470 , + p3471 , p3472 , p3473 , p3474 , p3475 , p3476 , p3477 , p3478 , p3479 , + p3480 , p3481 , p3482 , p3483 , p3484 , p3485 , p3486 , p3487 , p3488 , + p3489 , p3490 , p3491 , p3492 , p3493 , p3494 , p3495 , p3496 , p3497 , + p3498 , p3499 , p3500 , p3501 , p3502 , p3503 , p3504 , p3505 , p3506 , + p3507 , p3508 , p3509 , p3510 , p3511 , p3512 , p3513 , p3514 , p3515 , + p3516 , p3517 , p3518 , p3519 , p3520 , p3521 , p3522 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] IO_ISOL_N ; @@ -34281,6 +34659,3530 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; input sc_head ; output sc_tail ; +input h_incr0 ; +input p0 ; +input p1 ; +input p2 ; +input p3 ; +input p4 ; +input p5 ; +input p6 ; +input p7 ; +input p8 ; +input p9 ; +input p10 ; +input p11 ; +input p12 ; +input p13 ; +input p14 ; +input p15 ; +input p16 ; +input p17 ; +input p18 ; +input p19 ; +input p20 ; +input p21 ; +input p22 ; +input p23 ; +input p24 ; +input p25 ; +input p26 ; +input p27 ; +input p28 ; +input p29 ; +input p30 ; +input p31 ; +input p32 ; +input p33 ; +input p34 ; +input p35 ; +input p36 ; +input p37 ; +input p38 ; +input p39 ; +input p40 ; +input p41 ; +input p42 ; +input p43 ; +input p44 ; +input p45 ; +input p46 ; +input p47 ; +input p48 ; +input p49 ; +input p50 ; +input p51 ; +input p52 ; +input p53 ; +input p54 ; +input p55 ; +input p56 ; +input p57 ; +input p58 ; +input p59 ; +input p60 ; +input p61 ; +input p62 ; +input p63 ; +input p64 ; +input p65 ; +input p66 ; +input p67 ; +input p68 ; +input p69 ; +input p70 ; +input p71 ; +input p72 ; +input p73 ; +input p74 ; +input p75 ; +input p76 ; +input p77 ; +input p78 ; +input p79 ; +input p80 ; +input p81 ; +input p82 ; +input p83 ; +input p84 ; +input p85 ; +input p86 ; +input p87 ; +input p88 ; +input p89 ; +input p90 ; +input p91 ; +input p92 ; +input p93 ; +input p94 ; +input p95 ; +input p96 ; +input p97 ; +input p98 ; +input p99 ; +input p100 ; +input p101 ; +input p102 ; +input p103 ; +input p104 ; +input p105 ; +input p106 ; +input p107 ; +input p108 ; +input p109 ; +input p110 ; +input p111 ; +input p112 ; +input p113 ; +input p114 ; +input p115 ; +input p116 ; +input p117 ; +input p118 ; +input p119 ; +input p120 ; +input p121 ; +input p122 ; +input p123 ; +input p124 ; +input p125 ; +input p126 ; +input p127 ; +input p128 ; +input p129 ; +input p130 ; +input p131 ; +input p132 ; +input p133 ; +input p134 ; +input p135 ; +input p136 ; +input p137 ; +input p138 ; +input p139 ; +input p140 ; +input p141 ; +input p142 ; +input p143 ; +input p144 ; +input p145 ; +input p146 ; +input p147 ; +input p148 ; +input p149 ; +input p150 ; +input p151 ; +input p152 ; +input p153 ; +input p154 ; +input p155 ; +input p156 ; +input p157 ; +input p158 ; +input p159 ; +input p160 ; +input p161 ; +input p162 ; +input p163 ; +input p164 ; +input p165 ; +input p166 ; +input p167 ; +input p168 ; +input p169 ; +input p170 ; +input p171 ; +input p172 ; +input p173 ; +input p174 ; +input p175 ; +input p176 ; +input p177 ; +input p178 ; +input p179 ; +input p180 ; +input p181 ; +input p182 ; +input p183 ; +input p184 ; +input p185 ; +input p186 ; +input p187 ; +input p188 ; +input p189 ; +input p190 ; +input p191 ; +input p192 ; +input p193 ; +input p194 ; +input p195 ; +input p196 ; +input p197 ; +input p198 ; +input p199 ; +input p200 ; +input p201 ; +input p202 ; +input p203 ; +input p204 ; +input p205 ; +input p206 ; +input p207 ; +input p208 ; +input p209 ; +input p210 ; +input p211 ; +input p212 ; +input p213 ; +input p214 ; +input p215 ; +input p216 ; +input p217 ; +input p218 ; +input p219 ; +input p220 ; +input p221 ; +input p222 ; +input p223 ; +input p224 ; +input p225 ; +input p226 ; +input p227 ; +input p228 ; +input p229 ; +input p230 ; +input p231 ; +input p232 ; +input p233 ; +input p234 ; +input p235 ; +input p236 ; +input p237 ; +input p238 ; +input p239 ; +input p240 ; +input p241 ; +input p242 ; +input p243 ; +input p244 ; +input p245 ; +input p246 ; +input p247 ; +input p248 ; +input p249 ; +input p250 ; +input p251 ; +input p252 ; +input p253 ; +input p254 ; +input p255 ; +input p256 ; +input p257 ; +input p258 ; +input p259 ; +input p260 ; +input p261 ; +input p262 ; +input p263 ; +input p264 ; +input p265 ; +input p266 ; +input p267 ; +input p268 ; +input p269 ; +input p270 ; +input p271 ; +input p272 ; +input p273 ; +input p274 ; +input p275 ; +input p276 ; +input p277 ; +input p278 ; +input p279 ; +input p280 ; +input p281 ; +input p282 ; +input p283 ; +input p284 ; +input p285 ; +input p286 ; +input p287 ; +input p288 ; +input p289 ; +input p290 ; +input p291 ; +input p292 ; +input p293 ; +input p294 ; +input p295 ; +input p296 ; +input p297 ; +input p298 ; +input p299 ; +input p300 ; +input p301 ; +input p302 ; +input p303 ; +input p304 ; +input p305 ; +input p306 ; +input p307 ; +input p308 ; +input p309 ; +input p310 ; +input p311 ; +input p312 ; +input p313 ; +input p314 ; +input p315 ; +input p316 ; +input p317 ; +input p318 ; +input p319 ; +input p320 ; +input p321 ; +input p322 ; +input p323 ; +input p324 ; +input p325 ; +input p326 ; +input p327 ; +input p328 ; +input p329 ; +input p330 ; +input p331 ; +input p332 ; +input p333 ; +input p334 ; +input p335 ; +input p336 ; +input p337 ; +input p338 ; +input p339 ; +input p340 ; +input p341 ; +input p342 ; +input p343 ; +input p344 ; +input p345 ; +input p346 ; +input p347 ; +input p348 ; +input p349 ; +input p350 ; +input p351 ; +input p352 ; +input p353 ; +input p354 ; +input p355 ; +input p356 ; +input p357 ; +input p358 ; +input p359 ; +input p360 ; +input p361 ; +input p362 ; +input p363 ; +input p364 ; +input p365 ; +input p366 ; +input p367 ; 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p3005 ; +input p3006 ; +input p3007 ; +input p3008 ; +input p3009 ; +input p3010 ; +input p3011 ; +input p3012 ; +input p3013 ; +input p3014 ; +input p3015 ; +input p3016 ; +input p3017 ; +input p3018 ; +input p3019 ; +input p3020 ; +input p3021 ; +input p3022 ; +input p3023 ; +input p3024 ; +input p3025 ; +input p3026 ; +input p3027 ; +input p3028 ; +input p3029 ; +input p3030 ; +input p3031 ; +input p3032 ; +input p3033 ; +input p3034 ; +input p3035 ; +input p3036 ; +input p3037 ; +input p3038 ; +input p3039 ; +input p3040 ; +input p3041 ; +input p3042 ; +input p3043 ; +input p3044 ; +input p3045 ; +input p3046 ; +input p3047 ; +input p3048 ; +input p3049 ; +input p3050 ; +input p3051 ; +input p3052 ; +input p3053 ; +input p3054 ; +input p3055 ; +input p3056 ; +input p3057 ; +input p3058 ; +input p3059 ; +input p3060 ; +input p3061 ; +input p3062 ; +input p3063 ; +input p3064 ; +input p3065 ; +input p3066 ; +input p3067 ; +input p3068 ; +input p3069 ; +input p3070 ; +input p3071 ; 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p3138 ; +input p3139 ; +input p3140 ; +input p3141 ; +input p3142 ; +input p3143 ; +input p3144 ; +input p3145 ; +input p3146 ; +input p3147 ; +input p3148 ; +input p3149 ; +input p3150 ; +input p3151 ; +input p3152 ; +input p3153 ; +input p3154 ; +input p3155 ; +input p3156 ; +input p3157 ; +input p3158 ; +input p3159 ; +input p3160 ; +input p3161 ; +input p3162 ; +input p3163 ; +input p3164 ; +input p3165 ; +input p3166 ; +input p3167 ; +input p3168 ; +input p3169 ; +input p3170 ; +input p3171 ; +input p3172 ; +input p3173 ; +input p3174 ; +input p3175 ; +input p3176 ; +input p3177 ; +input p3178 ; +input p3179 ; +input p3180 ; +input p3181 ; +input p3182 ; +input p3183 ; +input p3184 ; +input p3185 ; +input p3186 ; +input p3187 ; +input p3188 ; +input p3189 ; +input p3190 ; +input p3191 ; +input p3192 ; +input p3193 ; +input p3194 ; +input p3195 ; +input p3196 ; +input p3197 ; +input p3198 ; +input p3199 ; +input p3200 ; +input p3201 ; +input p3202 ; +input p3203 ; +input p3204 ; +input p3205 ; +input p3206 ; +input p3207 ; +input p3208 ; +input p3209 ; +input p3210 ; +input p3211 ; +input p3212 ; +input p3213 ; +input p3214 ; +input p3215 ; +input p3216 ; +input p3217 ; +input p3218 ; +input p3219 ; +input p3220 ; +input p3221 ; +input p3222 ; +input p3223 ; +input p3224 ; +input p3225 ; +input p3226 ; +input p3227 ; +input p3228 ; +input p3229 ; +input p3230 ; +input p3231 ; +input p3232 ; +input p3233 ; +input p3234 ; +input p3235 ; +input p3236 ; +input p3237 ; +input p3238 ; +input p3239 ; +input p3240 ; +input p3241 ; +input p3242 ; +input p3243 ; +input p3244 ; +input p3245 ; +input p3246 ; +input p3247 ; +input p3248 ; +input p3249 ; +input p3250 ; +input p3251 ; +input p3252 ; +input p3253 ; +input p3254 ; +input p3255 ; +input p3256 ; +input p3257 ; +input p3258 ; +input p3259 ; +input p3260 ; +input p3261 ; +input p3262 ; +input p3263 ; +input p3264 ; +input p3265 ; +input p3266 ; +input p3267 ; +input p3268 ; +input p3269 ; +input p3270 ; +input p3271 ; +input p3272 ; +input p3273 ; +input p3274 ; +input p3275 ; +input p3276 ; +input p3277 ; +input p3278 ; +input p3279 ; +input p3280 ; +input p3281 ; +input p3282 ; +input p3283 ; +input p3284 ; +input p3285 ; +input p3286 ; +input p3287 ; +input p3288 ; +input p3289 ; +input p3290 ; +input p3291 ; +input p3292 ; +input p3293 ; +input p3294 ; +input p3295 ; +input p3296 ; +input p3297 ; +input p3298 ; +input p3299 ; +input p3300 ; +input p3301 ; +input p3302 ; +input p3303 ; +input p3304 ; +input p3305 ; +input p3306 ; +input p3307 ; +input p3308 ; +input p3309 ; +input p3310 ; +input p3311 ; +input p3312 ; +input p3313 ; +input p3314 ; +input p3315 ; +input p3316 ; +input p3317 ; +input p3318 ; +input p3319 ; +input p3320 ; +input p3321 ; +input p3322 ; +input p3323 ; +input p3324 ; +input p3325 ; +input p3326 ; +input p3327 ; +input p3328 ; +input p3329 ; +input p3330 ; +input p3331 ; +input p3332 ; +input p3333 ; +input p3334 ; +input p3335 ; +input p3336 ; +input p3337 ; +input p3338 ; +input p3339 ; +input p3340 ; +input p3341 ; +input p3342 ; +input p3343 ; +input p3344 ; +input p3345 ; +input p3346 ; +input p3347 ; +input p3348 ; +input p3349 ; +input p3350 ; +input p3351 ; +input p3352 ; +input p3353 ; +input p3354 ; +input p3355 ; +input p3356 ; +input p3357 ; +input p3358 ; +input p3359 ; +input p3360 ; +input p3361 ; +input p3362 ; +input p3363 ; +input p3364 ; +input p3365 ; +input p3366 ; +input p3367 ; +input p3368 ; +input p3369 ; +input p3370 ; +input p3371 ; +input p3372 ; +input p3373 ; +input p3374 ; +input p3375 ; +input p3376 ; +input p3377 ; +input p3378 ; +input p3379 ; +input p3380 ; +input p3381 ; +input p3382 ; +input p3383 ; +input p3384 ; +input p3385 ; +input p3386 ; +input p3387 ; +input p3388 ; +input p3389 ; +input p3390 ; +input p3391 ; +input p3392 ; +input p3393 ; +input p3394 ; +input p3395 ; +input p3396 ; +input p3397 ; +input p3398 ; +input p3399 ; +input p3400 ; +input p3401 ; +input p3402 ; +input p3403 ; +input p3404 ; +input p3405 ; +input p3406 ; +input p3407 ; +input p3408 ; +input p3409 ; +input p3410 ; +input p3411 ; +input p3412 ; +input p3413 ; +input p3414 ; +input p3415 ; +input p3416 ; +input p3417 ; +input p3418 ; +input p3419 ; +input p3420 ; +input p3421 ; +input p3422 ; +input p3423 ; +input p3424 ; +input p3425 ; +input p3426 ; +input p3427 ; +input p3428 ; +input p3429 ; +input p3430 ; +input p3431 ; +input p3432 ; +input p3433 ; +input p3434 ; +input p3435 ; +input p3436 ; +input p3437 ; +input p3438 ; +input p3439 ; +input p3440 ; +input p3441 ; +input p3442 ; +input p3443 ; +input p3444 ; +input p3445 ; +input p3446 ; +input p3447 ; +input p3448 ; +input p3449 ; +input p3450 ; +input p3451 ; +input p3452 ; +input p3453 ; +input p3454 ; +input p3455 ; +input p3456 ; +input p3457 ; +input p3458 ; +input p3459 ; +input p3460 ; +input p3461 ; +input p3462 ; +input p3463 ; +input p3464 ; +input p3465 ; +input p3466 ; +input p3467 ; +input p3468 ; +input p3469 ; +input p3470 ; +input p3471 ; +input p3472 ; +input p3473 ; +input p3474 ; +input p3475 ; +input p3476 ; +input p3477 ; +input p3478 ; +input p3479 ; +input p3480 ; +input p3481 ; +input p3482 ; +input p3483 ; +input p3484 ; +input p3485 ; +input p3486 ; +input p3487 ; +input p3488 ; +input p3489 ; +input p3490 ; +input p3491 ; +input p3492 ; +input p3493 ; +input p3494 ; +input p3495 ; +input p3496 ; +input p3497 ; +input p3498 ; +input p3499 ; +input p3500 ; +input p3501 ; +input p3502 ; +input p3503 ; +input p3504 ; +input p3505 ; +input p3506 ; +input p3507 ; +input p3508 ; +input p3509 ; +input p3510 ; +input p3511 ; +input p3512 ; +input p3513 ; +input p3514 ; +input p3515 ; +input p3516 ; +input p3517 ; +input p3518 ; +input p3519 ; +input p3520 ; +input p3521 ; +input p3522 ; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; @@ -58787,14 +62689,11 @@ sb_1__0_ sb_1__0_ ( .chany_top_in ( cby_1__1__0_chany_bottom_out ) , .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) , - .SC_OUT_TOP ( scff_Wires[27] ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1441 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1442 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1443 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1444 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1445 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1446 ) ) ; + .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( p1418 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1441 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p1418 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1442 ) , .clk_3_S_in ( p1418 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1443 ) ) ; sb_1__0_ sb_2__0_ ( .chany_top_in ( cby_1__1__12_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_12_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_12_right_width_0_height_0__pin_43_lower ) , @@ -58828,16 +62727,12 @@ sb_1__0_ sb_2__0_ ( .chany_top_in ( cby_1__1__12_chany_bottom_out ) , .chany_top_out ( sb_1__0__1_chany_top_out ) , .chanx_right_out ( sb_1__0__1_chanx_right_out ) , .chanx_left_out ( sb_1__0__1_chanx_left_out ) , - .ccff_tail ( sb_1__0__1_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1447 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1448 ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1449 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1450 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1451 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1452 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1453 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1454 ) ) ; + .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( p1466 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1444 ) , .Test_en_S_in ( p1549 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1445 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p1549 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1446 ) , .clk_3_S_in ( p1549 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1447 ) ) ; sb_1__0_ sb_3__0_ ( .chany_top_in ( cby_1__1__24_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_24_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_24_right_width_0_height_0__pin_43_lower ) , @@ -58872,14 +62767,11 @@ sb_1__0_ sb_3__0_ ( .chany_top_in ( cby_1__1__24_chany_bottom_out ) , .chanx_right_out ( sb_1__0__2_chanx_right_out ) , .chanx_left_out ( sb_1__0__2_chanx_left_out ) , .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) , - .SC_OUT_TOP ( scff_Wires[80] ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1455 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1456 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1457 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1458 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1459 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1460 ) ) ; + .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( p1255 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1448 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1677 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1449 ) , .clk_3_S_in ( p1677 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1450 ) ) ; sb_1__0_ sb_4__0_ ( .chany_top_in ( cby_1__1__36_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_36_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_36_right_width_0_height_0__pin_43_lower ) , @@ -58913,16 +62805,12 @@ sb_1__0_ sb_4__0_ ( .chany_top_in ( cby_1__1__36_chany_bottom_out ) , .chany_top_out ( sb_1__0__3_chany_top_out ) , .chanx_right_out ( sb_1__0__3_chanx_right_out ) , .chanx_left_out ( sb_1__0__3_chanx_left_out ) , - .ccff_tail ( sb_1__0__3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1461 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1462 ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1463 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1464 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1465 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1466 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1467 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1468 ) ) ; + .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( p1522 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1451 ) , .Test_en_S_in ( p1536 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1452 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1876 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1453 ) , .clk_3_S_in ( p1512 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1454 ) ) ; sb_1__0_ sb_5__0_ ( .chany_top_in ( cby_1__1__48_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_48_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_48_right_width_0_height_0__pin_43_lower ) , @@ -58957,14 +62845,11 @@ sb_1__0_ sb_5__0_ ( .chany_top_in ( cby_1__1__48_chany_bottom_out ) , .chanx_right_out ( sb_1__0__4_chanx_right_out ) , .chanx_left_out ( sb_1__0__4_chanx_left_out ) , .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) , - .SC_OUT_TOP ( scff_Wires[133] ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1469 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1470 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1471 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1472 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1473 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1474 ) ) ; + .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( p1128 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1455 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1128 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1456 ) , .clk_3_S_in ( p1128 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1457 ) ) ; sb_1__0_ sb_6__0_ ( .chany_top_in ( cby_1__1__60_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_60_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_60_right_width_0_height_0__pin_43_lower ) , @@ -58998,9 +62883,8 @@ sb_1__0_ sb_6__0_ ( .chany_top_in ( cby_1__1__60_chany_bottom_out ) , .chany_top_out ( sb_1__0__5_chany_top_out ) , .chanx_right_out ( sb_1__0__5_chanx_right_out ) , .chanx_left_out ( sb_1__0__5_chanx_left_out ) , - .ccff_tail ( sb_1__0__5_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1475 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1476 ) , .Test_en_S_in ( Test_en[0] ) , + .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( p1480 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1458 ) , .Test_en_S_in ( Test_en[0] ) , .Test_en_N_out ( Test_enWires[1] ) , .prog_clk_0_N_in ( prog_clk_0_wires[217] ) , .prog_clk_3_S_in ( prog_clk[0] ) , @@ -59040,14 +62924,11 @@ sb_1__0_ sb_7__0_ ( .chany_top_in ( cby_1__1__72_chany_bottom_out ) , .chanx_right_out ( sb_1__0__6_chanx_right_out ) , .chanx_left_out ( sb_1__0__6_chanx_left_out ) , .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) , - .SC_OUT_TOP ( scff_Wires[186] ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1477 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1478 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1479 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1480 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1481 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1482 ) ) ; + .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( p1290 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1459 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p1290 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1460 ) , .clk_3_S_in ( p1290 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1461 ) ) ; sb_1__0_ sb_8__0_ ( .chany_top_in ( cby_1__1__84_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_84_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_84_right_width_0_height_0__pin_43_lower ) , @@ -59081,16 +62962,12 @@ sb_1__0_ sb_8__0_ ( .chany_top_in ( cby_1__1__84_chany_bottom_out ) , .chany_top_out ( sb_1__0__7_chany_top_out ) , .chanx_right_out ( sb_1__0__7_chanx_right_out ) , .chanx_left_out ( sb_1__0__7_chanx_left_out ) , - .ccff_tail ( sb_1__0__7_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1483 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1484 ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1485 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1486 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1487 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1488 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1489 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1490 ) ) ; + .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( p1052 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1462 ) , .Test_en_S_in ( p1499 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1463 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p1499 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1464 ) , .clk_3_S_in ( p1499 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1465 ) ) ; sb_1__0_ sb_9__0_ ( .chany_top_in ( cby_1__1__96_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_96_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_96_right_width_0_height_0__pin_43_lower ) , @@ -59125,14 +63002,11 @@ sb_1__0_ sb_9__0_ ( .chany_top_in ( cby_1__1__96_chany_bottom_out ) , .chanx_right_out ( sb_1__0__8_chanx_right_out ) , .chanx_left_out ( sb_1__0__8_chanx_left_out ) , .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) , - .SC_OUT_TOP ( scff_Wires[239] ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1491 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1492 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1493 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1494 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1495 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1496 ) ) ; + .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( p1048 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1466 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1048 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1467 ) , .clk_3_S_in ( p1048 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1468 ) ) ; sb_1__0_ sb_10__0_ ( .chany_top_in ( cby_1__1__108_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_108_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_108_right_width_0_height_0__pin_43_lower ) , @@ -59166,16 +63040,12 @@ sb_1__0_ sb_10__0_ ( .chany_top_in ( cby_1__1__108_chany_bottom_out ) , .chany_top_out ( sb_1__0__9_chany_top_out ) , .chanx_right_out ( sb_1__0__9_chanx_right_out ) , .chanx_left_out ( sb_1__0__9_chanx_left_out ) , - .ccff_tail ( sb_1__0__9_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1497 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1498 ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1499 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1500 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1501 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1502 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1503 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1504 ) ) ; + .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( p1433 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1469 ) , .Test_en_S_in ( p1214 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1470 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p1214 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1471 ) , .clk_3_S_in ( p1214 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1472 ) ) ; sb_1__0_ sb_11__0_ ( .chany_top_in ( cby_1__1__120_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_120_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_120_right_width_0_height_0__pin_43_lower ) , @@ -59210,14 +63080,11 @@ sb_1__0_ sb_11__0_ ( .chany_top_in ( cby_1__1__120_chany_bottom_out ) , .chanx_right_out ( sb_1__0__10_chanx_right_out ) , .chanx_left_out ( sb_1__0__10_chanx_left_out ) , .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) , - .SC_OUT_TOP ( scff_Wires[292] ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1505 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1506 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1507 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1508 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1509 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1510 ) ) ; + .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( p1575 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1473 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1575 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1474 ) , .clk_3_S_in ( p1575 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1475 ) ) ; sb_1__1_ sb_1__1_ ( .chany_top_in ( cby_1__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , @@ -59259,49 +63126,38 @@ sb_1__1_ sb_1__1_ ( .chany_top_in ( cby_1__1__1_chany_bottom_out ) , .chanx_right_out ( sb_1__1__0_chanx_right_out ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1511 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1512 ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( p2348 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1476 ) , .prog_clk_0_N_in ( prog_clk_0_wires[8] ) , .prog_clk_1_N_in ( prog_clk_2_wires[4] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1513 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1477 ) , .prog_clk_1_E_out ( prog_clk_1_wires[1] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1514 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1515 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1516 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1517 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1518 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1519 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1520 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1521 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1522 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1523 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1524 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1525 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1526 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1527 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1528 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1529 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( p3191 ) , + .prog_clk_2_E_in ( p467 ) , .prog_clk_2_S_in ( p448 ) , + .prog_clk_2_W_in ( p86 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1478 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1479 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1480 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1481 ) , + .prog_clk_3_W_in ( p2899 ) , .prog_clk_3_E_in ( p425 ) , + .prog_clk_3_S_in ( p7 ) , .prog_clk_3_N_in ( p3163 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1482 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1483 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1484 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1485 ) , .clk_1_N_in ( clk_2_wires[4] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1530 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1486 ) , .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1531 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1532 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1533 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1534 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1535 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1536 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1537 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1538 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1539 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1540 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1541 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1542 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1543 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1544 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1545 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1546 ) ) ; + .clk_2_N_in ( p3031 ) , .clk_2_E_in ( p540 ) , .clk_2_S_in ( p2256 ) , + .clk_2_W_in ( p2812 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1487 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1488 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1489 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1490 ) , .clk_3_W_in ( p2138 ) , + .clk_3_E_in ( p906 ) , .clk_3_S_in ( p1295 ) , .clk_3_N_in ( p2957 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1491 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1492 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1493 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1494 ) ) ; sb_1__1_ sb_1__2_ ( .chany_top_in ( cby_1__1__2_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , @@ -59343,50 +63199,41 @@ sb_1__1_ sb_1__2_ ( .chany_top_in ( cby_1__1__2_chany_bottom_out ) , .chanx_right_out ( sb_1__1__1_chanx_right_out ) , .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) , .chanx_left_out ( sb_1__1__1_chanx_left_out ) , - .ccff_tail ( sb_1__1__1_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1547 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1548 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1549 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1550 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1551 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1552 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1553 ) , + .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( p2068 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1495 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( p3034 ) , + .prog_clk_1_S_in ( p109 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1496 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1497 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1498 ) , .prog_clk_2_E_in ( prog_clk_2_wires[1] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1554 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1555 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1556 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1499 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1500 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1501 ) , .prog_clk_2_S_out ( prog_clk_2_wires[3] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1557 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1558 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1559 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1560 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1561 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1562 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1563 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1564 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1565 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1566 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1567 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1568 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1569 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1570 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1571 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1502 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1503 ) , + .prog_clk_3_W_in ( p1680 ) , .prog_clk_3_E_in ( p150 ) , + .prog_clk_3_S_in ( p1936 ) , .prog_clk_3_N_in ( p1962 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1504 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1505 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1506 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1507 ) , .clk_1_N_in ( p2561 ) , + .clk_1_S_in ( p703 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1508 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1509 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1510 ) , .clk_2_E_in ( clk_2_wires[1] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1572 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1573 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1574 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1511 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1512 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1513 ) , .clk_2_S_out ( clk_2_wires[3] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1575 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1576 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1577 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1578 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1579 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1580 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1581 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1582 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1583 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1584 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1514 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1515 ) , .clk_3_W_in ( p1680 ) , + .clk_3_E_in ( p2663 ) , .clk_3_S_in ( p382 ) , .clk_3_N_in ( p2969 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1516 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1517 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1518 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1519 ) ) ; sb_1__1_ sb_1__3_ ( .chany_top_in ( cby_1__1__3_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , @@ -59428,49 +63275,38 @@ sb_1__1_ sb_1__3_ ( .chany_top_in ( cby_1__1__3_chany_bottom_out ) , .chanx_right_out ( sb_1__1__2_chanx_right_out ) , .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) , .chanx_left_out ( sb_1__1__2_chanx_left_out ) , - .ccff_tail ( sb_1__1__2_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1585 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1586 ) , + .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( p3127 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1520 ) , .prog_clk_0_N_in ( prog_clk_0_wires[18] ) , .prog_clk_1_N_in ( prog_clk_2_wires[11] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1587 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1521 ) , .prog_clk_1_E_out ( prog_clk_1_wires[8] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1588 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1589 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1590 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1591 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1592 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1593 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1594 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1595 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1596 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1597 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1598 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1599 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1600 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1601 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1602 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1603 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( p3331 ) , + .prog_clk_2_E_in ( p1247 ) , .prog_clk_2_S_in ( p545 ) , + .prog_clk_2_W_in ( p575 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1522 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1523 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1524 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1525 ) , + .prog_clk_3_W_in ( p3213 ) , .prog_clk_3_E_in ( p649 ) , + .prog_clk_3_S_in ( p155 ) , .prog_clk_3_N_in ( p3308 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1526 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1527 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1528 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1529 ) , .clk_1_N_in ( clk_2_wires[11] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1604 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1530 ) , .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1605 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1606 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1607 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1608 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1609 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1610 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1611 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1612 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1613 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1614 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1615 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1616 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1617 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1618 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1619 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1620 ) ) ; + .clk_2_N_in ( p3209 ) , .clk_2_E_in ( p236 ) , .clk_2_S_in ( p3092 ) , + .clk_2_W_in ( p3170 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1531 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1532 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1533 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1534 ) , .clk_3_W_in ( p1833 ) , + .clk_3_E_in ( p901 ) , .clk_3_S_in ( p1328 ) , .clk_3_N_in ( p3156 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1535 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1536 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1537 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1538 ) ) ; sb_1__1_ sb_1__4_ ( .chany_top_in ( cby_1__1__4_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_4_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_4_right_width_0_height_0__pin_43_lower ) , @@ -59512,49 +63348,40 @@ sb_1__1_ sb_1__4_ ( .chany_top_in ( cby_1__1__4_chany_bottom_out ) , .chanx_right_out ( sb_1__1__3_chanx_right_out ) , .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) , .chanx_left_out ( sb_1__1__3_chanx_left_out ) , - .ccff_tail ( sb_1__1__3_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1621 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1622 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1623 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1624 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1625 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1626 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1627 ) , + .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( p2365 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1539 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( p2600 ) , + .prog_clk_1_S_in ( p221 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1540 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1541 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1542 ) , .prog_clk_2_E_in ( prog_clk_2_wires[6] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1628 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1629 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1630 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1543 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1544 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1545 ) , .prog_clk_2_S_out ( prog_clk_2_wires[10] ) , .prog_clk_2_N_out ( prog_clk_2_wires[8] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1631 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1632 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1633 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1634 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1635 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1636 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1637 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1638 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1639 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1640 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1641 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1642 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1643 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1644 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1546 ) , + .prog_clk_3_W_in ( p2099 ) , .prog_clk_3_E_in ( p187 ) , + .prog_clk_3_S_in ( p2217 ) , .prog_clk_3_N_in ( p1920 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1547 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1548 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1549 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1550 ) , .clk_1_N_in ( p2017 ) , + .clk_1_S_in ( p1269 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1551 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1552 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1553 ) , .clk_2_E_in ( clk_2_wires[6] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1645 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1646 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1647 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1554 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1555 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1556 ) , .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1648 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1649 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1650 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1651 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1652 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1653 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1654 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1655 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1656 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1557 ) , .clk_3_W_in ( p2099 ) , + .clk_3_E_in ( p1349 ) , .clk_3_S_in ( p1253 ) , .clk_3_N_in ( p2438 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1558 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1559 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1560 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1561 ) ) ; sb_1__1_ sb_1__5_ ( .chany_top_in ( cby_1__1__5_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_5_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_5_right_width_0_height_0__pin_43_lower ) , @@ -59596,49 +63423,38 @@ sb_1__1_ sb_1__5_ ( .chany_top_in ( cby_1__1__5_chany_bottom_out ) , .chanx_right_out ( sb_1__1__4_chanx_right_out ) , .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) , .chanx_left_out ( sb_1__1__4_chanx_left_out ) , - .ccff_tail ( sb_1__1__4_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1657 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1658 ) , + .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( p2358 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1562 ) , .prog_clk_0_N_in ( prog_clk_0_wires[28] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1659 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1563 ) , .prog_clk_1_S_in ( prog_clk_2_wires[9] ) , .prog_clk_1_E_out ( prog_clk_1_wires[15] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1660 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1661 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1662 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1663 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1664 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1665 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1666 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1667 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1668 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1669 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1670 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1671 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1672 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1673 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1674 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1675 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1676 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , .prog_clk_2_N_in ( p3328 ) , + .prog_clk_2_E_in ( p956 ) , .prog_clk_2_S_in ( p1161 ) , + .prog_clk_2_W_in ( p1134 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1564 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1565 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1566 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1567 ) , + .prog_clk_3_W_in ( p2797 ) , .prog_clk_3_E_in ( p780 ) , + .prog_clk_3_S_in ( p288 ) , .prog_clk_3_N_in ( p3320 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1568 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1569 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1570 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1571 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1572 ) , .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) , - .clk_1_W_out ( clk_1_wires[16] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1677 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1678 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1679 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1680 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1681 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1682 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1683 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1684 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1685 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1686 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1687 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1688 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1689 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1690 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1691 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1692 ) ) ; + .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( p3479 ) , + .clk_2_E_in ( p135 ) , .clk_2_S_in ( p2190 ) , .clk_2_W_in ( p3253 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1573 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1574 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1575 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1576 ) , .clk_3_W_in ( p3284 ) , + .clk_3_E_in ( p802 ) , .clk_3_S_in ( p1346 ) , .clk_3_N_in ( p3471 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1577 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1578 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1579 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1580 ) ) ; sb_1__1_ sb_1__6_ ( .chany_top_in ( cby_1__1__6_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_6_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_6_right_width_0_height_0__pin_43_lower ) , @@ -59680,50 +63496,36 @@ sb_1__1_ sb_1__6_ ( .chany_top_in ( cby_1__1__6_chany_bottom_out ) , .chanx_right_out ( sb_1__1__5_chanx_right_out ) , .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) , .chanx_left_out ( sb_1__1__5_chanx_left_out ) , - .ccff_tail ( sb_1__1__5_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1693 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1694 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1695 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1696 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1697 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1698 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1699 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1700 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1701 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1702 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1703 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1704 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1705 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1706 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1707 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1708 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1709 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1710 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1711 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1712 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1713 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1714 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1715 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1716 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1717 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1718 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1719 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1720 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1721 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1722 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1723 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1724 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1725 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1726 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1727 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1728 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1729 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1730 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1731 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1732 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1733 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1734 ) ) ; + .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( p2892 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1581 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( p3197 ) , + .prog_clk_1_S_in ( p1263 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1582 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1583 ) , + .prog_clk_2_N_in ( p3442 ) , .prog_clk_2_E_in ( p751 ) , + .prog_clk_2_S_in ( p63 ) , .prog_clk_2_W_in ( p23 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1584 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1585 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1586 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1587 ) , + .prog_clk_3_W_in ( p2596 ) , .prog_clk_3_E_in ( p122 ) , + .prog_clk_3_S_in ( p1402 ) , .prog_clk_3_N_in ( p3430 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1588 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1589 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1590 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1591 ) , .clk_1_N_in ( p2789 ) , + .clk_1_S_in ( p439 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1592 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1593 ) , .clk_2_N_in ( p3201 ) , + .clk_2_E_in ( p991 ) , .clk_2_S_in ( p2849 ) , .clk_2_W_in ( p2666 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1594 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1595 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1596 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1597 ) , .clk_3_W_in ( p2784 ) , + .clk_3_E_in ( p687 ) , .clk_3_S_in ( p568 ) , .clk_3_N_in ( p3190 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1598 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1599 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1600 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1601 ) ) ; sb_1__1_ sb_1__7_ ( .chany_top_in ( cby_1__1__7_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_7_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_7_right_width_0_height_0__pin_43_lower ) , @@ -59765,49 +63567,38 @@ sb_1__1_ sb_1__7_ ( .chany_top_in ( cby_1__1__7_chany_bottom_out ) , .chanx_right_out ( sb_1__1__6_chanx_right_out ) , .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) , .chanx_left_out ( sb_1__1__6_chanx_left_out ) , - .ccff_tail ( sb_1__1__6_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1735 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1736 ) , + .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( p2521 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1602 ) , .prog_clk_0_N_in ( prog_clk_0_wires[38] ) , .prog_clk_1_N_in ( prog_clk_2_wires[18] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1737 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1603 ) , .prog_clk_1_E_out ( prog_clk_1_wires[22] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1738 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1739 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1740 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1741 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1742 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1743 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1744 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1745 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1746 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1747 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1748 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1749 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1750 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1751 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1752 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1753 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , .prog_clk_2_N_in ( p3393 ) , + .prog_clk_2_E_in ( p1091 ) , .prog_clk_2_S_in ( p1129 ) , + .prog_clk_2_W_in ( p198 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1604 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1605 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1606 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1607 ) , + .prog_clk_3_W_in ( p2893 ) , .prog_clk_3_E_in ( p656 ) , + .prog_clk_3_S_in ( p557 ) , .prog_clk_3_N_in ( p3371 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1608 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1609 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1610 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1611 ) , .clk_1_N_in ( clk_2_wires[18] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1754 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1612 ) , .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1755 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1756 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1757 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1758 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1759 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1760 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1761 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1762 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1763 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1764 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1765 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1766 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1767 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1768 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1769 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1770 ) ) ; + .clk_2_N_in ( p3131 ) , .clk_2_E_in ( p53 ) , .clk_2_S_in ( p2434 ) , + .clk_2_W_in ( p2977 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1613 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1614 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1615 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1616 ) , .clk_3_W_in ( p3024 ) , + .clk_3_E_in ( p304 ) , .clk_3_S_in ( p633 ) , .clk_3_N_in ( p3075 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1617 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1618 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1619 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1620 ) ) ; sb_1__1_ sb_1__8_ ( .chany_top_in ( cby_1__1__8_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_8_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_8_right_width_0_height_0__pin_43_lower ) , @@ -59849,49 +63640,40 @@ sb_1__1_ sb_1__8_ ( .chany_top_in ( cby_1__1__8_chany_bottom_out ) , .chanx_right_out ( sb_1__1__7_chanx_right_out ) , .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) , .chanx_left_out ( sb_1__1__7_chanx_left_out ) , - .ccff_tail ( sb_1__1__7_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1771 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1772 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1773 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1774 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1775 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1776 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1777 ) , + .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( p2764 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1621 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( p3395 ) , + .prog_clk_1_S_in ( p276 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1622 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1623 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1624 ) , .prog_clk_2_E_in ( prog_clk_2_wires[13] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1778 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1779 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1780 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1625 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1626 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1627 ) , .prog_clk_2_S_out ( prog_clk_2_wires[17] ) , .prog_clk_2_N_out ( prog_clk_2_wires[15] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1781 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1782 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1783 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1784 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1785 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1786 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1787 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1788 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1789 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1790 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1791 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1792 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1793 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1794 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1628 ) , + .prog_clk_3_W_in ( p1571 ) , .prog_clk_3_E_in ( p432 ) , + .prog_clk_3_S_in ( p2658 ) , .prog_clk_3_N_in ( p1922 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1629 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1630 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1631 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1632 ) , .clk_1_N_in ( p2122 ) , + .clk_1_S_in ( p462 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1633 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1634 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1635 ) , .clk_2_E_in ( clk_2_wires[13] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1795 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1796 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1797 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1636 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1637 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1638 ) , .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1798 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1799 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1800 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1801 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1802 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1803 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1804 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1805 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1806 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1639 ) , .clk_3_W_in ( p1571 ) , + .clk_3_E_in ( p190 ) , .clk_3_S_in ( p274 ) , .clk_3_N_in ( p3364 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1640 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1641 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1642 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1643 ) ) ; sb_1__1_ sb_1__9_ ( .chany_top_in ( cby_1__1__9_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_9_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_9_right_width_0_height_0__pin_43_lower ) , @@ -59933,49 +63715,38 @@ sb_1__1_ sb_1__9_ ( .chany_top_in ( cby_1__1__9_chany_bottom_out ) , .chanx_right_out ( sb_1__1__8_chanx_right_out ) , .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) , .chanx_left_out ( sb_1__1__8_chanx_left_out ) , - .ccff_tail ( sb_1__1__8_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1807 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1808 ) , + .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( p2528 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1644 ) , .prog_clk_0_N_in ( prog_clk_0_wires[48] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1809 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1645 ) , .prog_clk_1_S_in ( prog_clk_2_wires[16] ) , .prog_clk_1_E_out ( prog_clk_1_wires[29] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1810 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1811 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1812 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1813 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1814 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1815 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1816 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1817 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1818 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1819 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1820 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1821 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1822 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1823 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1824 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1825 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1826 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , .prog_clk_2_N_in ( p3452 ) , + .prog_clk_2_E_in ( p1257 ) , .prog_clk_2_S_in ( p1185 ) , + .prog_clk_2_W_in ( p1965 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1646 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1647 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1648 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1649 ) , + .prog_clk_3_W_in ( p2913 ) , .prog_clk_3_E_in ( p204 ) , + .prog_clk_3_S_in ( p730 ) , .prog_clk_3_N_in ( p3427 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1650 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1651 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1652 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1653 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1654 ) , .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) , - .clk_1_W_out ( clk_1_wires[30] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1827 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1828 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1829 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1830 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1831 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1832 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1833 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1834 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1835 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1836 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1837 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1838 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1839 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1840 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1841 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1842 ) ) ; + .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( p3443 ) , + .clk_2_E_in ( p370 ) , .clk_2_S_in ( p2457 ) , .clk_2_W_in ( p2807 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1655 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1656 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1657 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1658 ) , .clk_3_W_in ( p2758 ) , + .clk_3_E_in ( p1197 ) , .clk_3_S_in ( p1301 ) , .clk_3_N_in ( p3437 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1659 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1660 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1661 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1662 ) ) ; sb_1__1_ sb_1__10_ ( .chany_top_in ( cby_1__1__10_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_10_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_10_right_width_0_height_0__pin_43_lower ) , @@ -60017,50 +63788,41 @@ sb_1__1_ sb_1__10_ ( .chany_top_in ( cby_1__1__10_chany_bottom_out ) , .chanx_right_out ( sb_1__1__9_chanx_right_out ) , .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) , .chanx_left_out ( sb_1__1__9_chanx_left_out ) , - .ccff_tail ( sb_1__1__9_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1843 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1844 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1845 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1846 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1847 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1848 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1849 ) , + .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( p2724 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1663 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( p3385 ) , + .prog_clk_1_S_in ( p671 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1664 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1665 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1666 ) , .prog_clk_2_E_in ( prog_clk_2_wires[20] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1850 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1851 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1852 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1853 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1667 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1668 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1669 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1670 ) , .prog_clk_2_N_out ( prog_clk_2_wires[22] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1854 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1855 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1856 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1857 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1858 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1859 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1860 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1861 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1862 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1863 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1864 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1865 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1866 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1867 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1671 ) , + .prog_clk_3_W_in ( p1537 ) , .prog_clk_3_E_in ( p1192 ) , + .prog_clk_3_S_in ( p2667 ) , .prog_clk_3_N_in ( p127 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1672 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1673 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1674 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1675 ) , .clk_1_N_in ( p2296 ) , + .clk_1_S_in ( p1324 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1676 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1677 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1678 ) , .clk_2_E_in ( clk_2_wires[20] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1868 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1869 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1870 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1871 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1679 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1680 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1681 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1682 ) , .clk_2_N_out ( clk_2_wires[22] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1872 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1873 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1874 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1875 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1876 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1877 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1878 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1879 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1880 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1683 ) , .clk_3_W_in ( p1537 ) , + .clk_3_E_in ( p1933 ) , .clk_3_S_in ( p836 ) , .clk_3_N_in ( p3353 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1684 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1685 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1686 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1687 ) ) ; sb_1__1_ sb_1__11_ ( .chany_top_in ( cby_1__1__11_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_11_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_11_right_width_0_height_0__pin_43_lower ) , @@ -60102,49 +63864,38 @@ sb_1__1_ sb_1__11_ ( .chany_top_in ( cby_1__1__11_chany_bottom_out ) , .chanx_right_out ( sb_1__1__10_chanx_right_out ) , .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) , .chanx_left_out ( sb_1__1__10_chanx_left_out ) , - .ccff_tail ( sb_1__1__10_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1881 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1882 ) , + .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( p2398 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1688 ) , .prog_clk_0_N_in ( prog_clk_0_wires[58] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1883 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1689 ) , .prog_clk_1_S_in ( prog_clk_2_wires[23] ) , .prog_clk_1_E_out ( prog_clk_1_wires[36] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1884 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1885 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1886 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1887 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1888 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1889 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1890 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1891 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1892 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1893 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1894 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1895 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1896 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1897 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1898 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1899 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1900 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , .prog_clk_2_N_in ( p3392 ) , + .prog_clk_2_E_in ( p921 ) , .prog_clk_2_S_in ( p1148 ) , + .prog_clk_2_W_in ( p1076 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1690 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1691 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1692 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1693 ) , + .prog_clk_3_W_in ( p3003 ) , .prog_clk_3_E_in ( p757 ) , + .prog_clk_3_S_in ( p424 ) , .prog_clk_3_N_in ( p3374 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1694 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1695 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1696 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1697 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1698 ) , .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) , - .clk_1_W_out ( clk_1_wires[37] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1901 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1902 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1903 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1904 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1905 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1906 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1907 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1908 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1909 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1910 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1911 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1912 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1913 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1914 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1915 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1916 ) ) ; + .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( p3480 ) , + .clk_2_E_in ( p544 ) , .clk_2_S_in ( p2227 ) , .clk_2_W_in ( p3162 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1699 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1700 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1701 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1702 ) , .clk_3_W_in ( p3207 ) , + .clk_3_E_in ( p257 ) , .clk_3_S_in ( p1145 ) , .clk_3_N_in ( p3473 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1703 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1704 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1705 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1706 ) ) ; sb_1__1_ sb_2__1_ ( .chany_top_in ( cby_1__1__13_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_13_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_13_right_width_0_height_0__pin_43_lower ) , @@ -60186,50 +63937,36 @@ sb_1__1_ sb_2__1_ ( .chany_top_in ( cby_1__1__13_chany_bottom_out ) , .chanx_right_out ( sb_1__1__11_chanx_right_out ) , .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) , .chanx_left_out ( sb_1__1__11_chanx_left_out ) , - .ccff_tail ( sb_1__1__11_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1917 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1918 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1919 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1920 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1921 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1922 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1923 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1924 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1925 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1926 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1927 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1928 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1929 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1930 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1931 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1932 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1933 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1934 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1935 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1936 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1937 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1938 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1939 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1940 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1941 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1942 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1943 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1944 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1945 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1946 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1947 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1948 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1949 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1950 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1951 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1952 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1953 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1954 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1955 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1956 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1957 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1958 ) ) ; + .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( p2516 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1707 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( p2883 ) , + .prog_clk_1_S_in ( p1049 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1708 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1709 ) , + .prog_clk_2_N_in ( p3500 ) , .prog_clk_2_E_in ( p162 ) , + .prog_clk_2_S_in ( p315 ) , .prog_clk_2_W_in ( p598 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1710 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1711 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1712 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1713 ) , + .prog_clk_3_W_in ( p2791 ) , .prog_clk_3_E_in ( p800 ) , + .prog_clk_3_S_in ( p497 ) , .prog_clk_3_N_in ( p3496 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1714 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1715 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1716 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1717 ) , .clk_1_N_in ( p2046 ) , + .clk_1_S_in ( p693 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1718 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1719 ) , .clk_2_N_in ( p3440 ) , + .clk_2_E_in ( p1043 ) , .clk_2_S_in ( p2431 ) , .clk_2_W_in ( p3174 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1720 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1721 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1722 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1723 ) , .clk_3_W_in ( p3212 ) , + .clk_3_E_in ( p1110 ) , .clk_3_S_in ( p1121 ) , .clk_3_N_in ( p3439 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1724 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1725 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1726 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1727 ) ) ; sb_1__1_ sb_2__2_ ( .chany_top_in ( cby_1__1__14_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_14_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_14_right_width_0_height_0__pin_43_lower ) , @@ -60271,50 +64008,41 @@ sb_1__1_ sb_2__2_ ( .chany_top_in ( cby_1__1__14_chany_bottom_out ) , .chanx_right_out ( sb_1__1__12_chanx_right_out ) , .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) , .chanx_left_out ( sb_1__1__12_chanx_left_out ) , - .ccff_tail ( sb_1__1__12_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1959 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1960 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1961 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1962 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1963 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1964 ) , + .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( p2570 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1728 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( p3227 ) , + .prog_clk_1_S_in ( p293 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1729 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1730 ) , .prog_clk_2_N_in ( prog_clk_3_wires[69] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1965 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1966 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1967 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1731 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1732 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1733 ) , .prog_clk_2_W_out ( prog_clk_2_wires[2] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1968 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1969 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1970 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1971 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1972 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1973 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1974 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1975 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1976 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1977 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1978 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_1979 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1980 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1981 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1982 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1734 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1735 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1736 ) , + .prog_clk_3_W_in ( p1435 ) , .prog_clk_3_E_in ( p1208 ) , + .prog_clk_3_S_in ( p2451 ) , .prog_clk_3_N_in ( p287 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1737 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1738 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1739 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1740 ) , .clk_1_N_in ( p2613 ) , + .clk_1_S_in ( p896 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1741 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1742 ) , .clk_2_N_in ( clk_3_wires[69] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1983 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1984 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1985 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1743 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1744 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1745 ) , .clk_2_W_out ( clk_2_wires[2] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1986 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1987 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1988 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1989 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1990 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1991 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1992 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1993 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1994 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1995 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1996 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1746 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1747 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1748 ) , .clk_3_W_in ( p1435 ) , + .clk_3_E_in ( p237 ) , .clk_3_S_in ( p1061 ) , .clk_3_N_in ( p3175 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1749 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1750 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1751 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1752 ) ) ; sb_1__1_ sb_2__3_ ( .chany_top_in ( cby_1__1__15_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_15_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_15_right_width_0_height_0__pin_43_lower ) , @@ -60356,49 +64084,40 @@ sb_1__1_ sb_2__3_ ( .chany_top_in ( cby_1__1__15_chany_bottom_out ) , .chanx_right_out ( sb_1__1__13_chanx_right_out ) , .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) , .chanx_left_out ( sb_1__1__13_chanx_left_out ) , - .ccff_tail ( sb_1__1__13_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_1997 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1998 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_1999 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2000 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2001 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2002 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2003 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2004 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2005 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2006 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2007 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2008 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2009 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2010 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2011 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2012 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2013 ) , + .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( p2154 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1753 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( p1612 ) , + .prog_clk_1_S_in ( p878 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1754 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1755 ) , + .prog_clk_2_N_in ( p1612 ) , .prog_clk_2_E_in ( p256 ) , + .prog_clk_2_S_in ( p685 ) , .prog_clk_2_W_in ( p314 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1756 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1757 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1758 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1759 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1760 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1761 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1762 ) , .prog_clk_3_N_in ( prog_clk_3_wires[65] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2014 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2015 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2016 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2017 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2018 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2019 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2020 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2021 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2022 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2023 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2024 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2025 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2026 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2027 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2028 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2029 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2030 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2031 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1763 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1764 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1765 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( p1612 ) , + .clk_1_S_in ( p64 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1766 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1767 ) , .clk_2_N_in ( p1612 ) , + .clk_2_E_in ( p898 ) , .clk_2_S_in ( p1898 ) , .clk_2_W_in ( p910 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1768 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1769 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1770 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1771 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1772 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1773 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1774 ) , .clk_3_N_in ( clk_3_wires[65] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2032 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2033 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2034 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1775 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1776 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1777 ) , .clk_3_S_out ( clk_3_wires[68] ) ) ; sb_1__1_ sb_2__4_ ( .chany_top_in ( cby_1__1__16_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_16_right_width_0_height_0__pin_42_lower ) , @@ -60441,49 +64160,45 @@ sb_1__1_ sb_2__4_ ( .chany_top_in ( cby_1__1__16_chany_bottom_out ) , .chanx_right_out ( sb_1__1__14_chanx_right_out ) , .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) , .chanx_left_out ( sb_1__1__14_chanx_left_out ) , - .ccff_tail ( sb_1__1__14_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2035 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2036 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2037 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2038 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2039 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2040 ) , + .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( p1627 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1778 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( p1653 ) , + .prog_clk_1_S_in ( p337 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1779 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1780 ) , .prog_clk_2_N_in ( prog_clk_3_wires[59] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2041 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2042 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2043 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1781 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_1782 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1783 ) , .prog_clk_2_W_out ( prog_clk_2_wires[7] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2044 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2045 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2046 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2047 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2048 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2049 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1784 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1785 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1786 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1787 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1788 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1789 ) , .prog_clk_3_N_in ( prog_clk_3_wires[59] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2050 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2051 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2052 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2053 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2054 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2055 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2056 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1790 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1791 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1792 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( p1728 ) , + .clk_1_S_in ( p949 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1793 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1794 ) , .clk_2_N_in ( clk_3_wires[59] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2057 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2058 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2059 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1795 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_1796 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1797 ) , .clk_2_W_out ( clk_2_wires[7] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2060 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2061 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2062 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2063 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2064 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2065 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1798 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1799 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1800 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1801 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1802 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1803 ) , .clk_3_N_in ( clk_3_wires[59] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2066 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2067 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2068 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1804 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1805 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1806 ) , .clk_3_S_out ( clk_3_wires[64] ) ) ; sb_1__1_ sb_2__5_ ( .chany_top_in ( cby_1__1__17_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_17_right_width_0_height_0__pin_42_lower ) , @@ -60526,49 +64241,40 @@ sb_1__1_ sb_2__5_ ( .chany_top_in ( cby_1__1__17_chany_bottom_out ) , .chanx_right_out ( sb_1__1__15_chanx_right_out ) , .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) , .chanx_left_out ( sb_1__1__15_chanx_left_out ) , - .ccff_tail ( sb_1__1__15_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2069 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2070 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2071 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2072 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2073 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2074 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2075 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2076 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2077 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2078 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2079 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2080 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2081 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2082 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2083 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2084 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2085 ) , + .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( p2534 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1807 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( p1619 ) , + .prog_clk_1_S_in ( p726 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1808 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1809 ) , + .prog_clk_2_N_in ( p1619 ) , .prog_clk_2_E_in ( p765 ) , + .prog_clk_2_S_in ( p1902 ) , .prog_clk_2_W_in ( p140 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1810 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1811 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1812 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1813 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1814 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1815 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1816 ) , .prog_clk_3_N_in ( prog_clk_3_wires[55] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2086 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2087 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2088 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2089 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2090 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2091 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2092 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2093 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2094 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2095 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2096 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2097 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2098 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2099 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2100 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2101 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2102 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2103 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1817 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1818 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1819 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( p1619 ) , + .clk_1_S_in ( p341 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1820 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1821 ) , .clk_2_N_in ( p1619 ) , + .clk_2_E_in ( p301 ) , .clk_2_S_in ( p2466 ) , .clk_2_W_in ( p1268 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1822 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1823 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1824 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1825 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1826 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1827 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1828 ) , .clk_3_N_in ( clk_3_wires[55] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2104 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2105 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1829 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1830 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1831 ) , .clk_3_S_out ( clk_3_wires[58] ) ) ; sb_1__1_ sb_2__6_ ( .chany_top_in ( cby_1__1__18_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_18_right_width_0_height_0__pin_42_lower ) , @@ -60611,48 +64317,39 @@ sb_1__1_ sb_2__6_ ( .chany_top_in ( cby_1__1__18_chany_bottom_out ) , .chanx_right_out ( sb_1__1__16_chanx_right_out ) , .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) , .chanx_left_out ( sb_1__1__16_chanx_left_out ) , - .ccff_tail ( sb_1__1__16_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2107 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2108 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2109 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2110 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2111 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2112 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2113 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2114 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2115 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2116 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2117 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2118 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2119 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2120 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2121 ) , + .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( p2072 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1832 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( p1515 ) , + .prog_clk_1_S_in ( p225 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1833 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1834 ) , + .prog_clk_2_N_in ( p1711 ) , .prog_clk_2_E_in ( p128 ) , + .prog_clk_2_S_in ( p1894 ) , .prog_clk_2_W_in ( p449 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1835 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1836 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1837 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1838 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1839 ) , .prog_clk_3_E_in ( prog_clk_3_wires[51] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2122 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2123 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2124 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2125 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_1840 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1841 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1842 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1843 ) , .prog_clk_3_N_out ( prog_clk_3_wires[52] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2126 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2127 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2128 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2129 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2130 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2131 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2132 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2133 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2134 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2135 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2136 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2137 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2138 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( p1515 ) , + .clk_1_S_in ( p869 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1844 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1845 ) , .clk_2_N_in ( p1515 ) , + .clk_2_E_in ( p1207 ) , .clk_2_S_in ( p1967 ) , .clk_2_W_in ( p738 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1846 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1847 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1848 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1849 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1850 ) , .clk_3_E_in ( clk_3_wires[51] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2139 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2140 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2141 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2142 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_1851 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1852 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1853 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1854 ) , .clk_3_N_out ( clk_3_wires[52] ) , .clk_3_S_out ( clk_3_wires[54] ) ) ; sb_1__1_ sb_2__7_ ( .chany_top_in ( cby_1__1__19_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_19_right_width_0_height_0__pin_42_lower ) , @@ -60695,50 +64392,41 @@ sb_1__1_ sb_2__7_ ( .chany_top_in ( cby_1__1__19_chany_bottom_out ) , .chanx_right_out ( sb_1__1__17_chanx_right_out ) , .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) , .chanx_left_out ( sb_1__1__17_chanx_left_out ) , - .ccff_tail ( sb_1__1__17_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2143 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2144 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2145 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2146 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2147 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2148 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2149 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2150 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2151 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2152 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2153 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2154 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2155 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2156 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2157 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2158 ) , + .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( p1756 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1855 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( p1769 ) , + .prog_clk_1_S_in ( p1154 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1856 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1857 ) , + .prog_clk_2_N_in ( p1769 ) , .prog_clk_2_E_in ( p371 ) , + .prog_clk_2_S_in ( p2182 ) , .prog_clk_2_W_in ( p876 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1858 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1859 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1860 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1861 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1862 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1863 ) , .prog_clk_3_S_in ( prog_clk_3_wires[53] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2159 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2160 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2161 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1864 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1865 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1866 ) , .prog_clk_3_N_out ( prog_clk_3_wires[56] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2162 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2163 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2164 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2165 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2166 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2167 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2168 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2169 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2170 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2171 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2172 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2173 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2174 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2175 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2176 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1867 ) , .clk_1_N_in ( p1769 ) , + .clk_1_S_in ( p154 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1868 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1869 ) , .clk_2_N_in ( p1769 ) , + .clk_2_E_in ( p1256 ) , .clk_2_S_in ( p705 ) , .clk_2_W_in ( p935 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1870 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1871 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1872 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1873 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1874 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1875 ) , .clk_3_S_in ( clk_3_wires[53] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2177 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2178 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2179 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1876 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1877 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1878 ) , .clk_3_N_out ( clk_3_wires[56] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2180 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1879 ) ) ; sb_1__1_ sb_2__8_ ( .chany_top_in ( cby_1__1__20_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_20_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_20_right_width_0_height_0__pin_43_lower ) , @@ -60780,50 +64468,46 @@ sb_1__1_ sb_2__8_ ( .chany_top_in ( cby_1__1__20_chany_bottom_out ) , .chanx_right_out ( sb_1__1__18_chanx_right_out ) , .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) , .chanx_left_out ( sb_1__1__18_chanx_left_out ) , - .ccff_tail ( sb_1__1__18_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2181 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2182 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2183 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2184 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2185 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2186 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2187 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2188 ) , + .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( p1869 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1880 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( p1870 ) , + .prog_clk_1_S_in ( p952 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1881 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1882 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1883 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1884 ) , .prog_clk_2_S_in ( prog_clk_3_wires[57] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2189 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1885 ) , .prog_clk_2_W_out ( prog_clk_2_wires[14] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2190 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2191 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2192 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2193 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2194 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1886 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1887 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1888 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1889 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1890 ) , .prog_clk_3_S_in ( prog_clk_3_wires[57] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2195 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2196 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2197 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1891 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1892 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1893 ) , .prog_clk_3_N_out ( prog_clk_3_wires[62] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2198 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2199 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2200 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2201 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2202 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2203 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2204 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1894 ) , .clk_1_N_in ( p1870 ) , + .clk_1_S_in ( p343 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1895 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1896 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1897 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1898 ) , .clk_2_S_in ( clk_3_wires[57] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2205 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1899 ) , .clk_2_W_out ( clk_2_wires[14] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2206 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2207 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2208 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2209 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2210 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1900 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1901 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1902 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1903 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1904 ) , .clk_3_S_in ( clk_3_wires[57] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2211 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2212 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2213 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1905 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1906 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1907 ) , .clk_3_N_out ( clk_3_wires[62] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2214 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1908 ) ) ; sb_1__1_ sb_2__9_ ( .chany_top_in ( cby_1__1__21_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_21_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_21_right_width_0_height_0__pin_43_lower ) , @@ -60865,50 +64549,41 @@ sb_1__1_ sb_2__9_ ( .chany_top_in ( cby_1__1__21_chany_bottom_out ) , .chanx_right_out ( sb_1__1__19_chanx_right_out ) , .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) , .chanx_left_out ( sb_1__1__19_chanx_left_out ) , - .ccff_tail ( sb_1__1__19_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2215 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2216 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2217 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2218 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2219 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2220 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2221 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2222 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2223 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2224 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2225 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2226 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2227 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2228 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2229 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2230 ) , + .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( p3044 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1909 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( p1637 ) , + .prog_clk_1_S_in ( p865 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1910 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1911 ) , + .prog_clk_2_N_in ( p1637 ) , .prog_clk_2_E_in ( p1098 ) , + .prog_clk_2_S_in ( p19 ) , .prog_clk_2_W_in ( p145 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1912 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1913 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1914 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1915 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_1916 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_1917 ) , .prog_clk_3_S_in ( prog_clk_3_wires[63] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2231 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2232 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2233 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_1918 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1919 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1920 ) , .prog_clk_3_N_out ( prog_clk_3_wires[66] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2234 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2235 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2236 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2238 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2239 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2240 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2241 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2242 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2243 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2244 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2245 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2246 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2247 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2248 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1921 ) , .clk_1_N_in ( p1637 ) , + .clk_1_S_in ( p459 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1922 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1923 ) , .clk_2_N_in ( p1637 ) , + .clk_2_E_in ( p526 ) , .clk_2_S_in ( p2952 ) , .clk_2_W_in ( p982 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1924 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1925 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1926 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1927 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_1928 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_1929 ) , .clk_3_S_in ( clk_3_wires[63] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2249 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2250 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2251 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_1930 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1931 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1932 ) , .clk_3_N_out ( clk_3_wires[66] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2252 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1933 ) ) ; sb_1__1_ sb_2__10_ ( .chany_top_in ( cby_1__1__22_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_22_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_22_right_width_0_height_0__pin_43_lower ) , @@ -60950,50 +64625,41 @@ sb_1__1_ sb_2__10_ ( .chany_top_in ( cby_1__1__22_chany_bottom_out ) , .chanx_right_out ( sb_1__1__20_chanx_right_out ) , .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) , .chanx_left_out ( sb_1__1__20_chanx_left_out ) , - .ccff_tail ( sb_1__1__20_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2253 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2254 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2255 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2256 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2257 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2258 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2259 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2260 ) , + .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( p2386 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1934 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( p3421 ) , + .prog_clk_1_S_in ( p612 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1935 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1936 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_1937 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_1938 ) , .prog_clk_2_S_in ( prog_clk_3_wires[67] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2261 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_1939 ) , .prog_clk_2_W_out ( prog_clk_2_wires[21] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2262 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2263 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2264 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2265 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2266 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2267 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2268 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2269 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2270 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2271 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2272 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2273 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2274 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2275 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2276 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2277 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2278 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1940 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1941 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1942 ) , + .prog_clk_3_W_in ( p1227 ) , .prog_clk_3_E_in ( p339 ) , + .prog_clk_3_S_in ( p2231 ) , .prog_clk_3_N_in ( p2444 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1943 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1944 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1945 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1946 ) , .clk_1_N_in ( p2920 ) , + .clk_1_S_in ( p917 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1947 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1948 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_1949 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_1950 ) , .clk_2_S_in ( clk_3_wires[67] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2279 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_1951 ) , .clk_2_W_out ( clk_2_wires[21] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2280 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2281 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2282 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2283 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2284 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2285 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2286 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2287 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2288 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2289 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2290 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1952 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1953 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1954 ) , .clk_3_W_in ( p1227 ) , + .clk_3_E_in ( p1046 ) , .clk_3_S_in ( p152 ) , .clk_3_N_in ( p3409 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1955 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1956 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1957 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1958 ) ) ; sb_1__1_ sb_2__11_ ( .chany_top_in ( cby_1__1__23_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_23_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_23_right_width_0_height_0__pin_43_lower ) , @@ -61035,50 +64701,36 @@ sb_1__1_ sb_2__11_ ( .chany_top_in ( cby_1__1__23_chany_bottom_out ) , .chanx_right_out ( sb_1__1__21_chanx_right_out ) , .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) , .chanx_left_out ( sb_1__1__21_chanx_left_out ) , - .ccff_tail ( sb_1__1__21_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2291 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2292 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2293 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2294 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2295 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2296 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2297 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2298 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2299 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2300 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2301 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2302 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2303 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2304 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2305 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2306 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2307 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2308 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2309 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2310 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2311 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2312 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2313 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2314 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2315 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2316 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2317 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2318 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2319 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2320 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2321 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2322 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2323 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2324 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2325 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2326 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2327 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2328 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2329 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2330 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2331 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2332 ) ) ; + .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( p2737 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1959 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( p3325 ) , + .prog_clk_1_S_in ( p655 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_1960 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_1961 ) , + .prog_clk_2_N_in ( p3444 ) , .prog_clk_2_E_in ( p530 ) , + .prog_clk_2_S_in ( p512 ) , .prog_clk_2_W_in ( p767 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1962 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1963 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1964 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1965 ) , + .prog_clk_3_W_in ( p2537 ) , .prog_clk_3_E_in ( p947 ) , + .prog_clk_3_S_in ( p853 ) , .prog_clk_3_N_in ( p3438 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1966 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1967 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1968 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1969 ) , .clk_1_N_in ( p2612 ) , + .clk_1_S_in ( p877 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_1970 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_1971 ) , .clk_2_N_in ( p3468 ) , + .clk_2_E_in ( p297 ) , .clk_2_S_in ( p2681 ) , .clk_2_W_in ( p3311 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1972 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1973 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1974 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1975 ) , .clk_3_W_in ( p3346 ) , + .clk_3_E_in ( p923 ) , .clk_3_S_in ( p36 ) , .clk_3_N_in ( p3458 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1976 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1977 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1978 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1979 ) ) ; sb_1__1_ sb_3__1_ ( .chany_top_in ( cby_1__1__25_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_25_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_25_right_width_0_height_0__pin_43_lower ) , @@ -61120,49 +64772,38 @@ sb_1__1_ sb_3__1_ ( .chany_top_in ( cby_1__1__25_chany_bottom_out ) , .chanx_right_out ( sb_1__1__22_chanx_right_out ) , .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) , .chanx_left_out ( sb_1__1__22_chanx_left_out ) , - .ccff_tail ( sb_1__1__22_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2333 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2334 ) , + .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( p2530 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1980 ) , .prog_clk_0_N_in ( prog_clk_0_wires[106] ) , .prog_clk_1_N_in ( prog_clk_2_wires[30] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2335 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_1981 ) , .prog_clk_1_E_out ( prog_clk_1_wires[43] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2336 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2337 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2338 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2339 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2340 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2341 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2342 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2343 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2344 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2345 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2346 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2347 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2348 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2349 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2350 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2351 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , .prog_clk_2_N_in ( p2168 ) , + .prog_clk_2_E_in ( p1104 ) , .prog_clk_2_S_in ( p1147 ) , + .prog_clk_2_W_in ( p1961 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_1982 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_1983 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_1984 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_1985 ) , + .prog_clk_3_W_in ( p2734 ) , .prog_clk_3_E_in ( p502 ) , + .prog_clk_3_S_in ( p593 ) , .prog_clk_3_N_in ( p1954 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_1986 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_1987 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_1988 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_1989 ) , .clk_1_N_in ( clk_2_wires[30] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2352 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_1990 ) , .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2353 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2354 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2355 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2356 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2357 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2358 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2359 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2360 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2361 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2362 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2363 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2364 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2365 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2366 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2367 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2368 ) ) ; + .clk_2_N_in ( p3276 ) , .clk_2_E_in ( p159 ) , .clk_2_S_in ( p2454 ) , + .clk_2_W_in ( p3173 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_1991 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_1992 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_1993 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_1994 ) , .clk_3_W_in ( p3218 ) , + .clk_3_E_in ( p702 ) , .clk_3_S_in ( p1264 ) , .clk_3_N_in ( p3245 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_1995 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_1996 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_1997 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_1998 ) ) ; sb_1__1_ sb_3__2_ ( .chany_top_in ( cby_1__1__26_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_26_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_26_right_width_0_height_0__pin_43_lower ) , @@ -61204,50 +64845,41 @@ sb_1__1_ sb_3__2_ ( .chany_top_in ( cby_1__1__26_chany_bottom_out ) , .chanx_right_out ( sb_1__1__23_chanx_right_out ) , .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) , .chanx_left_out ( sb_1__1__23_chanx_left_out ) , - .ccff_tail ( sb_1__1__23_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2369 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2370 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2371 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2372 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2373 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2374 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2375 ) , + .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( p2728 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_1999 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , .prog_clk_1_N_in ( p1752 ) , + .prog_clk_1_S_in ( p84 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2000 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2001 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2002 ) , .prog_clk_2_E_in ( prog_clk_2_wires[28] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2376 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2377 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2378 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2003 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2004 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2005 ) , .prog_clk_2_S_out ( prog_clk_2_wires[29] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2379 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2380 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2381 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2382 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2383 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2384 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2385 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2386 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2387 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2388 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2389 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2390 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2391 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2392 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2393 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2006 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2007 ) , + .prog_clk_3_W_in ( p1755 ) , .prog_clk_3_E_in ( p1326 ) , + .prog_clk_3_S_in ( p2652 ) , .prog_clk_3_N_in ( p621 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2008 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2009 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2010 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2011 ) , .clk_1_N_in ( p1718 ) , + .clk_1_S_in ( p874 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2012 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2013 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2014 ) , .clk_2_E_in ( clk_2_wires[28] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2394 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2395 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2396 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2015 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2016 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2017 ) , .clk_2_S_out ( clk_2_wires[29] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2397 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2398 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2399 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2400 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2401 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2402 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2403 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2404 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2405 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2406 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2018 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2019 ) , .clk_3_W_in ( p1755 ) , + .clk_3_E_in ( p272 ) , .clk_3_S_in ( p252 ) , .clk_3_N_in ( p533 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2020 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2021 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2022 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2023 ) ) ; sb_1__1_ sb_3__3_ ( .chany_top_in ( cby_1__1__27_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_27_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_27_right_width_0_height_0__pin_43_lower ) , @@ -61289,49 +64921,38 @@ sb_1__1_ sb_3__3_ ( .chany_top_in ( cby_1__1__27_chany_bottom_out ) , .chanx_right_out ( sb_1__1__24_chanx_right_out ) , .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) , .chanx_left_out ( sb_1__1__24_chanx_left_out ) , - .ccff_tail ( sb_1__1__24_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2407 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2408 ) , + .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( p1759 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2024 ) , .prog_clk_0_N_in ( prog_clk_0_wires[112] ) , .prog_clk_1_N_in ( prog_clk_2_wires[41] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2409 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2025 ) , .prog_clk_1_E_out ( prog_clk_1_wires[50] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2410 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2411 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2412 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2413 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2414 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2415 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2416 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2417 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2418 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2419 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2420 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2421 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2422 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2423 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2424 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2425 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , .prog_clk_2_N_in ( p2589 ) , + .prog_clk_2_E_in ( p1333 ) , .prog_clk_2_S_in ( p1025 ) , + .prog_clk_2_W_in ( p535 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2026 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2027 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2028 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2029 ) , + .prog_clk_3_W_in ( p2988 ) , .prog_clk_3_E_in ( p246 ) , + .prog_clk_3_S_in ( p356 ) , .prog_clk_3_N_in ( p2477 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2030 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2031 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2032 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2033 ) , .clk_1_N_in ( clk_2_wires[41] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2426 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2034 ) , .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2427 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2428 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2429 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2430 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2431 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2432 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2433 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2434 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2435 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2436 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2437 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2438 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2439 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2440 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2441 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2442 ) ) ; + .clk_2_N_in ( p3501 ) , .clk_2_E_in ( p553 ) , .clk_2_S_in ( p32 ) , + .clk_2_W_in ( p3369 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2035 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2036 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2037 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2038 ) , .clk_3_W_in ( p3384 ) , + .clk_3_E_in ( p696 ) , .clk_3_S_in ( p1032 ) , .clk_3_N_in ( p3498 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2039 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2040 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2041 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2042 ) ) ; sb_1__1_ sb_3__4_ ( .chany_top_in ( cby_1__1__28_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_28_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_28_right_width_0_height_0__pin_43_lower ) , @@ -61373,49 +64994,40 @@ sb_1__1_ sb_3__4_ ( .chany_top_in ( cby_1__1__28_chany_bottom_out ) , .chanx_right_out ( sb_1__1__25_chanx_right_out ) , .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) , .chanx_left_out ( sb_1__1__25_chanx_left_out ) , - .ccff_tail ( sb_1__1__25_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2443 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2444 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2445 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2446 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2447 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2448 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2449 ) , + .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( p2315 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2043 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , .prog_clk_1_N_in ( p3028 ) , + .prog_clk_1_S_in ( p931 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2044 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2045 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2046 ) , .prog_clk_2_E_in ( prog_clk_2_wires[37] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2450 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2451 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2452 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2047 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2048 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2049 ) , .prog_clk_2_S_out ( prog_clk_2_wires[40] ) , .prog_clk_2_N_out ( prog_clk_2_wires[38] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2453 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2454 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2455 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2456 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2457 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2459 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2460 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2461 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2462 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2463 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2464 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2465 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2466 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2050 ) , + .prog_clk_3_W_in ( p2150 ) , .prog_clk_3_E_in ( p83 ) , + .prog_clk_3_S_in ( p2205 ) , .prog_clk_3_N_in ( p2180 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2051 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2052 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2053 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2054 ) , .clk_1_N_in ( p2770 ) , + .clk_1_S_in ( p214 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2055 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2056 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2057 ) , .clk_2_E_in ( clk_2_wires[37] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2467 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2468 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2469 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2058 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2059 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2470 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2471 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2472 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2473 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2474 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2475 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2476 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2477 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2478 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2061 ) , .clk_3_W_in ( p2150 ) , + .clk_3_E_in ( p969 ) , .clk_3_S_in ( p355 ) , .clk_3_N_in ( p2951 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2062 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2063 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2064 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2065 ) ) ; sb_1__1_ sb_3__5_ ( .chany_top_in ( cby_1__1__29_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_29_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_29_right_width_0_height_0__pin_43_lower ) , @@ -61457,49 +65069,38 @@ sb_1__1_ sb_3__5_ ( .chany_top_in ( cby_1__1__29_chany_bottom_out ) , .chanx_right_out ( sb_1__1__26_chanx_right_out ) , .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) , .chanx_left_out ( sb_1__1__26_chanx_left_out ) , - .ccff_tail ( sb_1__1__26_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2479 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2480 ) , + .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( p3014 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2066 ) , .prog_clk_0_N_in ( prog_clk_0_wires[118] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2481 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2067 ) , .prog_clk_1_S_in ( prog_clk_2_wires[39] ) , .prog_clk_1_E_out ( prog_clk_1_wires[57] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2482 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2483 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2484 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2485 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2486 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2487 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2488 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2489 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2490 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2491 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2492 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2493 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2494 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2495 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2496 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2497 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2498 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , .prog_clk_2_N_in ( p3043 ) , + .prog_clk_2_E_in ( p961 ) , .prog_clk_2_S_in ( p919 ) , + .prog_clk_2_W_in ( p404 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2068 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2069 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2070 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2071 ) , + .prog_clk_3_W_in ( p3147 ) , .prog_clk_3_E_in ( p1173 ) , + .prog_clk_3_S_in ( p1277 ) , .prog_clk_3_N_in ( p2947 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2072 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2073 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2074 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2075 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2076 ) , .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) , - .clk_1_W_out ( clk_1_wires[58] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2499 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2500 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2501 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2502 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2504 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2505 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2506 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2507 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2508 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2509 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2510 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2511 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2512 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2513 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2514 ) ) ; + .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( p2859 ) , + .clk_2_E_in ( p933 ) , .clk_2_S_in ( p2970 ) , .clk_2_W_in ( p3090 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2077 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2078 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2079 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2080 ) , .clk_3_W_in ( p2066 ) , + .clk_3_E_in ( p192 ) , .clk_3_S_in ( p395 ) , .clk_3_N_in ( p2845 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2081 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2082 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2083 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2084 ) ) ; sb_1__1_ sb_3__6_ ( .chany_top_in ( cby_1__1__30_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_30_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_30_right_width_0_height_0__pin_43_lower ) , @@ -61541,50 +65142,41 @@ sb_1__1_ sb_3__6_ ( .chany_top_in ( cby_1__1__30_chany_bottom_out ) , .chanx_right_out ( sb_1__1__27_chanx_right_out ) , .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) , .chanx_left_out ( sb_1__1__27_chanx_left_out ) , - .ccff_tail ( sb_1__1__27_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2515 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2516 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2517 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2518 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2519 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2520 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2521 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2522 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2523 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2524 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2525 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2526 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2527 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2528 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2529 ) , + .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( p2155 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2085 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , .prog_clk_1_N_in ( p1351 ) , + .prog_clk_1_S_in ( p541 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2086 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2087 ) , + .prog_clk_2_N_in ( p1597 ) , .prog_clk_2_E_in ( p264 ) , + .prog_clk_2_S_in ( p56 ) , .prog_clk_2_W_in ( p37 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2088 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2089 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2090 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2091 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2092 ) , .prog_clk_3_E_in ( prog_clk_3_wires[47] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2530 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2531 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2532 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2093 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2094 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2095 ) , .prog_clk_3_W_out ( prog_clk_3_wires[50] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2533 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2534 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2535 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2536 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2537 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2538 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2539 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2540 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2541 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2542 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2543 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2544 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2545 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2546 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2547 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2096 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2097 ) , .clk_1_N_in ( p1351 ) , + .clk_1_S_in ( p564 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2098 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2099 ) , .clk_2_N_in ( p1351 ) , + .clk_2_E_in ( p962 ) , .clk_2_S_in ( p1980 ) , .clk_2_W_in ( p1236 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2100 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2101 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2102 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2103 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2104 ) , .clk_3_E_in ( clk_3_wires[47] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2548 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2549 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2550 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2105 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2106 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2107 ) , .clk_3_W_out ( clk_3_wires[50] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2551 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2552 ) ) ; + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2108 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2109 ) ) ; sb_1__1_ sb_3__7_ ( .chany_top_in ( cby_1__1__31_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_31_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_31_right_width_0_height_0__pin_43_lower ) , @@ -61626,49 +65218,38 @@ sb_1__1_ sb_3__7_ ( .chany_top_in ( cby_1__1__31_chany_bottom_out ) , .chanx_right_out ( sb_1__1__28_chanx_right_out ) , .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) , .chanx_left_out ( sb_1__1__28_chanx_left_out ) , - .ccff_tail ( sb_1__1__28_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2553 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2554 ) , + .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( p2870 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2110 ) , .prog_clk_0_N_in ( prog_clk_0_wires[124] ) , .prog_clk_1_N_in ( prog_clk_2_wires[54] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2555 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2111 ) , .prog_clk_1_E_out ( prog_clk_1_wires[64] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2556 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2557 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2558 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2559 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2560 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2561 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2562 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2563 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2564 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2565 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2566 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2567 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2568 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2569 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2570 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2571 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , .prog_clk_2_N_in ( p2708 ) , + .prog_clk_2_E_in ( p119 ) , .prog_clk_2_S_in ( p247 ) , + .prog_clk_2_W_in ( p2261 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2112 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2113 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2114 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2115 ) , + .prog_clk_3_W_in ( p2405 ) , .prog_clk_3_E_in ( p920 ) , + .prog_clk_3_S_in ( p1330 ) , .prog_clk_3_N_in ( p2640 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2116 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2117 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2118 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2119 ) , .clk_1_N_in ( clk_2_wires[54] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2572 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2120 ) , .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2573 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2574 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2575 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2576 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2577 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2578 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2579 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2580 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2581 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2582 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2583 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2584 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2585 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2586 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2587 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2588 ) ) ; + .clk_2_N_in ( p3381 ) , .clk_2_E_in ( p971 ) , .clk_2_S_in ( p2808 ) , + .clk_2_W_in ( p2945 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2121 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2122 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2124 ) , .clk_3_W_in ( p3017 ) , + .clk_3_E_in ( p997 ) , .clk_3_S_in ( p475 ) , .clk_3_N_in ( p3363 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2125 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2126 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2127 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2128 ) ) ; sb_1__1_ sb_3__8_ ( .chany_top_in ( cby_1__1__32_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_32_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_32_right_width_0_height_0__pin_43_lower ) , @@ -61710,49 +65291,40 @@ sb_1__1_ sb_3__8_ ( .chany_top_in ( cby_1__1__32_chany_bottom_out ) , .chanx_right_out ( sb_1__1__29_chanx_right_out ) , .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) , .chanx_left_out ( sb_1__1__29_chanx_left_out ) , - .ccff_tail ( sb_1__1__29_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2589 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2590 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2591 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2592 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2593 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2594 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2595 ) , + .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( p1081 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2129 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , .prog_clk_1_N_in ( p3492 ) , + .prog_clk_1_S_in ( p1140 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2130 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2131 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2132 ) , .prog_clk_2_E_in ( prog_clk_2_wires[50] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2596 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2597 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2598 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2133 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2134 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2135 ) , .prog_clk_2_S_out ( prog_clk_2_wires[53] ) , .prog_clk_2_N_out ( prog_clk_2_wires[51] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2599 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2600 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2601 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2602 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2603 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2604 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2605 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2606 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2607 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2608 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2609 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2611 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2612 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2136 ) , + .prog_clk_3_W_in ( p2340 ) , .prog_clk_3_E_in ( p412 ) , + .prog_clk_3_S_in ( p114 ) , .prog_clk_3_N_in ( p2482 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2137 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2138 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2139 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_1_N_in ( p2048 ) , + .clk_1_S_in ( p130 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2141 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2142 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2143 ) , .clk_2_E_in ( clk_2_wires[50] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2613 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2614 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2615 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2144 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2145 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2146 ) , .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2616 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2617 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2618 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2619 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2620 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2621 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2622 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2623 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2624 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2147 ) , .clk_3_W_in ( p2722 ) , + .clk_3_E_in ( p1138 ) , .clk_3_S_in ( p711 ) , .clk_3_N_in ( p3486 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2148 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2149 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2150 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2151 ) ) ; sb_1__1_ sb_3__9_ ( .chany_top_in ( cby_1__1__33_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_33_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_33_right_width_0_height_0__pin_43_lower ) , @@ -61794,49 +65366,38 @@ sb_1__1_ sb_3__9_ ( .chany_top_in ( cby_1__1__33_chany_bottom_out ) , .chanx_right_out ( sb_1__1__30_chanx_right_out ) , .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) , .chanx_left_out ( sb_1__1__30_chanx_left_out ) , - .ccff_tail ( sb_1__1__30_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2625 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2626 ) , + .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( p3011 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2152 ) , .prog_clk_0_N_in ( prog_clk_0_wires[130] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2627 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2153 ) , .prog_clk_1_S_in ( prog_clk_2_wires[52] ) , .prog_clk_1_E_out ( prog_clk_1_wires[71] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2628 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2629 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2630 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2631 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2632 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2633 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2634 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2635 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2636 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2637 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2638 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2639 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2641 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2642 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2643 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2644 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , .prog_clk_2_N_in ( p3467 ) , + .prog_clk_2_E_in ( p1008 ) , .prog_clk_2_S_in ( p916 ) , + .prog_clk_2_W_in ( p1963 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2154 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2155 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2156 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2157 ) , + .prog_clk_3_W_in ( p3269 ) , .prog_clk_3_E_in ( p788 ) , + .prog_clk_3_S_in ( p367 ) , .prog_clk_3_N_in ( p3454 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2158 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2159 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2160 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2161 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2162 ) , .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) , - .clk_1_W_out ( clk_1_wires[72] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2645 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2646 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2647 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2648 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2649 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2650 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2651 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2652 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2653 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2654 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2655 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2656 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2657 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2658 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2659 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2660 ) ) ; + .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( p3286 ) , + .clk_2_E_in ( p26 ) , .clk_2_S_in ( p2959 ) , .clk_2_W_in ( p3252 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2163 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2164 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2165 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2166 ) , .clk_3_W_in ( p3134 ) , + .clk_3_E_in ( p666 ) , .clk_3_S_in ( p1409 ) , .clk_3_N_in ( p3256 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2167 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2168 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2169 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2170 ) ) ; sb_1__1_ sb_3__10_ ( .chany_top_in ( cby_1__1__34_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_34_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_34_right_width_0_height_0__pin_43_lower ) , @@ -61878,50 +65439,41 @@ sb_1__1_ sb_3__10_ ( .chany_top_in ( cby_1__1__34_chany_bottom_out ) , .chanx_right_out ( sb_1__1__31_chanx_right_out ) , .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) , .chanx_left_out ( sb_1__1__31_chanx_left_out ) , - .ccff_tail ( sb_1__1__31_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2661 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2662 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2663 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2664 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2665 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2666 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2667 ) , + .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( p1630 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2171 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , .prog_clk_1_N_in ( p3448 ) , + .prog_clk_1_S_in ( p743 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2172 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2173 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2174 ) , .prog_clk_2_E_in ( prog_clk_2_wires[63] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2668 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2669 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2670 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2671 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2175 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2176 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2177 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2178 ) , .prog_clk_2_N_out ( prog_clk_2_wires[64] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2672 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2673 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2674 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2675 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2676 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2677 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2678 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2679 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2680 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2681 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2682 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2683 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2684 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2685 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2179 ) , + .prog_clk_3_W_in ( p2332 ) , .prog_clk_3_E_in ( p844 ) , + .prog_clk_3_S_in ( p392 ) , .prog_clk_3_N_in ( p372 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2180 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2181 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2182 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2183 ) , .clk_1_N_in ( p2624 ) , + .clk_1_S_in ( p62 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2184 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2185 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2186 ) , .clk_2_E_in ( clk_2_wires[63] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2686 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2687 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2688 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2689 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2187 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2188 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2189 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2190 ) , .clk_2_N_out ( clk_2_wires[64] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2690 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2691 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2692 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2693 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2694 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2695 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2696 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2697 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2698 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2191 ) , .clk_3_W_in ( p2332 ) , + .clk_3_E_in ( p132 ) , .clk_3_S_in ( p1279 ) , .clk_3_N_in ( p3431 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2192 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2193 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2194 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2195 ) ) ; sb_1__1_ sb_3__11_ ( .chany_top_in ( cby_1__1__35_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_35_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_35_right_width_0_height_0__pin_43_lower ) , @@ -61963,49 +65515,38 @@ sb_1__1_ sb_3__11_ ( .chany_top_in ( cby_1__1__35_chany_bottom_out ) , .chanx_right_out ( sb_1__1__32_chanx_right_out ) , .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) , .chanx_left_out ( sb_1__1__32_chanx_left_out ) , - .ccff_tail ( sb_1__1__32_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2699 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2700 ) , + .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( p2713 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2196 ) , .prog_clk_0_N_in ( prog_clk_0_wires[136] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2701 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2197 ) , .prog_clk_1_S_in ( prog_clk_2_wires[65] ) , .prog_clk_1_E_out ( prog_clk_1_wires[78] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2702 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2703 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2704 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2705 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2706 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2707 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2708 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2709 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2710 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2711 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2712 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2713 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2714 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2715 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2716 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2717 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2718 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , .prog_clk_2_N_in ( p2738 ) , + .prog_clk_2_E_in ( p1096 ) , .prog_clk_2_S_in ( p665 ) , + .prog_clk_2_W_in ( p688 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2198 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2199 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2200 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2201 ) , + .prog_clk_3_W_in ( p3347 ) , .prog_clk_3_E_in ( p890 ) , + .prog_clk_3_S_in ( p1024 ) , .prog_clk_3_N_in ( p2684 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2202 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2203 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2204 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2205 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2206 ) , .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) , - .clk_1_W_out ( clk_1_wires[79] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2719 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2720 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2721 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2722 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2723 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2724 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2725 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2726 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2727 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2728 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2729 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2730 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2731 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2732 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2733 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2734 ) ) ; + .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( p3462 ) , + .clk_2_E_in ( p217 ) , .clk_2_S_in ( p2653 ) , .clk_2_W_in ( p3301 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2207 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2208 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2209 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2210 ) , .clk_3_W_in ( p3339 ) , + .clk_3_E_in ( p722 ) , .clk_3_S_in ( p157 ) , .clk_3_N_in ( p3459 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2211 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2212 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2213 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2214 ) ) ; sb_1__1_ sb_4__1_ ( .chany_top_in ( cby_1__1__37_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_37_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_37_right_width_0_height_0__pin_43_lower ) , @@ -62047,50 +65588,36 @@ sb_1__1_ sb_4__1_ ( .chany_top_in ( cby_1__1__37_chany_bottom_out ) , .chanx_right_out ( sb_1__1__33_chanx_right_out ) , .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) , .chanx_left_out ( sb_1__1__33_chanx_left_out ) , - .ccff_tail ( sb_1__1__33_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2735 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2736 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2737 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2738 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2739 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2740 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2741 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2742 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2743 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2744 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2745 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2746 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2747 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2748 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2749 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2750 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2751 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2752 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2753 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2754 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2755 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2756 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2757 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2758 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2759 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2760 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2761 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2762 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2763 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2764 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2765 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2766 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2767 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2768 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2769 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2770 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2771 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2772 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2773 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2774 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2775 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2776 ) ) ; + .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( p2294 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2215 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , .prog_clk_1_N_in ( p3004 ) , + .prog_clk_1_S_in ( p76 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2216 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2217 ) , + .prog_clk_2_N_in ( p3383 ) , .prog_clk_2_E_in ( p747 ) , + .prog_clk_2_S_in ( p1126 ) , .prog_clk_2_W_in ( p248 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2218 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2219 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2220 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2221 ) , + .prog_clk_3_W_in ( p3512 ) , .prog_clk_3_E_in ( p268 ) , + .prog_clk_3_S_in ( p859 ) , .prog_clk_3_N_in ( p3366 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2222 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2223 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2224 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2225 ) , .clk_1_N_in ( p3042 ) , + .clk_1_S_in ( p948 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2226 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2227 ) , .clk_2_N_in ( p3226 ) , + .clk_2_E_in ( p104 ) , .clk_2_S_in ( p2250 ) , .clk_2_W_in ( p3509 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2228 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2229 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2230 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2231 ) , .clk_3_W_in ( p3271 ) , + .clk_3_E_in ( p772 ) , .clk_3_S_in ( p380 ) , .clk_3_N_in ( p3182 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2232 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2233 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2234 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2235 ) ) ; sb_1__1_ sb_4__2_ ( .chany_top_in ( cby_1__1__38_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_38_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_38_right_width_0_height_0__pin_43_lower ) , @@ -62132,50 +65659,41 @@ sb_1__1_ sb_4__2_ ( .chany_top_in ( cby_1__1__38_chany_bottom_out ) , .chanx_right_out ( sb_1__1__34_chanx_right_out ) , .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) , .chanx_left_out ( sb_1__1__34_chanx_left_out ) , - .ccff_tail ( sb_1__1__34_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2777 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2778 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2779 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2780 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2781 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2782 ) , + .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( p1545 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2236 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , .prog_clk_1_N_in ( p3344 ) , + .prog_clk_1_S_in ( p798 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2237 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2238 ) , .prog_clk_2_N_in ( prog_clk_3_wires[25] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2783 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2784 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2785 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2239 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2240 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2241 ) , .prog_clk_2_W_out ( prog_clk_2_wires[27] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2786 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2787 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2788 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2789 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2790 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2791 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2792 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2793 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2794 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2795 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2796 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2797 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2798 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2799 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2242 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2243 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , .prog_clk_3_W_in ( p1763 ) , + .prog_clk_3_E_in ( p1139 ) , .prog_clk_3_S_in ( p451 ) , + .prog_clk_3_N_in ( p978 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2244 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2245 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2246 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2247 ) , .clk_1_N_in ( p2748 ) , + .clk_1_S_in ( p438 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2248 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2249 ) , .clk_2_N_in ( clk_3_wires[25] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2800 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2801 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2802 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2250 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2251 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2252 ) , .clk_2_W_out ( clk_2_wires[27] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2803 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2804 ) , - .clk_2_E_out ( clk_2_wires[25] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2805 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2806 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2807 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2808 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2809 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2810 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2811 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2812 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2253 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2254 ) , + .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( p1763 ) , + .clk_3_E_in ( p210 ) , .clk_3_S_in ( p330 ) , .clk_3_N_in ( p3317 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2255 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2256 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2257 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2258 ) ) ; sb_1__1_ sb_4__3_ ( .chany_top_in ( cby_1__1__39_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_39_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_39_right_width_0_height_0__pin_43_lower ) , @@ -62217,49 +65735,40 @@ sb_1__1_ sb_4__3_ ( .chany_top_in ( cby_1__1__39_chany_bottom_out ) , .chanx_right_out ( sb_1__1__35_chanx_right_out ) , .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) , .chanx_left_out ( sb_1__1__35_chanx_left_out ) , - .ccff_tail ( sb_1__1__35_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2813 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2814 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2815 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2816 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2817 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2818 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2819 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2820 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2821 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2822 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2823 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2824 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2825 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2826 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2827 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2828 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2829 ) , + .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( p2060 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2259 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , .prog_clk_1_N_in ( p1847 ) , + .prog_clk_1_S_in ( p1027 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2260 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2261 ) , + .prog_clk_2_N_in ( p1827 ) , .prog_clk_2_E_in ( p585 ) , + .prog_clk_2_S_in ( p1193 ) , .prog_clk_2_W_in ( p1211 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2262 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2263 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2264 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2265 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2266 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2267 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2268 ) , .prog_clk_3_N_in ( prog_clk_3_wires[21] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2830 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2831 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2832 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2833 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2834 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2835 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2836 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2837 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2838 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2839 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2840 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2841 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2842 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2843 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2844 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2845 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2846 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2847 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2269 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2270 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2271 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( p1648 ) , + .clk_1_S_in ( p617 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2272 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2273 ) , .clk_2_N_in ( p1847 ) , + .clk_2_E_in ( p626 ) , .clk_2_S_in ( p1917 ) , .clk_2_W_in ( p121 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2274 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2275 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2276 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2277 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2278 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2279 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2280 ) , .clk_3_N_in ( clk_3_wires[21] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2848 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2849 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2850 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2281 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2282 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2283 ) , .clk_3_S_out ( clk_3_wires[24] ) ) ; sb_1__1_ sb_4__4_ ( .chany_top_in ( cby_1__1__40_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_40_right_width_0_height_0__pin_42_lower ) , @@ -62302,49 +65811,45 @@ sb_1__1_ sb_4__4_ ( .chany_top_in ( cby_1__1__40_chany_bottom_out ) , .chanx_right_out ( sb_1__1__36_chanx_right_out ) , .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) , .chanx_left_out ( sb_1__1__36_chanx_left_out ) , - .ccff_tail ( sb_1__1__36_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2851 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2852 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2853 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2854 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2855 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2856 ) , + .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( p1743 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2284 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , .prog_clk_1_N_in ( p2091 ) , + .prog_clk_1_S_in ( p1042 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2285 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2286 ) , .prog_clk_2_N_in ( prog_clk_3_wires[15] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2857 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2858 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2859 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2287 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2288 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2289 ) , .prog_clk_2_W_out ( prog_clk_2_wires[36] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2860 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2861 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2290 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2291 ) , .prog_clk_2_E_out ( prog_clk_2_wires[34] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2862 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2863 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2864 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2292 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2293 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2294 ) , .prog_clk_3_N_in ( prog_clk_3_wires[15] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2865 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2866 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2867 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2868 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2869 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2870 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2871 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2295 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2296 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2297 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( p2091 ) , + .clk_1_S_in ( p125 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2298 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2299 ) , .clk_2_N_in ( clk_3_wires[15] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2872 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2873 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2874 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2300 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2301 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2302 ) , .clk_2_W_out ( clk_2_wires[36] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2875 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2876 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2303 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2304 ) , .clk_2_E_out ( clk_2_wires[34] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2877 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2878 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2879 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2305 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2306 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2307 ) , .clk_3_N_in ( clk_3_wires[15] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2880 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2881 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2882 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2308 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2309 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2310 ) , .clk_3_S_out ( clk_3_wires[20] ) ) ; sb_1__1_ sb_4__5_ ( .chany_top_in ( cby_1__1__41_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_41_right_width_0_height_0__pin_42_lower ) , @@ -62387,49 +65892,40 @@ sb_1__1_ sb_4__5_ ( .chany_top_in ( cby_1__1__41_chany_bottom_out ) , .chanx_right_out ( sb_1__1__37_chanx_right_out ) , .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) , .chanx_left_out ( sb_1__1__37_chanx_left_out ) , - .ccff_tail ( sb_1__1__37_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2883 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2884 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2885 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2886 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2887 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2888 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2889 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2890 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2891 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2892 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2893 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2894 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2895 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2896 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2897 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2898 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2899 ) , + .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( p2542 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2311 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , .prog_clk_1_N_in ( p1650 ) , + .prog_clk_1_S_in ( p92 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2312 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2313 ) , + .prog_clk_2_N_in ( p1650 ) , .prog_clk_2_E_in ( p1342 ) , + .prog_clk_2_S_in ( p1163 ) , .prog_clk_2_W_in ( p312 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2314 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2315 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2316 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2317 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2318 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2319 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2320 ) , .prog_clk_3_N_in ( prog_clk_3_wires[11] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2900 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2901 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2902 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2903 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2904 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2905 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2906 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2907 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2908 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2909 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2910 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2911 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2912 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2913 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2914 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2915 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2916 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2917 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2321 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2322 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2323 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( p1650 ) , + .clk_1_S_in ( p574 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2324 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2325 ) , .clk_2_N_in ( p1650 ) , + .clk_2_E_in ( p810 ) , .clk_2_S_in ( p2468 ) , .clk_2_W_in ( p870 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2326 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2327 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2328 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2329 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2330 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2331 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2332 ) , .clk_3_N_in ( clk_3_wires[11] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2918 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2919 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2920 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2333 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2334 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2335 ) , .clk_3_S_out ( clk_3_wires[14] ) ) ; sb_1__1_ sb_4__6_ ( .chany_top_in ( cby_1__1__42_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_42_right_width_0_height_0__pin_42_lower ) , @@ -62472,47 +65968,38 @@ sb_1__1_ sb_4__6_ ( .chany_top_in ( cby_1__1__42_chany_bottom_out ) , .chanx_right_out ( sb_1__1__38_chanx_right_out ) , .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) , .chanx_left_out ( sb_1__1__38_chanx_left_out ) , - .ccff_tail ( sb_1__1__38_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2921 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2922 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2923 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2924 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2925 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2926 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2927 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2928 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2929 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2930 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2931 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2932 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2933 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2934 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2935 ) , + .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( p1864 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2336 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , .prog_clk_1_N_in ( p1629 ) , + .prog_clk_1_S_in ( p1028 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2337 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2338 ) , + .prog_clk_2_N_in ( p1629 ) , .prog_clk_2_E_in ( p51 ) , + .prog_clk_2_S_in ( p1157 ) , .prog_clk_2_W_in ( p207 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2339 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2340 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2341 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2342 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2343 ) , .prog_clk_3_E_in ( prog_clk_3_wires[7] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2936 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2937 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2938 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2344 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2345 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2346 ) , .prog_clk_3_W_out ( prog_clk_3_wires[46] ) , .prog_clk_3_N_out ( prog_clk_3_wires[8] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2939 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2940 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2941 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2942 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2943 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2944 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2945 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2946 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2947 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2948 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2949 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2950 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2951 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( p1629 ) , + .clk_1_S_in ( p168 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2347 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2348 ) , .clk_2_N_in ( p1629 ) , + .clk_2_E_in ( p1317 ) , .clk_2_S_in ( p600 ) , .clk_2_W_in ( p1280 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2349 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2350 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2351 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2352 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2353 ) , .clk_3_E_in ( clk_3_wires[7] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2952 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2953 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2954 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2354 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2355 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2356 ) , .clk_3_W_out ( clk_3_wires[46] ) , .clk_3_N_out ( clk_3_wires[8] ) , .clk_3_S_out ( clk_3_wires[10] ) ) ; sb_1__1_ sb_4__7_ ( .chany_top_in ( cby_1__1__43_chany_bottom_out ) , @@ -62556,50 +66043,41 @@ sb_1__1_ sb_4__7_ ( .chany_top_in ( cby_1__1__43_chany_bottom_out ) , .chanx_right_out ( sb_1__1__39_chanx_right_out ) , .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) , .chanx_left_out ( sb_1__1__39_chanx_left_out ) , - .ccff_tail ( sb_1__1__39_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2955 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2956 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2957 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2958 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2959 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2960 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2961 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2962 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2963 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2964 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2965 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2966 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2967 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2968 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2969 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2970 ) , + .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( p2171 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2357 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , .prog_clk_1_N_in ( p1220 ) , + .prog_clk_1_S_in ( p354 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2358 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2359 ) , + .prog_clk_2_N_in ( p1220 ) , .prog_clk_2_E_in ( p973 ) , + .prog_clk_2_S_in ( p1285 ) , .prog_clk_2_W_in ( p466 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2360 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2361 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2362 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2363 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2364 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2365 ) , .prog_clk_3_S_in ( prog_clk_3_wires[9] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2971 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2972 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2973 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2366 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2367 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2368 ) , .prog_clk_3_N_out ( prog_clk_3_wires[12] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2974 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2975 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2976 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2977 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2978 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2979 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2980 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2981 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2982 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2983 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2984 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2985 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2986 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2987 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2988 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2369 ) , .clk_1_N_in ( p1220 ) , + .clk_1_S_in ( p1050 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2370 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2371 ) , .clk_2_N_in ( p1220 ) , + .clk_2_E_in ( p129 ) , .clk_2_S_in ( p1907 ) , .clk_2_W_in ( p1331 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2372 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2373 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2374 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2375 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2376 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2377 ) , .clk_3_S_in ( clk_3_wires[9] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2989 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2990 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2991 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2378 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2379 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2380 ) , .clk_3_N_out ( clk_3_wires[12] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2992 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2381 ) ) ; sb_1__1_ sb_4__8_ ( .chany_top_in ( cby_1__1__44_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_44_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_44_right_width_0_height_0__pin_43_lower ) , @@ -62641,50 +66119,46 @@ sb_1__1_ sb_4__8_ ( .chany_top_in ( cby_1__1__44_chany_bottom_out ) , .chanx_right_out ( sb_1__1__40_chanx_right_out ) , .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) , .chanx_left_out ( sb_1__1__40_chanx_left_out ) , - .ccff_tail ( sb_1__1__40_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_2993 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2994 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2995 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2996 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2997 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2998 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2999 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3000 ) , + .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( p1701 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2382 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , .prog_clk_1_N_in ( p1526 ) , + .prog_clk_1_S_in ( p43 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2383 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2384 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2385 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2386 ) , .prog_clk_2_S_in ( prog_clk_3_wires[13] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3001 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2387 ) , .prog_clk_2_W_out ( prog_clk_2_wires[49] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3002 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3003 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2388 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2389 ) , .prog_clk_2_E_out ( prog_clk_2_wires[47] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3004 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3005 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2390 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2391 ) , .prog_clk_3_S_in ( prog_clk_3_wires[13] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3006 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3007 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3008 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2392 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2393 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2394 ) , .prog_clk_3_N_out ( prog_clk_3_wires[18] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3009 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3010 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3011 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3012 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3013 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3014 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3015 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2395 ) , .clk_1_N_in ( p1526 ) , + .clk_1_S_in ( p778 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2396 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2397 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2398 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2399 ) , .clk_2_S_in ( clk_3_wires[13] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3016 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2400 ) , .clk_2_W_out ( clk_2_wires[49] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3017 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3018 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2401 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2402 ) , .clk_2_E_out ( clk_2_wires[47] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3019 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3020 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2403 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2404 ) , .clk_3_S_in ( clk_3_wires[13] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3021 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3022 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3023 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2405 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2406 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2407 ) , .clk_3_N_out ( clk_3_wires[18] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3024 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2408 ) ) ; sb_1__1_ sb_4__9_ ( .chany_top_in ( cby_1__1__45_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_45_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_45_right_width_0_height_0__pin_43_lower ) , @@ -62726,50 +66200,41 @@ sb_1__1_ sb_4__9_ ( .chany_top_in ( cby_1__1__45_chany_bottom_out ) , .chanx_right_out ( sb_1__1__41_chanx_right_out ) , .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) , .chanx_left_out ( sb_1__1__41_chanx_left_out ) , - .ccff_tail ( sb_1__1__41_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3025 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3026 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3027 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3028 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3029 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3030 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3031 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3032 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3033 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3034 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3035 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3036 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3037 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3038 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3039 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3040 ) , + .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( p2621 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2409 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , .prog_clk_1_N_in ( p1388 ) , + .prog_clk_1_S_in ( p289 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2410 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2411 ) , + .prog_clk_2_N_in ( p1388 ) , .prog_clk_2_E_in ( p1209 ) , + .prog_clk_2_S_in ( p1927 ) , .prog_clk_2_W_in ( p583 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2412 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2413 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2414 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2415 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2416 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2417 ) , .prog_clk_3_S_in ( prog_clk_3_wires[19] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3041 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3042 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3043 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2418 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2419 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2420 ) , .prog_clk_3_N_out ( prog_clk_3_wires[22] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3044 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3045 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3046 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3047 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3048 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3049 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3050 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3051 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3052 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3053 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3054 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3055 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3056 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3057 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3058 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2421 ) , .clk_1_N_in ( p1388 ) , + .clk_1_S_in ( p826 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2422 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2423 ) , .clk_2_N_in ( p1388 ) , + .clk_2_E_in ( p5 ) , .clk_2_S_in ( p2447 ) , .clk_2_W_in ( p988 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2424 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2425 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2426 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2427 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2428 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2429 ) , .clk_3_S_in ( clk_3_wires[19] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3059 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3060 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3061 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2430 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2431 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2432 ) , .clk_3_N_out ( clk_3_wires[22] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3062 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2433 ) ) ; sb_1__1_ sb_4__10_ ( .chany_top_in ( cby_1__1__46_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_46_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_46_right_width_0_height_0__pin_43_lower ) , @@ -62811,50 +66276,41 @@ sb_1__1_ sb_4__10_ ( .chany_top_in ( cby_1__1__46_chany_bottom_out ) , .chanx_right_out ( sb_1__1__42_chanx_right_out ) , .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) , .chanx_left_out ( sb_1__1__42_chanx_left_out ) , - .ccff_tail ( sb_1__1__42_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3063 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3064 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3065 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3066 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3067 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3068 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3069 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3070 ) , + .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( p2059 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2434 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , .prog_clk_1_N_in ( p3382 ) , + .prog_clk_1_S_in ( p981 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2435 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2436 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2437 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2438 ) , .prog_clk_2_S_in ( prog_clk_3_wires[23] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3071 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2439 ) , .prog_clk_2_W_out ( prog_clk_2_wires[62] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3072 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3073 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3074 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3075 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3076 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3077 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3078 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3079 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3080 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3081 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3082 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3083 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3084 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3085 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3086 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3087 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2440 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2441 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , .prog_clk_3_W_in ( p2536 ) , + .prog_clk_3_E_in ( p918 ) , .prog_clk_3_S_in ( p1906 ) , + .prog_clk_3_N_in ( p748 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2442 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2443 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2444 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2445 ) , .clk_1_N_in ( p2732 ) , + .clk_1_S_in ( p358 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2446 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2447 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2448 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2449 ) , .clk_2_S_in ( clk_3_wires[23] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3088 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2450 ) , .clk_2_W_out ( clk_2_wires[62] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3089 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3090 ) , - .clk_2_E_out ( clk_2_wires[60] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3091 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3092 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3093 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3094 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3095 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3096 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3097 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3098 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2451 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2452 ) , + .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( p2536 ) , + .clk_3_E_in ( p116 ) , .clk_3_S_in ( p1005 ) , .clk_3_N_in ( p3355 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2453 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2454 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2455 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2456 ) ) ; sb_1__1_ sb_4__11_ ( .chany_top_in ( cby_1__1__47_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_47_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_47_right_width_0_height_0__pin_43_lower ) , @@ -62896,50 +66352,36 @@ sb_1__1_ sb_4__11_ ( .chany_top_in ( cby_1__1__47_chany_bottom_out ) , .chanx_right_out ( sb_1__1__43_chanx_right_out ) , .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) , .chanx_left_out ( sb_1__1__43_chanx_left_out ) , - .ccff_tail ( sb_1__1__43_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3099 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3100 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3101 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3102 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3103 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3104 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3105 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3106 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3107 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3108 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3109 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3110 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3111 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3112 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3113 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3114 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3115 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3116 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3117 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3118 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3119 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3120 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3121 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3122 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3123 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3124 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3125 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3126 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3127 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3128 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3129 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3130 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3131 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3132 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3133 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3134 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3135 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3136 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3137 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3138 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3139 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3140 ) ) ; + .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( p2729 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2457 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , .prog_clk_1_N_in ( p3102 ) , + .prog_clk_1_S_in ( p1115 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2459 ) , + .prog_clk_2_N_in ( p3144 ) , .prog_clk_2_E_in ( p1372 ) , + .prog_clk_2_S_in ( p592 ) , .prog_clk_2_W_in ( p311 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2460 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2461 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2462 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2463 ) , + .prog_clk_3_W_in ( p2426 ) , .prog_clk_3_E_in ( p661 ) , + .prog_clk_3_S_in ( p1459 ) , .prog_clk_3_N_in ( p3069 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2464 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2465 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2466 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2467 ) , .clk_1_N_in ( p2611 ) , + .clk_1_S_in ( p446 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2468 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2469 ) , .clk_2_N_in ( p3502 ) , + .clk_2_E_in ( p720 ) , .clk_2_S_in ( p2637 ) , .clk_2_W_in ( p2963 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2470 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2471 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2472 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2473 ) , .clk_3_W_in ( p3048 ) , + .clk_3_E_in ( p98 ) , .clk_3_S_in ( p228 ) , .clk_3_N_in ( p3495 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2474 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2475 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2476 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2477 ) ) ; sb_1__1_ sb_5__1_ ( .chany_top_in ( cby_1__1__49_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_49_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_49_right_width_0_height_0__pin_43_lower ) , @@ -62981,49 +66423,38 @@ sb_1__1_ sb_5__1_ ( .chany_top_in ( cby_1__1__49_chany_bottom_out ) , .chanx_right_out ( sb_1__1__44_chanx_right_out ) , .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) , .chanx_left_out ( sb_1__1__44_chanx_left_out ) , - .ccff_tail ( sb_1__1__44_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3141 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3142 ) , + .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( p1853 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2478 ) , .prog_clk_0_N_in ( prog_clk_0_wires[182] ) , .prog_clk_1_N_in ( prog_clk_2_wires[32] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3143 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2479 ) , .prog_clk_1_E_out ( prog_clk_1_wires[85] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3144 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3145 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3146 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3147 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3148 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3149 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3150 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3151 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3152 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3153 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3154 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3155 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3156 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3157 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3158 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3159 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , .prog_clk_2_N_in ( p3478 ) , + .prog_clk_2_E_in ( p1114 ) , .prog_clk_2_S_in ( p391 ) , + .prog_clk_2_W_in ( p1338 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2480 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2481 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2482 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2483 ) , + .prog_clk_3_W_in ( p2736 ) , .prog_clk_3_E_in ( p258 ) , + .prog_clk_3_S_in ( p663 ) , .prog_clk_3_N_in ( p3475 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2484 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2485 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2486 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2487 ) , .clk_1_N_in ( clk_2_wires[32] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3160 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2488 ) , .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3161 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3162 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3163 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3164 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3165 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3166 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3167 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3168 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3169 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3170 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3171 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3172 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3173 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3174 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3175 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3176 ) ) ; + .clk_2_N_in ( p3264 ) , .clk_2_E_in ( p590 ) , .clk_2_S_in ( p133 ) , + .clk_2_W_in ( p3410 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2489 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2490 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2491 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2492 ) , .clk_3_W_in ( p3426 ) , + .clk_3_E_in ( p858 ) , .clk_3_S_in ( p1218 ) , .clk_3_N_in ( p3263 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2493 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2494 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2495 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2496 ) ) ; sb_1__1_ sb_5__2_ ( .chany_top_in ( cby_1__1__50_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_50_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_50_right_width_0_height_0__pin_43_lower ) , @@ -63065,50 +66496,41 @@ sb_1__1_ sb_5__2_ ( .chany_top_in ( cby_1__1__50_chany_bottom_out ) , .chanx_right_out ( sb_1__1__45_chanx_right_out ) , .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) , .chanx_left_out ( sb_1__1__45_chanx_left_out ) , - .ccff_tail ( sb_1__1__45_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3177 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3178 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3179 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3180 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3181 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3182 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3183 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3184 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3185 ) , + .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( p2274 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2497 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , .prog_clk_1_N_in ( p3166 ) , + .prog_clk_1_S_in ( p41 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2498 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2499 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2500 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2501 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2502 ) , .prog_clk_2_W_in ( prog_clk_2_wires[26] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3186 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2503 ) , .prog_clk_2_S_out ( prog_clk_2_wires[31] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3187 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3188 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3189 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3190 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3191 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3192 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3193 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3194 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3195 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3196 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3197 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3198 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3199 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3200 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3201 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3202 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3203 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2504 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2505 ) , + .prog_clk_3_W_in ( p2134 ) , .prog_clk_3_E_in ( p238 ) , + .prog_clk_3_S_in ( p2194 ) , .prog_clk_3_N_in ( p1887 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2506 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2507 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2508 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2509 ) , .clk_1_N_in ( p2769 ) , + .clk_1_S_in ( p659 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2510 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2511 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2512 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2513 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2514 ) , .clk_2_W_in ( clk_2_wires[26] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3204 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2515 ) , .clk_2_S_out ( clk_2_wires[31] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3205 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3206 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3207 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3208 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3209 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3210 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3211 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3212 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3213 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3214 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2516 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2517 ) , .clk_3_W_in ( p2134 ) , + .clk_3_E_in ( p794 ) , .clk_3_S_in ( p561 ) , .clk_3_N_in ( p3192 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2519 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2520 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2521 ) ) ; sb_1__1_ sb_5__3_ ( .chany_top_in ( cby_1__1__51_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_51_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_51_right_width_0_height_0__pin_43_lower ) , @@ -63150,49 +66572,38 @@ sb_1__1_ sb_5__3_ ( .chany_top_in ( cby_1__1__51_chany_bottom_out ) , .chanx_right_out ( sb_1__1__46_chanx_right_out ) , .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) , .chanx_left_out ( sb_1__1__46_chanx_left_out ) , - .ccff_tail ( sb_1__1__46_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3215 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3216 ) , + .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( p2319 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2522 ) , .prog_clk_0_N_in ( prog_clk_0_wires[188] ) , .prog_clk_1_N_in ( prog_clk_2_wires[45] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3217 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2523 ) , .prog_clk_1_E_out ( prog_clk_1_wires[92] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3218 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3219 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3220 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3221 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3222 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3223 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3224 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3225 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3226 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3227 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3228 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3229 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3230 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3231 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3232 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3233 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , .prog_clk_2_N_in ( p3445 ) , + .prog_clk_2_E_in ( p1461 ) , .prog_clk_2_S_in ( p510 ) , + .prog_clk_2_W_in ( p399 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2524 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2525 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2526 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2527 ) , + .prog_clk_3_W_in ( p3015 ) , .prog_clk_3_E_in ( p239 ) , + .prog_clk_3_S_in ( p1234 ) , .prog_clk_3_N_in ( p3432 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2528 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2529 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2530 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2531 ) , .clk_1_N_in ( clk_2_wires[45] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3234 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2532 ) , .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3235 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3236 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3237 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3238 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3239 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3240 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3241 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3242 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3243 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3244 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3245 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3246 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3247 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3248 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3249 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3250 ) ) ; + .clk_2_N_in ( p2900 ) , .clk_2_E_in ( p715 ) , .clk_2_S_in ( p2196 ) , + .clk_2_W_in ( p3246 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2533 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2534 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2535 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2536 ) , .clk_3_W_in ( p3268 ) , + .clk_3_E_in ( p1089 ) , .clk_3_S_in ( p112 ) , .clk_3_N_in ( p2846 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2537 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2538 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2539 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2540 ) ) ; sb_1__1_ sb_5__4_ ( .chany_top_in ( cby_1__1__52_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_52_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_52_right_width_0_height_0__pin_43_lower ) , @@ -63234,49 +66645,40 @@ sb_1__1_ sb_5__4_ ( .chany_top_in ( cby_1__1__52_chany_bottom_out ) , .chanx_right_out ( sb_1__1__47_chanx_right_out ) , .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) , .chanx_left_out ( sb_1__1__47_chanx_left_out ) , - .ccff_tail ( sb_1__1__47_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3251 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3252 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3253 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3254 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3255 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3256 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3257 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3258 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3259 ) , + .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( p2371 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2541 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , .prog_clk_1_N_in ( p3280 ) , + .prog_clk_1_S_in ( p320 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2542 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2543 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2544 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2545 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2546 ) , .prog_clk_2_W_in ( prog_clk_2_wires[35] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3260 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2547 ) , .prog_clk_2_S_out ( prog_clk_2_wires[44] ) , .prog_clk_2_N_out ( prog_clk_2_wires[42] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3261 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3262 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3263 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3264 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3265 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3266 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3267 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3268 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3269 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3270 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3271 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3272 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3273 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3274 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3275 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3276 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2548 ) , + .prog_clk_3_W_in ( p2512 ) , .prog_clk_3_E_in ( p326 ) , + .prog_clk_3_S_in ( p2178 ) , .prog_clk_3_N_in ( p2819 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2549 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2550 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2551 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2552 ) , .clk_1_N_in ( p1300 ) , + .clk_1_S_in ( p361 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2553 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2554 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2555 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2556 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2557 ) , .clk_2_W_in ( clk_2_wires[35] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3277 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2558 ) , .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3278 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3279 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3280 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3281 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3282 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3283 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3284 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3285 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3286 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2559 ) , .clk_3_W_in ( p2512 ) , + .clk_3_E_in ( p1229 ) , .clk_3_S_in ( p8 ) , .clk_3_N_in ( p3257 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2560 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2561 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2562 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2563 ) ) ; sb_1__1_ sb_5__5_ ( .chany_top_in ( cby_1__1__53_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_53_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_53_right_width_0_height_0__pin_43_lower ) , @@ -63318,49 +66720,38 @@ sb_1__1_ sb_5__5_ ( .chany_top_in ( cby_1__1__53_chany_bottom_out ) , .chanx_right_out ( sb_1__1__48_chanx_right_out ) , .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) , .chanx_left_out ( sb_1__1__48_chanx_left_out ) , - .ccff_tail ( sb_1__1__48_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3287 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3288 ) , + .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( p2759 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2564 ) , .prog_clk_0_N_in ( prog_clk_0_wires[194] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3289 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2565 ) , .prog_clk_1_S_in ( prog_clk_2_wires[43] ) , .prog_clk_1_E_out ( prog_clk_1_wires[99] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3290 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3291 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3292 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3293 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3294 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3295 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3296 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3297 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3298 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3299 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3300 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3301 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3302 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3303 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3304 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3305 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3306 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , .prog_clk_2_N_in ( p2706 ) , + .prog_clk_2_E_in ( p607 ) , .prog_clk_2_S_in ( p965 ) , + .prog_clk_2_W_in ( p305 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2566 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2567 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2568 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2569 ) , + .prog_clk_3_W_in ( p3272 ) , .prog_clk_3_E_in ( p18 ) , + .prog_clk_3_S_in ( p984 ) , .prog_clk_3_N_in ( p2688 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2570 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2571 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2572 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2573 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2574 ) , .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) , - .clk_1_W_out ( clk_1_wires[100] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3307 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3308 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3309 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3310 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3311 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3312 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3313 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3315 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3316 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3317 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3318 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3319 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3320 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3321 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3322 ) ) ; + .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( p3466 ) , + .clk_2_E_in ( p1202 ) , .clk_2_S_in ( p2648 ) , .clk_2_W_in ( p3237 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2575 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2576 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2577 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2578 ) , .clk_3_W_in ( p2344 ) , + .clk_3_E_in ( p807 ) , .clk_3_S_in ( p232 ) , .clk_3_N_in ( p3460 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2579 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2580 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2581 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2582 ) ) ; sb_1__1_ sb_5__6_ ( .chany_top_in ( cby_1__1__54_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_54_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_54_right_width_0_height_0__pin_43_lower ) , @@ -63402,50 +66793,41 @@ sb_1__1_ sb_5__6_ ( .chany_top_in ( cby_1__1__54_chany_bottom_out ) , .chanx_right_out ( sb_1__1__49_chanx_right_out ) , .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) , .chanx_left_out ( sb_1__1__49_chanx_left_out ) , - .ccff_tail ( sb_1__1__49_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3323 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3324 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3325 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3326 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3327 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3328 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3329 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3330 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3331 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3332 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3333 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3334 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3335 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3336 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3337 ) , + .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( p2880 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2583 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , .prog_clk_1_N_in ( p1690 ) , + .prog_clk_1_S_in ( p511 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2584 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2585 ) , + .prog_clk_2_N_in ( p1690 ) , .prog_clk_2_E_in ( p584 ) , + .prog_clk_2_S_in ( p1109 ) , .prog_clk_2_W_in ( p913 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2586 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2587 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2588 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2589 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2590 ) , .prog_clk_3_E_in ( prog_clk_3_wires[3] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3338 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3339 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3340 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2591 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2592 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2593 ) , .prog_clk_3_W_out ( prog_clk_3_wires[6] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3341 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3342 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3343 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3344 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3345 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3346 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3347 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3348 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3349 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3350 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3351 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3352 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3353 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3354 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3355 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2594 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2595 ) , .clk_1_N_in ( p1690 ) , + .clk_1_S_in ( p846 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2596 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2597 ) , .clk_2_N_in ( p1690 ) , + .clk_2_E_in ( p1127 ) , .clk_2_S_in ( p2799 ) , .clk_2_W_in ( p416 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2598 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2599 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2600 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2601 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2602 ) , .clk_3_E_in ( clk_3_wires[3] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3356 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3357 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3358 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2603 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2604 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2605 ) , .clk_3_W_out ( clk_3_wires[6] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3359 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3360 ) ) ; + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2606 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2607 ) ) ; sb_1__1_ sb_5__7_ ( .chany_top_in ( cby_1__1__55_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_55_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_55_right_width_0_height_0__pin_43_lower ) , @@ -63487,49 +66869,38 @@ sb_1__1_ sb_5__7_ ( .chany_top_in ( cby_1__1__55_chany_bottom_out ) , .chanx_right_out ( sb_1__1__50_chanx_right_out ) , .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) , .chanx_left_out ( sb_1__1__50_chanx_left_out ) , - .ccff_tail ( sb_1__1__50_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3361 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3362 ) , + .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( p2548 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2608 ) , .prog_clk_0_N_in ( prog_clk_0_wires[200] ) , .prog_clk_1_N_in ( prog_clk_2_wires[58] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3363 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2609 ) , .prog_clk_1_E_out ( prog_clk_1_wires[106] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3364 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3365 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3366 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3367 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3368 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3369 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3370 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3371 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3372 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3373 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3374 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3375 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3376 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3377 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3378 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3379 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , .prog_clk_2_N_in ( p3484 ) , + .prog_clk_2_E_in ( p1287 ) , .prog_clk_2_S_in ( p178 ) , + .prog_clk_2_W_in ( p336 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2610 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2611 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2612 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2613 ) , + .prog_clk_3_W_in ( p3296 ) , .prog_clk_3_E_in ( p925 ) , + .prog_clk_3_S_in ( p719 ) , .prog_clk_3_N_in ( p3476 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2614 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2615 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2616 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2617 ) , .clk_1_N_in ( clk_2_wires[58] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3380 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2618 ) , .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3381 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3382 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3383 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3384 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3385 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3386 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3387 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3388 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3389 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3390 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3391 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3392 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3393 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3394 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3395 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3396 ) ) ; + .clk_2_N_in ( p3447 ) , .clk_2_E_in ( p44 ) , .clk_2_S_in ( p2471 ) , + .clk_2_W_in ( p3247 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2619 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2620 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2621 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2622 ) , .clk_3_W_in ( p2735 ) , + .clk_3_E_in ( p595 ) , .clk_3_S_in ( p1100 ) , .clk_3_N_in ( p3435 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2623 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2624 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2625 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2626 ) ) ; sb_1__1_ sb_5__8_ ( .chany_top_in ( cby_1__1__56_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_56_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_56_right_width_0_height_0__pin_43_lower ) , @@ -63571,49 +66942,40 @@ sb_1__1_ sb_5__8_ ( .chany_top_in ( cby_1__1__56_chany_bottom_out ) , .chanx_right_out ( sb_1__1__51_chanx_right_out ) , .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) , .chanx_left_out ( sb_1__1__51_chanx_left_out ) , - .ccff_tail ( sb_1__1__51_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3397 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3398 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3399 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3400 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3401 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3402 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3403 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3404 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3405 ) , + .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( p2409 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2627 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , .prog_clk_1_N_in ( p3441 ) , + .prog_clk_1_S_in ( p458 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2628 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2629 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2630 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2631 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2632 ) , .prog_clk_2_W_in ( prog_clk_2_wires[48] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3406 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2633 ) , .prog_clk_2_S_out ( prog_clk_2_wires[57] ) , .prog_clk_2_N_out ( prog_clk_2_wires[55] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3407 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3408 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3409 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3410 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3411 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3412 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3413 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3414 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3415 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3416 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3417 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3418 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3419 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3420 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3421 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3422 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2634 ) , + .prog_clk_3_W_in ( p2355 ) , .prog_clk_3_E_in ( p376 ) , + .prog_clk_3_S_in ( p2186 ) , .prog_clk_3_N_in ( p80 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2635 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2636 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2637 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2638 ) , .clk_1_N_in ( p2036 ) , + .clk_1_S_in ( p851 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2639 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2640 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2641 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2642 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2643 ) , .clk_2_W_in ( clk_2_wires[48] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3423 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2644 ) , .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3424 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3425 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3426 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3427 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3428 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3429 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3430 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3431 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3432 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2645 ) , .clk_3_W_in ( p2355 ) , + .clk_3_E_in ( p977 ) , .clk_3_S_in ( p284 ) , .clk_3_N_in ( p3436 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2646 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2647 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2648 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2649 ) ) ; sb_1__1_ sb_5__9_ ( .chany_top_in ( cby_1__1__57_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_57_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_57_right_width_0_height_0__pin_43_lower ) , @@ -63655,49 +67017,38 @@ sb_1__1_ sb_5__9_ ( .chany_top_in ( cby_1__1__57_chany_bottom_out ) , .chanx_right_out ( sb_1__1__52_chanx_right_out ) , .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) , .chanx_left_out ( sb_1__1__52_chanx_left_out ) , - .ccff_tail ( sb_1__1__52_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3433 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3434 ) , + .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( p1803 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2650 ) , .prog_clk_0_N_in ( prog_clk_0_wires[206] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3435 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2651 ) , .prog_clk_1_S_in ( prog_clk_2_wires[56] ) , .prog_clk_1_E_out ( prog_clk_1_wires[113] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3436 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3437 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3438 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3439 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3440 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3441 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3442 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3443 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3444 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3445 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3446 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3447 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3448 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3449 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3450 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3451 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3452 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , .prog_clk_2_N_in ( p3275 ) , + .prog_clk_2_E_in ( p1084 ) , .prog_clk_2_S_in ( p331 ) , + .prog_clk_2_W_in ( p1957 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2652 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2653 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2654 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2655 ) , + .prog_clk_3_W_in ( p2935 ) , .prog_clk_3_E_in ( p723 ) , + .prog_clk_3_S_in ( p205 ) , .prog_clk_3_N_in ( p3238 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2656 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2657 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2658 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2659 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2660 ) , .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) , - .clk_1_W_out ( clk_1_wires[114] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3453 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3454 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3455 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3456 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3457 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3458 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3459 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3460 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3461 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3462 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3463 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3464 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3465 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3466 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3467 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3468 ) ) ; + .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( p2500 ) , + .clk_2_E_in ( p839 ) , .clk_2_S_in ( p872 ) , .clk_2_W_in ( p2976 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2661 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2662 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2663 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2664 ) , .clk_3_W_in ( p3038 ) , + .clk_3_E_in ( p100 ) , .clk_3_S_in ( p967 ) , .clk_3_N_in ( p2467 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2665 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2666 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2667 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2668 ) ) ; sb_1__1_ sb_5__10_ ( .chany_top_in ( cby_1__1__58_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_58_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_58_right_width_0_height_0__pin_43_lower ) , @@ -63739,50 +67090,41 @@ sb_1__1_ sb_5__10_ ( .chany_top_in ( cby_1__1__58_chany_bottom_out ) , .chanx_right_out ( sb_1__1__53_chanx_right_out ) , .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) , .chanx_left_out ( sb_1__1__53_chanx_left_out ) , - .ccff_tail ( sb_1__1__53_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3469 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3470 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3471 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3472 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3473 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3474 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3475 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3476 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3477 ) , + .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( p1667 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2669 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , .prog_clk_1_N_in ( p3342 ) , + .prog_clk_1_S_in ( p325 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2670 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2671 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2672 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2673 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2674 ) , .prog_clk_2_W_in ( prog_clk_2_wires[61] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3478 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3479 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2675 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2676 ) , .prog_clk_2_N_out ( prog_clk_2_wires[66] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3480 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3481 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3482 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3483 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3484 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3485 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3486 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3487 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3488 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3489 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3490 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3491 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3492 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3493 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3494 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3495 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2677 ) , + .prog_clk_3_W_in ( p2375 ) , .prog_clk_3_E_in ( p1212 ) , + .prog_clk_3_S_in ( p1294 ) , .prog_clk_3_N_in ( p2220 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2678 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2679 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2680 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2681 ) , .clk_1_N_in ( p2785 ) , + .clk_1_S_in ( p230 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2682 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2683 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2684 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2685 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2686 ) , .clk_2_W_in ( clk_2_wires[61] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3496 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3497 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2687 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2688 ) , .clk_2_N_out ( clk_2_wires[66] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3499 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3500 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3501 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3502 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3503 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3504 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3505 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3506 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2689 ) , .clk_3_W_in ( p2375 ) , + .clk_3_E_in ( p244 ) , .clk_3_S_in ( p515 ) , .clk_3_N_in ( p3315 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2690 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2691 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2692 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2693 ) ) ; sb_1__1_ sb_5__11_ ( .chany_top_in ( cby_1__1__59_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_59_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_59_right_width_0_height_0__pin_43_lower ) , @@ -63824,49 +67166,38 @@ sb_1__1_ sb_5__11_ ( .chany_top_in ( cby_1__1__59_chany_bottom_out ) , .chanx_right_out ( sb_1__1__54_chanx_right_out ) , .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) , .chanx_left_out ( sb_1__1__54_chanx_left_out ) , - .ccff_tail ( sb_1__1__54_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3507 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3508 ) , + .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( p1783 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2694 ) , .prog_clk_0_N_in ( prog_clk_0_wires[212] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3509 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2695 ) , .prog_clk_1_S_in ( prog_clk_2_wires[67] ) , .prog_clk_1_E_out ( prog_clk_1_wires[120] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3510 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3511 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3512 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3513 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3514 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3515 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3516 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3517 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3518 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3519 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3520 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3521 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3522 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3523 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3524 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3525 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3526 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , .prog_clk_2_N_in ( p2372 ) , + .prog_clk_2_E_in ( p1204 ) , .prog_clk_2_S_in ( p734 ) , + .prog_clk_2_W_in ( p1144 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2696 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2697 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2698 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2699 ) , + .prog_clk_3_W_in ( p3380 ) , .prog_clk_3_E_in ( p1037 ) , + .prog_clk_3_S_in ( p390 ) , .prog_clk_3_N_in ( p2230 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2700 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2701 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2702 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2703 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2704 ) , .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) , - .clk_1_W_out ( clk_1_wires[121] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3527 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3528 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3529 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3530 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3531 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3532 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3533 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3534 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3535 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3536 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3537 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3538 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3539 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3540 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3541 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3542 ) ) ; + .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( p3329 ) , + .clk_2_E_in ( p571 ) , .clk_2_S_in ( p426 ) , .clk_2_W_in ( p3368 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2705 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2706 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2707 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2708 ) , .clk_3_W_in ( p2896 ) , + .clk_3_E_in ( p255 ) , .clk_3_S_in ( p1067 ) , .clk_3_N_in ( p3322 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2709 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2710 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2711 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2712 ) ) ; sb_1__1_ sb_6__1_ ( .chany_top_in ( cby_1__1__61_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_61_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_61_right_width_0_height_0__pin_43_lower ) , @@ -63910,47 +67241,39 @@ sb_1__1_ sb_6__1_ ( .chany_top_in ( cby_1__1__61_chany_bottom_out ) , .chanx_left_out ( sb_1__1__55_chanx_left_out ) , .ccff_tail ( sb_1__1__55_ccff_tail ) , .Test_en_S_in ( Test_enWires[2] ) , .Test_en_N_out ( Test_enWires[3] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3543 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3544 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3545 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3546 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3547 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3548 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3549 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3550 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3551 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3552 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3553 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3554 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3555 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3556 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , .prog_clk_1_N_in ( p1245 ) , + .prog_clk_1_S_in ( p282 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2713 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2714 ) , + .prog_clk_2_N_in ( p1245 ) , .prog_clk_2_E_in ( p226 ) , + .prog_clk_2_S_in ( p1937 ) , .prog_clk_2_W_in ( p614 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2715 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2716 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2717 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2718 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2719 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2720 ) , .prog_clk_3_S_in ( prog_clk_3_wires[89] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3557 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3558 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3559 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2721 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2722 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2723 ) , .prog_clk_3_N_out ( prog_clk_3_wires[92] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3560 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3561 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3562 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3563 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3564 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3565 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3566 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3567 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3568 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3569 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3570 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3571 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3572 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3573 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3574 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2724 ) , .clk_1_N_in ( p1245 ) , + .clk_1_S_in ( p1155 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2725 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2726 ) , .clk_2_N_in ( p1245 ) , + .clk_2_E_in ( p680 ) , .clk_2_S_in ( p1302 ) , .clk_2_W_in ( p285 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2727 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2728 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2729 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2730 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2731 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2732 ) , .clk_3_S_in ( clk_3_wires[89] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3575 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3576 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3577 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2733 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2735 ) , .clk_3_N_out ( clk_3_wires[92] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3578 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2736 ) ) ; sb_1__1_ sb_6__2_ ( .chany_top_in ( cby_1__1__62_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_62_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_62_right_width_0_height_0__pin_43_lower ) , @@ -63994,47 +67317,39 @@ sb_1__1_ sb_6__2_ ( .chany_top_in ( cby_1__1__62_chany_bottom_out ) , .chanx_left_out ( sb_1__1__56_chanx_left_out ) , .ccff_tail ( sb_1__1__56_ccff_tail ) , .Test_en_S_in ( Test_enWires[4] ) , .Test_en_N_out ( Test_enWires[5] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3579 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3580 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3581 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3582 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3583 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3584 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3585 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3586 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3587 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3588 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3589 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3590 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3591 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3592 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , .prog_clk_1_N_in ( p1636 ) , + .prog_clk_1_S_in ( p172 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2737 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2738 ) , + .prog_clk_2_N_in ( p1636 ) , .prog_clk_2_E_in ( p1321 ) , + .prog_clk_2_S_in ( p1940 ) , .prog_clk_2_W_in ( p195 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2739 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2740 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2741 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2742 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2743 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2744 ) , .prog_clk_3_S_in ( prog_clk_3_wires[91] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3593 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3594 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3595 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2745 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2746 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2747 ) , .prog_clk_3_N_out ( prog_clk_3_wires[94] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3596 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3597 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3598 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3599 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3600 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3601 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3602 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3603 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3604 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3605 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3606 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3607 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3608 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3609 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3610 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2748 ) , .clk_1_N_in ( p1636 ) , + .clk_1_S_in ( p744 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2749 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2750 ) , .clk_2_N_in ( p1636 ) , + .clk_2_E_in ( p527 ) , .clk_2_S_in ( p505 ) , .clk_2_W_in ( p444 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2751 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2752 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2753 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2754 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2755 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2756 ) , .clk_3_S_in ( clk_3_wires[91] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3611 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3612 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3613 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2757 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2758 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2759 ) , .clk_3_N_out ( clk_3_wires[94] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3614 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2760 ) ) ; sb_1__1_ sb_6__3_ ( .chany_top_in ( cby_1__1__63_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_63_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_63_right_width_0_height_0__pin_43_lower ) , @@ -64078,47 +67393,39 @@ sb_1__1_ sb_6__3_ ( .chany_top_in ( cby_1__1__63_chany_bottom_out ) , .chanx_left_out ( sb_1__1__57_chanx_left_out ) , .ccff_tail ( sb_1__1__57_ccff_tail ) , .Test_en_S_in ( Test_enWires[6] ) , .Test_en_N_out ( Test_enWires[7] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3615 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3616 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3617 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3618 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3619 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3620 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3621 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3622 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3623 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3624 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3625 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3626 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3627 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3628 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , .prog_clk_1_N_in ( p1819 ) , + .prog_clk_1_S_in ( p605 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2761 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2762 ) , + .prog_clk_2_N_in ( p1819 ) , .prog_clk_2_E_in ( p431 ) , + .prog_clk_2_S_in ( p1323 ) , .prog_clk_2_W_in ( p57 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2763 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2764 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2765 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2766 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2767 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2768 ) , .prog_clk_3_S_in ( prog_clk_3_wires[93] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3629 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3630 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3631 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2769 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2770 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2771 ) , .prog_clk_3_N_out ( prog_clk_3_wires[96] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3632 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3633 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3634 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3635 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3636 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3637 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3638 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3639 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3640 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3641 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3642 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3643 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3644 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3645 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3646 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2772 ) , .clk_1_N_in ( p1819 ) , + .clk_1_S_in ( p643 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2773 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2774 ) , .clk_2_N_in ( p1819 ) , + .clk_2_E_in ( p1297 ) , .clk_2_S_in ( p219 ) , .clk_2_W_in ( p1200 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2775 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2776 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2777 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2778 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2779 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2780 ) , .clk_3_S_in ( clk_3_wires[93] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3647 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3648 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3649 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2781 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2782 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2783 ) , .clk_3_N_out ( clk_3_wires[96] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3650 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2784 ) ) ; sb_1__1_ sb_6__4_ ( .chany_top_in ( cby_1__1__64_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_64_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_64_right_width_0_height_0__pin_43_lower ) , @@ -64162,47 +67469,39 @@ sb_1__1_ sb_6__4_ ( .chany_top_in ( cby_1__1__64_chany_bottom_out ) , .chanx_left_out ( sb_1__1__58_chanx_left_out ) , .ccff_tail ( sb_1__1__58_ccff_tail ) , .Test_en_S_in ( Test_enWires[8] ) , .Test_en_N_out ( Test_enWires[9] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3651 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3652 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3653 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3654 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3655 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3656 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3657 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3658 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3659 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3660 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3661 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3662 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3663 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3664 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , .prog_clk_1_N_in ( p1436 ) , + .prog_clk_1_S_in ( p784 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2785 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2786 ) , + .prog_clk_2_N_in ( p1436 ) , .prog_clk_2_E_in ( p97 ) , + .prog_clk_2_S_in ( p2198 ) , .prog_clk_2_W_in ( p149 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2787 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2788 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2789 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2790 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2791 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2792 ) , .prog_clk_3_S_in ( prog_clk_3_wires[95] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3665 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3666 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3667 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2793 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2794 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2795 ) , .prog_clk_3_N_out ( prog_clk_3_wires[98] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3669 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3670 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3671 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3672 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3673 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3674 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3675 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3676 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3677 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3678 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3679 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3680 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3681 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3682 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2796 ) , .clk_1_N_in ( p1436 ) , + .clk_1_S_in ( p654 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2797 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2798 ) , .clk_2_N_in ( p1436 ) , + .clk_2_E_in ( p1276 ) , .clk_2_S_in ( p1111 ) , .clk_2_W_in ( p1320 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2799 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2800 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2801 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2802 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2803 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2804 ) , .clk_3_S_in ( clk_3_wires[95] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3683 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3684 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3685 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2805 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2806 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2807 ) , .clk_3_N_out ( clk_3_wires[98] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3686 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2808 ) ) ; sb_1__1_ sb_6__5_ ( .chany_top_in ( cby_1__1__65_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_65_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_65_right_width_0_height_0__pin_43_lower ) , @@ -64246,47 +67545,39 @@ sb_1__1_ sb_6__5_ ( .chany_top_in ( cby_1__1__65_chany_bottom_out ) , .chanx_left_out ( sb_1__1__59_chanx_left_out ) , .ccff_tail ( sb_1__1__59_ccff_tail ) , .Test_en_S_in ( Test_enWires[10] ) , .Test_en_N_out ( Test_enWires[11] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3687 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3688 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3689 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3690 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3691 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3692 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3693 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3694 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3695 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3696 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3697 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3698 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3699 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3700 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , .prog_clk_1_N_in ( p2011 ) , + .prog_clk_1_S_in ( p776 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2809 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2810 ) , + .prog_clk_2_N_in ( p2011 ) , .prog_clk_2_E_in ( p278 ) , + .prog_clk_2_S_in ( p2219 ) , .prog_clk_2_W_in ( p889 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2811 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2812 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2813 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2814 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2815 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2816 ) , .prog_clk_3_S_in ( prog_clk_3_wires[97] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3701 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3702 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3703 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2817 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2818 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2819 ) , .prog_clk_3_N_out ( prog_clk_3_wires[100] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3704 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3705 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3706 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3707 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3708 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3709 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3710 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3711 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3712 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3713 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3714 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3715 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3716 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3717 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3718 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2820 ) , .clk_1_N_in ( p2011 ) , + .clk_1_S_in ( p28 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2821 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2822 ) , .clk_2_N_in ( p2011 ) , + .clk_2_E_in ( p782 ) , .clk_2_S_in ( p1196 ) , .clk_2_W_in ( p335 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2823 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2824 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2825 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2826 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2827 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2828 ) , .clk_3_S_in ( clk_3_wires[97] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3719 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3720 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3721 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2829 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2830 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2831 ) , .clk_3_N_out ( clk_3_wires[100] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3722 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2832 ) ) ; sb_1__1_ sb_6__6_ ( .chany_top_in ( cby_1__1__66_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_66_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_66_right_width_0_height_0__pin_43_lower ) , @@ -64330,46 +67621,38 @@ sb_1__1_ sb_6__6_ ( .chany_top_in ( cby_1__1__66_chany_bottom_out ) , .chanx_left_out ( sb_1__1__60_chanx_left_out ) , .ccff_tail ( sb_1__1__60_ccff_tail ) , .Test_en_S_in ( Test_enWires[12] ) , .Test_en_N_out ( Test_enWires[13] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3723 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3724 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3725 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3726 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3727 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3728 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3729 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3730 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3731 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3732 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3733 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3734 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3735 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3736 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , .prog_clk_1_N_in ( p1748 ) , + .prog_clk_1_S_in ( p618 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2833 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2834 ) , + .prog_clk_2_N_in ( p1617 ) , .prog_clk_2_E_in ( p215 ) , + .prog_clk_2_S_in ( p1897 ) , .prog_clk_2_W_in ( p2176 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2835 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2836 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2837 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2839 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2840 ) , .prog_clk_3_S_in ( prog_clk_3_wires[99] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3737 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2841 ) , .prog_clk_3_E_out ( prog_clk_3_wires[0] ) , .prog_clk_3_W_out ( prog_clk_3_wires[2] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3738 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3739 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3740 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3741 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3742 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3743 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3744 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3745 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3746 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3747 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3748 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3749 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3750 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3751 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3752 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3753 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2842 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2843 ) , .clk_1_N_in ( p1748 ) , + .clk_1_S_in ( p822 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2844 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2845 ) , .clk_2_N_in ( p1748 ) , + .clk_2_E_in ( p482 ) , .clk_2_S_in ( p321 ) , .clk_2_W_in ( p677 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2846 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2847 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2848 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2849 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2850 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2851 ) , .clk_3_S_in ( clk_3_wires[99] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3754 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2852 ) , .clk_3_E_out ( clk_3_wires[0] ) , .clk_3_W_out ( clk_3_wires[2] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3755 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3756 ) ) ; + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2853 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2854 ) ) ; sb_1__1_ sb_6__7_ ( .chany_top_in ( cby_1__1__67_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_67_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_67_right_width_0_height_0__pin_43_lower ) , @@ -64413,47 +67696,34 @@ sb_1__1_ sb_6__7_ ( .chany_top_in ( cby_1__1__67_chany_bottom_out ) , .chanx_left_out ( sb_1__1__61_chanx_left_out ) , .ccff_tail ( sb_1__1__61_ccff_tail ) , .Test_en_S_in ( Test_enWires[14] ) , .Test_en_N_out ( Test_enWires[15] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3757 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3758 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3759 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3760 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3761 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3762 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3763 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3764 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3765 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3766 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3767 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3768 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3769 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3770 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3771 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3772 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3773 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3774 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3775 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3776 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3777 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3778 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3779 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3780 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3781 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3782 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3783 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3784 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3785 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3786 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3787 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3788 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3789 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3790 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3791 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3792 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3793 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3794 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3795 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3796 ) ) ; + .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , .prog_clk_1_N_in ( p3278 ) , + .prog_clk_1_S_in ( p453 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2855 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2856 ) , + .prog_clk_2_N_in ( p3412 ) , .prog_clk_2_E_in ( p1194 ) , + .prog_clk_2_S_in ( p808 ) , .prog_clk_2_W_in ( p735 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2857 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2858 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2859 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2860 ) , + .prog_clk_3_W_in ( p3106 ) , .prog_clk_3_E_in ( p543 ) , + .prog_clk_3_S_in ( p1199 ) , .prog_clk_3_N_in ( p3399 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2861 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2862 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2863 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2864 ) , .clk_1_N_in ( p2367 ) , + .clk_1_S_in ( p396 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2865 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2866 ) , .clk_2_N_in ( p3515 ) , + .clk_2_E_in ( p99 ) , .clk_2_S_in ( p504 ) , .clk_2_W_in ( p3085 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2867 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2868 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2869 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2870 ) , .clk_3_W_in ( p3146 ) , + .clk_3_E_in ( p1120 ) , .clk_3_S_in ( p452 ) , .clk_3_N_in ( p3513 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2871 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2872 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2873 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2874 ) ) ; sb_1__1_ sb_6__8_ ( .chany_top_in ( cby_1__1__68_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_68_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_68_right_width_0_height_0__pin_43_lower ) , @@ -64497,47 +67767,34 @@ sb_1__1_ sb_6__8_ ( .chany_top_in ( cby_1__1__68_chany_bottom_out ) , .chanx_left_out ( sb_1__1__62_chanx_left_out ) , .ccff_tail ( sb_1__1__62_ccff_tail ) , .Test_en_S_in ( Test_enWires[16] ) , .Test_en_N_out ( Test_enWires[17] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3797 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3798 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3799 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3800 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3801 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3802 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3803 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3804 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3805 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3806 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3807 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3808 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3809 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3810 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3811 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3812 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3813 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3814 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3815 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3816 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3817 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3818 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3819 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3820 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3821 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3822 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3823 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3824 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3825 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3826 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3827 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3828 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3829 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3830 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3831 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3832 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3833 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3834 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3835 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3836 ) ) ; + .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , .prog_clk_1_N_in ( p3413 ) , + .prog_clk_1_S_in ( p871 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2875 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2876 ) , + .prog_clk_2_N_in ( p2410 ) , .prog_clk_2_E_in ( p624 ) , + .prog_clk_2_S_in ( p465 ) , .prog_clk_2_W_in ( p1979 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2877 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2878 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2879 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2880 ) , + .prog_clk_3_W_in ( p3006 ) , .prog_clk_3_E_in ( p1250 ) , + .prog_clk_3_S_in ( p1307 ) , .prog_clk_3_N_in ( p2221 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2881 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2882 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2883 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2884 ) , .clk_1_N_in ( p2860 ) , + .clk_1_S_in ( p281 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2885 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2886 ) , .clk_2_N_in ( p3507 ) , + .clk_2_E_in ( p892 ) , .clk_2_S_in ( p888 ) , .clk_2_W_in ( p2962 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2887 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2888 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2889 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , .clk_3_W_in ( p2761 ) , + .clk_3_E_in ( p117 ) , .clk_3_S_in ( p9 ) , .clk_3_N_in ( p3503 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2891 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2892 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2893 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2894 ) ) ; sb_1__1_ sb_6__9_ ( .chany_top_in ( cby_1__1__69_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_69_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_69_right_width_0_height_0__pin_43_lower ) , @@ -64581,47 +67838,34 @@ sb_1__1_ sb_6__9_ ( .chany_top_in ( cby_1__1__69_chany_bottom_out ) , .chanx_left_out ( sb_1__1__63_chanx_left_out ) , .ccff_tail ( sb_1__1__63_ccff_tail ) , .Test_en_S_in ( Test_enWires[18] ) , .Test_en_N_out ( Test_enWires[19] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3837 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3838 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3839 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3840 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3841 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3842 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3843 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3844 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3845 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3846 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3847 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3848 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3849 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3850 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3851 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3852 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3853 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3854 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3855 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3856 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3857 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3858 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3859 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3860 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3861 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3862 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3863 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3864 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3865 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3866 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3867 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3868 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3869 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3870 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3871 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3872 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3873 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3875 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3876 ) ) ; + .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , .prog_clk_1_N_in ( p2564 ) , + .prog_clk_1_S_in ( p486 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2895 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2896 ) , + .prog_clk_2_N_in ( p3337 ) , .prog_clk_2_E_in ( p790 ) , + .prog_clk_2_S_in ( p189 ) , .prog_clk_2_W_in ( p266 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2897 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2898 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2899 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2900 ) , + .prog_clk_3_W_in ( p3148 ) , .prog_clk_3_E_in ( p954 ) , + .prog_clk_3_S_in ( p610 ) , .prog_clk_3_N_in ( p3318 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2901 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2902 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2903 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2904 ) , .clk_1_N_in ( p2385 ) , + .clk_1_S_in ( p1015 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2905 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2906 ) , .clk_2_N_in ( p3141 ) , + .clk_2_E_in ( p697 ) , .clk_2_S_in ( p1160 ) , .clk_2_W_in ( p3066 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2907 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2908 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2909 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2910 ) , .clk_3_W_in ( p3049 ) , + .clk_3_E_in ( p241 ) , .clk_3_S_in ( p983 ) , .clk_3_N_in ( p3088 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2911 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2912 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2913 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2914 ) ) ; sb_1__1_ sb_6__10_ ( .chany_top_in ( cby_1__1__70_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_70_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_70_right_width_0_height_0__pin_43_lower ) , @@ -64665,47 +67909,34 @@ sb_1__1_ sb_6__10_ ( .chany_top_in ( cby_1__1__70_chany_bottom_out ) , .chanx_left_out ( sb_1__1__64_chanx_left_out ) , .ccff_tail ( sb_1__1__64_ccff_tail ) , .Test_en_S_in ( Test_enWires[20] ) , .Test_en_N_out ( Test_enWires[21] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3877 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3878 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3879 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3880 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3881 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3882 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3883 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3884 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3885 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3886 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3887 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3888 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3889 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3890 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3891 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3892 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3893 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3894 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3895 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3896 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3897 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3898 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3899 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3900 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3901 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3902 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3903 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3904 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3905 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3906 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3907 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3908 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3909 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3910 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3911 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3912 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3913 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3914 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3915 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3916 ) ) ; + .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , .prog_clk_1_N_in ( p3142 ) , + .prog_clk_1_S_in ( p1105 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2915 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2916 ) , + .prog_clk_2_N_in ( p2278 ) , .prog_clk_2_E_in ( p957 ) , + .prog_clk_2_S_in ( p1131 ) , .prog_clk_2_W_in ( p1904 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2917 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2918 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2919 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2920 ) , + .prog_clk_3_W_in ( p3423 ) , .prog_clk_3_E_in ( p811 ) , + .prog_clk_3_S_in ( p435 ) , .prog_clk_3_N_in ( p2206 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2921 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2922 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2923 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2924 ) , .clk_1_N_in ( p2051 ) , + .clk_1_S_in ( p455 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2925 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2926 ) , .clk_2_N_in ( p3499 ) , + .clk_2_E_in ( p879 ) , .clk_2_S_in ( p141 ) , .clk_2_W_in ( p3407 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2927 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2928 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2929 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2930 ) , .clk_3_W_in ( p3214 ) , + .clk_3_E_in ( p94 ) , .clk_3_S_in ( p848 ) , .clk_3_N_in ( p3497 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2931 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2932 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2933 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2934 ) ) ; sb_1__1_ sb_6__11_ ( .chany_top_in ( cby_1__1__71_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_71_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_71_right_width_0_height_0__pin_43_lower ) , @@ -64749,47 +67980,34 @@ sb_1__1_ sb_6__11_ ( .chany_top_in ( cby_1__1__71_chany_bottom_out ) , .chanx_left_out ( sb_1__1__65_chanx_left_out ) , .ccff_tail ( sb_1__1__65_ccff_tail ) , .Test_en_S_in ( Test_enWires[22] ) , .Test_en_N_out ( Test_enWires[23] ) , - .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3917 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3918 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3919 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3920 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3921 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3922 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3923 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3924 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3925 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3926 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3927 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3928 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3929 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3930 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3931 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3932 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3933 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3934 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3935 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3936 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3937 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3938 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3939 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3940 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3941 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3942 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3943 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3944 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3945 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3946 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3947 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3948 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3949 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3950 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3951 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3952 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3953 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3954 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3955 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3956 ) ) ; + .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , .prog_clk_1_N_in ( p2567 ) , + .prog_clk_1_S_in ( p854 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2935 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2936 ) , + .prog_clk_2_N_in ( p3205 ) , .prog_clk_2_E_in ( p1055 ) , + .prog_clk_2_S_in ( p216 ) , .prog_clk_2_W_in ( p1977 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2937 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2938 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2939 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2940 ) , + .prog_clk_3_W_in ( p3222 ) , .prog_clk_3_E_in ( p937 ) , + .prog_clk_3_S_in ( p89 ) , .prog_clk_3_N_in ( p3172 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2941 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2942 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2943 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2944 ) , .clk_1_N_in ( p2339 ) , + .clk_1_S_in ( p309 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2945 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2946 ) , .clk_2_N_in ( p3446 ) , + .clk_2_E_in ( p199 ) , .clk_2_S_in ( p963 ) , .clk_2_W_in ( p3167 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2947 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2948 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2949 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2950 ) , .clk_3_W_in ( p2997 ) , + .clk_3_E_in ( p495 ) , .clk_3_S_in ( p1383 ) , .clk_3_N_in ( p3433 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2951 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2952 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2953 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2954 ) ) ; sb_1__1_ sb_7__1_ ( .chany_top_in ( cby_1__1__73_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_73_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_73_right_width_0_height_0__pin_43_lower ) , @@ -64831,49 +68049,38 @@ sb_1__1_ sb_7__1_ ( .chany_top_in ( cby_1__1__73_chany_bottom_out ) , .chanx_right_out ( sb_1__1__66_chanx_right_out ) , .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) , .chanx_left_out ( sb_1__1__66_chanx_left_out ) , - .ccff_tail ( sb_1__1__66_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3957 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3958 ) , + .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( p2772 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2955 ) , .prog_clk_0_N_in ( prog_clk_0_wires[258] ) , .prog_clk_1_N_in ( prog_clk_2_wires[74] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3959 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2956 ) , .prog_clk_1_E_out ( prog_clk_1_wires[127] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3960 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3961 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3962 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3963 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3964 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3965 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3966 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3967 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3968 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3969 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3970 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3971 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3972 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3973 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3974 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3975 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , .prog_clk_2_N_in ( p3516 ) , + .prog_clk_2_E_in ( p573 ) , .prog_clk_2_S_in ( p2 ) , + .prog_clk_2_W_in ( p429 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2957 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2958 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2959 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2960 ) , + .prog_clk_3_W_in ( p2933 ) , .prog_clk_3_E_in ( p732 ) , + .prog_clk_3_S_in ( p1309 ) , .prog_clk_3_N_in ( p3514 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2961 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2962 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2963 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2964 ) , .clk_1_N_in ( clk_2_wires[74] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3976 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2965 ) , .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3977 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3978 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3979 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3980 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3981 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3982 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3983 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3984 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3985 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3986 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3987 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3988 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3989 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3990 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3991 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3992 ) ) ; + .clk_2_N_in ( p2989 ) , .clk_2_E_in ( p1065 ) , .clk_2_S_in ( p2660 ) , + .clk_2_W_in ( p2831 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2966 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2967 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2968 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2969 ) , .clk_3_W_in ( p2781 ) , + .clk_3_E_in ( p1137 ) , .clk_3_S_in ( p340 ) , .clk_3_N_in ( p2949 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2970 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2971 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2972 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2973 ) ) ; sb_1__1_ sb_7__2_ ( .chany_top_in ( cby_1__1__74_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_74_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_74_right_width_0_height_0__pin_43_lower ) , @@ -64915,50 +68122,41 @@ sb_1__1_ sb_7__2_ ( .chany_top_in ( cby_1__1__74_chany_bottom_out ) , .chanx_right_out ( sb_1__1__67_chanx_right_out ) , .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) , .chanx_left_out ( sb_1__1__67_chanx_left_out ) , - .ccff_tail ( sb_1__1__67_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_3993 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3994 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3995 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3996 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3997 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3998 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3999 ) , + .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( p2756 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2974 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , .prog_clk_1_N_in ( p2580 ) , + .prog_clk_1_S_in ( p615 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2975 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2976 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2977 ) , .prog_clk_2_E_in ( prog_clk_2_wires[72] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4000 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4001 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4002 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2978 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2979 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2980 ) , .prog_clk_2_S_out ( prog_clk_2_wires[73] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4003 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4004 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4005 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4006 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4007 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4008 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4009 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4010 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4011 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4012 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4013 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4014 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4015 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4016 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4017 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2981 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2982 ) , + .prog_clk_3_W_in ( p1683 ) , .prog_clk_3_E_in ( p176 ) , + .prog_clk_3_S_in ( p2656 ) , .prog_clk_3_N_in ( p1931 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2983 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2984 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2985 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2986 ) , .clk_1_N_in ( p2019 ) , + .clk_1_S_in ( p777 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2987 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2988 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2989 ) , .clk_2_E_in ( clk_2_wires[72] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4018 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4019 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4020 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2990 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2991 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2992 ) , .clk_2_S_out ( clk_2_wires[73] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4021 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4022 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4023 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4024 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4025 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4026 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4027 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4028 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4029 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4030 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2993 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2994 ) , .clk_3_W_in ( p1683 ) , + .clk_3_E_in ( p1926 ) , .clk_3_S_in ( p762 ) , .clk_3_N_in ( p2439 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2995 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2996 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2997 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2998 ) ) ; sb_1__1_ sb_7__3_ ( .chany_top_in ( cby_1__1__75_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_75_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_75_right_width_0_height_0__pin_43_lower ) , @@ -65000,49 +68198,38 @@ sb_1__1_ sb_7__3_ ( .chany_top_in ( cby_1__1__75_chany_bottom_out ) , .chanx_right_out ( sb_1__1__68_chanx_right_out ) , .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) , .chanx_left_out ( sb_1__1__68_chanx_left_out ) , - .ccff_tail ( sb_1__1__68_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4031 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4032 ) , + .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( p2987 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2999 ) , .prog_clk_0_N_in ( prog_clk_0_wires[264] ) , .prog_clk_1_N_in ( prog_clk_2_wires[85] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4033 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3000 ) , .prog_clk_1_E_out ( prog_clk_1_wires[134] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4034 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4035 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4036 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4037 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4038 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4039 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4040 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4041 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4042 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4043 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4044 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4045 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4046 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4047 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4048 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4049 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , .prog_clk_2_N_in ( p3333 ) , + .prog_clk_2_E_in ( p1152 ) , .prog_clk_2_S_in ( p490 ) , + .prog_clk_2_W_in ( p472 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3001 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3002 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3003 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3004 ) , + .prog_clk_3_W_in ( p3223 ) , .prog_clk_3_E_in ( p912 ) , + .prog_clk_3_S_in ( p87 ) , .prog_clk_3_N_in ( p3312 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3005 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3006 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3007 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3008 ) , .clk_1_N_in ( clk_2_wires[85] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4050 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3009 ) , .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4051 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4052 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4053 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4054 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4055 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4056 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4057 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4058 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4059 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4060 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4061 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4062 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4063 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4064 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4065 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4066 ) ) ; + .clk_2_N_in ( p3518 ) , .clk_2_E_in ( p300 ) , .clk_2_S_in ( p2942 ) , + .clk_2_W_in ( p3183 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3010 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3011 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3012 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3013 ) , .clk_3_W_in ( p3037 ) , + .clk_3_E_in ( p850 ) , .clk_3_S_in ( p1406 ) , .clk_3_N_in ( p3517 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3014 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3015 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3016 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3017 ) ) ; sb_1__1_ sb_7__4_ ( .chany_top_in ( cby_1__1__76_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_76_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_76_right_width_0_height_0__pin_43_lower ) , @@ -65084,49 +68271,40 @@ sb_1__1_ sb_7__4_ ( .chany_top_in ( cby_1__1__76_chany_bottom_out ) , .chanx_right_out ( sb_1__1__69_chanx_right_out ) , .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) , .chanx_left_out ( sb_1__1__69_chanx_left_out ) , - .ccff_tail ( sb_1__1__69_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4067 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4068 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4069 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4070 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4071 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4072 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4073 ) , + .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( p2050 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3018 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , .prog_clk_1_N_in ( p2793 ) , + .prog_clk_1_S_in ( p648 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3019 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3020 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3021 ) , .prog_clk_2_E_in ( prog_clk_2_wires[81] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4074 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4075 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4076 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3022 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3023 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3024 ) , .prog_clk_2_S_out ( prog_clk_2_wires[84] ) , .prog_clk_2_N_out ( prog_clk_2_wires[82] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4077 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4078 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4079 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4080 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4081 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4082 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4083 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4084 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4085 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4086 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4087 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4088 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4089 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4090 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3025 ) , + .prog_clk_3_W_in ( p1691 ) , .prog_clk_3_E_in ( p761 ) , + .prog_clk_3_S_in ( p1916 ) , .prog_clk_3_N_in ( p838 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3026 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3027 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3028 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3029 ) , .clk_1_N_in ( p1296 ) , + .clk_1_S_in ( p483 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3030 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3031 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3032 ) , .clk_2_E_in ( clk_2_wires[81] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4091 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4092 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4093 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3033 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3034 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3035 ) , .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4094 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4095 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4096 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4097 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4098 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4099 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4100 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4101 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4102 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3036 ) , .clk_3_W_in ( p1691 ) , + .clk_3_E_in ( p1919 ) , .clk_3_S_in ( p578 ) , .clk_3_N_in ( p2631 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3037 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3038 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3039 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3040 ) ) ; sb_1__1_ sb_7__5_ ( .chany_top_in ( cby_1__1__77_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_77_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_77_right_width_0_height_0__pin_43_lower ) , @@ -65168,49 +68346,38 @@ sb_1__1_ sb_7__5_ ( .chany_top_in ( cby_1__1__77_chany_bottom_out ) , .chanx_right_out ( sb_1__1__70_chanx_right_out ) , .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) , .chanx_left_out ( sb_1__1__70_chanx_left_out ) , - .ccff_tail ( sb_1__1__70_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4103 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4104 ) , + .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( p1750 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3041 ) , .prog_clk_0_N_in ( prog_clk_0_wires[270] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4105 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3042 ) , .prog_clk_1_S_in ( prog_clk_2_wires[83] ) , .prog_clk_1_E_out ( prog_clk_1_wires[141] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4106 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4107 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4108 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4109 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4110 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4111 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4112 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4113 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4114 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4115 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4116 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4117 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4118 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4119 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4120 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4121 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4122 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , .prog_clk_2_N_in ( p3511 ) , + .prog_clk_2_E_in ( p1077 ) , .prog_clk_2_S_in ( p477 ) , + .prog_clk_2_W_in ( p1198 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3043 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3044 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3045 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3046 ) , + .prog_clk_3_W_in ( p3352 ) , .prog_clk_3_E_in ( p46 ) , + .prog_clk_3_S_in ( p867 ) , .prog_clk_3_N_in ( p3510 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3047 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3048 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3049 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3050 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3051 ) , .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) , - .clk_1_W_out ( clk_1_wires[142] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4123 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4124 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4125 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4126 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4127 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4128 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4129 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4130 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4131 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4132 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4133 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4134 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4135 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4136 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4137 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4138 ) ) ; + .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( p3481 ) , + .clk_2_E_in ( p283 ) , .clk_2_S_in ( p1401 ) , .clk_2_W_in ( p3302 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3052 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3053 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3054 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3055 ) , .clk_3_W_in ( p3145 ) , + .clk_3_E_in ( p1000 ) , .clk_3_S_in ( p137 ) , .clk_3_N_in ( p3474 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3056 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3057 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3058 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3059 ) ) ; sb_1__1_ sb_7__6_ ( .chany_top_in ( cby_1__1__78_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_78_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_78_right_width_0_height_0__pin_43_lower ) , @@ -65252,50 +68419,41 @@ sb_1__1_ sb_7__6_ ( .chany_top_in ( cby_1__1__78_chany_bottom_out ) , .chanx_right_out ( sb_1__1__71_chanx_right_out ) , .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) , .chanx_left_out ( sb_1__1__71_chanx_left_out ) , - .ccff_tail ( sb_1__1__71_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4139 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4140 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4141 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4142 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4143 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4144 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4145 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4146 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4147 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4148 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4149 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4150 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4151 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4152 ) , + .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( p2513 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3060 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , .prog_clk_1_N_in ( p1457 ) , + .prog_clk_1_S_in ( p972 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3061 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3062 ) , + .prog_clk_2_N_in ( p1838 ) , .prog_clk_2_E_in ( p955 ) , + .prog_clk_2_S_in ( p1075 ) , .prog_clk_2_W_in ( p2209 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3063 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3064 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3065 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3066 ) , .prog_clk_3_W_in ( prog_clk_3_wires[1] ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4153 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4154 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4155 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3067 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3068 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3069 ) , .prog_clk_3_E_out ( prog_clk_3_wires[4] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4156 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4157 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4158 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4159 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4160 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4161 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4162 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4163 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4164 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4165 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4166 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4167 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4168 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4169 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4170 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3070 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3071 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3072 ) , .clk_1_N_in ( p1457 ) , + .clk_1_S_in ( p646 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3073 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3074 ) , .clk_2_N_in ( p1457 ) , + .clk_2_E_in ( p265 ) , .clk_2_S_in ( p2495 ) , .clk_2_W_in ( p1124 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3075 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3076 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3077 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3078 ) , .clk_3_W_in ( clk_3_wires[1] ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4171 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4172 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4173 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3079 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3080 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3081 ) , .clk_3_E_out ( clk_3_wires[4] ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4174 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4175 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4176 ) ) ; + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3082 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3083 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3084 ) ) ; sb_1__1_ sb_7__7_ ( .chany_top_in ( cby_1__1__79_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_79_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_79_right_width_0_height_0__pin_43_lower ) , @@ -65337,49 +68495,38 @@ sb_1__1_ sb_7__7_ ( .chany_top_in ( cby_1__1__79_chany_bottom_out ) , .chanx_right_out ( sb_1__1__72_chanx_right_out ) , .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) , .chanx_left_out ( sb_1__1__72_chanx_left_out ) , - .ccff_tail ( sb_1__1__72_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4177 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4178 ) , + .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( p2571 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3085 ) , .prog_clk_0_N_in ( prog_clk_0_wires[276] ) , .prog_clk_1_N_in ( prog_clk_2_wires[98] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4179 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3086 ) , .prog_clk_1_E_out ( prog_clk_1_wires[148] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4180 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4181 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4182 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4183 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4184 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4185 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4186 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4187 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4188 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4189 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4190 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4191 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4192 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4193 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4194 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4195 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , .prog_clk_2_N_in ( p2921 ) , + .prog_clk_2_E_in ( p1054 ) , .prog_clk_2_S_in ( p220 ) , + .prog_clk_2_W_in ( p834 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3087 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3088 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3089 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3090 ) , + .prog_clk_3_W_in ( p3118 ) , .prog_clk_3_E_in ( p454 ) , + .prog_clk_3_S_in ( p689 ) , .prog_clk_3_N_in ( p2815 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3091 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3092 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3093 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3094 ) , .clk_1_N_in ( clk_2_wires[98] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4196 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3095 ) , .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4197 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4198 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4199 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4200 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4201 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4202 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4203 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4204 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4205 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4206 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4207 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4208 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4209 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4210 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4211 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4212 ) ) ; + .clk_2_N_in ( p3508 ) , .clk_2_E_in ( p126 ) , .clk_2_S_in ( p2479 ) , + .clk_2_W_in ( p3071 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3096 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3097 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3098 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3099 ) , .clk_3_W_in ( p2318 ) , + .clk_3_E_in ( p894 ) , .clk_3_S_in ( p55 ) , .clk_3_N_in ( p3505 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3100 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3101 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3102 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3103 ) ) ; sb_1__1_ sb_7__8_ ( .chany_top_in ( cby_1__1__80_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_80_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_80_right_width_0_height_0__pin_43_lower ) , @@ -65421,49 +68568,40 @@ sb_1__1_ sb_7__8_ ( .chany_top_in ( cby_1__1__80_chany_bottom_out ) , .chanx_right_out ( sb_1__1__73_chanx_right_out ) , .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) , .chanx_left_out ( sb_1__1__73_chanx_left_out ) , - .ccff_tail ( sb_1__1__73_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4213 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4214 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4215 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4216 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4217 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4218 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4219 ) , + .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( p2743 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3104 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , .prog_clk_1_N_in ( p3379 ) , + .prog_clk_1_S_in ( p647 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3105 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3106 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3107 ) , .prog_clk_2_E_in ( prog_clk_2_wires[94] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4220 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4221 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4222 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3108 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3109 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3110 ) , .prog_clk_2_S_out ( prog_clk_2_wires[97] ) , .prog_clk_2_N_out ( prog_clk_2_wires[95] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4223 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4224 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4225 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4226 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4227 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4228 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4229 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4230 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4231 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4232 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4233 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4234 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4235 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4236 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3111 ) , + .prog_clk_3_W_in ( p1562 ) , .prog_clk_3_E_in ( p234 ) , + .prog_clk_3_S_in ( p2646 ) , .prog_clk_3_N_in ( p1901 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3112 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3113 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3114 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3115 ) , .clk_1_N_in ( p2421 ) , + .clk_1_S_in ( p151 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3116 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3117 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3118 ) , .clk_2_E_in ( clk_2_wires[94] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4237 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4238 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4239 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3119 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3120 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3121 ) , .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4240 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4241 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4242 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4243 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4244 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4245 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4246 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4247 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4248 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3122 ) , .clk_3_W_in ( p2523 ) , + .clk_3_E_in ( p565 ) , .clk_3_S_in ( p1464 ) , .clk_3_N_in ( p3367 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3123 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3124 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3125 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3126 ) ) ; sb_1__1_ sb_7__9_ ( .chany_top_in ( cby_1__1__81_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_81_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_81_right_width_0_height_0__pin_43_lower ) , @@ -65505,49 +68643,38 @@ sb_1__1_ sb_7__9_ ( .chany_top_in ( cby_1__1__81_chany_bottom_out ) , .chanx_right_out ( sb_1__1__74_chanx_right_out ) , .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) , .chanx_left_out ( sb_1__1__74_chanx_left_out ) , - .ccff_tail ( sb_1__1__74_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4249 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4250 ) , + .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( p2559 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3127 ) , .prog_clk_0_N_in ( prog_clk_0_wires[282] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4251 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3128 ) , .prog_clk_1_S_in ( prog_clk_2_wires[96] ) , .prog_clk_1_E_out ( prog_clk_1_wires[155] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4252 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4253 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4254 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4255 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4256 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4257 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4258 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4259 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4260 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4261 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4262 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4263 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4264 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4265 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4266 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4267 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4268 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , .prog_clk_2_N_in ( p3130 ) , + .prog_clk_2_E_in ( p938 ) , .prog_clk_2_S_in ( p775 ) , + .prog_clk_2_W_in ( p177 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3129 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3130 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3131 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3132 ) , + .prog_clk_3_W_in ( p3047 ) , .prog_clk_3_E_in ( p975 ) , + .prog_clk_3_S_in ( p191 ) , .prog_clk_3_N_in ( p3078 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3133 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3134 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3135 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3136 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3137 ) , .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) , - .clk_1_W_out ( clk_1_wires[156] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4269 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4270 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4271 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4272 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4273 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4274 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4275 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4276 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4277 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4278 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4279 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4280 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4281 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4282 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4283 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4284 ) ) ; + .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( p3491 ) , + .clk_2_E_in ( p1210 ) , .clk_2_S_in ( p2469 ) , .clk_2_W_in ( p2955 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3138 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3139 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3140 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3141 ) , .clk_3_W_in ( p2020 ) , + .clk_3_E_in ( p14 ) , .clk_3_S_in ( p1097 ) , .clk_3_N_in ( p3488 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3142 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3143 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3144 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3145 ) ) ; sb_1__1_ sb_7__10_ ( .chany_top_in ( cby_1__1__82_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_82_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_82_right_width_0_height_0__pin_43_lower ) , @@ -65589,50 +68716,41 @@ sb_1__1_ sb_7__10_ ( .chany_top_in ( cby_1__1__82_chany_bottom_out ) , .chanx_right_out ( sb_1__1__75_chanx_right_out ) , .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) , .chanx_left_out ( sb_1__1__75_chanx_left_out ) , - .ccff_tail ( sb_1__1__75_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4285 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4286 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4287 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4288 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4289 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4290 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4291 ) , + .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( p2366 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3146 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , .prog_clk_1_N_in ( p3204 ) , + .prog_clk_1_S_in ( p73 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3147 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3148 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3149 ) , .prog_clk_2_E_in ( prog_clk_2_wires[107] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4292 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4293 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4294 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4295 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3150 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3151 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3152 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3153 ) , .prog_clk_2_N_out ( prog_clk_2_wires[108] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4296 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4297 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4298 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4299 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4300 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4301 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4302 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4303 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4304 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4305 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4306 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4307 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4308 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4309 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3154 ) , + .prog_clk_3_W_in ( p2081 ) , .prog_clk_3_E_in ( p852 ) , + .prog_clk_3_S_in ( p2183 ) , .prog_clk_3_N_in ( p2241 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3155 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3156 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3157 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3158 ) , .clk_1_N_in ( p2885 ) , + .clk_1_S_in ( p501 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3159 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3160 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3161 ) , .clk_2_E_in ( clk_2_wires[107] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4310 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4311 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4312 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4313 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3162 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3163 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3164 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3165 ) , .clk_2_N_out ( clk_2_wires[108] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4314 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4315 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4316 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4317 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4318 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4319 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4320 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4321 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4322 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , .clk_3_W_in ( p2081 ) , + .clk_3_E_in ( p279 ) , .clk_3_S_in ( p295 ) , .clk_3_N_in ( p3171 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3167 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3168 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3169 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3170 ) ) ; sb_1__1_ sb_7__11_ ( .chany_top_in ( cby_1__1__83_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_83_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_83_right_width_0_height_0__pin_43_lower ) , @@ -65674,49 +68792,38 @@ sb_1__1_ sb_7__11_ ( .chany_top_in ( cby_1__1__83_chany_bottom_out ) , .chanx_right_out ( sb_1__1__76_chanx_right_out ) , .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) , .chanx_left_out ( sb_1__1__76_chanx_left_out ) , - .ccff_tail ( sb_1__1__76_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4323 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4324 ) , + .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( p2416 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3171 ) , .prog_clk_0_N_in ( prog_clk_0_wires[288] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4325 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3172 ) , .prog_clk_1_S_in ( prog_clk_2_wires[109] ) , .prog_clk_1_E_out ( prog_clk_1_wires[162] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4326 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4327 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4328 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4329 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4330 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4331 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4332 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4333 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4334 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4335 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4336 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4337 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4338 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4339 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4340 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4341 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4342 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , .prog_clk_2_N_in ( p3470 ) , + .prog_clk_2_E_in ( p797 ) , .prog_clk_2_S_in ( p40 ) , + .prog_clk_2_W_in ( p245 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3173 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3174 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3175 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3176 ) , + .prog_clk_3_W_in ( p3013 ) , .prog_clk_3_E_in ( p39 ) , + .prog_clk_3_S_in ( p1191 ) , .prog_clk_3_N_in ( p3455 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3177 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3178 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3179 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3180 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3181 ) , .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) , - .clk_1_W_out ( clk_1_wires[163] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4343 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4344 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4345 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4346 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4347 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4348 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4349 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4350 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4351 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4352 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4353 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4354 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4355 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4356 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4357 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4358 ) ) ; + .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( p3451 ) , + .clk_2_E_in ( p1206 ) , .clk_2_S_in ( p2247 ) , .clk_2_W_in ( p3360 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3182 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3183 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3184 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3185 ) , .clk_3_W_in ( p3391 ) , + .clk_3_E_in ( p886 ) , .clk_3_S_in ( p754 ) , .clk_3_N_in ( p3428 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3186 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3187 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3188 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3189 ) ) ; sb_1__1_ sb_8__1_ ( .chany_top_in ( cby_1__1__85_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_85_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_85_right_width_0_height_0__pin_43_lower ) , @@ -65758,50 +68865,36 @@ sb_1__1_ sb_8__1_ ( .chany_top_in ( cby_1__1__85_chany_bottom_out ) , .chanx_right_out ( sb_1__1__77_chanx_right_out ) , .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) , .chanx_left_out ( sb_1__1__77_chanx_left_out ) , - .ccff_tail ( sb_1__1__77_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4359 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4360 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4361 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4362 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4363 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4364 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4365 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4366 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4367 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4368 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4369 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4370 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4371 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4372 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4373 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4374 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4375 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4376 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4377 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4378 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4379 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4380 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4381 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4382 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4383 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4384 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4385 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4386 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4387 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4388 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4389 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4390 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4391 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4392 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4393 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4394 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4395 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4396 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4397 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4398 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4399 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4400 ) ) ; + .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( p2908 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3190 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , .prog_clk_1_N_in ( p3194 ) , + .prog_clk_1_S_in ( p1093 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3191 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3192 ) , + .prog_clk_2_N_in ( p3351 ) , .prog_clk_2_E_in ( p809 ) , + .prog_clk_2_S_in ( p786 ) , .prog_clk_2_W_in ( p492 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3193 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3194 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3195 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , + .prog_clk_3_W_in ( p3114 ) , .prog_clk_3_E_in ( p1094 ) , + .prog_clk_3_S_in ( p327 ) , .prog_clk_3_N_in ( p3300 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3197 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3198 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3199 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3200 ) , .clk_1_N_in ( p2393 ) , + .clk_1_S_in ( p430 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3201 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3202 ) , .clk_2_N_in ( p3348 ) , + .clk_2_E_in ( p628 ) , .clk_2_S_in ( p2833 ) , .clk_2_W_in ( p3055 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3203 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3204 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3205 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3206 ) , .clk_3_W_in ( p1669 ) , + .clk_3_E_in ( p352 ) , .clk_3_S_in ( p1066 ) , .clk_3_N_in ( p3324 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3207 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3208 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3209 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3210 ) ) ; sb_1__1_ sb_8__2_ ( .chany_top_in ( cby_1__1__86_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_86_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_86_right_width_0_height_0__pin_43_lower ) , @@ -65843,50 +68936,41 @@ sb_1__1_ sb_8__2_ ( .chany_top_in ( cby_1__1__86_chany_bottom_out ) , .chanx_right_out ( sb_1__1__78_chanx_right_out ) , .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) , .chanx_left_out ( sb_1__1__78_chanx_left_out ) , - .ccff_tail ( sb_1__1__78_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4401 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4402 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4403 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4404 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4405 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4406 ) , + .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( p2992 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3211 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , .prog_clk_1_N_in ( p3422 ) , + .prog_clk_1_S_in ( p832 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3212 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3213 ) , .prog_clk_2_N_in ( prog_clk_3_wires[43] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4407 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4408 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4409 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3214 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3215 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3216 ) , .prog_clk_2_W_out ( prog_clk_2_wires[71] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4410 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4411 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4412 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4413 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4414 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4415 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4416 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4417 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4418 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4419 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4420 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4421 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4422 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4423 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3217 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3218 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , .prog_clk_3_W_in ( p1560 ) , + .prog_clk_3_E_in ( p211 ) , .prog_clk_3_S_in ( p2975 ) , + .prog_clk_3_N_in ( p299 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3219 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3220 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3221 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3222 ) , .clk_1_N_in ( p2337 ) , + .clk_1_S_in ( p138 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3223 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3224 ) , .clk_2_N_in ( clk_3_wires[43] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4424 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4425 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4426 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3225 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3226 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3227 ) , .clk_2_W_out ( clk_2_wires[71] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4427 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4428 ) , - .clk_2_E_out ( clk_2_wires[69] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4429 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4430 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4431 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4432 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4433 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4434 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4435 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4436 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3228 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3229 ) , + .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( p1560 ) , + .clk_3_E_in ( p567 ) , .clk_3_S_in ( p409 ) , .clk_3_N_in ( p3408 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3230 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3231 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3232 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3233 ) ) ; sb_1__1_ sb_8__3_ ( .chany_top_in ( cby_1__1__87_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_87_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_87_right_width_0_height_0__pin_43_lower ) , @@ -65928,49 +69012,40 @@ sb_1__1_ sb_8__3_ ( .chany_top_in ( cby_1__1__87_chany_bottom_out ) , .chanx_right_out ( sb_1__1__79_chanx_right_out ) , .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) , .chanx_left_out ( sb_1__1__79_chanx_left_out ) , - .ccff_tail ( sb_1__1__79_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4437 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4438 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4439 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4440 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4441 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4442 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4443 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4444 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4445 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4446 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4447 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4448 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4449 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4450 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4451 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4452 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4453 ) , + .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( p2588 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3234 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , .prog_clk_1_N_in ( p2044 ) , + .prog_clk_1_S_in ( p317 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3235 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3236 ) , + .prog_clk_2_N_in ( p2044 ) , .prog_clk_2_E_in ( p987 ) , + .prog_clk_2_S_in ( p1924 ) , .prog_clk_2_W_in ( p1007 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3237 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3238 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3239 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3240 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3241 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3242 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3243 ) , .prog_clk_3_N_in ( prog_clk_3_wires[39] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4454 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4455 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4456 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4457 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4458 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4459 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4460 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4461 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4462 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4463 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4464 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4465 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4466 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4467 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4468 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4469 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4470 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4471 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3244 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3245 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3246 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( p2044 ) , + .clk_1_S_in ( p883 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3247 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3248 ) , .clk_2_N_in ( p2044 ) , + .clk_2_E_in ( p47 ) , .clk_2_S_in ( p2452 ) , .clk_2_W_in ( p517 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3249 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3250 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3251 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3253 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3254 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3255 ) , .clk_3_N_in ( clk_3_wires[39] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4472 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4473 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4474 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3256 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3257 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3258 ) , .clk_3_S_out ( clk_3_wires[42] ) ) ; sb_1__1_ sb_8__4_ ( .chany_top_in ( cby_1__1__88_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_88_right_width_0_height_0__pin_42_lower ) , @@ -66013,49 +69088,45 @@ sb_1__1_ sb_8__4_ ( .chany_top_in ( cby_1__1__88_chany_bottom_out ) , .chanx_right_out ( sb_1__1__80_chanx_right_out ) , .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) , .chanx_left_out ( sb_1__1__80_chanx_left_out ) , - .ccff_tail ( sb_1__1__80_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4475 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4476 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4477 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4478 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4479 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4480 ) , + .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( p1225 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3259 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , .prog_clk_1_N_in ( p2103 ) , + .prog_clk_1_S_in ( p6 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3260 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3261 ) , .prog_clk_2_N_in ( prog_clk_3_wires[33] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4481 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4482 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4483 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3262 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3263 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3264 ) , .prog_clk_2_W_out ( prog_clk_2_wires[80] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4484 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4485 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3265 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3266 ) , .prog_clk_2_E_out ( prog_clk_2_wires[78] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4486 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4487 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4488 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3267 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3268 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3269 ) , .prog_clk_3_N_in ( prog_clk_3_wires[33] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4489 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4490 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4491 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4492 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4493 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4494 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4495 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3270 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3271 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3272 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( p2103 ) , + .clk_1_S_in ( p771 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3273 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3274 ) , .clk_2_N_in ( clk_3_wires[33] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4496 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4497 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4498 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3275 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3276 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3277 ) , .clk_2_W_out ( clk_2_wires[80] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4499 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4500 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3278 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3279 ) , .clk_2_E_out ( clk_2_wires[78] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4501 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4502 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4503 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3280 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3281 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3282 ) , .clk_3_N_in ( clk_3_wires[33] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4504 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4505 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4506 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3283 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3284 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3285 ) , .clk_3_S_out ( clk_3_wires[38] ) ) ; sb_1__1_ sb_8__5_ ( .chany_top_in ( cby_1__1__89_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_89_right_width_0_height_0__pin_42_lower ) , @@ -66098,49 +69169,40 @@ sb_1__1_ sb_8__5_ ( .chany_top_in ( cby_1__1__89_chany_bottom_out ) , .chanx_right_out ( sb_1__1__81_chanx_right_out ) , .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) , .chanx_left_out ( sb_1__1__81_chanx_left_out ) , - .ccff_tail ( sb_1__1__81_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4507 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4508 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4509 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4510 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4511 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4512 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4513 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4514 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4515 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4516 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4517 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4518 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4519 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4520 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4521 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4522 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4523 ) , + .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( p2412 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3286 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , .prog_clk_1_N_in ( p1405 ) , + .prog_clk_1_S_in ( p929 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3287 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3288 ) , + .prog_clk_2_N_in ( p1405 ) , .prog_clk_2_E_in ( p1187 ) , + .prog_clk_2_S_in ( p820 ) , .prog_clk_2_W_in ( p414 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3289 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3290 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3291 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3292 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3293 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3294 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3295 ) , .prog_clk_3_N_in ( prog_clk_3_wires[29] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4524 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4525 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4526 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4527 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4528 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4529 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4530 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4531 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4532 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4533 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4534 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4535 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4536 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4537 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4538 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4539 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4540 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4541 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3296 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3297 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3298 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( p1844 ) , + .clk_1_S_in ( p218 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3299 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3300 ) , .clk_2_N_in ( p1405 ) , + .clk_2_E_in ( p161 ) , .clk_2_S_in ( p2175 ) , .clk_2_W_in ( p939 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3301 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3302 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3303 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3304 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3305 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3306 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3307 ) , .clk_3_N_in ( clk_3_wires[29] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4542 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4543 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4544 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3308 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3309 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3310 ) , .clk_3_S_out ( clk_3_wires[32] ) ) ; sb_1__1_ sb_8__6_ ( .chany_top_in ( cby_1__1__90_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_90_right_width_0_height_0__pin_42_lower ) , @@ -66183,48 +69245,39 @@ sb_1__1_ sb_8__6_ ( .chany_top_in ( cby_1__1__90_chany_bottom_out ) , .chanx_right_out ( sb_1__1__82_chanx_right_out ) , .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) , .chanx_left_out ( sb_1__1__82_chanx_left_out ) , - .ccff_tail ( sb_1__1__82_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4545 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4546 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4547 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4548 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4549 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4550 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4551 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4552 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4553 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4554 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4555 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4556 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4557 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4558 ) , + .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( p1742 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3311 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , .prog_clk_1_N_in ( p1559 ) , + .prog_clk_1_S_in ( p549 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3312 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3313 ) , + .prog_clk_2_N_in ( p1559 ) , .prog_clk_2_E_in ( p17 ) , + .prog_clk_2_S_in ( p2212 ) , .prog_clk_2_W_in ( p1930 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3314 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3315 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3316 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3317 ) , .prog_clk_3_W_in ( prog_clk_3_wires[5] ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4559 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4560 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4561 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3318 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3319 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3320 ) , .prog_clk_3_E_out ( prog_clk_3_wires[44] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4562 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3321 ) , .prog_clk_3_N_out ( prog_clk_3_wires[26] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4563 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4564 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4565 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4566 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4567 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4568 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4569 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4570 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4571 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4572 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4573 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4574 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( p1559 ) , + .clk_1_S_in ( p290 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3322 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3323 ) , .clk_2_N_in ( p1559 ) , + .clk_2_E_in ( p1146 ) , .clk_2_S_in ( p572 ) , .clk_2_W_in ( p1006 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3324 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3325 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3326 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3327 ) , .clk_3_W_in ( clk_3_wires[5] ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4575 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4576 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4577 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3328 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3329 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3330 ) , .clk_3_E_out ( clk_3_wires[44] ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4578 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3331 ) , .clk_3_N_out ( clk_3_wires[26] ) , .clk_3_S_out ( clk_3_wires[28] ) ) ; sb_1__1_ sb_8__7_ ( .chany_top_in ( cby_1__1__91_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_91_right_width_0_height_0__pin_42_lower ) , @@ -66267,50 +69320,41 @@ sb_1__1_ sb_8__7_ ( .chany_top_in ( cby_1__1__91_chany_bottom_out ) , .chanx_right_out ( sb_1__1__83_chanx_right_out ) , .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) , .chanx_left_out ( sb_1__1__83_chanx_left_out ) , - .ccff_tail ( sb_1__1__83_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4579 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4580 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4581 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4582 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4583 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4584 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4585 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4586 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4587 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4588 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4589 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4590 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4591 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4592 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4593 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4594 ) , + .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( p1547 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3332 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , .prog_clk_1_N_in ( p1426 ) , + .prog_clk_1_S_in ( p915 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3333 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3334 ) , + .prog_clk_2_N_in ( p1426 ) , .prog_clk_2_E_in ( p658 ) , + .prog_clk_2_S_in ( p2450 ) , .prog_clk_2_W_in ( p570 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3335 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3336 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3337 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3338 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3339 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3340 ) , .prog_clk_3_S_in ( prog_clk_3_wires[27] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4595 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4596 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4597 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3341 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3343 ) , .prog_clk_3_N_out ( prog_clk_3_wires[30] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4598 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4599 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4600 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4601 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4602 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4603 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4604 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4605 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4606 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4607 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4608 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4609 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4610 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4611 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4612 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3344 ) , .clk_1_N_in ( p1426 ) , + .clk_1_S_in ( p437 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3345 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3346 ) , .clk_2_N_in ( p1426 ) , + .clk_2_E_in ( p147 ) , .clk_2_S_in ( p652 ) , .clk_2_W_in ( p318 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3347 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3348 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3349 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3350 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3351 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3352 ) , .clk_3_S_in ( clk_3_wires[27] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4613 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4614 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4615 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3353 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3354 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3355 ) , .clk_3_N_out ( clk_3_wires[30] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4616 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3356 ) ) ; sb_1__1_ sb_8__8_ ( .chany_top_in ( cby_1__1__92_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_92_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_92_right_width_0_height_0__pin_43_lower ) , @@ -66352,50 +69396,46 @@ sb_1__1_ sb_8__8_ ( .chany_top_in ( cby_1__1__92_chany_bottom_out ) , .chanx_right_out ( sb_1__1__84_chanx_right_out ) , .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) , .chanx_left_out ( sb_1__1__84_chanx_left_out ) , - .ccff_tail ( sb_1__1__84_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4617 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4618 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4619 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4620 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4621 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4622 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4623 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4624 ) , + .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( p1586 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3357 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , .prog_clk_1_N_in ( p1577 ) , + .prog_clk_1_S_in ( p118 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3358 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3359 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3360 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3361 ) , .prog_clk_2_S_in ( prog_clk_3_wires[31] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4625 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3362 ) , .prog_clk_2_W_out ( prog_clk_2_wires[93] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4626 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4627 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3363 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3364 ) , .prog_clk_2_E_out ( prog_clk_2_wires[91] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4628 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4629 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3365 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3366 ) , .prog_clk_3_S_in ( prog_clk_3_wires[31] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4630 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4631 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4632 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3367 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3368 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3369 ) , .prog_clk_3_N_out ( prog_clk_3_wires[36] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4633 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4634 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4635 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4636 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4637 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4638 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4639 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3370 ) , .clk_1_N_in ( p1577 ) , + .clk_1_S_in ( p845 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3371 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3372 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3373 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3374 ) , .clk_2_S_in ( clk_3_wires[31] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4640 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3375 ) , .clk_2_W_out ( clk_2_wires[93] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4641 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4642 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3376 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3377 ) , .clk_2_E_out ( clk_2_wires[91] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4643 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4644 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3378 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3379 ) , .clk_3_S_in ( clk_3_wires[31] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4645 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4646 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4647 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3380 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3381 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3382 ) , .clk_3_N_out ( clk_3_wires[36] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4648 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3383 ) ) ; sb_1__1_ sb_8__9_ ( .chany_top_in ( cby_1__1__93_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_93_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_93_right_width_0_height_0__pin_43_lower ) , @@ -66437,50 +69477,41 @@ sb_1__1_ sb_8__9_ ( .chany_top_in ( cby_1__1__93_chany_bottom_out ) , .chanx_right_out ( sb_1__1__85_chanx_right_out ) , .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) , .chanx_left_out ( sb_1__1__85_chanx_left_out ) , - .ccff_tail ( sb_1__1__85_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4649 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4650 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4651 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4652 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4653 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4654 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4655 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4656 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4657 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4658 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4659 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4660 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4661 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4662 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4663 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4664 ) , + .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( p2016 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3384 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , .prog_clk_1_N_in ( p1554 ) , + .prog_clk_1_S_in ( p934 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3385 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3386 ) , + .prog_clk_2_N_in ( p1554 ) , .prog_clk_2_E_in ( p105 ) , + .prog_clk_2_S_in ( p170 ) , .prog_clk_2_W_in ( p885 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3387 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3388 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3389 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3390 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3391 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3392 ) , .prog_clk_3_S_in ( prog_clk_3_wires[37] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4665 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4666 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4667 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3393 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3394 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3395 ) , .prog_clk_3_N_out ( prog_clk_3_wires[40] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4668 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4669 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4670 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4671 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4672 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4673 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4674 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4675 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4676 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4677 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4678 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4679 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4680 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4681 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4682 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3396 ) , .clk_1_N_in ( p1554 ) , + .clk_1_S_in ( p588 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3397 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3398 ) , .clk_2_N_in ( p1554 ) , + .clk_2_E_in ( p899 ) , .clk_2_S_in ( p1921 ) , .clk_2_W_in ( p158 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3399 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3400 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3401 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3402 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3403 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3404 ) , .clk_3_S_in ( clk_3_wires[37] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4683 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4684 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4685 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3405 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3406 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3407 ) , .clk_3_N_out ( clk_3_wires[40] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4686 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3408 ) ) ; sb_1__1_ sb_8__10_ ( .chany_top_in ( cby_1__1__94_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_94_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_94_right_width_0_height_0__pin_43_lower ) , @@ -66522,50 +69553,41 @@ sb_1__1_ sb_8__10_ ( .chany_top_in ( cby_1__1__94_chany_bottom_out ) , .chanx_right_out ( sb_1__1__86_chanx_right_out ) , .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) , .chanx_left_out ( sb_1__1__86_chanx_left_out ) , - .ccff_tail ( sb_1__1__86_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4687 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4688 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4689 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4690 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4691 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4692 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4693 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4694 ) , + .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( p1684 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3409 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , .prog_clk_1_N_in ( p3450 ) , + .prog_clk_1_S_in ( p884 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3410 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3411 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3412 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3413 ) , .prog_clk_2_S_in ( prog_clk_3_wires[41] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4695 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3414 ) , .prog_clk_2_W_out ( prog_clk_2_wires[106] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4696 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4697 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4698 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4699 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4700 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4701 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4702 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4703 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4704 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4705 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4706 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4707 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4708 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4709 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4710 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4711 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3415 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3416 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , .prog_clk_3_W_in ( p2324 ) , + .prog_clk_3_E_in ( p1132 ) , .prog_clk_3_S_in ( p179 ) , + .prog_clk_3_N_in ( p2223 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3417 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3418 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3419 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3420 ) , .clk_1_N_in ( p2858 ) , + .clk_1_S_in ( p428 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3421 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3422 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3423 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3424 ) , .clk_2_S_in ( clk_3_wires[41] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4712 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3425 ) , .clk_2_W_out ( clk_2_wires[106] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4713 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4714 ) , - .clk_2_E_out ( clk_2_wires[104] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4715 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4716 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4717 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4718 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4719 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4720 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4721 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4722 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3426 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3427 ) , + .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( p2324 ) , + .clk_3_E_in ( p175 ) , .clk_3_S_in ( p1181 ) , .clk_3_N_in ( p3434 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3428 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3429 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3430 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3431 ) ) ; sb_1__1_ sb_8__11_ ( .chany_top_in ( cby_1__1__95_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_95_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_95_right_width_0_height_0__pin_43_lower ) , @@ -66607,50 +69629,36 @@ sb_1__1_ sb_8__11_ ( .chany_top_in ( cby_1__1__95_chany_bottom_out ) , .chanx_right_out ( sb_1__1__87_chanx_right_out ) , .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) , .chanx_left_out ( sb_1__1__87_chanx_left_out ) , - .ccff_tail ( sb_1__1__87_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4723 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4724 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4725 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4726 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4727 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4728 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4729 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4730 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4731 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4732 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4733 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4734 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4735 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4736 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4737 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4738 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4739 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4740 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4741 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4742 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4743 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4744 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4745 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4746 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4747 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4748 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4749 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4750 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4751 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4752 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4753 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4754 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4755 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4756 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4757 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4758 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4759 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4760 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4761 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4762 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4763 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4764 ) ) ; + .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( p2026 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3432 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , .prog_clk_1_N_in ( p3416 ) , + .prog_clk_1_S_in ( p903 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3433 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3434 ) , + .prog_clk_2_N_in ( p2782 ) , .prog_clk_2_E_in ( p682 ) , + .prog_clk_2_S_in ( p1106 ) , .prog_clk_2_W_in ( p932 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3435 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3436 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3437 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3438 ) , + .prog_clk_3_W_in ( p3151 ) , .prog_clk_3_E_in ( p745 ) , + .prog_clk_3_S_in ( p302 ) , .prog_clk_3_N_in ( p2628 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3439 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3440 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3441 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3442 ) , .clk_1_N_in ( p3100 ) , + .clk_1_S_in ( p569 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3443 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3444 ) , .clk_2_N_in ( p3449 ) , + .clk_2_E_in ( p1016 ) , .clk_2_S_in ( p1949 ) , .clk_2_W_in ( p3072 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3445 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3446 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3447 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3448 ) , .clk_3_W_in ( p3009 ) , + .clk_3_E_in ( p197 ) , .clk_3_S_in ( p1068 ) , .clk_3_N_in ( p3429 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3449 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3450 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3451 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3452 ) ) ; sb_1__1_ sb_9__1_ ( .chany_top_in ( cby_1__1__97_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_97_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_97_right_width_0_height_0__pin_43_lower ) , @@ -66692,49 +69700,38 @@ sb_1__1_ sb_9__1_ ( .chany_top_in ( cby_1__1__97_chany_bottom_out ) , .chanx_right_out ( sb_1__1__88_chanx_right_out ) , .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) , .chanx_left_out ( sb_1__1__88_chanx_left_out ) , - .ccff_tail ( sb_1__1__88_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4765 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4766 ) , + .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( p2401 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3453 ) , .prog_clk_0_N_in ( prog_clk_0_wires[334] ) , .prog_clk_1_N_in ( prog_clk_2_wires[76] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4767 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3454 ) , .prog_clk_1_E_out ( prog_clk_1_wires[169] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4768 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4769 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4770 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4771 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4772 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4773 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4774 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4775 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4776 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4777 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4778 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4779 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4780 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4781 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4782 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4783 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , .prog_clk_2_N_in ( p3135 ) , + .prog_clk_2_E_in ( p684 ) , .prog_clk_2_S_in ( p1182 ) , + .prog_clk_2_W_in ( p856 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3455 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3456 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3457 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3458 ) , + .prog_clk_3_W_in ( p3026 ) , .prog_clk_3_E_in ( p1304 ) , + .prog_clk_3_S_in ( p1030 ) , .prog_clk_3_N_in ( p3086 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3459 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3460 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3461 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3462 ) , .clk_1_N_in ( clk_2_wires[76] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4784 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3463 ) , .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4785 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4786 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4787 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4788 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4789 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4790 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4791 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4792 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4793 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4794 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4795 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4796 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4797 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4798 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4799 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4800 ) ) ; + .clk_2_N_in ( p3506 ) , .clk_2_E_in ( p1009 ) , .clk_2_S_in ( p2216 ) , + .clk_2_W_in ( p2948 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3464 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3465 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3466 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3467 ) , .clk_3_W_in ( p2878 ) , + .clk_3_E_in ( p377 ) , .clk_3_S_in ( p201 ) , .clk_3_N_in ( p3504 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3468 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3469 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3470 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3471 ) ) ; sb_1__1_ sb_9__2_ ( .chany_top_in ( cby_1__1__98_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_98_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_98_right_width_0_height_0__pin_43_lower ) , @@ -66776,50 +69773,41 @@ sb_1__1_ sb_9__2_ ( .chany_top_in ( cby_1__1__98_chany_bottom_out ) , .chanx_right_out ( sb_1__1__89_chanx_right_out ) , .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) , .chanx_left_out ( sb_1__1__89_chanx_left_out ) , - .ccff_tail ( sb_1__1__89_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4801 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4802 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4803 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4804 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4805 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4806 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4807 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4808 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4809 ) , + .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( p2765 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3472 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , .prog_clk_1_N_in ( p3482 ) , + .prog_clk_1_S_in ( p539 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3473 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3474 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3475 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3476 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3477 ) , .prog_clk_2_W_in ( prog_clk_2_wires[70] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4810 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3478 ) , .prog_clk_2_S_out ( prog_clk_2_wires[75] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4811 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4812 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4813 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4814 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4815 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4816 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4817 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4818 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4819 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4820 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4821 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4822 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4823 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4824 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4825 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4826 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4827 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3479 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3480 ) , + .prog_clk_3_W_in ( p1465 ) , .prog_clk_3_E_in ( p1064 ) , + .prog_clk_3_S_in ( p2638 ) , .prog_clk_3_N_in ( p2237 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3481 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3482 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3483 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3484 ) , .clk_1_N_in ( p3021 ) , + .clk_1_S_in ( p964 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3485 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3486 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3487 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3488 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3489 ) , .clk_2_W_in ( clk_2_wires[70] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4828 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3490 ) , .clk_2_S_out ( clk_2_wires[75] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4829 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4830 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4831 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4832 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4833 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4834 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4835 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4836 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4837 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4838 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3491 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3492 ) , .clk_3_W_in ( p1465 ) , + .clk_3_E_in ( p231 ) , .clk_3_S_in ( p1334 ) , .clk_3_N_in ( p3472 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3493 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3494 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3495 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3496 ) ) ; sb_1__1_ sb_9__3_ ( .chany_top_in ( cby_1__1__99_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_99_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_99_right_width_0_height_0__pin_43_lower ) , @@ -66861,49 +69849,38 @@ sb_1__1_ sb_9__3_ ( .chany_top_in ( cby_1__1__99_chany_bottom_out ) , .chanx_right_out ( sb_1__1__90_chanx_right_out ) , .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) , .chanx_left_out ( sb_1__1__90_chanx_left_out ) , - .ccff_tail ( sb_1__1__90_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4839 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4840 ) , + .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( p2788 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3497 ) , .prog_clk_0_N_in ( prog_clk_0_wires[340] ) , .prog_clk_1_N_in ( prog_clk_2_wires[89] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4841 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3498 ) , .prog_clk_1_E_out ( prog_clk_1_wires[176] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4842 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4843 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4844 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4845 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4846 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4847 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4848 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4849 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4850 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4851 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4852 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4853 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4854 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4855 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4856 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4857 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , .prog_clk_2_N_in ( p3522 ) , + .prog_clk_2_E_in ( p1286 ) , .prog_clk_2_S_in ( p61 ) , + .prog_clk_2_W_in ( p843 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3499 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3500 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3501 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3502 ) , + .prog_clk_3_W_in ( p3012 ) , .prog_clk_3_E_in ( p25 ) , + .prog_clk_3_S_in ( p196 ) , .prog_clk_3_N_in ( p3521 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3503 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3504 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3505 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3506 ) , .clk_1_N_in ( clk_2_wires[89] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4858 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3507 ) , .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4859 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4860 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4861 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4862 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4863 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4864 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4865 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4866 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4867 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4868 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4869 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4870 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4871 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4872 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4873 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4874 ) ) ; + .clk_2_N_in ( p3287 ) , .clk_2_E_in ( p716 ) , .clk_2_S_in ( p2677 ) , + .clk_2_W_in ( p3402 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3508 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3509 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3510 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_3_W_in ( p3415 ) , + .clk_3_E_in ( p1171 ) , .clk_3_S_in ( p1262 ) , .clk_3_N_in ( p3248 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3512 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3513 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3514 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3515 ) ) ; sb_1__1_ sb_9__4_ ( .chany_top_in ( cby_1__1__100_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_100_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_100_right_width_0_height_0__pin_43_lower ) , @@ -66945,49 +69922,40 @@ sb_1__1_ sb_9__4_ ( .chany_top_in ( cby_1__1__100_chany_bottom_out ) , .chanx_right_out ( sb_1__1__91_chanx_right_out ) , .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) , .chanx_left_out ( sb_1__1__91_chanx_left_out ) , - .ccff_tail ( sb_1__1__91_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4875 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4876 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4877 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4878 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4879 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4880 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4881 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4882 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4883 ) , + .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( p2368 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3516 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , .prog_clk_1_N_in ( p3469 ) , + .prog_clk_1_S_in ( p914 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3517 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3518 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3519 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3520 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3521 ) , .prog_clk_2_W_in ( prog_clk_2_wires[79] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4884 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3522 ) , .prog_clk_2_S_out ( prog_clk_2_wires[88] ) , .prog_clk_2_N_out ( prog_clk_2_wires[86] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4885 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4886 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4887 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4888 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4889 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4890 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4891 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4892 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4893 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4894 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4895 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4896 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4897 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4898 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4899 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4900 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3523 ) , + .prog_clk_3_W_in ( p2423 ) , .prog_clk_3_E_in ( p306 ) , + .prog_clk_3_S_in ( p2229 ) , .prog_clk_3_N_in ( p608 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3524 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3525 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3526 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3527 ) , .clk_1_N_in ( p2031 ) , + .clk_1_S_in ( p551 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3528 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3529 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3530 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3531 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3532 ) , .clk_2_W_in ( clk_2_wires[79] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4901 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3533 ) , .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4902 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4903 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4904 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4905 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4906 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4907 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4908 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4909 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4910 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3534 ) , .clk_3_W_in ( p2423 ) , + .clk_3_E_in ( p1149 ) , .clk_3_S_in ( p769 ) , .clk_3_N_in ( p3461 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3535 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3536 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3537 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3538 ) ) ; sb_1__1_ sb_9__5_ ( .chany_top_in ( cby_1__1__101_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_101_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_101_right_width_0_height_0__pin_43_lower ) , @@ -67029,49 +69997,38 @@ sb_1__1_ sb_9__5_ ( .chany_top_in ( cby_1__1__101_chany_bottom_out ) , .chanx_right_out ( sb_1__1__92_chanx_right_out ) , .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) , .chanx_left_out ( sb_1__1__92_chanx_left_out ) , - .ccff_tail ( sb_1__1__92_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4911 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4912 ) , + .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( p2725 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3539 ) , .prog_clk_0_N_in ( prog_clk_0_wires[346] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4913 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3540 ) , .prog_clk_1_S_in ( prog_clk_2_wires[87] ) , .prog_clk_1_E_out ( prog_clk_1_wires[183] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4914 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4915 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4916 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4917 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4918 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4919 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4920 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4921 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4922 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4923 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4924 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4925 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4926 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4927 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4928 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4929 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4930 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , .prog_clk_2_N_in ( p2101 ) , + .prog_clk_2_E_in ( p1353 ) , .prog_clk_2_S_in ( p488 ) , + .prog_clk_2_W_in ( p642 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3541 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3542 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3543 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3544 ) , + .prog_clk_3_W_in ( p3376 ) , .prog_clk_3_E_in ( p825 ) , + .prog_clk_3_S_in ( p709 ) , .prog_clk_3_N_in ( p2641 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3545 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3546 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3547 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3548 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3549 ) , .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) , - .clk_1_W_out ( clk_1_wires[184] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4931 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4932 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4933 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4934 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4935 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4936 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4937 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4938 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4939 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4940 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4941 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4942 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4943 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4944 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4945 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4946 ) ) ; + .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( p3378 ) , + .clk_2_E_in ( p900 ) , .clk_2_S_in ( p2668 ) , .clk_2_W_in ( p3370 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3550 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3551 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3552 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3553 ) , .clk_3_W_in ( p3036 ) , + .clk_3_E_in ( p42 ) , .clk_3_S_in ( p927 ) , .clk_3_N_in ( p3372 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3554 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3555 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3556 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3557 ) ) ; sb_1__1_ sb_9__6_ ( .chany_top_in ( cby_1__1__102_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_102_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_102_right_width_0_height_0__pin_43_lower ) , @@ -67113,50 +70070,41 @@ sb_1__1_ sb_9__6_ ( .chany_top_in ( cby_1__1__102_chany_bottom_out ) , .chanx_right_out ( sb_1__1__93_chanx_right_out ) , .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) , .chanx_left_out ( sb_1__1__93_chanx_left_out ) , - .ccff_tail ( sb_1__1__93_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4947 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4948 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4949 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4950 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4951 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4952 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4953 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4954 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4955 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4956 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4957 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4958 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4959 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4960 ) , + .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( p2715 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3558 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , .prog_clk_1_N_in ( p1796 ) , + .prog_clk_1_S_in ( p513 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3559 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3560 ) , + .prog_clk_2_N_in ( p1852 ) , .prog_clk_2_E_in ( p1316 ) , + .prog_clk_2_S_in ( p324 ) , .prog_clk_2_W_in ( p924 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3561 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3562 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3563 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3564 ) , .prog_clk_3_W_in ( prog_clk_3_wires[45] ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4961 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4962 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4963 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3565 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3566 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3567 ) , .prog_clk_3_E_out ( prog_clk_3_wires[48] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4964 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4965 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4966 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4967 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4968 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4969 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4970 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4971 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4972 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4973 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4974 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4975 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4976 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4977 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4978 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3568 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3569 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3570 ) , .clk_1_N_in ( p1796 ) , + .clk_1_S_in ( p804 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3571 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3572 ) , .clk_2_N_in ( p1796 ) , + .clk_2_E_in ( p78 ) , .clk_2_S_in ( p2675 ) , .clk_2_W_in ( p349 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3573 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3574 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3575 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3576 ) , .clk_3_W_in ( clk_3_wires[45] ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4979 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4980 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4981 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3577 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3578 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3579 ) , .clk_3_E_out ( clk_3_wires[48] ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4982 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4983 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4984 ) ) ; + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3580 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3581 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3582 ) ) ; sb_1__1_ sb_9__7_ ( .chany_top_in ( cby_1__1__103_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_103_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_103_right_width_0_height_0__pin_43_lower ) , @@ -67198,49 +70146,38 @@ sb_1__1_ sb_9__7_ ( .chany_top_in ( cby_1__1__103_chany_bottom_out ) , .chanx_right_out ( sb_1__1__94_chanx_right_out ) , .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) , .chanx_left_out ( sb_1__1__94_chanx_left_out ) , - .ccff_tail ( sb_1__1__94_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_4985 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4986 ) , + .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( p3123 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3583 ) , .prog_clk_0_N_in ( prog_clk_0_wires[352] ) , .prog_clk_1_N_in ( prog_clk_2_wires[102] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4987 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3584 ) , .prog_clk_1_E_out ( prog_clk_1_wires[190] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4988 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4989 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4990 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4991 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4992 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4993 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4994 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4995 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4996 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4997 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4998 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4999 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5000 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5001 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5002 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5003 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , .prog_clk_2_N_in ( p2876 ) , + .prog_clk_2_E_in ( p275 ) , .prog_clk_2_S_in ( p271 ) , + .prog_clk_2_W_in ( p2502 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3585 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3586 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3587 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3588 ) , + .prog_clk_3_W_in ( p3411 ) , .prog_clk_3_E_in ( p833 ) , + .prog_clk_3_S_in ( p95 ) , .prog_clk_3_N_in ( p2804 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3589 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3590 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3591 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3592 ) , .clk_1_N_in ( clk_2_wires[102] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5004 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3593 ) , .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5005 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5006 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5007 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5008 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5009 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5010 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5011 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5012 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5013 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5014 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5015 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5016 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5017 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5018 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5019 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5020 ) ) ; + .clk_2_N_in ( p3483 ) , .clk_2_E_in ( p1164 ) , .clk_2_S_in ( p3095 ) , + .clk_2_W_in ( p3405 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3594 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3595 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3596 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3597 ) , .clk_3_W_in ( p2591 ) , + .clk_3_E_in ( p1184 ) , .clk_3_S_in ( p1001 ) , .clk_3_N_in ( p3477 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3598 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3599 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3600 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3601 ) ) ; sb_1__1_ sb_9__8_ ( .chany_top_in ( cby_1__1__104_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_104_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_104_right_width_0_height_0__pin_43_lower ) , @@ -67282,49 +70219,40 @@ sb_1__1_ sb_9__8_ ( .chany_top_in ( cby_1__1__104_chany_bottom_out ) , .chanx_right_out ( sb_1__1__95_chanx_right_out ) , .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) , .chanx_left_out ( sb_1__1__95_chanx_left_out ) , - .ccff_tail ( sb_1__1__95_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5021 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5022 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5023 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5024 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5025 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5026 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5027 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5028 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5029 ) , + .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( p2617 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3602 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , .prog_clk_1_N_in ( p3210 ) , + .prog_clk_1_S_in ( p1275 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3603 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3604 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3605 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3606 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3607 ) , .prog_clk_2_W_in ( prog_clk_2_wires[92] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5030 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3608 ) , .prog_clk_2_S_out ( prog_clk_2_wires[101] ) , .prog_clk_2_N_out ( prog_clk_2_wires[99] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5031 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5032 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5033 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5034 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5035 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5036 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5037 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5038 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5039 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5040 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5041 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5042 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5043 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5044 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5045 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5046 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3609 ) , + .prog_clk_3_W_in ( p2163 ) , .prog_clk_3_E_in ( p366 ) , + .prog_clk_3_S_in ( p2458 ) , .prog_clk_3_N_in ( p1959 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3610 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3611 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3612 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3613 ) , .clk_1_N_in ( p2996 ) , + .clk_1_S_in ( p638 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3614 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3615 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3616 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3617 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3618 ) , .clk_2_W_in ( clk_2_wires[92] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5047 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3619 ) , .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5048 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5049 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5050 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5051 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5052 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5053 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5054 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5055 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5056 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3620 ) , .clk_3_W_in ( p2163 ) , + .clk_3_E_in ( p992 ) , .clk_3_S_in ( p494 ) , .clk_3_N_in ( p3181 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3621 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3622 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3623 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3624 ) ) ; sb_1__1_ sb_9__9_ ( .chany_top_in ( cby_1__1__105_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_105_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_105_right_width_0_height_0__pin_43_lower ) , @@ -67366,49 +70294,38 @@ sb_1__1_ sb_9__9_ ( .chany_top_in ( cby_1__1__105_chany_bottom_out ) , .chanx_right_out ( sb_1__1__96_chanx_right_out ) , .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) , .chanx_left_out ( sb_1__1__96_chanx_left_out ) , - .ccff_tail ( sb_1__1__96_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5057 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5058 ) , + .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( p2159 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3625 ) , .prog_clk_0_N_in ( prog_clk_0_wires[358] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5059 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3626 ) , .prog_clk_1_S_in ( prog_clk_2_wires[100] ) , .prog_clk_1_E_out ( prog_clk_1_wires[197] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5060 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5061 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5062 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5063 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5064 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5065 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5066 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5067 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5068 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5069 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5070 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5071 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5072 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5073 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5074 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5075 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5076 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , .prog_clk_2_N_in ( p3273 ) , + .prog_clk_2_E_in ( p1203 ) , .prog_clk_2_S_in ( p989 ) , + .prog_clk_2_W_in ( p165 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3627 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3628 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3629 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3630 ) , + .prog_clk_3_W_in ( p3334 ) , .prog_clk_3_E_in ( p603 ) , + .prog_clk_3_S_in ( p1444 ) , .prog_clk_3_N_in ( p3260 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3631 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3632 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3633 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3634 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3635 ) , .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) , - .clk_1_W_out ( clk_1_wires[198] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5077 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5078 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5079 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5080 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5081 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5082 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5083 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5084 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5085 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5086 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5087 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5088 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5089 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5090 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5091 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5092 ) ) ; + .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( p3394 ) , + .clk_2_E_in ( p70 ) , .clk_2_S_in ( p1899 ) , .clk_2_W_in ( p3316 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3636 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3637 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3638 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3639 ) , .clk_3_W_in ( p3122 ) , + .clk_3_E_in ( p1125 ) , .clk_3_S_in ( p364 ) , .clk_3_N_in ( p3361 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3640 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3641 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3642 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3643 ) ) ; sb_1__1_ sb_9__10_ ( .chany_top_in ( cby_1__1__106_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_106_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_106_right_width_0_height_0__pin_43_lower ) , @@ -67450,50 +70367,41 @@ sb_1__1_ sb_9__10_ ( .chany_top_in ( cby_1__1__106_chany_bottom_out ) , .chanx_right_out ( sb_1__1__97_chanx_right_out ) , .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) , .chanx_left_out ( sb_1__1__97_chanx_left_out ) , - .ccff_tail ( sb_1__1__97_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5093 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5094 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5095 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5096 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5097 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5098 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5099 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5100 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5101 ) , + .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( p1812 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3644 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , .prog_clk_1_N_in ( p3349 ) , + .prog_clk_1_S_in ( p193 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3645 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3646 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3647 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3648 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3649 ) , .prog_clk_2_W_in ( prog_clk_2_wires[105] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5102 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5103 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3650 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3651 ) , .prog_clk_2_N_out ( prog_clk_2_wires[110] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5104 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5105 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5106 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5107 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5108 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5109 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5110 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5111 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5112 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5113 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5114 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5115 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5116 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5117 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5118 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5119 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3652 ) , + .prog_clk_3_W_in ( p1581 ) , .prog_clk_3_E_in ( p182 ) , + .prog_clk_3_S_in ( p1136 ) , .prog_clk_3_N_in ( p2632 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3653 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3654 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3655 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3656 ) , .clk_1_N_in ( p2868 ) , + .clk_1_S_in ( p375 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3657 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3658 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3659 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3660 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3661 ) , .clk_2_W_in ( clk_2_wires[105] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5120 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5121 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3662 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3663 ) , .clk_2_N_out ( clk_2_wires[110] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5122 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5123 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5124 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5125 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5126 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5127 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5128 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5129 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5130 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3664 ) , .clk_3_W_in ( p1581 ) , + .clk_3_E_in ( p736 ) , .clk_3_S_in ( p489 ) , .clk_3_N_in ( p3309 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3665 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3666 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3667 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3668 ) ) ; sb_1__1_ sb_9__11_ ( .chany_top_in ( cby_1__1__107_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_107_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_107_right_width_0_height_0__pin_43_lower ) , @@ -67535,49 +70443,38 @@ sb_1__1_ sb_9__11_ ( .chany_top_in ( cby_1__1__107_chany_bottom_out ) , .chanx_right_out ( sb_1__1__98_chanx_right_out ) , .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) , .chanx_left_out ( sb_1__1__98_chanx_left_out ) , - .ccff_tail ( sb_1__1__98_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5131 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5132 ) , + .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( p2873 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3669 ) , .prog_clk_0_N_in ( prog_clk_0_wires[364] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5133 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3670 ) , .prog_clk_1_S_in ( prog_clk_2_wires[111] ) , .prog_clk_1_E_out ( prog_clk_1_wires[204] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5134 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5135 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5136 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5137 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5138 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5139 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5140 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5141 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5142 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5143 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5144 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5145 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5146 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5147 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5148 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5149 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5150 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , .prog_clk_2_N_in ( p3417 ) , + .prog_clk_2_E_in ( p841 ) , .prog_clk_2_S_in ( p990 ) , + .prog_clk_2_W_in ( p707 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3671 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3672 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3673 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3674 ) , + .prog_clk_3_W_in ( p3196 ) , .prog_clk_3_E_in ( p893 ) , + .prog_clk_3_S_in ( p120 ) , .prog_clk_3_N_in ( p3406 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3675 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3676 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3677 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3678 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3679 ) , .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) , - .clk_1_W_out ( clk_1_wires[205] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5151 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5152 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5153 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5154 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5155 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5156 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5157 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5158 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5159 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5160 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5161 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5162 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5163 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5164 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5165 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5166 ) ) ; + .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( p3520 ) , + .clk_2_E_in ( p1238 ) , .clk_2_S_in ( p2798 ) , .clk_2_W_in ( p3155 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3680 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3681 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3682 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3683 ) , .clk_3_W_in ( p2152 ) , + .clk_3_E_in ( p59 ) , .clk_3_S_in ( p785 ) , .clk_3_N_in ( p3519 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3684 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3685 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3686 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3687 ) ) ; sb_1__1_ sb_10__1_ ( .chany_top_in ( cby_1__1__109_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_109_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_109_right_width_0_height_0__pin_43_lower ) , @@ -67619,50 +70516,36 @@ sb_1__1_ sb_10__1_ ( .chany_top_in ( cby_1__1__109_chany_bottom_out ) , .chanx_right_out ( sb_1__1__99_chanx_right_out ) , .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) , .chanx_left_out ( sb_1__1__99_chanx_left_out ) , - .ccff_tail ( sb_1__1__99_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5167 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5168 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5169 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5170 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5171 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5172 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5173 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5174 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5175 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5176 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5177 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5178 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5179 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5180 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5181 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5182 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5183 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5184 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5185 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5186 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5187 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5188 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5189 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5190 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5191 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5192 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5193 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5194 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5195 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5196 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5197 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5198 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5199 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5200 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5201 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5202 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5203 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5204 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5205 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5206 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5207 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5208 ) ) ; + .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( p2901 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3688 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , .prog_clk_1_N_in ( p2711 ) , + .prog_clk_1_S_in ( p50 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3689 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3690 ) , + .prog_clk_2_N_in ( p3390 ) , .prog_clk_2_E_in ( p1117 ) , + .prog_clk_2_S_in ( p1292 ) , .prog_clk_2_W_in ( p1085 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3691 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3692 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3693 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3694 ) , + .prog_clk_3_W_in ( p2923 ) , .prog_clk_3_E_in ( p1101 ) , + .prog_clk_3_S_in ( p1391 ) , .prog_clk_3_N_in ( p3357 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3695 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3696 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3697 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3698 ) , .clk_1_N_in ( p2251 ) , + .clk_1_S_in ( p558 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3699 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3700 ) , .clk_2_N_in ( p3113 ) , + .clk_2_E_in ( p1293 ) , .clk_2_S_in ( p2835 ) , .clk_2_W_in ( p2953 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3701 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3702 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3703 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3704 ) , .clk_3_W_in ( p3007 ) , + .clk_3_E_in ( p30 ) , .clk_3_S_in ( p407 ) , .clk_3_N_in ( p3068 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3705 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3706 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3707 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3708 ) ) ; sb_1__1_ sb_10__2_ ( .chany_top_in ( cby_1__1__110_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_110_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_110_right_width_0_height_0__pin_43_lower ) , @@ -67704,50 +70587,41 @@ sb_1__1_ sb_10__2_ ( .chany_top_in ( cby_1__1__110_chany_bottom_out ) , .chanx_right_out ( sb_1__1__100_chanx_right_out ) , .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) , .chanx_left_out ( sb_1__1__100_chanx_left_out ) , - .ccff_tail ( sb_1__1__100_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5209 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5210 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5211 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5212 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5213 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5214 ) , + .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( p2376 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3709 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , .prog_clk_1_N_in ( p3225 ) , + .prog_clk_1_S_in ( p873 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3710 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3711 ) , .prog_clk_2_N_in ( prog_clk_3_wires[87] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5215 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5216 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5217 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5218 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5219 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5220 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5221 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5222 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5223 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5224 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5225 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5226 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5227 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5228 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5229 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5230 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5231 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5232 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3712 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3713 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3714 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3715 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3716 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3717 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , .prog_clk_3_W_in ( p2562 ) , + .prog_clk_3_E_in ( p2189 ) , .prog_clk_3_S_in ( p2211 ) , + .prog_clk_3_N_in ( p579 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3718 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3719 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3720 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3721 ) , .clk_1_N_in ( p2889 ) , + .clk_1_S_in ( p235 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3722 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3723 ) , .clk_2_N_in ( clk_3_wires[87] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5233 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5234 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5235 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5236 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5237 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5238 ) , - .clk_2_E_out ( clk_2_wires[114] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5239 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5240 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5241 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5242 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5243 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5244 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5245 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5246 ) ) ; + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3724 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3725 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3726 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3727 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3728 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3729 ) , + .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( p2614 ) , + .clk_3_E_in ( p2435 ) , .clk_3_S_in ( p1216 ) , .clk_3_N_in ( p3160 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3730 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3731 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3732 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3733 ) ) ; sb_1__1_ sb_10__3_ ( .chany_top_in ( cby_1__1__111_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_111_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_111_right_width_0_height_0__pin_43_lower ) , @@ -67789,49 +70663,40 @@ sb_1__1_ sb_10__3_ ( .chany_top_in ( cby_1__1__111_chany_bottom_out ) , .chanx_right_out ( sb_1__1__101_chanx_right_out ) , .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) , .chanx_left_out ( sb_1__1__101_chanx_left_out ) , - .ccff_tail ( sb_1__1__101_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5247 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5248 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5249 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5250 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5251 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5252 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5253 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5254 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5255 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5256 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5257 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5258 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5259 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5260 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5261 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5262 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5263 ) , + .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( p2795 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3734 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , .prog_clk_1_N_in ( p1744 ) , + .prog_clk_1_S_in ( p650 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3735 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3736 ) , + .prog_clk_2_N_in ( p1744 ) , .prog_clk_2_E_in ( p928 ) , + .prog_clk_2_S_in ( p1981 ) , .prog_clk_2_W_in ( p1022 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3737 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3738 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3739 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3740 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3741 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3742 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3743 ) , .prog_clk_3_N_in ( prog_clk_3_wires[83] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5264 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5265 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5266 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5267 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5268 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5269 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5270 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5271 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5272 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5273 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5274 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5275 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5276 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5277 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5278 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5279 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5280 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5281 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3744 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3745 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3746 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( p1744 ) , + .clk_1_S_in ( p1044 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3747 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3748 ) , .clk_2_N_in ( p1744 ) , + .clk_2_E_in ( p31 ) , .clk_2_S_in ( p2642 ) , .clk_2_W_in ( p303 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3749 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3750 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3751 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3752 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3753 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3754 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3755 ) , .clk_3_N_in ( clk_3_wires[83] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5282 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5283 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5284 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3756 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3757 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3758 ) , .clk_3_S_out ( clk_3_wires[86] ) ) ; sb_1__1_ sb_10__4_ ( .chany_top_in ( cby_1__1__112_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_112_right_width_0_height_0__pin_42_lower ) , @@ -67874,49 +70739,45 @@ sb_1__1_ sb_10__4_ ( .chany_top_in ( cby_1__1__112_chany_bottom_out ) , .chanx_right_out ( sb_1__1__102_chanx_right_out ) , .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) , .chanx_left_out ( sb_1__1__102_chanx_left_out ) , - .ccff_tail ( sb_1__1__102_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5285 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5286 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5287 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5288 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5289 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5290 ) , + .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( p1557 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3759 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , .prog_clk_1_N_in ( p1699 ) , + .prog_clk_1_S_in ( p329 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3760 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3761 ) , .prog_clk_2_N_in ( prog_clk_3_wires[77] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5291 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5292 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5293 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5294 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5295 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5296 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3762 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3763 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3764 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3765 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3766 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3767 ) , .prog_clk_2_E_out ( prog_clk_2_wires[119] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5297 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5298 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5299 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3768 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3769 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3770 ) , .prog_clk_3_N_in ( prog_clk_3_wires[77] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5300 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5301 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5302 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5303 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5304 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5305 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5306 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3771 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3772 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3773 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( p1699 ) , + .clk_1_S_in ( p457 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3774 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3775 ) , .clk_2_N_in ( clk_3_wires[77] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5307 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5308 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5309 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5310 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5311 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5312 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3776 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3777 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3778 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3779 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3780 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3781 ) , .clk_2_E_out ( clk_2_wires[119] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5313 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5314 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5315 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3782 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3783 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3784 ) , .clk_3_N_in ( clk_3_wires[77] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5316 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5317 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5318 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3785 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3786 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3787 ) , .clk_3_S_out ( clk_3_wires[82] ) ) ; sb_1__1_ sb_10__5_ ( .chany_top_in ( cby_1__1__113_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_113_right_width_0_height_0__pin_42_lower ) , @@ -67959,49 +70820,40 @@ sb_1__1_ sb_10__5_ ( .chany_top_in ( cby_1__1__113_chany_bottom_out ) , .chanx_right_out ( sb_1__1__103_chanx_right_out ) , .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) , .chanx_left_out ( sb_1__1__103_chanx_left_out ) , - .ccff_tail ( sb_1__1__103_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5319 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5320 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5321 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5322 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5323 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5324 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5325 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5326 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5327 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5328 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5329 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5330 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5331 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5332 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5333 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5334 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5335 ) , + .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( p2753 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3788 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , .prog_clk_1_N_in ( p1854 ) , + .prog_clk_1_S_in ( p942 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3789 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3790 ) , + .prog_clk_2_N_in ( p1854 ) , .prog_clk_2_E_in ( p174 ) , + .prog_clk_2_S_in ( p1172 ) , .prog_clk_2_W_in ( p249 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3791 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3792 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3793 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3794 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3795 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3796 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3797 ) , .prog_clk_3_N_in ( prog_clk_3_wires[73] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5336 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5337 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5338 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5339 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5340 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5341 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5342 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5343 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5344 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5345 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5346 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5347 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5348 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5349 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5350 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5351 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5352 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5353 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3798 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3799 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3800 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( p1685 ) , + .clk_1_S_in ( p142 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3801 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_2_N_in ( p1854 ) , + .clk_2_E_in ( p1056 ) , .clk_2_S_in ( p2643 ) , .clk_2_W_in ( p831 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3803 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3804 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3805 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3806 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3807 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3808 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3809 ) , .clk_3_N_in ( clk_3_wires[73] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5354 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5355 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5356 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3810 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3811 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3812 ) , .clk_3_S_out ( clk_3_wires[76] ) ) ; sb_1__1_ sb_10__6_ ( .chany_top_in ( cby_1__1__114_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_114_right_width_0_height_0__pin_42_lower ) , @@ -68044,48 +70896,39 @@ sb_1__1_ sb_10__6_ ( .chany_top_in ( cby_1__1__114_chany_bottom_out ) , .chanx_right_out ( sb_1__1__104_chanx_right_out ) , .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) , .chanx_left_out ( sb_1__1__104_chanx_left_out ) , - .ccff_tail ( sb_1__1__104_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5357 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5358 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5359 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5360 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5361 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5362 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5363 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5364 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5365 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5366 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5367 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5368 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5369 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5370 ) , + .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( p3116 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3813 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , .prog_clk_1_N_in ( p1362 ) , + .prog_clk_1_S_in ( p296 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3814 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3815 ) , + .prog_clk_2_N_in ( p1765 ) , .prog_clk_2_E_in ( p410 ) , + .prog_clk_2_S_in ( p2272 ) , .prog_clk_2_W_in ( p2459 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3816 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3817 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3818 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3819 ) , .prog_clk_3_W_in ( prog_clk_3_wires[49] ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5371 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5372 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5373 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5374 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5375 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3820 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3821 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3822 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3823 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3824 ) , .prog_clk_3_N_out ( prog_clk_3_wires[70] ) , - .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5376 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5377 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5378 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5379 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5380 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5381 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5382 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5383 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5384 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5385 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5386 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5387 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( p1362 ) , + .clk_1_S_in ( p676 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3825 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_2_N_in ( p1362 ) , + .clk_2_E_in ( p840 ) , .clk_2_S_in ( p3061 ) , .clk_2_W_in ( p1011 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3827 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3828 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3829 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3830 ) , .clk_3_W_in ( clk_3_wires[49] ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5388 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5389 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5390 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5391 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5392 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3831 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3832 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3833 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3834 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3835 ) , .clk_3_N_out ( clk_3_wires[70] ) , .clk_3_S_out ( clk_3_wires[72] ) ) ; sb_1__1_ sb_10__7_ ( .chany_top_in ( cby_1__1__115_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_115_right_width_0_height_0__pin_42_lower ) , @@ -68128,50 +70971,41 @@ sb_1__1_ sb_10__7_ ( .chany_top_in ( cby_1__1__115_chany_bottom_out ) , .chanx_right_out ( sb_1__1__105_chanx_right_out ) , .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) , .chanx_left_out ( sb_1__1__105_chanx_left_out ) , - .ccff_tail ( sb_1__1__105_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5393 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5394 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5395 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5396 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5397 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5398 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5399 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5400 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5401 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5402 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5403 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5404 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5405 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5406 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5407 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5408 ) , + .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( p1997 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3836 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , .prog_clk_1_N_in ( p1804 ) , + .prog_clk_1_S_in ( p418 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3837 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3838 ) , + .prog_clk_2_N_in ( p1804 ) , .prog_clk_2_E_in ( p673 ) , + .prog_clk_2_S_in ( p2201 ) , .prog_clk_2_W_in ( p1156 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3839 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3840 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3841 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3842 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3843 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3844 ) , .prog_clk_3_S_in ( prog_clk_3_wires[71] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5409 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5410 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5411 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3845 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3846 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3847 ) , .prog_clk_3_N_out ( prog_clk_3_wires[74] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5412 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5413 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5414 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5415 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5416 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5417 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5418 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5419 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5420 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5421 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5422 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5423 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5424 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5425 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5426 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3848 ) , .clk_1_N_in ( p1804 ) , + .clk_1_S_in ( p960 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3849 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3850 ) , .clk_2_N_in ( p1804 ) , + .clk_2_E_in ( p389 ) , .clk_2_S_in ( p1999 ) , .clk_2_W_in ( p54 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3851 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3852 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3853 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3854 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3855 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3856 ) , .clk_3_S_in ( clk_3_wires[71] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5427 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5428 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5429 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3857 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3858 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3859 ) , .clk_3_N_out ( clk_3_wires[74] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5430 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3860 ) ) ; sb_1__1_ sb_10__8_ ( .chany_top_in ( cby_1__1__116_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_116_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_116_right_width_0_height_0__pin_43_lower ) , @@ -68213,50 +71047,46 @@ sb_1__1_ sb_10__8_ ( .chany_top_in ( cby_1__1__116_chany_bottom_out ) , .chanx_right_out ( sb_1__1__106_chanx_right_out ) , .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) , .chanx_left_out ( sb_1__1__106_chanx_left_out ) , - .ccff_tail ( sb_1__1__106_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5431 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5432 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5433 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5434 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5435 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5436 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5437 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5438 ) , + .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( p1774 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3861 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , .prog_clk_1_N_in ( p1874 ) , + .prog_clk_1_S_in ( p427 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3862 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3863 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3864 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3865 ) , .prog_clk_2_S_in ( prog_clk_3_wires[75] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5439 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5440 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5441 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5442 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3866 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3867 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3868 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3869 ) , .prog_clk_2_E_out ( prog_clk_2_wires[126] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5443 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5444 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3870 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3871 ) , .prog_clk_3_S_in ( prog_clk_3_wires[75] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5445 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5446 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5447 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3872 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3873 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3874 ) , .prog_clk_3_N_out ( prog_clk_3_wires[80] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5448 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5449 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5450 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5451 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5452 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5453 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5454 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3875 ) , .clk_1_N_in ( p1874 ) , + .clk_1_S_in ( p1112 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3876 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3877 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3878 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3879 ) , .clk_2_S_in ( clk_3_wires[75] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5455 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5456 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5457 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5458 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3880 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3881 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3882 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3883 ) , .clk_2_E_out ( clk_2_wires[126] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5459 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5460 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3884 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3885 ) , .clk_3_S_in ( clk_3_wires[75] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5461 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5462 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5463 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3886 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3887 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3888 ) , .clk_3_N_out ( clk_3_wires[80] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5464 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3889 ) ) ; sb_1__1_ sb_10__9_ ( .chany_top_in ( cby_1__1__117_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_117_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_117_right_width_0_height_0__pin_43_lower ) , @@ -68298,50 +71128,41 @@ sb_1__1_ sb_10__9_ ( .chany_top_in ( cby_1__1__117_chany_bottom_out ) , .chanx_right_out ( sb_1__1__107_chanx_right_out ) , .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) , .chanx_left_out ( sb_1__1__107_chanx_left_out ) , - .ccff_tail ( sb_1__1__107_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5465 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5466 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5467 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5468 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5469 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5470 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5471 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5472 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5473 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5474 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5475 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5476 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5477 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5478 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5479 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5480 ) , + .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( p1663 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3890 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , .prog_clk_1_N_in ( p803 ) , + .prog_clk_1_S_in ( p860 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3891 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3892 ) , + .prog_clk_2_N_in ( p803 ) , .prog_clk_2_E_in ( p773 ) , + .prog_clk_2_S_in ( p1915 ) , .prog_clk_2_W_in ( p394 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3893 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3894 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3895 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3896 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3897 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3898 ) , .prog_clk_3_S_in ( prog_clk_3_wires[81] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5481 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5482 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5483 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3899 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3900 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3901 ) , .prog_clk_3_N_out ( prog_clk_3_wires[84] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5484 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5485 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5486 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5487 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5488 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5489 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5490 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5491 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5492 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5493 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5494 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5495 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5496 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5497 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5498 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3902 ) , .clk_1_N_in ( p803 ) , + .clk_1_S_in ( p38 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3903 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3904 ) , .clk_2_N_in ( p803 ) , + .clk_2_E_in ( p21 ) , .clk_2_S_in ( p542 ) , .clk_2_W_in ( p333 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3905 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3906 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3907 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3908 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3909 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3910 ) , .clk_3_S_in ( clk_3_wires[81] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5499 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5500 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5501 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3911 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3912 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3913 ) , .clk_3_N_out ( clk_3_wires[84] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5502 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3914 ) ) ; sb_1__1_ sb_10__10_ ( .chany_top_in ( cby_1__1__118_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_118_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_118_right_width_0_height_0__pin_43_lower ) , @@ -68383,50 +71204,41 @@ sb_1__1_ sb_10__10_ ( .chany_top_in ( cby_1__1__118_chany_bottom_out ) , .chanx_right_out ( sb_1__1__108_chanx_right_out ) , .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) , .chanx_left_out ( sb_1__1__108_chanx_left_out ) , - .ccff_tail ( sb_1__1__108_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5503 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5504 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5505 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5506 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5507 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5508 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5509 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5510 ) , + .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( p2361 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3915 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , .prog_clk_1_N_in ( p2563 ) , + .prog_clk_1_S_in ( p82 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3916 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3917 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3918 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3919 ) , .prog_clk_2_S_in ( prog_clk_3_wires[85] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5511 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5512 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5513 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5514 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5515 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5516 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5517 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5518 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5519 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5520 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5521 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5522 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5523 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5524 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5525 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5526 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5527 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5528 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3920 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3921 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3922 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3923 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , .prog_clk_3_W_in ( p1475 ) , + .prog_clk_3_E_in ( p262 ) , .prog_clk_3_S_in ( p2179 ) , + .prog_clk_3_N_in ( p1889 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3924 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3925 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3926 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3927 ) , .clk_1_N_in ( p2080 ) , + .clk_1_S_in ( p1271 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3928 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3929 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3930 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3931 ) , .clk_2_S_in ( clk_3_wires[85] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5529 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5530 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5531 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5532 ) , - .clk_2_E_out ( clk_2_wires[133] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5533 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5534 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5535 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5536 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5537 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5538 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5539 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5540 ) ) ; + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3932 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3933 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3934 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3935 ) , + .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( p1475 ) , + .clk_3_E_in ( p891 ) , .clk_3_S_in ( p552 ) , .clk_3_N_in ( p2460 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3936 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3937 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3938 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3939 ) ) ; sb_1__1_ sb_10__11_ ( .chany_top_in ( cby_1__1__119_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_119_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_119_right_width_0_height_0__pin_43_lower ) , @@ -68468,50 +71280,36 @@ sb_1__1_ sb_10__11_ ( .chany_top_in ( cby_1__1__119_chany_bottom_out ) , .chanx_right_out ( sb_1__1__109_chanx_right_out ) , .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) , .chanx_left_out ( sb_1__1__109_chanx_left_out ) , - .ccff_tail ( sb_1__1__109_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5541 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5542 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5543 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5544 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5545 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5546 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5547 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5548 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5549 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5550 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5551 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5552 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5553 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5554 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5555 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5556 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5557 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5558 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5559 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5560 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5561 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5562 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5563 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5564 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5565 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5566 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5567 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5568 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5569 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5570 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5571 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5572 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5573 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5574 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5575 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5576 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5577 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5578 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5579 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5580 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5581 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5582 ) ) ; + .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( p2877 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3940 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , .prog_clk_1_N_in ( p3208 ) , + .prog_clk_1_S_in ( p758 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3941 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3942 ) , + .prog_clk_2_N_in ( p3464 ) , .prog_clk_2_E_in ( p830 ) , + .prog_clk_2_S_in ( p307 ) , .prog_clk_2_W_in ( p111 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3943 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3944 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3945 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3946 ) , + .prog_clk_3_W_in ( p3490 ) , .prog_clk_3_E_in ( p185 ) , + .prog_clk_3_S_in ( p1432 ) , .prog_clk_3_N_in ( p3457 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3947 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3948 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3949 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3950 ) , .clk_1_N_in ( p3045 ) , + .clk_1_S_in ( p499 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3951 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3952 ) , .clk_2_N_in ( p3375 ) , + .clk_2_E_in ( p789 ) , .clk_2_S_in ( p2805 ) , .clk_2_W_in ( p3489 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3953 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3954 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3955 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3956 ) , .clk_3_W_in ( p2909 ) , + .clk_3_E_in ( p1012 ) , .clk_3_S_in ( p169 ) , .clk_3_N_in ( p3358 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3957 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3958 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3959 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3960 ) ) ; sb_1__1_ sb_11__1_ ( .chany_top_in ( cby_1__1__121_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_121_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_121_right_width_0_height_0__pin_43_lower ) , @@ -68553,49 +71351,38 @@ sb_1__1_ sb_11__1_ ( .chany_top_in ( cby_1__1__121_chany_bottom_out ) , .chanx_right_out ( sb_1__1__110_chanx_right_out ) , .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) , .chanx_left_out ( sb_1__1__110_chanx_left_out ) , - .ccff_tail ( sb_1__1__110_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5583 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5584 ) , + .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( p1702 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3961 ) , .prog_clk_0_N_in ( prog_clk_0_wires[410] ) , .prog_clk_1_N_in ( prog_clk_2_wires[116] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5585 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3962 ) , .prog_clk_1_E_out ( prog_clk_1_wires[211] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5586 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5587 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5588 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5589 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5590 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5591 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5592 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5593 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5594 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5595 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5596 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5597 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5598 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5599 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5600 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5601 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , .prog_clk_2_N_in ( p3463 ) , + .prog_clk_2_E_in ( p1325 ) , .prog_clk_2_S_in ( p136 ) , + .prog_clk_2_W_in ( p1274 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3963 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3964 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3965 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3966 ) , + .prog_clk_3_W_in ( p2776 ) , .prog_clk_3_E_in ( p402 ) , + .prog_clk_3_S_in ( p678 ) , .prog_clk_3_N_in ( p3453 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3967 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3968 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3969 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3970 ) , .clk_1_N_in ( clk_2_wires[116] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5602 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3971 ) , .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5603 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5604 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5605 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5606 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5607 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5608 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5609 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5610 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5611 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5612 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5613 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5614 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5615 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5616 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5617 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5618 ) ) ; + .clk_2_N_in ( p2519 ) , .clk_2_E_in ( p381 ) , .clk_2_S_in ( p1108 ) , + .clk_2_W_in ( p2974 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3972 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3973 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3974 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3975 ) , .clk_3_W_in ( p3008 ) , + .clk_3_E_in ( p611 ) , .clk_3_S_in ( p1069 ) , .clk_3_N_in ( p2445 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3976 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3977 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3978 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3979 ) ) ; sb_1__1_ sb_11__2_ ( .chany_top_in ( cby_1__1__122_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_122_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_122_right_width_0_height_0__pin_43_lower ) , @@ -68637,50 +71424,41 @@ sb_1__1_ sb_11__2_ ( .chany_top_in ( cby_1__1__122_chany_bottom_out ) , .chanx_right_out ( sb_1__1__111_chanx_right_out ) , .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) , .chanx_left_out ( sb_1__1__111_chanx_left_out ) , - .ccff_tail ( sb_1__1__111_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5619 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5620 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5621 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5622 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5623 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5624 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5625 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5626 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5627 ) , + .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( p1487 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3980 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , .prog_clk_1_N_in ( p3290 ) , + .prog_clk_1_S_in ( p4 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3981 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3982 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3983 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3984 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3985 ) , .prog_clk_2_W_in ( prog_clk_2_wires[113] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5628 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3986 ) , .prog_clk_2_S_out ( prog_clk_2_wires[115] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5629 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5630 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5631 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5632 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5633 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5634 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5635 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5636 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5637 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5638 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5639 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5640 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5641 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5642 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5643 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5644 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5645 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3987 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3988 ) , + .prog_clk_3_W_in ( p2124 ) , .prog_clk_3_E_in ( p334 ) , + .prog_clk_3_S_in ( p587 ) , .prog_clk_3_N_in ( p1978 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3989 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3990 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3991 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3992 ) , .clk_1_N_in ( p2566 ) , + .clk_1_S_in ( p1205 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3993 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3994 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3995 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3996 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3997 ) , .clk_2_W_in ( clk_2_wires[113] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5646 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3998 ) , .clk_2_S_out ( clk_2_wires[115] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5647 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5648 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5649 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5650 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5651 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5652 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5653 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5654 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5655 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5656 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3999 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4000 ) , .clk_3_W_in ( p2124 ) , + .clk_3_E_in ( p1010 ) , .clk_3_S_in ( p365 ) , .clk_3_N_in ( p3250 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4001 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4002 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4003 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4004 ) ) ; sb_1__1_ sb_11__3_ ( .chany_top_in ( cby_1__1__123_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_123_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_123_right_width_0_height_0__pin_43_lower ) , @@ -68722,49 +71500,38 @@ sb_1__1_ sb_11__3_ ( .chany_top_in ( cby_1__1__123_chany_bottom_out ) , .chanx_right_out ( sb_1__1__112_chanx_right_out ) , .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) , .chanx_left_out ( sb_1__1__112_chanx_left_out ) , - .ccff_tail ( sb_1__1__112_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5657 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5658 ) , + .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( p2527 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4005 ) , .prog_clk_0_N_in ( prog_clk_0_wires[416] ) , .prog_clk_1_N_in ( prog_clk_2_wires[123] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5659 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4006 ) , .prog_clk_1_E_out ( prog_clk_1_wires[218] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5660 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5661 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5662 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5663 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5664 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5665 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5666 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5667 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5668 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5669 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5670 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5671 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5672 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5673 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5674 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5675 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , .prog_clk_2_N_in ( p3419 ) , + .prog_clk_2_E_in ( p909 ) , .prog_clk_2_S_in ( p1060 ) , + .prog_clk_2_W_in ( p160 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4007 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4008 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4009 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4010 ) , + .prog_clk_3_W_in ( p2620 ) , .prog_clk_3_E_in ( p943 ) , + .prog_clk_3_S_in ( p1310 ) , .prog_clk_3_N_in ( p3398 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4011 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4012 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4013 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4014 ) , .clk_1_N_in ( clk_2_wires[123] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5676 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4015 ) , .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5677 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5678 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5679 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5680 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5681 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5682 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5683 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5684 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5685 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5686 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5687 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5688 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5689 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5690 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5691 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5692 ) ) ; + .clk_2_N_in ( p3138 ) , .clk_2_E_in ( p613 ) , .clk_2_S_in ( p2494 ) , + .clk_2_W_in ( p3404 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4016 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4017 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4018 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4019 ) , .clk_3_W_in ( p3420 ) , + .clk_3_E_in ( p263 ) , .clk_3_S_in ( p101 ) , .clk_3_N_in ( p3067 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4020 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4021 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4022 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4023 ) ) ; sb_1__1_ sb_11__4_ ( .chany_top_in ( cby_1__1__124_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_124_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_124_right_width_0_height_0__pin_43_lower ) , @@ -68806,49 +71573,40 @@ sb_1__1_ sb_11__4_ ( .chany_top_in ( cby_1__1__124_chany_bottom_out ) , .chanx_right_out ( sb_1__1__113_chanx_right_out ) , .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) , .chanx_left_out ( sb_1__1__113_chanx_left_out ) , - .ccff_tail ( sb_1__1__113_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5693 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5694 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5695 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5696 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5697 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5698 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5699 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5700 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5701 ) , + .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( p2903 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4024 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , .prog_clk_1_N_in ( p3389 ) , + .prog_clk_1_S_in ( p139 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4025 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4026 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4027 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4028 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4029 ) , .prog_clk_2_W_in ( prog_clk_2_wires[118] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5702 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4030 ) , .prog_clk_2_S_out ( prog_clk_2_wires[122] ) , .prog_clk_2_N_out ( prog_clk_2_wires[120] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5703 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5704 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5705 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5706 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5707 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5708 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5709 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5710 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5711 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5712 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5713 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5714 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5715 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5716 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5717 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5718 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4031 ) , + .prog_clk_3_W_in ( p1641 ) , .prog_clk_3_E_in ( p1273 ) , + .prog_clk_3_S_in ( p2826 ) , .prog_clk_3_N_in ( p385 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4032 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4033 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4034 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4035 ) , .clk_1_N_in ( p1272 ) , + .clk_1_S_in ( p1045 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4036 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4037 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4038 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4039 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4040 ) , .clk_2_W_in ( clk_2_wires[118] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5719 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4041 ) , .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5720 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5721 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5722 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5723 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5724 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5725 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5726 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5727 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5728 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4042 ) , .clk_3_W_in ( p1641 ) , + .clk_3_E_in ( p519 ) , .clk_3_S_in ( p1178 ) , .clk_3_N_in ( p3365 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4043 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4044 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4045 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4046 ) ) ; sb_1__1_ sb_11__5_ ( .chany_top_in ( cby_1__1__125_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_125_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_125_right_width_0_height_0__pin_43_lower ) , @@ -68890,49 +71648,38 @@ sb_1__1_ sb_11__5_ ( .chany_top_in ( cby_1__1__125_chany_bottom_out ) , .chanx_right_out ( sb_1__1__114_chanx_right_out ) , .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) , .chanx_left_out ( sb_1__1__114_chanx_left_out ) , - .ccff_tail ( sb_1__1__114_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5729 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5730 ) , + .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( p2742 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4047 ) , .prog_clk_0_N_in ( prog_clk_0_wires[422] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5731 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4048 ) , .prog_clk_1_S_in ( prog_clk_2_wires[121] ) , .prog_clk_1_E_out ( prog_clk_1_wires[225] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5732 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5733 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5734 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5735 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5736 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5737 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5738 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5739 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5740 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5741 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5742 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5743 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5744 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5745 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5746 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5747 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5748 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , .prog_clk_2_N_in ( p3341 ) , + .prog_clk_2_E_in ( p1190 ) , .prog_clk_2_S_in ( p576 ) , + .prog_clk_2_W_in ( p998 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4049 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4050 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4051 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4052 ) , + .prog_clk_3_W_in ( p3217 ) , .prog_clk_3_E_in ( p817 ) , + .prog_clk_3_S_in ( p970 ) , .prog_clk_3_N_in ( p3314 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4053 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4054 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4055 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4056 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4057 ) , .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) , - .clk_1_W_out ( clk_1_wires[226] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5749 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5750 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5751 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5752 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5753 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5754 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5755 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5756 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5757 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5758 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5759 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5760 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5761 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5762 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5763 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5764 ) ) ; + .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( p3035 ) , + .clk_2_E_in ( p737 ) , .clk_2_S_in ( p2665 ) , .clk_2_W_in ( p3164 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4058 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4059 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4060 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4061 ) , .clk_3_W_in ( p2123 ) , + .clk_3_E_in ( p123 ) , .clk_3_S_in ( p227 ) , .clk_3_N_in ( p2971 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4062 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4063 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4064 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4065 ) ) ; sb_1__1_ sb_11__6_ ( .chany_top_in ( cby_1__1__126_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_126_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_126_right_width_0_height_0__pin_43_lower ) , @@ -68974,50 +71721,36 @@ sb_1__1_ sb_11__6_ ( .chany_top_in ( cby_1__1__126_chany_bottom_out ) , .chanx_right_out ( sb_1__1__115_chanx_right_out ) , .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) , .chanx_left_out ( sb_1__1__115_chanx_left_out ) , - .ccff_tail ( sb_1__1__115_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5765 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5766 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5767 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5768 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5769 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5770 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5771 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5772 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5773 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5774 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5775 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5776 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5777 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5778 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5779 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5780 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5781 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5782 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5783 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5784 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5785 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5786 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5787 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5788 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5789 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5790 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5791 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5792 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5793 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5794 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5795 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5796 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5797 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5798 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5799 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5800 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5801 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5802 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5805 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5806 ) ) ; + .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( p2311 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4066 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , .prog_clk_1_N_in ( p2505 ) , + .prog_clk_1_S_in ( p606 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4067 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4068 ) , + .prog_clk_2_N_in ( p3387 ) , .prog_clk_2_E_in ( p108 ) , + .prog_clk_2_S_in ( p183 ) , .prog_clk_2_W_in ( p422 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4069 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4070 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4071 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4072 ) , + .prog_clk_3_W_in ( p2411 ) , .prog_clk_3_E_in ( p338 ) , + .prog_clk_3_S_in ( p1267 ) , .prog_clk_3_N_in ( p3362 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4073 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4074 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4075 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_1_N_in ( p2399 ) , + .clk_1_S_in ( p1057 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4077 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4078 ) , .clk_2_N_in ( p3493 ) , + .clk_2_E_in ( p1379 ) , .clk_2_S_in ( p2207 ) , .clk_2_W_in ( p2818 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4079 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4080 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4081 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4082 ) , .clk_3_W_in ( p2932 ) , + .clk_3_E_in ( p403 ) , .clk_3_S_in ( p328 ) , .clk_3_N_in ( p3487 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4083 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4084 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4085 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4086 ) ) ; sb_1__1_ sb_11__7_ ( .chany_top_in ( cby_1__1__127_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_127_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_127_right_width_0_height_0__pin_43_lower ) , @@ -69059,49 +71792,38 @@ sb_1__1_ sb_11__7_ ( .chany_top_in ( cby_1__1__127_chany_bottom_out ) , .chanx_right_out ( sb_1__1__116_chanx_right_out ) , .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) , .chanx_left_out ( sb_1__1__116_chanx_left_out ) , - .ccff_tail ( sb_1__1__116_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5807 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5808 ) , + .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( p2135 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4087 ) , .prog_clk_0_N_in ( prog_clk_0_wires[428] ) , .prog_clk_1_N_in ( prog_clk_2_wires[130] ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5809 ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4088 ) , .prog_clk_1_E_out ( prog_clk_1_wires[232] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5810 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5811 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5812 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5813 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5814 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5815 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5816 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5817 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5818 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5819 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5820 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5821 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5822 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5823 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5824 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5825 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , .prog_clk_2_N_in ( p3292 ) , + .prog_clk_2_E_in ( p1241 ) , .prog_clk_2_S_in ( p496 ) , + .prog_clk_2_W_in ( p863 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4089 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4090 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4091 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4092 ) , + .prog_clk_3_W_in ( p3195 ) , .prog_clk_3_E_in ( p783 ) , + .prog_clk_3_S_in ( p107 ) , .prog_clk_3_N_in ( p3243 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4093 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4094 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4095 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4096 ) , .clk_1_N_in ( clk_2_wires[130] ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5826 ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4097 ) , .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5827 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5828 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5829 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5830 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5831 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5832 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5833 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5835 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5836 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5837 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5838 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5839 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5840 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5841 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5842 ) ) ; + .clk_2_N_in ( p2875 ) , .clk_2_E_in ( p423 ) , .clk_2_S_in ( p1911 ) , + .clk_2_W_in ( p3165 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4098 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4099 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4100 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4101 ) , .clk_3_W_in ( p3132 ) , + .clk_3_E_in ( p692 ) , .clk_3_S_in ( p781 ) , .clk_3_N_in ( p2822 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4102 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4103 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4104 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4105 ) ) ; sb_1__1_ sb_11__8_ ( .chany_top_in ( cby_1__1__128_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_128_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_128_right_width_0_height_0__pin_43_lower ) , @@ -69143,49 +71865,40 @@ sb_1__1_ sb_11__8_ ( .chany_top_in ( cby_1__1__128_chany_bottom_out ) , .chanx_right_out ( sb_1__1__117_chanx_right_out ) , .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) , .chanx_left_out ( sb_1__1__117_chanx_left_out ) , - .ccff_tail ( sb_1__1__117_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5843 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5844 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5845 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5846 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5847 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5848 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5849 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5850 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5851 ) , + .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( p2774 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4106 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , .prog_clk_1_N_in ( p3424 ) , + .prog_clk_1_S_in ( p602 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4107 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4108 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4109 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4110 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4111 ) , .prog_clk_2_W_in ( prog_clk_2_wires[125] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5852 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4112 ) , .prog_clk_2_S_out ( prog_clk_2_wires[129] ) , .prog_clk_2_N_out ( prog_clk_2_wires[127] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5853 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5854 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5855 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5856 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5857 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5858 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5859 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5860 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5861 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5862 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5863 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5864 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5865 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5866 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5867 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5868 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4113 ) , + .prog_clk_3_W_in ( p1741 ) , .prog_clk_3_E_in ( p950 ) , + .prog_clk_3_S_in ( p2651 ) , .prog_clk_3_N_in ( p1923 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4114 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4115 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4116 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4117 ) , .clk_1_N_in ( p2088 ) , + .clk_1_S_in ( p847 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4118 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4119 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4120 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4121 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4122 ) , .clk_2_W_in ( clk_2_wires[125] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5869 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4123 ) , .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5870 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5871 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5872 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5873 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5874 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5875 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5876 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5877 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5878 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4124 ) , .clk_3_W_in ( p1879 ) , + .clk_3_E_in ( p85 ) , .clk_3_S_in ( p206 ) , .clk_3_N_in ( p3403 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4125 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4126 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4127 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4128 ) ) ; sb_1__1_ sb_11__9_ ( .chany_top_in ( cby_1__1__129_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_129_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_129_right_width_0_height_0__pin_43_lower ) , @@ -69227,49 +71940,38 @@ sb_1__1_ sb_11__9_ ( .chany_top_in ( cby_1__1__129_chany_bottom_out ) , .chanx_right_out ( sb_1__1__118_chanx_right_out ) , .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) , .chanx_left_out ( sb_1__1__118_chanx_left_out ) , - .ccff_tail ( sb_1__1__118_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5879 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5880 ) , + .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( p2090 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4129 ) , .prog_clk_0_N_in ( prog_clk_0_wires[434] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5881 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4130 ) , .prog_clk_1_S_in ( prog_clk_2_wires[128] ) , .prog_clk_1_E_out ( prog_clk_1_wires[239] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5882 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5883 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5884 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5885 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5886 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5887 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5888 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5889 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5890 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5891 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5892 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5893 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5894 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5895 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5896 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5897 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5898 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , .prog_clk_2_N_in ( p3396 ) , + .prog_clk_2_E_in ( p805 ) , .prog_clk_2_S_in ( p601 ) , + .prog_clk_2_W_in ( p1118 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4131 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4132 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4133 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4134 ) , + .prog_clk_3_W_in ( p3234 ) , .prog_clk_3_E_in ( p1237 ) , + .prog_clk_3_S_in ( p10 ) , .prog_clk_3_N_in ( p3373 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4135 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4136 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4137 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4138 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4139 ) , .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) , - .clk_1_W_out ( clk_1_wires[240] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5899 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5900 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5901 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5902 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5903 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5904 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5905 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5906 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5907 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5908 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5909 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5910 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5911 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5912 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5913 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5914 ) ) ; + .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( p3494 ) , + .clk_2_E_in ( p1397 ) , .clk_2_S_in ( p1946 ) , .clk_2_W_in ( p3177 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4140 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4141 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4142 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4143 ) , .clk_3_W_in ( p2927 ) , + .clk_3_E_in ( p75 ) , .clk_3_S_in ( p1167 ) , .clk_3_N_in ( p3485 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4144 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4145 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4146 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4147 ) ) ; sb_1__1_ sb_11__10_ ( .chany_top_in ( cby_1__1__130_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_130_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_130_right_width_0_height_0__pin_43_lower ) , @@ -69311,50 +72013,41 @@ sb_1__1_ sb_11__10_ ( .chany_top_in ( cby_1__1__130_chany_bottom_out ) , .chanx_right_out ( sb_1__1__119_chanx_right_out ) , .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) , .chanx_left_out ( sb_1__1__119_chanx_left_out ) , - .ccff_tail ( sb_1__1__119_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5915 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5916 ) , - .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5917 ) , - .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5918 ) , - .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5919 ) , - .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5920 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5921 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5922 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5923 ) , + .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( p1985 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4148 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , .prog_clk_1_N_in ( p3041 ) , + .prog_clk_1_S_in ( p864 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4149 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4150 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4151 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4152 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4153 ) , .prog_clk_2_W_in ( prog_clk_2_wires[132] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5924 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5925 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4154 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4155 ) , .prog_clk_2_N_out ( prog_clk_2_wires[134] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5926 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5927 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5928 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5929 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5930 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5932 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5933 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5934 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5935 ) , - .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5936 ) , - .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5937 ) , - .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5938 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5939 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5940 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5941 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4156 ) , + .prog_clk_3_W_in ( p2578 ) , .prog_clk_3_E_in ( p379 ) , + .prog_clk_3_S_in ( p1910 ) , .prog_clk_3_N_in ( p2191 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4157 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4158 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4159 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4160 ) , .clk_1_N_in ( p2544 ) , + .clk_1_S_in ( p184 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4161 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4162 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4163 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4164 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4165 ) , .clk_2_W_in ( clk_2_wires[132] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5942 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5943 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4166 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4167 ) , .clk_2_N_out ( clk_2_wires[134] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5944 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5945 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5946 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5947 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5948 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5949 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5950 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5951 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5952 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4168 ) , .clk_3_W_in ( p2578 ) , + .clk_3_E_in ( p71 ) , .clk_3_S_in ( p1035 ) , .clk_3_N_in ( p2944 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4169 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4170 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4171 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4172 ) ) ; sb_1__1_ sb_11__11_ ( .chany_top_in ( cby_1__1__131_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_131_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_131_right_width_0_height_0__pin_43_lower ) , @@ -69396,49 +72089,38 @@ sb_1__1_ sb_11__11_ ( .chany_top_in ( cby_1__1__131_chany_bottom_out ) , .chanx_right_out ( sb_1__1__120_chanx_right_out ) , .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) , .chanx_left_out ( sb_1__1__120_chanx_left_out ) , - .ccff_tail ( sb_1__1__120_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5953 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5954 ) , + .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( p2902 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4173 ) , .prog_clk_0_N_in ( prog_clk_0_wires[440] ) , - .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5955 ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4174 ) , .prog_clk_1_S_in ( prog_clk_2_wires[135] ) , .prog_clk_1_E_out ( prog_clk_1_wires[246] ) , - .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5956 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5957 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5958 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5959 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5960 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5961 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5962 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5963 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5964 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5965 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_5966 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5967 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5968 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5969 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5970 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5971 ) , - .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5972 ) , + .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , .prog_clk_2_N_in ( p3291 ) , + .prog_clk_2_E_in ( p1130 ) , .prog_clk_2_S_in ( p594 ) , + .prog_clk_2_W_in ( p387 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4175 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4176 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4177 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4178 ) , + .prog_clk_3_W_in ( p2773 ) , .prog_clk_3_E_in ( p1014 ) , + .prog_clk_3_S_in ( p1195 ) , .prog_clk_3_N_in ( p3261 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4179 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4180 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4181 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4182 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4183 ) , .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) , - .clk_1_W_out ( clk_1_wires[247] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5973 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5974 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5975 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5976 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5977 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5978 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5979 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5980 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5981 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5982 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_5983 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5984 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5985 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5986 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5987 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5988 ) ) ; + .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( p3350 ) , + .clk_2_E_in ( p1318 ) , .clk_2_S_in ( p2839 ) , .clk_2_W_in ( p2809 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4184 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4185 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4186 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4187 ) , .clk_3_W_in ( p2872 ) , + .clk_3_E_in ( p362 ) , .clk_3_S_in ( p188 ) , .clk_3_N_in ( p3323 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4188 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4189 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4190 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4191 ) ) ; sb_1__2_ sb_1__12_ ( .chanx_right_in ( cbx_1__12__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_23_top_width_0_height_0__pin_34_upper ) , @@ -69472,9 +72154,8 @@ sb_1__2_ sb_1__12_ ( .chanx_right_in ( cbx_1__12__1_chanx_left_out ) , .chanx_right_out ( sb_1__12__0_chanx_right_out ) , .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) , .chanx_left_out ( sb_1__12__0_chanx_left_out ) , - .ccff_tail ( sb_1__12__0_ccff_tail ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5989 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5990 ) , + .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( p1368 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4192 ) , .prog_clk_0_S_in ( prog_clk_0_wires[60] ) ) ; sb_1__2_ sb_2__12_ ( .chanx_right_in ( cbx_1__12__2_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , @@ -69545,9 +72226,8 @@ sb_1__2_ sb_3__12_ ( .chanx_right_in ( cbx_1__12__3_chanx_left_out ) , .chanx_right_out ( sb_1__12__2_chanx_right_out ) , .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) , .chanx_left_out ( sb_1__12__2_chanx_left_out ) , - .ccff_tail ( sb_1__12__2_ccff_tail ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5991 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5992 ) , + .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( p1422 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4193 ) , .prog_clk_0_S_in ( prog_clk_0_wires[138] ) ) ; sb_1__2_ sb_4__12_ ( .chanx_right_in ( cbx_1__12__4_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , @@ -69618,9 +72298,8 @@ sb_1__2_ sb_5__12_ ( .chanx_right_in ( cbx_1__12__5_chanx_left_out ) , .chanx_right_out ( sb_1__12__4_chanx_right_out ) , .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) , .chanx_left_out ( sb_1__12__4_chanx_left_out ) , - .ccff_tail ( sb_1__12__4_ccff_tail ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5993 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5994 ) , + .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( p1589 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4194 ) , .prog_clk_0_S_in ( prog_clk_0_wires[214] ) ) ; sb_1__2_ sb_6__12_ ( .chanx_right_in ( cbx_1__12__6_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , @@ -69691,9 +72370,8 @@ sb_1__2_ sb_7__12_ ( .chanx_right_in ( cbx_1__12__7_chanx_left_out ) , .chanx_right_out ( sb_1__12__6_chanx_right_out ) , .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) , .chanx_left_out ( sb_1__12__6_chanx_left_out ) , - .ccff_tail ( sb_1__12__6_ccff_tail ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5995 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5996 ) , + .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( p1652 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4195 ) , .prog_clk_0_S_in ( prog_clk_0_wires[290] ) ) ; sb_1__2_ sb_8__12_ ( .chanx_right_in ( cbx_1__12__8_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , @@ -69764,9 +72442,8 @@ sb_1__2_ sb_9__12_ ( .chanx_right_in ( cbx_1__12__9_chanx_left_out ) , .chanx_right_out ( sb_1__12__8_chanx_right_out ) , .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) , .chanx_left_out ( sb_1__12__8_chanx_left_out ) , - .ccff_tail ( sb_1__12__8_ccff_tail ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5997 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5998 ) , + .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( p1523 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4196 ) , .prog_clk_0_S_in ( prog_clk_0_wires[366] ) ) ; sb_1__2_ sb_10__12_ ( .chanx_right_in ( cbx_1__12__10_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , @@ -69837,9 +72514,8 @@ sb_1__2_ sb_11__12_ ( .chanx_right_in ( cbx_1__12__11_chanx_left_out ) , .chanx_right_out ( sb_1__12__10_chanx_right_out ) , .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) , .chanx_left_out ( sb_1__12__10_chanx_left_out ) , - .ccff_tail ( sb_1__12__10_ccff_tail ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5999 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6000 ) , + .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( p1533 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4197 ) , .prog_clk_0_S_in ( prog_clk_0_wires[442] ) ) ; sb_2__0_ sb_12__0_ ( .chany_top_in ( cby_12__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_132_right_width_0_height_0__pin_42_lower ) , @@ -70322,8 +72998,7 @@ cbx_1__0_ cbx_1__0_ ( .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6001 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6002 ) , + .SC_IN_BOT ( p1123 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4198 ) , .prog_clk_0_N_in ( prog_clk_0_wires[0] ) , .prog_clk_0_W_out ( prog_clk_0_wires[5] ) ) ; cbx_1__0_ cbx_2__0_ ( .chanx_left_in ( sb_1__0__0_chanx_right_out ) , @@ -70371,11 +73046,10 @@ cbx_1__0_ cbx_2__0_ ( .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6003 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6004 ) , + .SC_IN_TOP ( p1466 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4199 ) , .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) , .prog_clk_0_N_in ( prog_clk_0_wires[63] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6005 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4200 ) ) ; cbx_1__0_ cbx_3__0_ ( .chanx_left_in ( sb_1__0__1_chanx_right_out ) , .chanx_right_in ( sb_1__0__2_chanx_left_out ) , .ccff_head ( sb_1__0__2_ccff_tail ) , @@ -70422,10 +73096,9 @@ cbx_1__0_ cbx_3__0_ ( .chanx_left_in ( sb_1__0__1_chanx_right_out ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6006 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6007 ) , + .SC_IN_BOT ( p1616 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4201 ) , .prog_clk_0_N_in ( prog_clk_0_wires[101] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6008 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4202 ) ) ; cbx_1__0_ cbx_4__0_ ( .chanx_left_in ( sb_1__0__2_chanx_right_out ) , .chanx_right_in ( sb_1__0__3_chanx_left_out ) , .ccff_head ( sb_1__0__3_ccff_tail ) , @@ -70471,11 +73144,10 @@ cbx_1__0_ cbx_4__0_ ( .chanx_left_in ( sb_1__0__2_chanx_right_out ) , .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6009 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6010 ) , + .SC_IN_TOP ( p1522 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4203 ) , .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) , .prog_clk_0_N_in ( prog_clk_0_wires[139] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6011 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4204 ) ) ; cbx_1__0_ cbx_5__0_ ( .chanx_left_in ( sb_1__0__3_chanx_right_out ) , .chanx_right_in ( sb_1__0__4_chanx_left_out ) , .ccff_head ( sb_1__0__4_ccff_tail ) , @@ -70522,10 +73194,9 @@ cbx_1__0_ cbx_5__0_ ( .chanx_left_in ( sb_1__0__3_chanx_right_out ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6012 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6013 ) , + .SC_IN_BOT ( p1646 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4205 ) , .prog_clk_0_N_in ( prog_clk_0_wires[177] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6014 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4206 ) ) ; cbx_1__0_ cbx_6__0_ ( .chanx_left_in ( sb_1__0__4_chanx_right_out ) , .chanx_right_in ( sb_1__0__5_chanx_left_out ) , .ccff_head ( sb_1__0__5_ccff_tail ) , @@ -70571,11 +73242,10 @@ cbx_1__0_ cbx_6__0_ ( .chanx_left_in ( sb_1__0__4_chanx_right_out ) , .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6015 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6016 ) , + .SC_IN_TOP ( p1480 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4207 ) , .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) , .prog_clk_0_N_in ( prog_clk_0_wires[215] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6017 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4208 ) ) ; cbx_1__0_ cbx_7__0_ ( .chanx_left_in ( sb_1__0__5_chanx_right_out ) , .chanx_right_in ( sb_1__0__6_chanx_left_out ) , .ccff_head ( sb_1__0__6_ccff_tail ) , @@ -70622,10 +73292,9 @@ cbx_1__0_ cbx_7__0_ ( .chanx_left_in ( sb_1__0__5_chanx_right_out ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6018 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6019 ) , + .SC_IN_BOT ( p2028 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4209 ) , .prog_clk_0_N_in ( prog_clk_0_wires[253] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6020 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4210 ) ) ; cbx_1__0_ cbx_8__0_ ( .chanx_left_in ( sb_1__0__6_chanx_right_out ) , .chanx_right_in ( sb_1__0__7_chanx_left_out ) , .ccff_head ( sb_1__0__7_ccff_tail ) , @@ -70671,11 +73340,10 @@ cbx_1__0_ cbx_8__0_ ( .chanx_left_in ( sb_1__0__6_chanx_right_out ) , .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6021 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6022 ) , + .SC_IN_TOP ( p1052 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4211 ) , .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) , .prog_clk_0_N_in ( prog_clk_0_wires[291] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6023 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4212 ) ) ; cbx_1__0_ cbx_9__0_ ( .chanx_left_in ( sb_1__0__7_chanx_right_out ) , .chanx_right_in ( sb_1__0__8_chanx_left_out ) , .ccff_head ( sb_1__0__8_ccff_tail ) , @@ -70722,10 +73390,9 @@ cbx_1__0_ cbx_9__0_ ( .chanx_left_in ( sb_1__0__7_chanx_right_out ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6024 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6025 ) , + .SC_IN_BOT ( p1661 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4213 ) , .prog_clk_0_N_in ( prog_clk_0_wires[329] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6026 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4214 ) ) ; cbx_1__0_ cbx_10__0_ ( .chanx_left_in ( sb_1__0__8_chanx_right_out ) , .chanx_right_in ( sb_1__0__9_chanx_left_out ) , .ccff_head ( sb_1__0__9_ccff_tail ) , @@ -70771,11 +73438,10 @@ cbx_1__0_ cbx_10__0_ ( .chanx_left_in ( sb_1__0__8_chanx_right_out ) , .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6027 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6028 ) , + .SC_IN_TOP ( p1433 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4215 ) , .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) , .prog_clk_0_N_in ( prog_clk_0_wires[367] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6029 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4216 ) ) ; cbx_1__0_ cbx_11__0_ ( .chanx_left_in ( sb_1__0__9_chanx_right_out ) , .chanx_right_in ( sb_1__0__10_chanx_left_out ) , .ccff_head ( sb_1__0__10_ccff_tail ) , @@ -70822,10 +73488,9 @@ cbx_1__0_ cbx_11__0_ ( .chanx_left_in ( sb_1__0__9_chanx_right_out ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6030 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6031 ) , + .SC_IN_BOT ( p2022 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4217 ) , .prog_clk_0_N_in ( prog_clk_0_wires[405] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6032 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4218 ) ) ; cbx_1__0_ cbx_12__0_ ( .chanx_left_in ( sb_1__0__10_chanx_right_out ) , .chanx_right_in ( sb_12__0__0_chanx_left_out ) , .ccff_head ( sb_12__0__0_ccff_tail ) , @@ -70871,11 +73536,10 @@ cbx_1__0_ cbx_12__0_ ( .chanx_left_in ( sb_1__0__10_chanx_right_out ) , .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6033 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6034 ) , + .SC_IN_TOP ( p1514 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4219 ) , .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) , .prog_clk_0_N_in ( prog_clk_0_wires[443] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6035 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4220 ) ) ; cbx_1__1_ cbx_1__1_ ( .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , @@ -70898,36 +73562,29 @@ cbx_1__1_ cbx_1__1_ ( .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) , - .SC_OUT_BOT ( scff_Wires[23] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6036 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6037 ) , + .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( p2148 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4221 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) , .prog_clk_0_N_in ( prog_clk_0_wires[6] ) , .prog_clk_0_W_out ( prog_clk_0_wires[4] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6038 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4222 ) , .prog_clk_1_E_in ( prog_clk_1_wires[2] ) , .prog_clk_1_N_out ( prog_clk_1_wires[3] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6039 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6040 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6041 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6042 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6043 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6044 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6045 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6046 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6047 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( p2750 ) , + .prog_clk_2_W_in ( p881 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4223 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4224 ) , + .prog_clk_3_W_in ( p1733 ) , .prog_clk_3_E_in ( p746 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4225 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4226 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4227 ) , .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) , - .clk_1_S_out ( clk_1_wires[4] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6048 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6049 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6050 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6051 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6052 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6053 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6054 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6055 ) ) ; + .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( p1696 ) , + .clk_2_W_in ( p397 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4228 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4229 ) , .clk_3_W_in ( p1861 ) , + .clk_3_E_in ( p2630 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4230 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4231 ) ) ; cbx_1__1_ cbx_1__2_ ( .chanx_left_in ( sb_0__1__1_chanx_right_out ) , .chanx_right_in ( sb_1__1__1_chanx_left_out ) , .ccff_head ( sb_1__1__1_ccff_tail ) , @@ -70950,37 +73607,27 @@ cbx_1__1_ cbx_1__2_ ( .chanx_left_in ( sb_0__1__1_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) , - .SC_OUT_BOT ( scff_Wires[21] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6056 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6057 ) , + .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( p1601 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4232 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) , .prog_clk_0_N_in ( prog_clk_0_wires[11] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6058 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6059 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6060 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6061 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6062 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6063 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6064 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6065 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6066 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6067 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6068 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6069 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6070 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6071 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6072 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6073 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6074 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6075 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6076 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6077 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6078 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6079 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6080 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6081 ) ) ; + .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , .prog_clk_1_W_in ( p1425 ) , + .prog_clk_1_E_in ( p91 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4233 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4234 ) , + .prog_clk_2_E_in ( p2345 ) , .prog_clk_2_W_in ( p636 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4235 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4236 ) , + .prog_clk_3_W_in ( p1569 ) , .prog_clk_3_E_in ( p2669 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4237 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4238 ) , .clk_1_W_in ( p1425 ) , + .clk_1_E_in ( p1490 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4239 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4240 ) , .clk_2_E_in ( p2727 ) , + .clk_2_W_in ( p1228 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4241 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4242 ) , .clk_3_W_in ( p1569 ) , + .clk_3_E_in ( p2232 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4243 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4244 ) ) ; cbx_1__1_ cbx_1__3_ ( .chanx_left_in ( sb_0__1__2_chanx_right_out ) , .chanx_right_in ( sb_1__1__2_chanx_left_out ) , .ccff_head ( sb_1__1__2_ccff_tail ) , @@ -71003,36 +73650,29 @@ cbx_1__1_ cbx_1__3_ ( .chanx_left_in ( sb_0__1__2_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) , - .SC_OUT_BOT ( scff_Wires[19] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6082 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6083 ) , + .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( p1448 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4245 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) , .prog_clk_0_N_in ( prog_clk_0_wires[16] ) , .prog_clk_0_W_out ( prog_clk_0_wires[15] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6084 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4246 ) , .prog_clk_1_E_in ( prog_clk_1_wires[9] ) , .prog_clk_1_N_out ( prog_clk_1_wires[10] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6085 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6086 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6087 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6089 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6090 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6091 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6092 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6093 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , .prog_clk_2_E_in ( p2915 ) , + .prog_clk_2_W_in ( p103 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4247 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4248 ) , + .prog_clk_3_W_in ( p1973 ) , .prog_clk_3_E_in ( p2689 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4249 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4250 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4251 ) , .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) , - .clk_1_S_out ( clk_1_wires[11] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6094 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6095 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6096 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6097 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6098 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6099 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6100 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6101 ) ) ; + .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( p2731 ) , + .clk_2_W_in ( p2008 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4252 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4253 ) , .clk_3_W_in ( p1973 ) , + .clk_3_E_in ( p2854 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4254 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4255 ) ) ; cbx_1__1_ cbx_1__4_ ( .chanx_left_in ( sb_0__1__3_chanx_right_out ) , .chanx_right_in ( sb_1__1__3_chanx_left_out ) , .ccff_head ( sb_1__1__3_ccff_tail ) , @@ -71055,37 +73695,27 @@ cbx_1__1_ cbx_1__4_ ( .chanx_left_in ( sb_0__1__3_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) , - .SC_OUT_BOT ( scff_Wires[17] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6102 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6103 ) , + .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( p1183 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4256 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) , .prog_clk_0_N_in ( prog_clk_0_wires[21] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6104 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6105 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6106 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6107 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6108 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6109 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6110 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6111 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6112 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6113 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6114 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6115 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6116 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6117 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6118 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6119 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6120 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6121 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6122 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6123 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6124 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6125 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6126 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6127 ) ) ; + .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , .prog_clk_1_W_in ( p2131 ) , + .prog_clk_1_E_in ( p641 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4257 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4258 ) , + .prog_clk_2_E_in ( p2025 ) , .prog_clk_2_W_in ( p1935 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4259 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4260 ) , + .prog_clk_3_W_in ( p2605 ) , .prog_clk_3_E_in ( p2940 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4261 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4262 ) , .clk_1_W_in ( p2131 ) , + .clk_1_E_in ( p1500 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4263 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4264 ) , .clk_2_E_in ( p3053 ) , + .clk_2_W_in ( p2476 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4265 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4266 ) , .clk_3_W_in ( p2605 ) , + .clk_3_E_in ( p1914 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4267 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4268 ) ) ; cbx_1__1_ cbx_1__5_ ( .chanx_left_in ( sb_0__1__4_chanx_right_out ) , .chanx_right_in ( sb_1__1__4_chanx_left_out ) , .ccff_head ( sb_1__1__4_ccff_tail ) , @@ -71108,36 +73738,29 @@ cbx_1__1_ cbx_1__5_ ( .chanx_left_in ( sb_0__1__4_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) , - .SC_OUT_BOT ( scff_Wires[15] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6128 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6129 ) , + .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( p1814 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4269 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) , .prog_clk_0_N_in ( prog_clk_0_wires[26] ) , .prog_clk_0_W_out ( prog_clk_0_wires[25] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6130 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4270 ) , .prog_clk_1_E_in ( prog_clk_1_wires[16] ) , .prog_clk_1_N_out ( prog_clk_1_wires[17] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6131 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6132 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6133 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6134 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6135 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6136 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6138 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6139 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , .prog_clk_2_E_in ( p1235 ) , + .prog_clk_2_W_in ( p200 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4271 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4272 ) , + .prog_clk_3_W_in ( p1826 ) , .prog_clk_3_E_in ( p2848 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4273 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4274 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4275 ) , .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) , - .clk_1_S_out ( clk_1_wires[18] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6140 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6141 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6142 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6143 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6144 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6145 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6146 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6147 ) ) ; + .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( p2879 ) , + .clk_2_W_in ( p1222 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4276 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4277 ) , .clk_3_W_in ( p1826 ) , + .clk_3_E_in ( p1377 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4278 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4279 ) ) ; cbx_1__1_ cbx_1__6_ ( .chanx_left_in ( sb_0__1__5_chanx_right_out ) , .chanx_right_in ( sb_1__1__5_chanx_left_out ) , .ccff_head ( sb_1__1__5_ccff_tail ) , @@ -71160,37 +73783,27 @@ cbx_1__1_ cbx_1__6_ ( .chanx_left_in ( sb_0__1__5_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) , - .SC_OUT_BOT ( scff_Wires[13] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6148 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6149 ) , + .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( p1580 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4280 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) , .prog_clk_0_N_in ( prog_clk_0_wires[31] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6150 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6151 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6152 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6153 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6154 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6155 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6156 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6157 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6158 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6159 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6160 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6161 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6162 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6163 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6164 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6165 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6166 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6167 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6168 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6169 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6170 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6171 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6172 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6173 ) ) ; + .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , .prog_clk_1_W_in ( p1305 ) , + .prog_clk_1_E_in ( p581 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4281 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4282 ) , + .prog_clk_2_E_in ( p2568 ) , .prog_clk_2_W_in ( p669 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4283 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4284 ) , + .prog_clk_3_W_in ( p2714 ) , .prog_clk_3_E_in ( p3089 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4285 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4286 ) , .clk_1_W_in ( p1305 ) , + .clk_1_E_in ( p1424 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4287 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4288 ) , .clk_2_E_in ( p3121 ) , + .clk_2_W_in ( p2682 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4289 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4290 ) , .clk_3_W_in ( p2714 ) , + .clk_3_E_in ( p2506 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4291 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4292 ) ) ; cbx_1__1_ cbx_1__7_ ( .chanx_left_in ( sb_0__1__6_chanx_right_out ) , .chanx_right_in ( sb_1__1__6_chanx_left_out ) , .ccff_head ( sb_1__1__6_ccff_tail ) , @@ -71213,36 +73826,29 @@ cbx_1__1_ cbx_1__7_ ( .chanx_left_in ( sb_0__1__6_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) , - .SC_OUT_BOT ( scff_Wires[11] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6174 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6175 ) , + .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( p1518 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4293 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) , .prog_clk_0_N_in ( prog_clk_0_wires[36] ) , .prog_clk_0_W_out ( prog_clk_0_wires[35] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6176 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4294 ) , .prog_clk_1_E_in ( prog_clk_1_wires[23] ) , .prog_clk_1_N_out ( prog_clk_1_wires[24] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6177 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6178 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6179 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6180 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6181 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6182 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6183 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6184 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6185 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , .prog_clk_2_E_in ( p2089 ) , + .prog_clk_2_W_in ( p463 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4295 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4296 ) , + .prog_clk_3_W_in ( p2057 ) , .prog_clk_3_E_in ( p3083 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4297 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4298 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4299 ) , .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) , - .clk_1_S_out ( clk_1_wires[25] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6186 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6187 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6188 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6189 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6190 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6191 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6192 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6193 ) ) ; + .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( p3120 ) , + .clk_2_W_in ( p1948 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4301 ) , .clk_3_W_in ( p2057 ) , + .clk_3_E_in ( p2005 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4302 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4303 ) ) ; cbx_1__1_ cbx_1__8_ ( .chanx_left_in ( sb_0__1__7_chanx_right_out ) , .chanx_right_in ( sb_1__1__7_chanx_left_out ) , .ccff_head ( sb_1__1__7_ccff_tail ) , @@ -71265,36 +73871,27 @@ cbx_1__1_ cbx_1__8_ ( .chanx_left_in ( sb_0__1__7_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) , - .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6194 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6195 ) , + .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( p1824 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4304 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) , .prog_clk_0_N_in ( prog_clk_0_wires[41] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6196 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6197 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6198 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6199 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6200 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6201 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6202 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6203 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6204 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6205 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6206 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6207 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6208 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6209 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6210 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6211 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6212 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6213 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6214 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6215 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6216 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6217 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6218 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6219 ) ) ; + .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , .prog_clk_1_W_in ( p1494 ) , + .prog_clk_1_E_in ( p1364 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4305 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4306 ) , + .prog_clk_2_E_in ( p1534 ) , .prog_clk_2_W_in ( p332 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4307 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4308 ) , + .prog_clk_3_W_in ( p1885 ) , .prog_clk_3_E_in ( p2939 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4309 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4310 ) , .clk_1_W_in ( p1494 ) , + .clk_1_E_in ( p164 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4311 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4312 ) , .clk_2_E_in ( p3023 ) , + .clk_2_W_in ( p1483 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4313 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4314 ) , .clk_3_W_in ( p1885 ) , + .clk_3_E_in ( p405 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4315 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4316 ) ) ; cbx_1__1_ cbx_1__9_ ( .chanx_left_in ( sb_0__1__8_chanx_right_out ) , .chanx_right_in ( sb_1__1__8_chanx_left_out ) , .ccff_head ( sb_1__1__8_ccff_tail ) , @@ -71317,35 +73914,29 @@ cbx_1__1_ cbx_1__9_ ( .chanx_left_in ( sb_0__1__8_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) , - .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6220 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6221 ) , + .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( p1654 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4317 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) , .prog_clk_0_N_in ( prog_clk_0_wires[46] ) , .prog_clk_0_W_out ( prog_clk_0_wires[45] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6222 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4318 ) , .prog_clk_1_E_in ( prog_clk_1_wires[30] ) , .prog_clk_1_N_out ( prog_clk_1_wires[31] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6223 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6224 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6225 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6226 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6227 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6228 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6229 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6230 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6231 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , .prog_clk_2_E_in ( p1662 ) , + .prog_clk_2_W_in ( p1113 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4319 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4320 ) , + .prog_clk_3_W_in ( p2359 ) , .prog_clk_3_E_in ( p3059 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4321 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4322 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4323 ) , .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) , - .clk_1_S_out ( clk_1_wires[32] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6232 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6233 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6234 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6235 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6236 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6237 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6238 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6239 ) ) ; + .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( p3125 ) , + .clk_2_W_in ( p2245 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4324 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4325 ) , .clk_3_W_in ( p2359 ) , + .clk_3_E_in ( p1408 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4326 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4327 ) ) ; cbx_1__1_ cbx_1__10_ ( .chanx_left_in ( sb_0__1__9_chanx_right_out ) , .chanx_right_in ( sb_1__1__9_chanx_left_out ) , .ccff_head ( sb_1__1__9_ccff_tail ) , @@ -71368,36 +73959,27 @@ cbx_1__1_ cbx_1__10_ ( .chanx_left_in ( sb_0__1__9_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) , - .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6240 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6241 ) , + .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( p2140 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4328 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) , .prog_clk_0_N_in ( prog_clk_0_wires[51] ) , - .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6242 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6243 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6244 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6245 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6246 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6247 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6248 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6249 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6250 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6251 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6252 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6253 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6254 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6255 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6256 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6257 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6258 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6259 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6260 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6261 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6262 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6263 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6265 ) ) ; + .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , .prog_clk_1_W_in ( p1703 ) , + .prog_clk_1_E_in ( p1446 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4329 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4330 ) , + .prog_clk_2_E_in ( p2583 ) , .prog_clk_2_W_in ( p1392 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4331 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4332 ) , + .prog_clk_3_W_in ( p1793 ) , .prog_clk_3_E_in ( p2841 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4333 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4334 ) , .clk_1_W_in ( p1703 ) , + .clk_1_E_in ( p1942 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4335 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4336 ) , .clk_2_E_in ( p2910 ) , + .clk_2_W_in ( p679 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4337 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4338 ) , .clk_3_W_in ( p1793 ) , + .clk_3_E_in ( p2446 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4339 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4340 ) ) ; cbx_1__1_ cbx_1__11_ ( .chanx_left_in ( sb_0__1__10_chanx_right_out ) , .chanx_right_in ( sb_1__1__10_chanx_left_out ) , .ccff_head ( sb_1__1__10_ccff_tail ) , @@ -71420,35 +74002,29 @@ cbx_1__1_ cbx_1__11_ ( .chanx_left_in ( sb_0__1__10_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) , - .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6266 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6267 ) , + .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( p1638 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4341 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) , .prog_clk_0_N_in ( prog_clk_0_wires[56] ) , .prog_clk_0_W_out ( prog_clk_0_wires[55] ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6268 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4342 ) , .prog_clk_1_E_in ( prog_clk_1_wires[37] ) , .prog_clk_1_N_out ( prog_clk_1_wires[38] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6269 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6270 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6271 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6272 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6273 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6274 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6275 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6276 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6277 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , .prog_clk_2_E_in ( p1735 ) , + .prog_clk_2_W_in ( p1361 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4343 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4344 ) , + .prog_clk_3_W_in ( p2615 ) , .prog_clk_3_E_in ( p2855 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4345 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4346 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4347 ) , .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) , - .clk_1_S_out ( clk_1_wires[39] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6278 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6279 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6280 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6281 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6282 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6283 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6284 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6285 ) ) ; + .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( p2929 ) , + .clk_2_W_in ( p2464 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4348 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4349 ) , .clk_3_W_in ( p2615 ) , + .clk_3_E_in ( p1142 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4350 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4351 ) ) ; cbx_1__1_ cbx_2__1_ ( .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__11_chanx_left_out ) , .ccff_head ( sb_1__1__11_ccff_tail ) , @@ -71470,37 +74046,31 @@ cbx_1__1_ cbx_2__1_ ( .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__11_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6286 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6287 ) , + .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( p1460 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4352 ) , .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[11] ) , .prog_clk_0_N_in ( prog_clk_0_wires[66] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6288 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4353 ) , .prog_clk_1_W_in ( prog_clk_1_wires[1] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6289 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4354 ) , .prog_clk_1_N_out ( prog_clk_1_wires[5] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6290 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6291 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6292 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6293 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6294 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6295 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6297 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( p2363 ) , + .prog_clk_2_W_in ( p16 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4355 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4356 ) , + .prog_clk_3_W_in ( p2407 ) , .prog_clk_3_E_in ( p3073 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4357 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4358 ) , .clk_1_W_in ( clk_1_wires[1] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6298 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4359 ) , .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6299 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6300 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6301 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6302 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6303 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6304 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6305 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6306 ) ) ; + .clk_2_E_in ( p3143 ) , .clk_2_W_in ( p2238 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4360 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4361 ) , .clk_3_W_in ( p2407 ) , + .clk_3_E_in ( p2257 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4362 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4363 ) ) ; cbx_1__1_ cbx_2__2_ ( .chanx_left_in ( sb_1__1__1_chanx_right_out ) , .chanx_right_in ( sb_1__1__12_chanx_left_out ) , .ccff_head ( sb_1__1__12_ccff_tail ) , @@ -71522,38 +74092,31 @@ cbx_1__1_ cbx_2__2_ ( .chanx_left_in ( sb_1__1__1_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__12_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6307 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6308 ) , + .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( p1410 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4364 ) , .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[12] ) , .prog_clk_0_N_in ( prog_clk_0_wires[69] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6309 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6310 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6311 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6312 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6313 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4365 ) , + .prog_clk_1_W_in ( p1213 ) , .prog_clk_1_E_in ( p1366 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4366 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4367 ) , .prog_clk_2_E_in ( prog_clk_2_wires[2] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6314 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4368 ) , .prog_clk_2_W_out ( prog_clk_2_wires[1] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6315 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6316 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6317 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6318 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6319 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6320 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6321 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6322 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6323 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4369 ) , + .prog_clk_3_W_in ( p2707 ) , .prog_clk_3_E_in ( p622 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4370 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4371 ) , .clk_1_W_in ( p1213 ) , + .clk_1_E_in ( p791 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4372 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4373 ) , .clk_2_E_in ( clk_2_wires[2] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6324 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4374 ) , .clk_2_W_out ( clk_2_wires[1] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6325 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6326 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6327 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6329 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4375 ) , .clk_3_W_in ( p2707 ) , + .clk_3_E_in ( p1412 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4376 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4377 ) ) ; cbx_1__1_ cbx_2__3_ ( .chanx_left_in ( sb_1__1__2_chanx_right_out ) , .chanx_right_in ( sb_1__1__13_chanx_left_out ) , .ccff_head ( sb_1__1__13_ccff_tail ) , @@ -71575,37 +74138,31 @@ cbx_1__1_ cbx_2__3_ ( .chanx_left_in ( sb_1__1__2_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__13_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6330 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6331 ) , + .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( p1644 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4378 ) , .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[13] ) , .prog_clk_0_N_in ( prog_clk_0_wires[72] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6332 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4379 ) , .prog_clk_1_W_in ( prog_clk_1_wires[8] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6333 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4380 ) , .prog_clk_1_N_out ( prog_clk_1_wires[12] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6334 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6335 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6336 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6337 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6338 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6339 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6340 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6341 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , .prog_clk_2_E_in ( p902 ) , + .prog_clk_2_W_in ( p599 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4381 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4382 ) , + .prog_clk_3_W_in ( p2607 ) , .prog_clk_3_E_in ( p2847 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4383 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4384 ) , .clk_1_W_in ( clk_1_wires[8] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6342 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4385 ) , .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6343 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6344 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6345 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6346 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6347 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6348 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6349 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6350 ) ) ; + .clk_2_E_in ( p2925 ) , .clk_2_W_in ( p2456 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4386 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4387 ) , .clk_3_W_in ( p2607 ) , + .clk_3_E_in ( p1520 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4388 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4389 ) ) ; cbx_1__1_ cbx_2__4_ ( .chanx_left_in ( sb_1__1__3_chanx_right_out ) , .chanx_right_in ( sb_1__1__14_chanx_left_out ) , .ccff_head ( sb_1__1__14_ccff_tail ) , @@ -71627,38 +74184,31 @@ cbx_1__1_ cbx_2__4_ ( .chanx_left_in ( sb_1__1__3_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__14_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6351 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6352 ) , + .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( p1694 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4390 ) , .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[14] ) , .prog_clk_0_N_in ( prog_clk_0_wires[75] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6353 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6354 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6355 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6356 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6357 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4391 ) , + .prog_clk_1_W_in ( p1558 ) , .prog_clk_1_E_in ( p419 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4392 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4393 ) , .prog_clk_2_E_in ( prog_clk_2_wires[7] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6358 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4394 ) , .prog_clk_2_W_out ( prog_clk_2_wires[6] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6360 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6361 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6362 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6363 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6364 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6365 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6366 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6367 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4395 ) , + .prog_clk_3_W_in ( p1883 ) , .prog_clk_3_E_in ( p694 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4396 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4397 ) , .clk_1_W_in ( p1558 ) , + .clk_1_E_in ( p1532 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4398 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4399 ) , .clk_2_E_in ( clk_2_wires[7] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6368 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4400 ) , .clk_2_W_out ( clk_2_wires[6] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6369 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6370 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6371 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6372 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6373 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4401 ) , .clk_3_W_in ( p1883 ) , + .clk_3_E_in ( p1039 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4402 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4403 ) ) ; cbx_1__1_ cbx_2__5_ ( .chanx_left_in ( sb_1__1__4_chanx_right_out ) , .chanx_right_in ( sb_1__1__15_chanx_left_out ) , .ccff_head ( sb_1__1__15_ccff_tail ) , @@ -71680,37 +74230,31 @@ cbx_1__1_ cbx_2__5_ ( .chanx_left_in ( sb_1__1__4_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__15_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6374 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6375 ) , + .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( p2107 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4404 ) , .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[15] ) , .prog_clk_0_N_in ( prog_clk_0_wires[78] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6376 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4405 ) , .prog_clk_1_W_in ( prog_clk_1_wires[15] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6377 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4406 ) , .prog_clk_1_N_out ( prog_clk_1_wires[19] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6378 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6379 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6380 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6381 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6382 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6383 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6384 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6385 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , .prog_clk_2_E_in ( p2316 ) , + .prog_clk_2_W_in ( p631 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4407 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4408 ) , + .prog_clk_3_W_in ( p2557 ) , .prog_clk_3_E_in ( p2655 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4409 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4410 ) , .clk_1_W_in ( clk_1_wires[15] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6386 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4411 ) , .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6387 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6388 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6389 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6390 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6391 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6392 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6393 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6394 ) ) ; + .clk_2_E_in ( p2730 ) , .clk_2_W_in ( p2475 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4412 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4413 ) , .clk_3_W_in ( p2557 ) , + .clk_3_E_in ( p2246 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4414 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4415 ) ) ; cbx_1__1_ cbx_2__6_ ( .chanx_left_in ( sb_1__1__5_chanx_right_out ) , .chanx_right_in ( sb_1__1__16_chanx_left_out ) , .ccff_head ( sb_1__1__16_ccff_tail ) , @@ -71732,38 +74276,28 @@ cbx_1__1_ cbx_2__6_ ( .chanx_left_in ( sb_1__1__5_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__16_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6395 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6396 ) , + .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( p2306 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4416 ) , .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[16] ) , .prog_clk_0_N_in ( prog_clk_0_wires[81] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6397 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6398 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6399 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6400 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6401 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6402 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6403 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6404 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6405 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6406 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6407 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6408 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6409 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6410 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6411 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6412 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6413 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6414 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6415 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6416 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6417 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6418 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6419 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6420 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6421 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4417 ) , + .prog_clk_1_W_in ( p1501 ) , .prog_clk_1_E_in ( p1394 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4418 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4419 ) , + .prog_clk_2_E_in ( p1611 ) , .prog_clk_2_W_in ( p1019 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4420 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4421 ) , + .prog_clk_3_W_in ( p2267 ) , .prog_clk_3_E_in ( p2973 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4422 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4423 ) , .clk_1_W_in ( p1501 ) , + .clk_1_E_in ( p589 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4424 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4425 ) , .clk_2_E_in ( p3032 ) , + .clk_2_W_in ( p2233 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4426 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4427 ) , .clk_3_W_in ( p2267 ) , + .clk_3_E_in ( p1574 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4428 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4429 ) ) ; cbx_1__1_ cbx_2__7_ ( .chanx_left_in ( sb_1__1__6_chanx_right_out ) , .chanx_right_in ( sb_1__1__17_chanx_left_out ) , .ccff_head ( sb_1__1__17_ccff_tail ) , @@ -71785,37 +74319,31 @@ cbx_1__1_ cbx_2__7_ ( .chanx_left_in ( sb_1__1__6_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__17_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6422 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6423 ) , + .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( p1552 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4430 ) , .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[17] ) , .prog_clk_0_N_in ( prog_clk_0_wires[84] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6424 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4431 ) , .prog_clk_1_W_in ( prog_clk_1_wires[22] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6425 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4432 ) , .prog_clk_1_N_out ( prog_clk_1_wires[26] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6426 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6427 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6428 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6429 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6430 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6431 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6432 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6433 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , .prog_clk_2_E_in ( p1080 ) , + .prog_clk_2_W_in ( p1431 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4433 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4434 ) , + .prog_clk_3_W_in ( p2108 ) , .prog_clk_3_E_in ( p3091 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4435 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4436 ) , .clk_1_W_in ( clk_1_wires[22] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6434 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4437 ) , .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6435 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6436 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6437 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6439 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6440 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6441 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6442 ) ) ; + .clk_2_E_in ( p3104 ) , .clk_2_W_in ( p1903 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4438 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4439 ) , .clk_3_W_in ( p2108 ) , + .clk_3_E_in ( p1159 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4440 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4441 ) ) ; cbx_1__1_ cbx_2__8_ ( .chanx_left_in ( sb_1__1__7_chanx_right_out ) , .chanx_right_in ( sb_1__1__18_chanx_left_out ) , .ccff_head ( sb_1__1__18_ccff_tail ) , @@ -71837,38 +74365,31 @@ cbx_1__1_ cbx_2__8_ ( .chanx_left_in ( sb_1__1__7_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__18_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6443 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6444 ) , + .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( p2576 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4442 ) , .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[18] ) , .prog_clk_0_N_in ( prog_clk_0_wires[87] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6445 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6446 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6447 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6448 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6449 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4443 ) , + .prog_clk_1_W_in ( p1625 ) , .prog_clk_1_E_in ( p1389 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4444 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4445 ) , .prog_clk_2_E_in ( prog_clk_2_wires[14] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6450 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4446 ) , .prog_clk_2_W_out ( prog_clk_2_wires[13] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6451 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6452 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6453 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6454 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6455 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6456 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6457 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6458 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6459 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4447 ) , + .prog_clk_3_W_in ( p1553 ) , .prog_clk_3_E_in ( p2487 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4448 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4449 ) , .clk_1_W_in ( p1828 ) , + .clk_1_E_in ( p753 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4450 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4451 ) , .clk_2_E_in ( clk_2_wires[14] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6460 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4452 ) , .clk_2_W_out ( clk_2_wires[13] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6461 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6462 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6463 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6464 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6465 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4453 ) , .clk_3_W_in ( p1553 ) , + .clk_3_E_in ( p1443 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4454 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4455 ) ) ; cbx_1__1_ cbx_2__9_ ( .chanx_left_in ( sb_1__1__8_chanx_right_out ) , .chanx_right_in ( sb_1__1__19_chanx_left_out ) , .ccff_head ( sb_1__1__19_ccff_tail ) , @@ -71890,37 +74411,31 @@ cbx_1__1_ cbx_2__9_ ( .chanx_left_in ( sb_1__1__8_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__19_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6466 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6467 ) , + .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( p2143 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4456 ) , .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[19] ) , .prog_clk_0_N_in ( prog_clk_0_wires[90] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6468 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4457 ) , .prog_clk_1_W_in ( prog_clk_1_wires[29] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6469 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4458 ) , .prog_clk_1_N_out ( prog_clk_1_wires[33] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6470 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6471 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6472 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6473 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6474 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6475 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6476 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6477 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , .prog_clk_2_E_in ( p2012 ) , + .prog_clk_2_W_in ( p1251 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4459 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4460 ) , + .prog_clk_3_W_in ( p2577 ) , .prog_clk_3_E_in ( p2448 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4461 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4462 ) , .clk_1_W_in ( clk_1_wires[29] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6478 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4463 ) , .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6479 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6480 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6481 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6482 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6483 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6484 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6485 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6486 ) ) ; + .clk_2_E_in ( p2550 ) , .clk_2_W_in ( p2478 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4464 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4465 ) , .clk_3_W_in ( p2577 ) , + .clk_3_E_in ( p1983 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4466 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4467 ) ) ; cbx_1__1_ cbx_2__10_ ( .chanx_left_in ( sb_1__1__9_chanx_right_out ) , .chanx_right_in ( sb_1__1__20_chanx_left_out ) , .ccff_head ( sb_1__1__20_ccff_tail ) , @@ -71942,38 +74457,31 @@ cbx_1__1_ cbx_2__10_ ( .chanx_left_in ( sb_1__1__9_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__20_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6487 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6488 ) , + .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( p1615 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4468 ) , .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[20] ) , .prog_clk_0_N_in ( prog_clk_0_wires[93] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6489 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6490 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6491 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6492 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6493 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4469 ) , + .prog_clk_1_W_in ( p1704 ) , .prog_clk_1_E_in ( p348 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4470 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4471 ) , .prog_clk_2_E_in ( prog_clk_2_wires[21] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6494 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4472 ) , .prog_clk_2_W_out ( prog_clk_2_wires[20] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6495 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6496 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6497 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6498 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6499 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6500 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6501 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6502 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6503 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4473 ) , + .prog_clk_3_W_in ( p2034 ) , .prog_clk_3_E_in ( p629 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4474 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4475 ) , .clk_1_W_in ( p1704 ) , + .clk_1_E_in ( p471 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4476 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4477 ) , .clk_2_E_in ( clk_2_wires[21] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6504 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4478 ) , .clk_2_W_out ( clk_2_wires[20] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6505 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6506 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6507 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6508 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6509 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4479 ) , .clk_3_W_in ( p2034 ) , + .clk_3_E_in ( p1423 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4480 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4481 ) ) ; cbx_1__1_ cbx_2__11_ ( .chanx_left_in ( sb_1__1__10_chanx_right_out ) , .chanx_right_in ( sb_1__1__21_chanx_left_out ) , .ccff_head ( sb_1__1__21_ccff_tail ) , @@ -71995,37 +74503,31 @@ cbx_1__1_ cbx_2__11_ ( .chanx_left_in ( sb_1__1__10_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__21_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6510 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6511 ) , + .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( p1583 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4482 ) , .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[21] ) , .prog_clk_0_N_in ( prog_clk_0_wires[96] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6512 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4483 ) , .prog_clk_1_W_in ( prog_clk_1_wires[36] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6513 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4484 ) , .prog_clk_1_N_out ( prog_clk_1_wires[40] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6514 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6515 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6516 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6517 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6518 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6519 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6520 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6521 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , .prog_clk_2_E_in ( p2079 ) , + .prog_clk_2_W_in ( p728 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4485 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4486 ) , + .prog_clk_3_W_in ( p1811 ) , .prog_clk_3_E_in ( p2978 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4487 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4488 ) , .clk_1_W_in ( clk_1_wires[36] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6522 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4489 ) , .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6523 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6524 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6525 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6526 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6527 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6528 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6529 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6530 ) ) ; + .clk_2_E_in ( p3033 ) , .clk_2_W_in ( p2840 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4490 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4491 ) , .clk_3_W_in ( p2856 ) , + .clk_3_E_in ( p1958 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4492 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4493 ) ) ; cbx_1__1_ cbx_3__1_ ( .chanx_left_in ( sb_1__1__11_chanx_right_out ) , .chanx_right_in ( sb_1__1__22_chanx_left_out ) , .ccff_head ( sb_1__1__22_ccff_tail ) , @@ -72048,36 +74550,29 @@ cbx_1__1_ cbx_3__1_ ( .chanx_left_in ( sb_1__1__11_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) , - .SC_OUT_BOT ( scff_Wires[76] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6531 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6532 ) , + .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( p1746 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4494 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) , .prog_clk_0_N_in ( prog_clk_0_wires[104] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6533 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6534 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4495 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4496 ) , .prog_clk_1_E_in ( prog_clk_1_wires[44] ) , .prog_clk_1_N_out ( prog_clk_1_wires[45] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6535 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6536 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6537 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6538 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6539 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6540 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6541 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6542 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6543 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , .prog_clk_2_E_in ( p2098 ) , + .prog_clk_2_W_in ( p1219 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4497 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4498 ) , + .prog_clk_3_W_in ( p2560 ) , .prog_clk_3_E_in ( p2986 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4499 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4500 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4501 ) , .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) , - .clk_1_S_out ( clk_1_wires[46] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6544 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6545 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6546 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6547 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6548 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6549 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6550 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6551 ) ) ; + .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( p2991 ) , + .clk_2_W_in ( p2442 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4502 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4503 ) , .clk_3_W_in ( p2560 ) , + .clk_3_E_in ( p2013 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4504 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4505 ) ) ; cbx_1__1_ cbx_3__2_ ( .chanx_left_in ( sb_1__1__12_chanx_right_out ) , .chanx_right_in ( sb_1__1__23_chanx_left_out ) , .ccff_head ( sb_1__1__23_ccff_tail ) , @@ -72100,37 +74595,27 @@ cbx_1__1_ cbx_3__2_ ( .chanx_left_in ( sb_1__1__12_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) , - .SC_OUT_BOT ( scff_Wires[74] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6552 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6553 ) , + .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( p1808 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4506 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) , .prog_clk_0_N_in ( prog_clk_0_wires[107] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6554 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6555 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6556 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6557 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6558 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6559 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6560 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6561 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6562 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6563 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6564 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6565 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6566 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6567 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6568 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6569 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6570 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6571 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6572 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6573 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6574 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6575 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6576 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6577 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6578 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4507 ) , + .prog_clk_1_W_in ( p1445 ) , .prog_clk_1_E_in ( p441 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4508 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4509 ) , + .prog_clk_2_E_in ( p1753 ) , .prog_clk_2_W_in ( p1488 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4510 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4511 ) , + .prog_clk_3_W_in ( p2039 ) , .prog_clk_3_E_in ( p2972 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4512 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4513 ) , .clk_1_W_in ( p1445 ) , + .clk_1_E_in ( p1417 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4514 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4515 ) , .clk_2_E_in ( p3040 ) , + .clk_2_W_in ( p1955 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4516 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4517 ) , .clk_3_W_in ( p2039 ) , + .clk_3_E_in ( p163 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4518 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4519 ) ) ; cbx_1__1_ cbx_3__3_ ( .chanx_left_in ( sb_1__1__13_chanx_right_out ) , .chanx_right_in ( sb_1__1__24_chanx_left_out ) , .ccff_head ( sb_1__1__24_ccff_tail ) , @@ -72153,36 +74638,29 @@ cbx_1__1_ cbx_3__3_ ( .chanx_left_in ( sb_1__1__13_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) , - .SC_OUT_BOT ( scff_Wires[72] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6579 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6580 ) , + .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( p1498 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4520 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) , .prog_clk_0_N_in ( prog_clk_0_wires[110] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6581 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6582 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4521 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4522 ) , .prog_clk_1_E_in ( prog_clk_1_wires[51] ) , .prog_clk_1_N_out ( prog_clk_1_wires[52] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6583 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6584 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6585 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6586 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6587 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6588 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6589 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6590 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6591 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , .prog_clk_2_E_in ( p1709 ) , + .prog_clk_2_W_in ( p945 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4523 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4524 ) , + .prog_clk_3_W_in ( p1407 ) , .prog_clk_3_E_in ( p1992 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4525 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4526 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4527 ) , .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) , - .clk_1_S_out ( clk_1_wires[53] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6592 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6593 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6594 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6595 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6596 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6597 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6599 ) ) ; + .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( p1944 ) , + .clk_2_W_in ( p1455 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4528 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4529 ) , .clk_3_W_in ( p1407 ) , + .clk_3_E_in ( p1298 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4530 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4531 ) ) ; cbx_1__1_ cbx_3__4_ ( .chanx_left_in ( sb_1__1__14_chanx_right_out ) , .chanx_right_in ( sb_1__1__25_chanx_left_out ) , .ccff_head ( sb_1__1__25_ccff_tail ) , @@ -72205,37 +74683,27 @@ cbx_1__1_ cbx_3__4_ ( .chanx_left_in ( sb_1__1__14_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) , - .SC_OUT_BOT ( scff_Wires[70] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6600 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6601 ) , + .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( p1705 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4532 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) , .prog_clk_0_N_in ( prog_clk_0_wires[113] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6602 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6603 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6604 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6605 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6606 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6607 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6608 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6609 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6610 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6611 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6612 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6614 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6615 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6616 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6617 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6618 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6619 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6620 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6621 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6622 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6623 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6624 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6625 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6626 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4533 ) , + .prog_clk_1_W_in ( p1221 ) , .prog_clk_1_E_in ( p1341 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4534 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4535 ) , + .prog_clk_2_E_in ( p2905 ) , .prog_clk_2_W_in ( p267 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4536 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4537 ) , + .prog_clk_3_W_in ( p2078 ) , .prog_clk_3_E_in ( p2509 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4538 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4539 ) , .clk_1_W_in ( p1221 ) , + .clk_1_E_in ( p524 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4540 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4541 ) , .clk_2_E_in ( p2593 ) , + .clk_2_W_in ( p2253 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4542 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4543 ) , .clk_3_W_in ( p2284 ) , + .clk_3_E_in ( p2843 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4544 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4545 ) ) ; cbx_1__1_ cbx_3__5_ ( .chanx_left_in ( sb_1__1__15_chanx_right_out ) , .chanx_right_in ( sb_1__1__26_chanx_left_out ) , .ccff_head ( sb_1__1__26_ccff_tail ) , @@ -72258,36 +74726,29 @@ cbx_1__1_ cbx_3__5_ ( .chanx_left_in ( sb_1__1__15_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) , - .SC_OUT_BOT ( scff_Wires[68] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6627 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6628 ) , + .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( p1555 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4546 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) , .prog_clk_0_N_in ( prog_clk_0_wires[116] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6629 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6630 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4547 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4548 ) , .prog_clk_1_E_in ( prog_clk_1_wires[58] ) , .prog_clk_1_N_out ( prog_clk_1_wires[59] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6631 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6632 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6633 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6634 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6635 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6636 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6637 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6638 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6639 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , .prog_clk_2_E_in ( p1866 ) , + .prog_clk_2_W_in ( p823 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4549 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4550 ) , + .prog_clk_3_W_in ( p2522 ) , .prog_clk_3_E_in ( p1913 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4551 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4552 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4553 ) , .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) , - .clk_1_S_out ( clk_1_wires[60] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6640 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6641 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6642 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6643 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6644 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6645 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6647 ) ) ; + .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( p2047 ) , + .clk_2_W_in ( p2430 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4554 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4555 ) , .clk_3_W_in ( p2522 ) , + .clk_3_E_in ( p12 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4556 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4557 ) ) ; cbx_1__1_ cbx_3__6_ ( .chanx_left_in ( sb_1__1__16_chanx_right_out ) , .chanx_right_in ( sb_1__1__27_chanx_left_out ) , .ccff_head ( sb_1__1__27_ccff_tail ) , @@ -72310,36 +74771,29 @@ cbx_1__1_ cbx_3__6_ ( .chanx_left_in ( sb_1__1__16_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) , - .SC_OUT_BOT ( scff_Wires[66] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6648 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6649 ) , + .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( p1758 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4558 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) , .prog_clk_0_N_in ( prog_clk_0_wires[119] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6650 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6651 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6652 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6653 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6654 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6655 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6656 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6657 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6658 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6659 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4559 ) , + .prog_clk_1_W_in ( p1386 ) , .prog_clk_1_E_in ( p1059 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4560 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4561 ) , + .prog_clk_2_E_in ( p1773 ) , .prog_clk_2_W_in ( p1240 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4562 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4563 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4564 ) , .prog_clk_3_E_in ( prog_clk_3_wires[50] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6660 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6661 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6662 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6663 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6664 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6665 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6666 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6667 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6668 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6669 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4565 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( p1386 ) , + .clk_1_E_in ( p223 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4566 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4567 ) , .clk_2_E_in ( p1712 ) , + .clk_2_W_in ( p986 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4568 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4569 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4570 ) , .clk_3_E_in ( clk_3_wires[50] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6670 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4571 ) , .clk_3_W_out ( clk_3_wires[51] ) ) ; cbx_1__1_ cbx_3__7_ ( .chanx_left_in ( sb_1__1__17_chanx_right_out ) , .chanx_right_in ( sb_1__1__28_chanx_left_out ) , @@ -72363,36 +74817,29 @@ cbx_1__1_ cbx_3__7_ ( .chanx_left_in ( sb_1__1__17_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) , - .SC_OUT_BOT ( scff_Wires[64] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6671 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6672 ) , + .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( p1335 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4572 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) , .prog_clk_0_N_in ( prog_clk_0_wires[122] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6673 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6674 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4573 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4574 ) , .prog_clk_1_E_in ( prog_clk_1_wires[65] ) , .prog_clk_1_N_out ( prog_clk_1_wires[66] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6675 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6676 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6677 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6678 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6679 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6680 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6681 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6682 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6683 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , .prog_clk_2_E_in ( p2700 ) , + .prog_clk_2_W_in ( p1491 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4575 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4576 ) , + .prog_clk_3_W_in ( p1801 ) , .prog_clk_3_E_in ( p2507 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4577 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4578 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4579 ) , .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) , - .clk_1_S_out ( clk_1_wires[67] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6684 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6685 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6686 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6687 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6688 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6689 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6690 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6691 ) ) ; + .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( p2511 ) , + .clk_2_W_in ( p222 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4580 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4581 ) , .clk_3_W_in ( p1801 ) , + .clk_3_E_in ( p2629 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4582 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4583 ) ) ; cbx_1__1_ cbx_3__8_ ( .chanx_left_in ( sb_1__1__18_chanx_right_out ) , .chanx_right_in ( sb_1__1__29_chanx_left_out ) , .ccff_head ( sb_1__1__29_ccff_tail ) , @@ -72415,37 +74862,27 @@ cbx_1__1_ cbx_3__8_ ( .chanx_left_in ( sb_1__1__18_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) , - .SC_OUT_BOT ( scff_Wires[62] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6692 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6693 ) , + .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( p2069 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4584 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) , .prog_clk_0_N_in ( prog_clk_0_wires[125] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6694 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6695 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6696 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6697 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6698 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6699 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6700 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6701 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6702 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6703 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6704 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6705 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6706 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6707 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6708 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6709 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6710 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6711 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6712 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6713 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6714 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6715 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6716 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6717 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6718 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4585 ) , + .prog_clk_1_W_in ( p1566 ) , .prog_clk_1_E_in ( p625 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4586 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4587 ) , + .prog_clk_2_E_in ( p2340 ) , .prog_clk_2_W_in ( p13 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4588 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4589 ) , + .prog_clk_3_W_in ( p1855 ) , .prog_clk_3_E_in ( p2455 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4590 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4591 ) , .clk_1_W_in ( p1566 ) , + .clk_1_E_in ( p1896 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4592 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4593 ) , .clk_2_E_in ( p2626 ) , + .clk_2_W_in ( p1495 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4594 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4595 ) , .clk_3_W_in ( p1790 ) , + .clk_3_E_in ( p2678 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4596 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4597 ) ) ; cbx_1__1_ cbx_3__9_ ( .chanx_left_in ( sb_1__1__19_chanx_right_out ) , .chanx_right_in ( sb_1__1__30_chanx_left_out ) , .ccff_head ( sb_1__1__30_ccff_tail ) , @@ -72468,36 +74905,29 @@ cbx_1__1_ cbx_3__9_ ( .chanx_left_in ( sb_1__1__19_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) , - .SC_OUT_BOT ( scff_Wires[60] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6719 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6720 ) , + .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( p1563 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4598 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) , .prog_clk_0_N_in ( prog_clk_0_wires[128] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6721 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6722 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4599 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4600 ) , .prog_clk_1_E_in ( prog_clk_1_wires[72] ) , .prog_clk_1_N_out ( prog_clk_1_wires[73] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6723 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6724 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6727 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6728 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6729 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6730 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6731 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , .prog_clk_2_E_in ( p1539 ) , + .prog_clk_2_W_in ( p1470 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4601 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4602 ) , + .prog_clk_3_W_in ( p2112 ) , .prog_clk_3_E_in ( p2980 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4603 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4604 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4605 ) , .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) , - .clk_1_S_out ( clk_1_wires[74] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6732 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6733 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6734 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6735 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6736 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6737 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6738 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6739 ) ) ; + .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( p2999 ) , + .clk_2_W_in ( p1890 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4606 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4607 ) , .clk_3_W_in ( p2112 ) , + .clk_3_E_in ( p1365 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4608 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4609 ) ) ; cbx_1__1_ cbx_3__10_ ( .chanx_left_in ( sb_1__1__20_chanx_right_out ) , .chanx_right_in ( sb_1__1__31_chanx_left_out ) , .ccff_head ( sb_1__1__31_ccff_tail ) , @@ -72520,37 +74950,27 @@ cbx_1__1_ cbx_3__10_ ( .chanx_left_in ( sb_1__1__20_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) , - .SC_OUT_BOT ( scff_Wires[58] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6740 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6741 ) , + .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( p1751 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4610 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) , .prog_clk_0_N_in ( prog_clk_0_wires[131] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6742 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6743 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6744 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6745 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6746 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6747 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6748 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6749 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6750 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6751 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6752 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6753 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6754 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6755 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6756 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6757 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6758 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6759 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6760 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6761 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6762 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6763 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6764 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6765 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6766 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4611 ) , + .prog_clk_1_W_in ( p1414 ) , .prog_clk_1_E_in ( p529 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4612 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4613 ) , + .prog_clk_2_E_in ( p2696 ) , .prog_clk_2_W_in ( p718 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4614 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4615 ) , + .prog_clk_3_W_in ( p2771 ) , .prog_clk_3_E_in ( p2276 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4616 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4617 ) , .clk_1_W_in ( p1414 ) , + .clk_1_E_in ( p531 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4618 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4619 ) , .clk_2_E_in ( p2290 ) , + .clk_2_W_in ( p2683 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4620 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4621 ) , .clk_3_W_in ( p2771 ) , + .clk_3_E_in ( p2672 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4622 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4623 ) ) ; cbx_1__1_ cbx_3__11_ ( .chanx_left_in ( sb_1__1__21_chanx_right_out ) , .chanx_right_in ( sb_1__1__32_chanx_left_out ) , .ccff_head ( sb_1__1__32_ccff_tail ) , @@ -72573,36 +74993,29 @@ cbx_1__1_ cbx_3__11_ ( .chanx_left_in ( sb_1__1__21_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) , - .SC_OUT_BOT ( scff_Wires[56] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_6767 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6768 ) , + .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( p1452 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4624 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) , .prog_clk_0_N_in ( prog_clk_0_wires[134] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6769 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6770 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4625 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4626 ) , .prog_clk_1_E_in ( prog_clk_1_wires[79] ) , .prog_clk_1_N_out ( prog_clk_1_wires[80] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6771 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6772 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6773 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6774 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6775 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6776 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6777 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6778 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6779 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , .prog_clk_2_E_in ( p2317 ) , + .prog_clk_2_W_in ( p1239 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4627 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4628 ) , + .prog_clk_3_W_in ( p1732 ) , .prog_clk_3_E_in ( p2010 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4629 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4630 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4631 ) , .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) , - .clk_1_S_out ( clk_1_wires[81] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6780 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6781 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6782 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6783 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6784 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6785 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6786 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6787 ) ) ; + .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( p2144 ) , + .clk_2_W_in ( p634 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4632 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4633 ) , .clk_3_W_in ( p1732 ) , + .clk_3_E_in ( p2281 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4634 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4635 ) ) ; cbx_1__1_ cbx_4__1_ ( .chanx_left_in ( sb_1__1__22_chanx_right_out ) , .chanx_right_in ( sb_1__1__33_chanx_left_out ) , .ccff_head ( sb_1__1__33_ccff_tail ) , @@ -72624,37 +75037,31 @@ cbx_1__1_ cbx_4__1_ ( .chanx_left_in ( sb_1__1__22_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__33_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6788 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6789 ) , + .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( p2151 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4636 ) , .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[33] ) , .prog_clk_0_N_in ( prog_clk_0_wires[142] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6790 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4637 ) , .prog_clk_1_W_in ( prog_clk_1_wires[43] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6791 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4638 ) , .prog_clk_1_N_out ( prog_clk_1_wires[47] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6792 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6793 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6794 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6795 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6796 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6797 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6798 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6799 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , .prog_clk_2_E_in ( p1835 ) , + .prog_clk_2_W_in ( p1355 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4639 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4640 ) , + .prog_clk_3_W_in ( p1626 ) , .prog_clk_3_E_in ( p2680 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4641 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4642 ) , .clk_1_W_in ( clk_1_wires[43] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6800 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4643 ) , .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6801 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6802 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6803 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6804 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6805 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6806 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6807 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6808 ) ) ; + .clk_2_E_in ( p2786 ) , .clk_2_W_in ( p2834 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4644 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4645 ) , .clk_3_W_in ( p2897 ) , + .clk_3_E_in ( p1442 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4646 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4647 ) ) ; cbx_1__1_ cbx_4__2_ ( .chanx_left_in ( sb_1__1__23_chanx_right_out ) , .chanx_right_in ( sb_1__1__34_chanx_left_out ) , .ccff_head ( sb_1__1__34_ccff_tail ) , @@ -72676,38 +75083,31 @@ cbx_1__1_ cbx_4__2_ ( .chanx_left_in ( sb_1__1__23_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__34_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6809 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6810 ) , + .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( p1994 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4648 ) , .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[34] ) , .prog_clk_0_N_in ( prog_clk_0_wires[145] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6811 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6812 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6813 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6814 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6815 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4649 ) , + .prog_clk_1_W_in ( p1021 ) , .prog_clk_1_E_in ( p1363 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4650 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4651 ) , .prog_clk_2_E_in ( prog_clk_2_wires[27] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6816 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4652 ) , .prog_clk_2_W_out ( prog_clk_2_wires[28] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6817 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6818 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6819 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6821 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6822 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6823 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6824 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6825 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4653 ) , + .prog_clk_3_W_in ( p1802 ) , .prog_clk_3_E_in ( p1886 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4654 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4655 ) , .clk_1_W_in ( p1021 ) , + .clk_1_E_in ( p759 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4656 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4657 ) , .clk_2_E_in ( clk_2_wires[27] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6826 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4658 ) , .clk_2_W_out ( clk_2_wires[28] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6827 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6828 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6829 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6830 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6831 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4659 ) , .clk_3_W_in ( p1802 ) , + .clk_3_E_in ( p1231 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4660 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4661 ) ) ; cbx_1__1_ cbx_4__3_ ( .chanx_left_in ( sb_1__1__24_chanx_right_out ) , .chanx_right_in ( sb_1__1__35_chanx_left_out ) , .ccff_head ( sb_1__1__35_ccff_tail ) , @@ -72729,37 +75129,31 @@ cbx_1__1_ cbx_4__3_ ( .chanx_left_in ( sb_1__1__24_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__35_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6832 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6833 ) , + .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( p2121 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4662 ) , .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[35] ) , .prog_clk_0_N_in ( prog_clk_0_wires[148] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6834 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4663 ) , .prog_clk_1_W_in ( prog_clk_1_wires[50] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6835 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4664 ) , .prog_clk_1_N_out ( prog_clk_1_wires[54] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6836 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6837 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6838 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6839 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6840 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6841 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6842 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6843 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , .prog_clk_2_E_in ( p1764 ) , + .prog_clk_2_W_in ( p1047 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4665 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4666 ) , + .prog_clk_3_W_in ( p2384 ) , .prog_clk_3_E_in ( p2654 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4667 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4668 ) , .clk_1_W_in ( clk_1_wires[50] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6844 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4669 ) , .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6845 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6846 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6847 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6848 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6849 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6850 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6851 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6852 ) ) ; + .clk_2_E_in ( p2779 ) , .clk_2_W_in ( p2258 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4670 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4671 ) , .clk_3_W_in ( p2403 ) , + .clk_3_E_in ( p1319 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4672 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4673 ) ) ; cbx_1__1_ cbx_4__4_ ( .chanx_left_in ( sb_1__1__25_chanx_right_out ) , .chanx_right_in ( sb_1__1__36_chanx_left_out ) , .ccff_head ( sb_1__1__36_ccff_tail ) , @@ -72781,38 +75175,31 @@ cbx_1__1_ cbx_4__4_ ( .chanx_left_in ( sb_1__1__25_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__36_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6853 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6854 ) , + .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( p1531 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4674 ) , .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[36] ) , .prog_clk_0_N_in ( prog_clk_0_wires[151] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6855 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6856 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6857 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6858 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6859 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4675 ) , + .prog_clk_1_W_in ( p1427 ) , .prog_clk_1_E_in ( p270 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4676 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4677 ) , .prog_clk_2_E_in ( prog_clk_2_wires[36] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6860 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4678 ) , .prog_clk_2_W_out ( prog_clk_2_wires[37] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6861 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6862 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6863 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6864 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6865 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6866 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6867 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6868 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6869 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4679 ) , + .prog_clk_3_W_in ( p1618 ) , .prog_clk_3_E_in ( p491 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4680 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4681 ) , .clk_1_W_in ( p1598 ) , + .clk_1_E_in ( p1429 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4682 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4683 ) , .clk_2_E_in ( clk_2_wires[36] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6870 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_2_W_out ( clk_2_wires[37] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6871 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6872 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6873 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6874 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6875 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4685 ) , .clk_3_W_in ( p1618 ) , + .clk_3_E_in ( p1428 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4686 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4687 ) ) ; cbx_1__1_ cbx_4__5_ ( .chanx_left_in ( sb_1__1__26_chanx_right_out ) , .chanx_right_in ( sb_1__1__37_chanx_left_out ) , .ccff_head ( sb_1__1__37_ccff_tail ) , @@ -72834,37 +75221,31 @@ cbx_1__1_ cbx_4__5_ ( .chanx_left_in ( sb_1__1__26_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__37_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6876 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6877 ) , + .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( p1778 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4688 ) , .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[37] ) , .prog_clk_0_N_in ( prog_clk_0_wires[154] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6878 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4689 ) , .prog_clk_1_W_in ( prog_clk_1_wires[57] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6879 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4690 ) , .prog_clk_1_N_out ( prog_clk_1_wires[61] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6880 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6881 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6882 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6883 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6884 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6885 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6886 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6887 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , .prog_clk_2_E_in ( p2279 ) , + .prog_clk_2_W_in ( p1086 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4691 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4692 ) , + .prog_clk_3_W_in ( p2137 ) , .prog_clk_3_E_in ( p2282 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4693 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4694 ) , .clk_1_W_in ( clk_1_wires[57] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6888 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4695 ) , .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6889 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6890 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6891 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6892 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6893 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6894 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6895 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6896 ) ) ; + .clk_2_E_in ( p2417 ) , .clk_2_W_in ( p3057 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4696 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4697 ) , .clk_3_W_in ( p3101 ) , + .clk_3_E_in ( p2204 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4698 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4699 ) ) ; cbx_1__1_ cbx_4__6_ ( .chanx_left_in ( sb_1__1__27_chanx_right_out ) , .chanx_right_in ( sb_1__1__38_chanx_left_out ) , .ccff_head ( sb_1__1__38_ccff_tail ) , @@ -72886,37 +75267,30 @@ cbx_1__1_ cbx_4__6_ ( .chanx_left_in ( sb_1__1__27_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__38_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6897 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6898 ) , + .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( p1584 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4700 ) , .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[38] ) , .prog_clk_0_N_in ( prog_clk_0_wires[157] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6899 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6900 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6901 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6902 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6903 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6904 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6905 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6906 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6907 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6908 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4701 ) , + .prog_clk_1_W_in ( p1656 ) , .prog_clk_1_E_in ( p1226 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4702 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4703 ) , + .prog_clk_2_E_in ( p1551 ) , .prog_clk_2_W_in ( p484 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4704 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4705 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4706 ) , .prog_clk_3_E_in ( prog_clk_3_wires[46] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6909 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6910 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6911 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6912 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6913 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6914 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6915 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6916 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6917 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6918 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4707 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( p1656 ) , + .clk_1_E_in ( p383 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4708 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4709 ) , .clk_2_E_in ( p1837 ) , + .clk_2_W_in ( p1373 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4710 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4711 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4712 ) , .clk_3_E_in ( clk_3_wires[46] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6919 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4713 ) , .clk_3_W_out ( clk_3_wires[47] ) ) ; cbx_1__1_ cbx_4__7_ ( .chanx_left_in ( sb_1__1__28_chanx_right_out ) , .chanx_right_in ( sb_1__1__39_chanx_left_out ) , @@ -72939,37 +75313,31 @@ cbx_1__1_ cbx_4__7_ ( .chanx_left_in ( sb_1__1__28_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__39_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6920 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6921 ) , + .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( p1862 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4714 ) , .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[39] ) , .prog_clk_0_N_in ( prog_clk_0_wires[160] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6922 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4715 ) , .prog_clk_1_W_in ( prog_clk_1_wires[64] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6923 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4716 ) , .prog_clk_1_N_out ( prog_clk_1_wires[68] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6924 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6925 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6926 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6927 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6928 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6929 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6930 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6931 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , .prog_clk_2_E_in ( p2309 ) , + .prog_clk_2_W_in ( p507 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4717 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4718 ) , + .prog_clk_3_W_in ( p2569 ) , .prog_clk_3_E_in ( p22 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4719 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4720 ) , .clk_1_W_in ( clk_1_wires[64] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6932 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4721 ) , .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6933 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6934 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6935 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6936 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6937 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6938 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6939 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6940 ) ) ; + .clk_2_E_in ( p1862 ) , .clk_2_W_in ( p2443 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4722 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4723 ) , .clk_3_W_in ( p2579 ) , + .clk_3_E_in ( p2177 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4724 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4725 ) ) ; cbx_1__1_ cbx_4__8_ ( .chanx_left_in ( sb_1__1__29_chanx_right_out ) , .chanx_right_in ( sb_1__1__40_chanx_left_out ) , .ccff_head ( sb_1__1__40_ccff_tail ) , @@ -72991,38 +75359,31 @@ cbx_1__1_ cbx_4__8_ ( .chanx_left_in ( sb_1__1__29_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__40_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6941 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6942 ) , + .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( p1687 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4726 ) , .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[40] ) , .prog_clk_0_N_in ( prog_clk_0_wires[163] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6943 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6944 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6945 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6946 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6947 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4727 ) , + .prog_clk_1_W_in ( p755 ) , .prog_clk_1_E_in ( p664 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4728 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4729 ) , .prog_clk_2_E_in ( prog_clk_2_wires[49] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6948 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4730 ) , .prog_clk_2_W_out ( prog_clk_2_wires[50] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6949 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6950 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6951 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6952 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6953 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6954 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6955 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6956 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6957 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4731 ) , + .prog_clk_3_W_in ( p1493 ) , .prog_clk_3_E_in ( p203 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4732 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4733 ) , .clk_1_W_in ( p755 ) , + .clk_1_E_in ( p796 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4734 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4735 ) , .clk_2_E_in ( clk_2_wires[49] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6958 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4736 ) , .clk_2_W_out ( clk_2_wires[50] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6959 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6960 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6961 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6962 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6963 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4737 ) , .clk_3_W_in ( p1493 ) , + .clk_3_E_in ( p1339 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4738 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4739 ) ) ; cbx_1__1_ cbx_4__9_ ( .chanx_left_in ( sb_1__1__30_chanx_right_out ) , .chanx_right_in ( sb_1__1__41_chanx_left_out ) , .ccff_head ( sb_1__1__41_ccff_tail ) , @@ -73044,37 +75405,31 @@ cbx_1__1_ cbx_4__9_ ( .chanx_left_in ( sb_1__1__30_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__41_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6964 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6965 ) , + .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( p2313 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4740 ) , .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[41] ) , .prog_clk_0_N_in ( prog_clk_0_wires[166] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6966 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4741 ) , .prog_clk_1_W_in ( prog_clk_1_wires[71] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6967 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4742 ) , .prog_clk_1_N_out ( prog_clk_1_wires[75] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6968 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6969 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6970 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6971 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6972 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6973 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6974 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6975 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , .prog_clk_2_E_in ( p1546 ) , + .prog_clk_2_W_in ( p1369 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4743 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4744 ) , + .prog_clk_3_W_in ( p2586 ) , .prog_clk_3_E_in ( p2664 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4745 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4746 ) , .clk_1_W_in ( clk_1_wires[71] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6976 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4747 ) , .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6977 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6978 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6979 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6980 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6981 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6982 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6983 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6984 ) ) ; + .clk_2_E_in ( p2719 ) , .clk_2_W_in ( p2821 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4748 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4749 ) , .clk_3_W_in ( p2881 ) , + .clk_3_E_in ( p1357 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4750 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4751 ) ) ; cbx_1__1_ cbx_4__10_ ( .chanx_left_in ( sb_1__1__31_chanx_right_out ) , .chanx_right_in ( sb_1__1__42_chanx_left_out ) , .ccff_head ( sb_1__1__42_ccff_tail ) , @@ -73096,38 +75451,31 @@ cbx_1__1_ cbx_4__10_ ( .chanx_left_in ( sb_1__1__31_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__42_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_6985 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6986 ) , + .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( p1780 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4752 ) , .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[42] ) , .prog_clk_0_N_in ( prog_clk_0_wires[169] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6987 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6988 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6989 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6990 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6991 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4753 ) , + .prog_clk_1_W_in ( p1496 ) , .prog_clk_1_E_in ( p577 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4754 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4755 ) , .prog_clk_2_E_in ( prog_clk_2_wires[62] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6992 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4756 ) , .prog_clk_2_W_out ( prog_clk_2_wires[63] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6993 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6994 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6995 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6997 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6998 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6999 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7000 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7001 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4757 ) , + .prog_clk_3_W_in ( p1643 ) , .prog_clk_3_E_in ( p1484 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4758 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4759 ) , .clk_1_W_in ( p1496 ) , + .clk_1_E_in ( p1380 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4760 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4761 ) , .clk_2_E_in ( clk_2_wires[62] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7002 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4762 ) , .clk_2_W_out ( clk_2_wires[63] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7003 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7004 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7005 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7006 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7007 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4763 ) , .clk_3_W_in ( p1643 ) , + .clk_3_E_in ( p2429 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4764 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4765 ) ) ; cbx_1__1_ cbx_4__11_ ( .chanx_left_in ( sb_1__1__32_chanx_right_out ) , .chanx_right_in ( sb_1__1__43_chanx_left_out ) , .ccff_head ( sb_1__1__43_ccff_tail ) , @@ -73149,37 +75497,31 @@ cbx_1__1_ cbx_4__11_ ( .chanx_left_in ( sb_1__1__32_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__43_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7008 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7009 ) , + .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( p2302 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4766 ) , .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[43] ) , .prog_clk_0_N_in ( prog_clk_0_wires[172] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7010 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4767 ) , .prog_clk_1_W_in ( prog_clk_1_wires[78] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7011 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4768 ) , .prog_clk_1_N_out ( prog_clk_1_wires[82] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7012 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7013 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7014 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7015 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7016 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7017 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7018 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7019 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , .prog_clk_2_E_in ( p2739 ) , + .prog_clk_2_W_in ( p1020 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4769 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4770 ) , + .prog_clk_3_W_in ( p2166 ) , .prog_clk_3_E_in ( p2690 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4771 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4772 ) , .clk_1_W_in ( clk_1_wires[78] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7020 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4773 ) , .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7021 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7022 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7023 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7024 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7025 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7026 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7028 ) ) ; + .clk_2_E_in ( p2767 ) , .clk_2_W_in ( p2836 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4774 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4775 ) , .clk_3_W_in ( p2874 ) , + .clk_3_E_in ( p2645 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4776 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4777 ) ) ; cbx_1__1_ cbx_5__1_ ( .chanx_left_in ( sb_1__1__33_chanx_right_out ) , .chanx_right_in ( sb_1__1__44_chanx_left_out ) , .ccff_head ( sb_1__1__44_ccff_tail ) , @@ -73202,36 +75544,29 @@ cbx_1__1_ cbx_5__1_ ( .chanx_left_in ( sb_1__1__33_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) , - .SC_OUT_BOT ( scff_Wires[129] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7029 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7030 ) , + .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( p1818 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4778 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) , .prog_clk_0_N_in ( prog_clk_0_wires[180] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7031 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7032 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4779 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4780 ) , .prog_clk_1_E_in ( prog_clk_1_wires[86] ) , .prog_clk_1_N_out ( prog_clk_1_wires[87] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7033 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7034 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7035 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7036 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7037 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7038 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7039 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7040 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7041 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , .prog_clk_2_E_in ( p2926 ) , + .prog_clk_2_W_in ( p1543 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4781 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4782 ) , + .prog_clk_3_W_in ( p2543 ) , .prog_clk_3_E_in ( p2000 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4783 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4784 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4785 ) , .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) , - .clk_1_S_out ( clk_1_wires[88] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7042 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7043 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7044 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7045 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7046 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7047 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7048 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7049 ) ) ; + .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( p2132 ) , + .clk_2_W_in ( p2470 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4786 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4787 ) , .clk_3_W_in ( p2543 ) , + .clk_3_E_in ( p2825 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4788 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4789 ) ) ; cbx_1__1_ cbx_5__2_ ( .chanx_left_in ( sb_1__1__34_chanx_right_out ) , .chanx_right_in ( sb_1__1__45_chanx_left_out ) , .ccff_head ( sb_1__1__45_ccff_tail ) , @@ -73254,37 +75589,30 @@ cbx_1__1_ cbx_5__2_ ( .chanx_left_in ( sb_1__1__34_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) , - .SC_OUT_BOT ( scff_Wires[127] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7050 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7051 ) , + .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( p1762 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4790 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) , .prog_clk_0_N_in ( prog_clk_0_wires[183] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7052 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7053 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7054 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7055 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7056 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7057 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4791 ) , + .prog_clk_1_W_in ( p1404 ) , .prog_clk_1_E_in ( p369 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4792 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4793 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4794 ) , .prog_clk_2_W_in ( prog_clk_2_wires[25] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7059 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7060 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7061 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7062 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7063 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7064 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7065 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7066 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7067 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4795 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , .prog_clk_3_W_in ( p1836 ) , + .prog_clk_3_E_in ( p253 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4796 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4797 ) , .clk_1_W_in ( p1404 ) , + .clk_1_E_in ( p1265 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4798 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4799 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4800 ) , .clk_2_W_in ( clk_2_wires[25] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7068 ) , - .clk_2_E_out ( clk_2_wires[26] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7069 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7070 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7071 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7072 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4801 ) , + .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1836 ) , + .clk_3_E_in ( p1939 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4802 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4803 ) ) ; cbx_1__1_ cbx_5__3_ ( .chanx_left_in ( sb_1__1__35_chanx_right_out ) , .chanx_right_in ( sb_1__1__46_chanx_left_out ) , .ccff_head ( sb_1__1__46_ccff_tail ) , @@ -73307,36 +75635,29 @@ cbx_1__1_ cbx_5__3_ ( .chanx_left_in ( sb_1__1__35_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) , - .SC_OUT_BOT ( scff_Wires[125] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7073 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7074 ) , + .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( p1456 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4804 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) , .prog_clk_0_N_in ( prog_clk_0_wires[186] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7075 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7076 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4805 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4806 ) , .prog_clk_1_E_in ( prog_clk_1_wires[93] ) , .prog_clk_1_N_out ( prog_clk_1_wires[94] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7077 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7078 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7079 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7080 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7081 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7082 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7083 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7084 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7085 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , .prog_clk_2_E_in ( p2587 ) , + .prog_clk_2_W_in ( p52 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4807 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4808 ) , + .prog_clk_3_W_in ( p2594 ) , .prog_clk_3_E_in ( p1966 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4809 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4810 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4811 ) , .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) , - .clk_1_S_out ( clk_1_wires[95] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7086 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7087 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7088 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7089 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7090 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7091 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7093 ) ) ; + .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( p2067 ) , + .clk_2_W_in ( p2966 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4812 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4813 ) , .clk_3_W_in ( p3018 ) , + .clk_3_E_in ( p2489 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4814 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4815 ) ) ; cbx_1__1_ cbx_5__4_ ( .chanx_left_in ( sb_1__1__36_chanx_right_out ) , .chanx_right_in ( sb_1__1__47_chanx_left_out ) , .ccff_head ( sb_1__1__47_ccff_tail ) , @@ -73359,37 +75680,30 @@ cbx_1__1_ cbx_5__4_ ( .chanx_left_in ( sb_1__1__36_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) , - .SC_OUT_BOT ( scff_Wires[123] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7094 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7095 ) , + .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( p2116 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4816 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) , .prog_clk_0_N_in ( prog_clk_0_wires[189] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7096 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7097 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7098 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7099 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7100 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7101 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4817 ) , + .prog_clk_1_W_in ( p1497 ) , .prog_clk_1_E_in ( p966 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4818 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4819 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4820 ) , .prog_clk_2_W_in ( prog_clk_2_wires[34] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7102 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7103 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7104 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7105 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7106 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7107 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7108 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7109 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7110 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7111 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4821 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , .prog_clk_3_W_in ( p1242 ) , + .prog_clk_3_E_in ( p393 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4822 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4823 ) , .clk_1_W_in ( p1497 ) , + .clk_1_E_in ( p1943 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4824 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4825 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4826 ) , .clk_2_W_in ( clk_2_wires[34] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7112 ) , - .clk_2_E_out ( clk_2_wires[35] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7113 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7114 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7115 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7116 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4827 ) , + .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p1242 ) , + .clk_3_E_in ( p2472 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4828 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4829 ) ) ; cbx_1__1_ cbx_5__5_ ( .chanx_left_in ( sb_1__1__37_chanx_right_out ) , .chanx_right_in ( sb_1__1__48_chanx_left_out ) , .ccff_head ( sb_1__1__48_ccff_tail ) , @@ -73412,36 +75726,29 @@ cbx_1__1_ cbx_5__5_ ( .chanx_left_in ( sb_1__1__37_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) , - .SC_OUT_BOT ( scff_Wires[121] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7117 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7118 ) , + .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( p1666 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4830 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) , .prog_clk_0_N_in ( prog_clk_0_wires[192] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7119 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7120 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4831 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4832 ) , .prog_clk_1_E_in ( prog_clk_1_wires[100] ) , .prog_clk_1_N_out ( prog_clk_1_wires[101] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7121 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7122 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7123 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7124 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7125 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7126 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7127 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7128 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7129 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , .prog_clk_2_E_in ( p2133 ) , + .prog_clk_2_W_in ( p1284 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4833 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4834 ) , + .prog_clk_3_W_in ( p2400 ) , .prog_clk_3_E_in ( p2474 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4835 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4836 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4837 ) , .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) , - .clk_1_S_out ( clk_1_wires[102] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7130 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7131 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7132 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7133 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7134 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7135 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7136 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7137 ) ) ; + .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( p2565 ) , + .clk_2_W_in ( p2226 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4838 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4839 ) , .clk_3_W_in ( p2406 ) , + .clk_3_E_in ( p1991 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4840 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4841 ) ) ; cbx_1__1_ cbx_5__6_ ( .chanx_left_in ( sb_1__1__38_chanx_right_out ) , .chanx_right_in ( sb_1__1__49_chanx_left_out ) , .ccff_head ( sb_1__1__49_ccff_tail ) , @@ -73464,36 +75771,29 @@ cbx_1__1_ cbx_5__6_ ( .chanx_left_in ( sb_1__1__38_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) , - .SC_OUT_BOT ( scff_Wires[119] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7138 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7139 ) , + .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( p2149 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4842 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) , .prog_clk_0_N_in ( prog_clk_0_wires[195] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7140 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7141 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7142 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7143 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7144 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7145 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7146 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7147 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7148 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7149 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4843 ) , + .prog_clk_1_W_in ( p1692 ) , .prog_clk_1_E_in ( p261 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4844 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4845 ) , + .prog_clk_2_E_in ( p1697 ) , .prog_clk_2_W_in ( p683 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4846 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4847 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4848 ) , .prog_clk_3_E_in ( prog_clk_3_wires[6] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7150 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7151 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7152 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7153 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7154 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7155 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7156 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7157 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7158 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7159 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4849 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( p1692 ) , + .clk_1_E_in ( p1892 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4850 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4851 ) , .clk_2_E_in ( p1697 ) , + .clk_2_W_in ( p1299 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4852 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4853 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4854 ) , .clk_3_E_in ( clk_3_wires[6] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7160 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4855 ) , .clk_3_W_out ( clk_3_wires[7] ) ) ; cbx_1__1_ cbx_5__7_ ( .chanx_left_in ( sb_1__1__39_chanx_right_out ) , .chanx_right_in ( sb_1__1__50_chanx_left_out ) , @@ -73517,36 +75817,29 @@ cbx_1__1_ cbx_5__7_ ( .chanx_left_in ( sb_1__1__39_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) , - .SC_OUT_BOT ( scff_Wires[117] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7161 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7162 ) , + .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( p2347 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4856 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) , .prog_clk_0_N_in ( prog_clk_0_wires[198] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7163 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7164 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4857 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4858 ) , .prog_clk_1_E_in ( prog_clk_1_wires[107] ) , .prog_clk_1_N_out ( prog_clk_1_wires[108] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7165 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7166 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7167 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7168 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7169 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7170 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7172 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7173 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , .prog_clk_2_E_in ( p2325 ) , + .prog_clk_2_W_in ( p1289 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4859 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4860 ) , + .prog_clk_3_W_in ( p2170 ) , .prog_clk_3_E_in ( p1951 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4861 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4862 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4863 ) , .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) , - .clk_1_S_out ( clk_1_wires[109] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7174 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7175 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7176 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7177 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7178 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7179 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7180 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7181 ) ) ; + .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( p2115 ) , + .clk_2_W_in ( p1952 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4864 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4865 ) , .clk_3_W_in ( p2170 ) , + .clk_3_E_in ( p2275 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4866 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4867 ) ) ; cbx_1__1_ cbx_5__8_ ( .chanx_left_in ( sb_1__1__40_chanx_right_out ) , .chanx_right_in ( sb_1__1__51_chanx_left_out ) , .ccff_head ( sb_1__1__51_ccff_tail ) , @@ -73569,37 +75862,30 @@ cbx_1__1_ cbx_5__8_ ( .chanx_left_in ( sb_1__1__40_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) , - .SC_OUT_BOT ( scff_Wires[115] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7182 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7183 ) , + .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( p1463 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4868 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) , .prog_clk_0_N_in ( prog_clk_0_wires[201] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7184 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7185 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7186 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7187 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7188 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7189 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4869 ) , + .prog_clk_1_W_in ( p1396 ) , .prog_clk_1_E_in ( p81 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4870 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4871 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4872 ) , .prog_clk_2_W_in ( prog_clk_2_wires[47] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7190 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7191 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7192 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7193 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7194 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7195 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7196 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7197 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7198 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7199 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4873 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , .prog_clk_3_W_in ( p1513 ) , + .prog_clk_3_E_in ( p1343 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4874 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4875 ) , .clk_1_W_in ( p1396 ) , + .clk_1_E_in ( p1119 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4876 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4877 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4878 ) , .clk_2_W_in ( clk_2_wires[47] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7200 ) , - .clk_2_E_out ( clk_2_wires[48] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7201 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7202 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7204 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4879 ) , + .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p1513 ) , + .clk_3_E_in ( p2222 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4880 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4881 ) ) ; cbx_1__1_ cbx_5__9_ ( .chanx_left_in ( sb_1__1__41_chanx_right_out ) , .chanx_right_in ( sb_1__1__52_chanx_left_out ) , .ccff_head ( sb_1__1__52_ccff_tail ) , @@ -73622,36 +75908,29 @@ cbx_1__1_ cbx_5__9_ ( .chanx_left_in ( sb_1__1__41_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) , - .SC_OUT_BOT ( scff_Wires[113] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7205 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7206 ) , + .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( p1367 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4882 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) , .prog_clk_0_N_in ( prog_clk_0_wires[204] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7207 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7208 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4883 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4884 ) , .prog_clk_1_E_in ( prog_clk_1_wires[114] ) , .prog_clk_1_N_out ( prog_clk_1_wires[115] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7209 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7210 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7211 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7212 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7213 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7214 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7215 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7216 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7217 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , .prog_clk_2_E_in ( p1821 ) , + .prog_clk_2_W_in ( p456 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4885 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4886 ) , + .prog_clk_3_W_in ( p2787 ) , .prog_clk_3_E_in ( p2817 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4887 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4888 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4889 ) , .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) , - .clk_1_S_out ( clk_1_wires[116] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7218 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7219 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7220 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7221 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7222 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7223 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7224 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7225 ) ) ; + .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( p2906 ) , + .clk_2_W_in ( p2649 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4890 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4891 ) , .clk_3_W_in ( p2787 ) , + .clk_3_E_in ( p1133 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4892 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4893 ) ) ; cbx_1__1_ cbx_5__10_ ( .chanx_left_in ( sb_1__1__42_chanx_right_out ) , .chanx_right_in ( sb_1__1__53_chanx_left_out ) , .ccff_head ( sb_1__1__53_ccff_tail ) , @@ -73674,37 +75953,30 @@ cbx_1__1_ cbx_5__10_ ( .chanx_left_in ( sb_1__1__42_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) , - .SC_OUT_BOT ( scff_Wires[111] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7226 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7227 ) , + .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( p1385 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4894 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) , .prog_clk_0_N_in ( prog_clk_0_wires[207] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7228 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7229 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7230 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7231 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7232 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7233 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4895 ) , + .prog_clk_1_W_in ( p1608 ) , .prog_clk_1_E_in ( p461 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4896 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4897 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4898 ) , .prog_clk_2_W_in ( prog_clk_2_wires[60] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7234 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7235 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7236 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7237 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7238 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7239 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7240 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7241 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7242 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7243 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4899 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , .prog_clk_3_W_in ( p1657 ) , + .prog_clk_3_E_in ( p291 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4900 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4901 ) , .clk_1_W_in ( p1608 ) , + .clk_1_E_in ( p999 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4902 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4903 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4904 ) , .clk_2_W_in ( clk_2_wires[60] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7244 ) , - .clk_2_E_out ( clk_2_wires[61] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7245 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7246 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7247 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7248 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4905 ) , + .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p1657 ) , + .clk_3_E_in ( p2197 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4906 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4907 ) ) ; cbx_1__1_ cbx_5__11_ ( .chanx_left_in ( sb_1__1__43_chanx_right_out ) , .chanx_right_in ( sb_1__1__54_chanx_left_out ) , .ccff_head ( sb_1__1__54_ccff_tail ) , @@ -73727,36 +75999,29 @@ cbx_1__1_ cbx_5__11_ ( .chanx_left_in ( sb_1__1__43_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) , - .SC_OUT_BOT ( scff_Wires[109] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7249 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7250 ) , + .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( p1336 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4908 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) , .prog_clk_0_N_in ( prog_clk_0_wires[210] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7251 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7252 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4909 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_4910 ) , .prog_clk_1_E_in ( prog_clk_1_wires[121] ) , .prog_clk_1_N_out ( prog_clk_1_wires[122] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7253 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7254 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7255 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7256 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7257 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7258 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7259 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7260 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7261 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , .prog_clk_2_E_in ( p1591 ) , + .prog_clk_2_W_in ( p958 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4911 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4912 ) , + .prog_clk_3_W_in ( p2320 ) , .prog_clk_3_E_in ( p2486 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4913 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4914 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_4915 ) , .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) , - .clk_1_S_out ( clk_1_wires[123] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7262 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7263 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7264 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7265 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7266 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7267 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7268 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7269 ) ) ; + .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( p2625 ) , + .clk_2_W_in ( p2208 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4916 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4917 ) , .clk_3_W_in ( p2320 ) , + .clk_3_E_in ( p1556 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4918 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4919 ) ) ; cbx_1__1_ cbx_6__1_ ( .chanx_left_in ( sb_1__1__44_chanx_right_out ) , .chanx_right_in ( sb_1__1__55_chanx_left_out ) , .ccff_head ( sb_1__1__55_ccff_tail ) , @@ -73778,37 +76043,31 @@ cbx_1__1_ cbx_6__1_ ( .chanx_left_in ( sb_1__1__44_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__55_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7270 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7271 ) , + .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( p2382 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4920 ) , .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[55] ) , .prog_clk_0_N_in ( prog_clk_0_wires[218] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7272 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4921 ) , .prog_clk_1_W_in ( prog_clk_1_wires[85] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7273 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4922 ) , .prog_clk_1_N_out ( prog_clk_1_wires[89] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7274 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7275 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7276 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7277 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7278 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7279 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7280 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7281 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , .prog_clk_2_E_in ( p2867 ) , + .prog_clk_2_W_in ( p1082 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4923 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4924 ) , + .prog_clk_3_W_in ( p1469 ) , .prog_clk_3_E_in ( p2674 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4925 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4926 ) , .clk_1_W_in ( clk_1_wires[85] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7282 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4927 ) , .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7283 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7284 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7285 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7286 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7287 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7288 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7289 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7290 ) ) ; + .clk_2_E_in ( p2792 ) , .clk_2_W_in ( p787 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4928 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4929 ) , .clk_3_W_in ( p1469 ) , + .clk_3_E_in ( p2829 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4930 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4931 ) ) ; cbx_1__1_ cbx_6__2_ ( .chanx_left_in ( sb_1__1__45_chanx_right_out ) , .chanx_right_in ( sb_1__1__56_chanx_left_out ) , .ccff_head ( sb_1__1__56_ccff_tail ) , @@ -73830,38 +76089,28 @@ cbx_1__1_ cbx_6__2_ ( .chanx_left_in ( sb_1__1__45_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__56_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7291 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7292 ) , + .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( p1797 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4932 ) , .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[56] ) , .prog_clk_0_N_in ( prog_clk_0_wires[221] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7293 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7294 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7295 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7296 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7297 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7298 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7299 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7300 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7301 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7302 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7303 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7304 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7305 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7306 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7307 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7308 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7309 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7310 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7311 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7314 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7315 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7316 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7317 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4933 ) , + .prog_clk_1_W_in ( p1568 ) , .prog_clk_1_E_in ( p835 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4934 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4935 ) , + .prog_clk_2_E_in ( p2147 ) , .prog_clk_2_W_in ( p905 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4936 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4937 ) , + .prog_clk_3_W_in ( p1670 ) , .prog_clk_3_E_in ( p1928 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4938 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4939 ) , .clk_1_W_in ( p1568 ) , + .clk_1_E_in ( p408 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4940 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4941 ) , .clk_2_E_in ( p2030 ) , + .clk_2_W_in ( p1314 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4942 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4943 ) , .clk_3_W_in ( p1670 ) , + .clk_3_E_in ( p2006 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4944 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4945 ) ) ; cbx_1__1_ cbx_6__3_ ( .chanx_left_in ( sb_1__1__46_chanx_right_out ) , .chanx_right_in ( sb_1__1__57_chanx_left_out ) , .ccff_head ( sb_1__1__57_ccff_tail ) , @@ -73883,37 +76132,31 @@ cbx_1__1_ cbx_6__3_ ( .chanx_left_in ( sb_1__1__46_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__57_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7318 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7319 ) , + .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( p1440 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4946 ) , .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[57] ) , .prog_clk_0_N_in ( prog_clk_0_wires[224] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7320 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4947 ) , .prog_clk_1_W_in ( prog_clk_1_wires[92] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7321 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4948 ) , .prog_clk_1_N_out ( prog_clk_1_wires[96] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7322 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7323 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7324 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7325 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7326 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7327 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7328 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7329 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , .prog_clk_2_E_in ( p2751 ) , + .prog_clk_2_W_in ( p532 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4949 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4950 ) , + .prog_clk_3_W_in ( p1649 ) , .prog_clk_3_E_in ( p2634 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4951 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4952 ) , .clk_1_W_in ( clk_1_wires[92] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7330 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4953 ) , .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7331 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7332 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7333 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7334 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7335 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7336 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7337 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7338 ) ) ; + .clk_2_E_in ( p2768 ) , .clk_2_W_in ( p1345 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4954 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4955 ) , .clk_3_W_in ( p1649 ) , + .clk_3_E_in ( p2697 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4956 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4957 ) ) ; cbx_1__1_ cbx_6__4_ ( .chanx_left_in ( sb_1__1__47_chanx_right_out ) , .chanx_right_in ( sb_1__1__58_chanx_left_out ) , .ccff_head ( sb_1__1__58_ccff_tail ) , @@ -73935,38 +76178,28 @@ cbx_1__1_ cbx_6__4_ ( .chanx_left_in ( sb_1__1__47_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__58_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7339 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7340 ) , + .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( p1613 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4958 ) , .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[58] ) , .prog_clk_0_N_in ( prog_clk_0_wires[227] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7341 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7342 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7343 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7344 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7345 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7346 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7347 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7348 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7349 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7350 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7351 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7352 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7353 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7354 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7355 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7356 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7357 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7358 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7359 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7360 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7361 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7362 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7363 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7364 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7365 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4959 ) , + .prog_clk_1_W_in ( p1489 ) , .prog_clk_1_E_in ( p700 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4960 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4961 ) , + .prog_clk_2_E_in ( p1506 ) , .prog_clk_2_W_in ( p930 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4962 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4963 ) , + .prog_clk_3_W_in ( p1668 ) , .prog_clk_3_E_in ( p347 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4964 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4965 ) , .clk_1_W_in ( p1489 ) , + .clk_1_E_in ( p1092 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4966 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4967 ) , .clk_2_E_in ( p1613 ) , + .clk_2_W_in ( p346 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4968 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4969 ) , .clk_3_W_in ( p1640 ) , + .clk_3_E_in ( p686 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4970 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4971 ) ) ; cbx_1__1_ cbx_6__5_ ( .chanx_left_in ( sb_1__1__48_chanx_right_out ) , .chanx_right_in ( sb_1__1__59_chanx_left_out ) , .ccff_head ( sb_1__1__59_ccff_tail ) , @@ -73988,37 +76221,31 @@ cbx_1__1_ cbx_6__5_ ( .chanx_left_in ( sb_1__1__48_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__59_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7366 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7367 ) , + .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( p2305 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4972 ) , .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[59] ) , .prog_clk_0_N_in ( prog_clk_0_wires[230] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7368 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4973 ) , .prog_clk_1_W_in ( prog_clk_1_wires[99] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7369 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_4974 ) , .prog_clk_1_N_out ( prog_clk_1_wires[103] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7370 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7371 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7372 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7373 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7374 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7375 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7376 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7377 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , .prog_clk_2_E_in ( p2424 ) , + .prog_clk_2_W_in ( p1441 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4975 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4976 ) , + .prog_clk_3_W_in ( p1771 ) , .prog_clk_3_E_in ( p2830 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4977 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4978 ) , .clk_1_W_in ( clk_1_wires[99] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7378 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_4979 ) , .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7379 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7380 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7381 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7382 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7383 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7384 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7385 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7386 ) ) ; + .clk_2_E_in ( p2912 ) , .clk_2_W_in ( p842 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4980 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4981 ) , .clk_3_W_in ( p1771 ) , + .clk_3_E_in ( p2286 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4982 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4983 ) ) ; cbx_1__1_ cbx_6__6_ ( .chanx_left_in ( sb_1__1__49_chanx_right_out ) , .chanx_right_in ( sb_1__1__60_chanx_left_out ) , .ccff_head ( sb_1__1__60_ccff_tail ) , @@ -74040,37 +76267,30 @@ cbx_1__1_ cbx_6__6_ ( .chanx_left_in ( sb_1__1__49_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__60_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7387 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7388 ) , + .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( p1816 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4984 ) , .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[60] ) , .prog_clk_0_N_in ( prog_clk_0_wires[233] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7389 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7390 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7391 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7392 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7393 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7394 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7395 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7396 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7397 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7398 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4985 ) , + .prog_clk_1_W_in ( p1747 ) , .prog_clk_1_E_in ( p951 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_4986 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_4987 ) , + .prog_clk_2_E_in ( p2415 ) , .prog_clk_2_W_in ( p131 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4988 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4989 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4990 ) , .prog_clk_3_E_in ( prog_clk_3_wires[2] ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7399 ) , - .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7400 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7401 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7402 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7403 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7404 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7405 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7406 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7407 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7408 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4991 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( p1747 ) , + .clk_1_E_in ( p609 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_4992 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_4993 ) , .clk_2_E_in ( p1786 ) , + .clk_2_W_in ( p1413 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4994 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4995 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4996 ) , .clk_3_E_in ( clk_3_wires[2] ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4997 ) , .clk_3_W_out ( clk_3_wires[3] ) ) ; cbx_1__1_ cbx_6__7_ ( .chanx_left_in ( sb_1__1__50_chanx_right_out ) , .chanx_right_in ( sb_1__1__61_chanx_left_out ) , @@ -74093,37 +76313,31 @@ cbx_1__1_ cbx_6__7_ ( .chanx_left_in ( sb_1__1__50_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__61_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7410 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7411 ) , + .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( p2408 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_4998 ) , .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[61] ) , .prog_clk_0_N_in ( prog_clk_0_wires[236] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7412 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_4999 ) , .prog_clk_1_W_in ( prog_clk_1_wires[106] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7413 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5000 ) , .prog_clk_1_N_out ( prog_clk_1_wires[110] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7414 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7415 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7416 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7417 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7418 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7419 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7420 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7421 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , .prog_clk_2_E_in ( p2402 ) , + .prog_clk_2_W_in ( p277 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5001 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5002 ) , + .prog_clk_3_W_in ( p2546 ) , .prog_clk_3_E_in ( p2263 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5003 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5004 ) , .clk_1_W_in ( clk_1_wires[106] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7422 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5005 ) , .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7423 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7424 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7425 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7426 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7427 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7428 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7429 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7430 ) ) ; + .clk_2_E_in ( p2408 ) , .clk_2_W_in ( p2485 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5006 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5007 ) , .clk_3_W_in ( p2573 ) , + .clk_3_E_in ( p2193 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5008 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5009 ) ) ; cbx_1__1_ cbx_6__8_ ( .chanx_left_in ( sb_1__1__51_chanx_right_out ) , .chanx_right_in ( sb_1__1__62_chanx_left_out ) , .ccff_head ( sb_1__1__62_ccff_tail ) , @@ -74145,38 +76359,28 @@ cbx_1__1_ cbx_6__8_ ( .chanx_left_in ( sb_1__1__51_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__62_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7431 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7432 ) , + .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( p1800 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5010 ) , .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[62] ) , .prog_clk_0_N_in ( prog_clk_0_wires[239] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7433 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7434 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7435 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7436 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7437 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7438 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7439 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7442 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7443 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7444 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7445 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7446 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7447 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7448 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7449 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7450 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7451 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7452 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7453 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7454 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7455 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7456 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7457 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5011 ) , + .prog_clk_1_W_in ( p1473 ) , .prog_clk_1_E_in ( p1438 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5012 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5013 ) , + .prog_clk_2_E_in ( p1772 ) , .prog_clk_2_W_in ( p812 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5014 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5015 ) , + .prog_clk_3_W_in ( p1594 ) , .prog_clk_3_E_in ( p96 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5016 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5017 ) , .clk_1_W_in ( p1473 ) , + .clk_1_E_in ( p559 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5018 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5019 ) , .clk_2_E_in ( p1800 ) , + .clk_2_W_in ( p1189 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5020 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5021 ) , .clk_3_W_in ( p1594 ) , + .clk_3_E_in ( p1063 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5022 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5023 ) ) ; cbx_1__1_ cbx_6__9_ ( .chanx_left_in ( sb_1__1__52_chanx_right_out ) , .chanx_right_in ( sb_1__1__63_chanx_left_out ) , .ccff_head ( sb_1__1__63_ccff_tail ) , @@ -74198,37 +76402,31 @@ cbx_1__1_ cbx_6__9_ ( .chanx_left_in ( sb_1__1__52_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__63_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7458 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7459 ) , + .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( p2291 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5024 ) , .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[63] ) , .prog_clk_0_N_in ( prog_clk_0_wires[242] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7460 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5025 ) , .prog_clk_1_W_in ( prog_clk_1_wires[113] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7461 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5026 ) , .prog_clk_1_N_out ( prog_clk_1_wires[117] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7462 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7463 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7464 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7465 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7466 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7467 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7468 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7469 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , .prog_clk_2_E_in ( p2510 ) , + .prog_clk_2_W_in ( p1303 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5027 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5028 ) , + .prog_clk_3_W_in ( p1416 ) , .prog_clk_3_E_in ( p2960 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5029 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5030 ) , .clk_1_W_in ( clk_1_wires[113] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7470 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5031 ) , .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7471 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7472 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7473 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7474 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7475 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7476 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7477 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7478 ) ) ; + .clk_2_E_in ( p3022 ) , .clk_2_W_in ( p521 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5032 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5033 ) , .clk_3_W_in ( p1416 ) , + .clk_3_E_in ( p2433 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5034 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5035 ) ) ; cbx_1__1_ cbx_6__10_ ( .chanx_left_in ( sb_1__1__53_chanx_right_out ) , .chanx_right_in ( sb_1__1__64_chanx_left_out ) , .ccff_head ( sb_1__1__64_ccff_tail ) , @@ -74250,38 +76448,28 @@ cbx_1__1_ cbx_6__10_ ( .chanx_left_in ( sb_1__1__53_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__64_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7479 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7480 ) , + .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( p2096 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5036 ) , .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[64] ) , .prog_clk_0_N_in ( prog_clk_0_wires[245] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7481 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7482 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7483 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7484 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7485 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7486 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7487 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7488 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7489 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7490 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7491 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7492 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7493 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7494 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7495 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7496 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7497 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7498 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7499 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7500 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7501 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7502 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7503 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7504 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7505 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5037 ) , + .prog_clk_1_W_in ( p1686 ) , .prog_clk_1_E_in ( p668 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5038 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5039 ) , + .prog_clk_2_E_in ( p2113 ) , .prog_clk_2_W_in ( p1564 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5040 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5041 ) , + .prog_clk_3_W_in ( p2052 ) , .prog_clk_3_E_in ( p2800 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5042 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5043 ) , .clk_1_W_in ( p1686 ) , + .clk_1_E_in ( p1308 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5044 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5045 ) , .clk_2_E_in ( p2934 ) , + .clk_2_W_in ( p1941 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5046 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5047 ) , .clk_3_W_in ( p2052 ) , + .clk_3_E_in ( p1993 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5048 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5049 ) ) ; cbx_1__1_ cbx_6__11_ ( .chanx_left_in ( sb_1__1__54_chanx_right_out ) , .chanx_right_in ( sb_1__1__65_chanx_left_out ) , .ccff_head ( sb_1__1__65_ccff_tail ) , @@ -74303,37 +76491,31 @@ cbx_1__1_ cbx_6__11_ ( .chanx_left_in ( sb_1__1__54_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__65_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7506 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7507 ) , + .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( p1882 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5050 ) , .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[65] ) , .prog_clk_0_N_in ( prog_clk_0_wires[248] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7508 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5051 ) , .prog_clk_1_W_in ( prog_clk_1_wires[120] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7509 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5052 ) , .prog_clk_1_N_out ( prog_clk_1_wires[124] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7510 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7511 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7512 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7513 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7514 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7515 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7516 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7517 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , .prog_clk_2_E_in ( p2292 ) , + .prog_clk_2_W_in ( p657 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5053 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5054 ) , + .prog_clk_3_W_in ( p1434 ) , .prog_clk_3_E_in ( p1447 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5055 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5056 ) , .clk_1_W_in ( clk_1_wires[120] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7518 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5057 ) , .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7519 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7520 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7521 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7522 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7523 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7524 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7525 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7526 ) ) ; + .clk_2_E_in ( p1882 ) , .clk_2_W_in ( p2181 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5058 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5059 ) , .clk_3_W_in ( p2326 ) , + .clk_3_E_in ( p2188 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5060 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5061 ) ) ; cbx_1__1_ cbx_7__1_ ( .chanx_left_in ( sb_1__1__55_chanx_right_out ) , .chanx_right_in ( sb_1__1__66_chanx_left_out ) , .ccff_head ( sb_1__1__66_ccff_tail ) , @@ -74356,36 +76538,29 @@ cbx_1__1_ cbx_7__1_ ( .chanx_left_in ( sb_1__1__55_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) , - .SC_OUT_BOT ( scff_Wires[182] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7527 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7528 ) , + .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( p1781 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5062 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) , .prog_clk_0_N_in ( prog_clk_0_wires[256] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7529 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7530 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5063 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5064 ) , .prog_clk_1_E_in ( prog_clk_1_wires[128] ) , .prog_clk_1_N_out ( prog_clk_1_wires[129] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7531 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7532 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7533 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7534 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7535 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7536 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7538 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7539 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , .prog_clk_2_E_in ( p1737 ) , + .prog_clk_2_W_in ( p1254 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5065 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5066 ) , + .prog_clk_3_W_in ( p1770 ) , .prog_clk_3_E_in ( p2497 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5067 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5068 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5069 ) , .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) , - .clk_1_S_out ( clk_1_wires[130] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7540 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7541 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7542 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7543 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7544 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7545 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7546 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7547 ) ) ; + .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( p2541 ) , + .clk_2_W_in ( p760 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5070 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5071 ) , .clk_3_W_in ( p1770 ) , + .clk_3_E_in ( p29 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5072 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5073 ) ) ; cbx_1__1_ cbx_7__2_ ( .chanx_left_in ( sb_1__1__56_chanx_right_out ) , .chanx_right_in ( sb_1__1__67_chanx_left_out ) , .ccff_head ( sb_1__1__67_ccff_tail ) , @@ -74408,37 +76583,27 @@ cbx_1__1_ cbx_7__2_ ( .chanx_left_in ( sb_1__1__56_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) , - .SC_OUT_BOT ( scff_Wires[180] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7548 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7549 ) , + .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( p2518 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5074 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) , .prog_clk_0_N_in ( prog_clk_0_wires[259] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7550 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7551 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7552 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7553 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7554 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7555 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7556 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7557 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7558 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7559 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7560 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7561 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7562 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7563 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7564 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7565 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7566 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7567 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7568 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7569 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7570 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7571 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7572 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7573 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7574 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5075 ) , + .prog_clk_1_W_in ( p1789 ) , .prog_clk_1_E_in ( p534 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5076 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5077 ) , + .prog_clk_2_E_in ( p1749 ) , .prog_clk_2_W_in ( p1462 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5078 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5079 ) , + .prog_clk_3_W_in ( p1867 ) , .prog_clk_3_E_in ( p1932 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5080 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5081 ) , .clk_1_W_in ( p1789 ) , + .clk_1_E_in ( p2462 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5082 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5083 ) , .clk_2_E_in ( p2058 ) , + .clk_2_W_in ( p67 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5084 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5085 ) , .clk_3_W_in ( p1867 ) , + .clk_3_E_in ( p148 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5086 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5087 ) ) ; cbx_1__1_ cbx_7__3_ ( .chanx_left_in ( sb_1__1__57_chanx_right_out ) , .chanx_right_in ( sb_1__1__68_chanx_left_out ) , .ccff_head ( sb_1__1__68_ccff_tail ) , @@ -74461,36 +76626,29 @@ cbx_1__1_ cbx_7__3_ ( .chanx_left_in ( sb_1__1__57_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) , - .SC_OUT_BOT ( scff_Wires[178] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7575 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7576 ) , + .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( p1528 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5088 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) , .prog_clk_0_N_in ( prog_clk_0_wires[262] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7577 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7578 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5089 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5090 ) , .prog_clk_1_E_in ( prog_clk_1_wires[135] ) , .prog_clk_1_N_out ( prog_clk_1_wires[136] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7579 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7580 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7581 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7582 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7583 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7584 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7586 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7587 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , .prog_clk_2_E_in ( p1842 ) , + .prog_clk_2_W_in ( p1176 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5091 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5092 ) , + .prog_clk_3_W_in ( p2064 ) , .prog_clk_3_E_in ( p2811 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5093 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5094 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5095 ) , .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) , - .clk_1_S_out ( clk_1_wires[137] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7588 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7589 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7590 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7591 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7592 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7593 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7594 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7595 ) ) ; + .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( p2894 ) , + .clk_2_W_in ( p1969 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5096 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5097 ) , .clk_3_W_in ( p2064 ) , + .clk_3_E_in ( p604 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5098 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5099 ) ) ; cbx_1__1_ cbx_7__4_ ( .chanx_left_in ( sb_1__1__58_chanx_right_out ) , .chanx_right_in ( sb_1__1__69_chanx_left_out ) , .ccff_head ( sb_1__1__69_ccff_tail ) , @@ -74513,37 +76671,27 @@ cbx_1__1_ cbx_7__4_ ( .chanx_left_in ( sb_1__1__58_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) , - .SC_OUT_BOT ( scff_Wires[176] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7596 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7597 ) , + .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( p1419 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5100 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) , .prog_clk_0_N_in ( prog_clk_0_wires[265] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7598 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7599 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7600 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7601 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7602 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7603 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7604 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7605 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7606 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7607 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7608 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7609 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7610 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7611 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7612 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7613 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7614 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7615 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7616 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7617 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7618 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7619 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7620 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7621 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7622 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5101 ) , + .prog_clk_1_W_in ( p1582 ) , .prog_clk_1_E_in ( p1332 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5102 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5103 ) , + .prog_clk_2_E_in ( p2127 ) , .prog_clk_2_W_in ( p1384 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5104 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5105 ) , + .prog_clk_3_W_in ( p1791 ) , .prog_clk_3_E_in ( p3168 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5106 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5107 ) , .clk_1_W_in ( p1582 ) , + .clk_1_E_in ( p434 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5108 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5109 ) , .clk_2_E_in ( p3203 ) , + .clk_2_W_in ( p481 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5110 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5111 ) , .clk_3_W_in ( p1791 ) , + .clk_3_E_in ( p1982 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5112 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5113 ) ) ; cbx_1__1_ cbx_7__5_ ( .chanx_left_in ( sb_1__1__59_chanx_right_out ) , .chanx_right_in ( sb_1__1__70_chanx_left_out ) , .ccff_head ( sb_1__1__70_ccff_tail ) , @@ -74566,36 +76714,29 @@ cbx_1__1_ cbx_7__5_ ( .chanx_left_in ( sb_1__1__59_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) , - .SC_OUT_BOT ( scff_Wires[174] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7623 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7624 ) , + .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( p1588 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5114 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) , .prog_clk_0_N_in ( prog_clk_0_wires[268] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7625 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7626 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5115 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5116 ) , .prog_clk_1_E_in ( prog_clk_1_wires[142] ) , .prog_clk_1_N_out ( prog_clk_1_wires[143] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7627 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7628 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7629 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7630 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7631 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7632 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7634 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7635 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , .prog_clk_2_E_in ( p280 ) , + .prog_clk_2_W_in ( p110 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5117 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5118 ) , + .prog_clk_3_W_in ( p1665 ) , .prog_clk_3_E_in ( p3249 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5119 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5120 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5121 ) , .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) , - .clk_1_S_out ( clk_1_wires[144] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7636 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7637 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7638 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7639 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7640 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7641 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7642 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7643 ) ) ; + .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( p3267 ) , + .clk_2_W_in ( p926 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5122 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5123 ) , .clk_3_W_in ( p1665 ) , + .clk_3_E_in ( p792 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5124 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5125 ) ) ; cbx_1__1_ cbx_7__6_ ( .chanx_left_in ( sb_1__1__60_chanx_right_out ) , .chanx_right_in ( sb_1__1__71_chanx_left_out ) , .ccff_head ( sb_1__1__71_ccff_tail ) , @@ -74618,37 +76759,30 @@ cbx_1__1_ cbx_7__6_ ( .chanx_left_in ( sb_1__1__60_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) , - .SC_OUT_BOT ( scff_Wires[172] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7644 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7645 ) , + .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( p2418 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5126 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) , .prog_clk_0_N_in ( prog_clk_0_wires[271] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7646 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7647 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7648 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7649 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7650 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7651 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7652 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7653 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7654 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5127 ) , + .prog_clk_1_W_in ( p1607 ) , .prog_clk_1_E_in ( p1175 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5128 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5129 ) , + .prog_clk_2_E_in ( p2354 ) , .prog_clk_2_W_in ( p447 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5130 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5131 ) , .prog_clk_3_W_in ( prog_clk_3_wires[0] ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7655 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5132 ) , .prog_clk_3_E_out ( prog_clk_3_wires[1] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7656 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7657 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7658 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7659 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7660 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7661 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7662 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7663 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7664 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5133 ) , .clk_1_W_in ( p1607 ) , + .clk_1_E_in ( p2255 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5134 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5135 ) , .clk_2_E_in ( p1620 ) , + .clk_2_W_in ( p1403 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5136 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5137 ) , .clk_3_W_in ( clk_3_wires[0] ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7665 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5138 ) , .clk_3_E_out ( clk_3_wires[1] ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7666 ) ) ; + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5139 ) ) ; cbx_1__1_ cbx_7__7_ ( .chanx_left_in ( sb_1__1__61_chanx_right_out ) , .chanx_right_in ( sb_1__1__72_chanx_left_out ) , .ccff_head ( sb_1__1__72_ccff_tail ) , @@ -74671,36 +76805,29 @@ cbx_1__1_ cbx_7__7_ ( .chanx_left_in ( sb_1__1__61_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) , - .SC_OUT_BOT ( scff_Wires[170] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7667 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7668 ) , + .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( p1767 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5140 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) , .prog_clk_0_N_in ( prog_clk_0_wires[274] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7669 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7670 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5141 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5142 ) , .prog_clk_1_E_in ( prog_clk_1_wires[149] ) , .prog_clk_1_N_out ( prog_clk_1_wires[150] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7671 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7672 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7673 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7674 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7675 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7676 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7677 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7678 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7679 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , .prog_clk_2_E_in ( p2173 ) , + .prog_clk_2_W_in ( p882 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5143 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5144 ) , + .prog_clk_3_W_in ( p2271 ) , .prog_clk_3_E_in ( p2983 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5145 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5146 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5147 ) , .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) , - .clk_1_S_out ( clk_1_wires[151] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7680 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7681 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7682 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7683 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7684 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7685 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7686 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7687 ) ) ; + .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( p2990 ) , + .clk_2_W_in ( p2234 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5148 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5149 ) , .clk_3_W_in ( p2271 ) , + .clk_3_E_in ( p1950 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5150 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5151 ) ) ; cbx_1__1_ cbx_7__8_ ( .chanx_left_in ( sb_1__1__62_chanx_right_out ) , .chanx_right_in ( sb_1__1__73_chanx_left_out ) , .ccff_head ( sb_1__1__73_ccff_tail ) , @@ -74723,37 +76850,27 @@ cbx_1__1_ cbx_7__8_ ( .chanx_left_in ( sb_1__1__62_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) , - .SC_OUT_BOT ( scff_Wires[168] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7688 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7689 ) , + .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( p1785 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5152 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) , .prog_clk_0_N_in ( prog_clk_0_wires[277] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7690 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7691 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7692 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7693 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7694 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7695 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7696 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7697 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7698 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7699 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7700 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7701 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7702 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7703 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7704 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7705 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7706 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7707 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7708 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7709 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7710 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7711 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7712 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7713 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7714 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5153 ) , + .prog_clk_1_W_in ( p1809 ) , .prog_clk_1_E_in ( p1281 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5154 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5155 ) , + .prog_clk_2_E_in ( p1562 ) , .prog_clk_2_W_in ( p725 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5156 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5157 ) , + .prog_clk_3_W_in ( p2342 ) , .prog_clk_3_E_in ( p2823 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5158 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5159 ) , .clk_1_W_in ( p1509 ) , + .clk_1_E_in ( p209 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5160 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5161 ) , .clk_2_E_in ( p2884 ) , + .clk_2_W_in ( p2838 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5162 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5163 ) , .clk_3_W_in ( p2919 ) , + .clk_3_E_in ( p2499 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5164 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5165 ) ) ; cbx_1__1_ cbx_7__9_ ( .chanx_left_in ( sb_1__1__63_chanx_right_out ) , .chanx_right_in ( sb_1__1__74_chanx_left_out ) , .ccff_head ( sb_1__1__74_ccff_tail ) , @@ -74776,36 +76893,29 @@ cbx_1__1_ cbx_7__9_ ( .chanx_left_in ( sb_1__1__63_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) , - .SC_OUT_BOT ( scff_Wires[166] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7715 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7716 ) , + .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( p799 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5166 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) , .prog_clk_0_N_in ( prog_clk_0_wires[280] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7717 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7718 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5167 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5168 ) , .prog_clk_1_E_in ( prog_clk_1_wires[156] ) , .prog_clk_1_N_out ( prog_clk_1_wires[157] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7719 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7720 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7721 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7722 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7723 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7724 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7725 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7726 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7727 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , .prog_clk_2_E_in ( p2092 ) , + .prog_clk_2_W_in ( p640 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5169 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5170 ) , + .prog_clk_3_W_in ( p2703 ) , .prog_clk_3_E_in ( p2844 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5171 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5172 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5173 ) , .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) , - .clk_1_S_out ( clk_1_wires[158] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7728 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7729 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7730 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7731 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7732 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7733 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7734 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7735 ) ) ; + .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( p2891 ) , + .clk_2_W_in ( p2686 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5174 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5175 ) , .clk_3_W_in ( p2755 ) , + .clk_3_E_in ( p1984 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5176 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5177 ) ) ; cbx_1__1_ cbx_7__10_ ( .chanx_left_in ( sb_1__1__64_chanx_right_out ) , .chanx_right_in ( sb_1__1__75_chanx_left_out ) , .ccff_head ( sb_1__1__75_ccff_tail ) , @@ -74828,37 +76938,27 @@ cbx_1__1_ cbx_7__10_ ( .chanx_left_in ( sb_1__1__64_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) , - .SC_OUT_BOT ( scff_Wires[164] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7736 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7737 ) , + .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( p2119 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5178 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) , .prog_clk_0_N_in ( prog_clk_0_wires[283] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7738 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7739 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7740 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7741 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7742 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7743 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7744 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7745 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7746 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7747 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7748 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7749 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7750 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7751 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7752 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7753 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7754 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7755 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7756 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7757 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7758 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7759 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7760 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7761 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7762 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5179 ) , + .prog_clk_1_W_in ( p1535 ) , .prog_clk_1_E_in ( p704 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5180 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5181 ) , + .prog_clk_2_E_in ( p2070 ) , .prog_clk_2_W_in ( p701 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5182 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5183 ) , + .prog_clk_3_W_in ( p1486 ) , .prog_clk_3_E_in ( p2820 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5184 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5185 ) , .clk_1_W_in ( p1535 ) , + .clk_1_E_in ( p1934 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5186 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5187 ) , .clk_2_E_in ( p2928 ) , + .clk_2_W_in ( p1291 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5188 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5189 ) , .clk_3_W_in ( p1486 ) , + .clk_3_E_in ( p2001 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5190 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5191 ) ) ; cbx_1__1_ cbx_7__11_ ( .chanx_left_in ( sb_1__1__65_chanx_right_out ) , .chanx_right_in ( sb_1__1__76_chanx_left_out ) , .ccff_head ( sb_1__1__76_ccff_tail ) , @@ -74881,36 +76981,29 @@ cbx_1__1_ cbx_7__11_ ( .chanx_left_in ( sb_1__1__65_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) , - .SC_OUT_BOT ( scff_Wires[162] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_7763 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7764 ) , + .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( p1398 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5192 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) , .prog_clk_0_N_in ( prog_clk_0_wires[286] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7765 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7766 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5193 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5194 ) , .prog_clk_1_E_in ( prog_clk_1_wires[163] ) , .prog_clk_1_N_out ( prog_clk_1_wires[164] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7767 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7768 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7769 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7770 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7771 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7772 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7773 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7774 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7775 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , .prog_clk_2_E_in ( p2139 ) , + .prog_clk_2_W_in ( p837 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5195 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5196 ) , + .prog_clk_3_W_in ( p1989 ) , .prog_clk_3_E_in ( p2692 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5197 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5198 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5199 ) , .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) , - .clk_1_S_out ( clk_1_wires[165] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7776 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7777 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7778 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7779 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7780 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7781 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7782 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7783 ) ) ; + .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( p2757 ) , + .clk_2_W_in ( p1888 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5200 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5201 ) , .clk_3_W_in ( p2141 ) , + .clk_3_E_in ( p1964 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5202 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5203 ) ) ; cbx_1__1_ cbx_8__1_ ( .chanx_left_in ( sb_1__1__66_chanx_right_out ) , .chanx_right_in ( sb_1__1__77_chanx_left_out ) , .ccff_head ( sb_1__1__77_ccff_tail ) , @@ -74932,37 +77025,31 @@ cbx_1__1_ cbx_8__1_ ( .chanx_left_in ( sb_1__1__66_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__77_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7784 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7785 ) , + .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( p2095 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5204 ) , .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[77] ) , .prog_clk_0_N_in ( prog_clk_0_wires[294] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7786 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5205 ) , .prog_clk_1_W_in ( prog_clk_1_wires[127] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7787 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5206 ) , .prog_clk_1_N_out ( prog_clk_1_wires[131] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7788 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7789 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7790 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7791 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7792 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7793 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7794 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7795 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , .prog_clk_2_E_in ( p2532 ) , + .prog_clk_2_W_in ( p1215 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5207 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5208 ) , + .prog_clk_3_W_in ( p2117 ) , .prog_clk_3_E_in ( p2504 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5209 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5210 ) , .clk_1_W_in ( clk_1_wires[127] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7796 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5211 ) , .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7797 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7798 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7799 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7800 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7801 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7802 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7803 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7804 ) ) ; + .clk_2_E_in ( p2601 ) , .clk_2_W_in ( p1956 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5212 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5213 ) , .clk_3_W_in ( p2126 ) , + .clk_3_E_in ( p2427 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5214 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5215 ) ) ; cbx_1__1_ cbx_8__2_ ( .chanx_left_in ( sb_1__1__67_chanx_right_out ) , .chanx_right_in ( sb_1__1__78_chanx_left_out ) , .ccff_head ( sb_1__1__78_ccff_tail ) , @@ -74984,38 +77071,31 @@ cbx_1__1_ cbx_8__2_ ( .chanx_left_in ( sb_1__1__67_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__78_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7805 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7806 ) , + .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( p2063 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5216 ) , .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[78] ) , .prog_clk_0_N_in ( prog_clk_0_wires[297] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7807 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7808 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7809 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7810 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7811 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5217 ) , + .prog_clk_1_W_in ( p1725 ) , .prog_clk_1_E_in ( p953 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5218 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5219 ) , .prog_clk_2_E_in ( prog_clk_2_wires[71] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7812 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5220 ) , .prog_clk_2_W_out ( prog_clk_2_wires[72] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7813 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7814 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7815 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7816 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7817 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7818 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7819 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7820 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7821 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5221 ) , + .prog_clk_3_W_in ( p2114 ) , .prog_clk_3_E_in ( p1953 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5222 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5223 ) , .clk_1_W_in ( p1725 ) , + .clk_1_E_in ( p413 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5224 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5225 ) , .clk_2_E_in ( clk_2_wires[71] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7822 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5226 ) , .clk_2_W_out ( clk_2_wires[72] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7823 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7824 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7825 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7826 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7827 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5227 ) , .clk_3_W_in ( p2114 ) , + .clk_3_E_in ( p1350 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5228 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5229 ) ) ; cbx_1__1_ cbx_8__3_ ( .chanx_left_in ( sb_1__1__68_chanx_right_out ) , .chanx_right_in ( sb_1__1__79_chanx_left_out ) , .ccff_head ( sb_1__1__79_ccff_tail ) , @@ -75037,37 +77117,31 @@ cbx_1__1_ cbx_8__3_ ( .chanx_left_in ( sb_1__1__68_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__79_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7828 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7829 ) , + .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( p1717 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5230 ) , .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[79] ) , .prog_clk_0_N_in ( prog_clk_0_wires[300] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7830 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5231 ) , .prog_clk_1_W_in ( prog_clk_1_wires[134] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7831 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5232 ) , .prog_clk_1_N_out ( prog_clk_1_wires[138] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7832 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7833 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7834 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7835 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7836 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7837 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7838 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7839 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , .prog_clk_2_E_in ( p1777 ) , + .prog_clk_2_W_in ( p3 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5233 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5234 ) , + .prog_clk_3_W_in ( p2377 ) , .prog_clk_3_E_in ( p208 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5235 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5236 ) , .clk_1_W_in ( clk_1_wires[134] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7840 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5237 ) , .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7841 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7842 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7843 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7844 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7845 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7846 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7847 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7848 ) ) ; + .clk_2_E_in ( p1868 ) , .clk_2_W_in ( p2210 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5238 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5239 ) , .clk_3_W_in ( p2377 ) , + .clk_3_E_in ( p1168 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5240 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5241 ) ) ; cbx_1__1_ cbx_8__4_ ( .chanx_left_in ( sb_1__1__69_chanx_right_out ) , .chanx_right_in ( sb_1__1__80_chanx_left_out ) , .ccff_head ( sb_1__1__80_ccff_tail ) , @@ -75089,38 +77163,31 @@ cbx_1__1_ cbx_8__4_ ( .chanx_left_in ( sb_1__1__69_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__80_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7849 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7850 ) , + .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( p2273 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5242 ) , .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[80] ) , .prog_clk_0_N_in ( prog_clk_0_wires[303] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7851 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7852 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7853 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7854 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7855 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5243 ) , + .prog_clk_1_W_in ( p1610 ) , .prog_clk_1_E_in ( p259 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5244 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5245 ) , .prog_clk_2_E_in ( prog_clk_2_wires[80] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7856 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5246 ) , .prog_clk_2_W_out ( prog_clk_2_wires[81] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7857 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7858 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7859 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7860 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7861 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7862 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7863 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7864 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7865 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5247 ) , + .prog_clk_3_W_in ( p2118 ) , .prog_clk_3_E_in ( p2228 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5248 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5249 ) , .clk_1_W_in ( p1610 ) , + .clk_1_E_in ( p1122 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5250 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5251 ) , .clk_2_E_in ( clk_2_wires[80] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7866 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5252 ) , .clk_2_W_out ( clk_2_wires[81] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7867 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7868 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7869 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7870 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7871 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5253 ) , .clk_3_W_in ( p2041 ) , + .clk_3_E_in ( p20 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5254 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5255 ) ) ; cbx_1__1_ cbx_8__5_ ( .chanx_left_in ( sb_1__1__70_chanx_right_out ) , .chanx_right_in ( sb_1__1__81_chanx_left_out ) , .ccff_head ( sb_1__1__81_ccff_tail ) , @@ -75142,37 +77209,31 @@ cbx_1__1_ cbx_8__5_ ( .chanx_left_in ( sb_1__1__70_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__81_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7872 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7873 ) , + .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( p2556 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5256 ) , .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[81] ) , .prog_clk_0_N_in ( prog_clk_0_wires[306] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7874 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5257 ) , .prog_clk_1_W_in ( prog_clk_1_wires[141] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7875 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5258 ) , .prog_clk_1_N_out ( prog_clk_1_wires[145] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7876 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7877 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7878 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7879 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7880 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7881 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7882 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7883 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , .prog_clk_2_E_in ( p2298 ) , + .prog_clk_2_W_in ( p1381 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5259 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5260 ) , + .prog_clk_3_W_in ( p2004 ) , .prog_clk_3_E_in ( p3087 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5261 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5262 ) , .clk_1_W_in ( clk_1_wires[141] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7884 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5263 ) , .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7885 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7886 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7887 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7888 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7889 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7890 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7891 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7892 ) ) ; + .clk_2_E_in ( p3140 ) , .clk_2_W_in ( p2635 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5264 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5265 ) , .clk_3_W_in ( p2775 ) , + .clk_3_E_in ( p2264 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5266 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5267 ) ) ; cbx_1__1_ cbx_8__6_ ( .chanx_left_in ( sb_1__1__71_chanx_right_out ) , .chanx_right_in ( sb_1__1__82_chanx_left_out ) , .ccff_head ( sb_1__1__82_ccff_tail ) , @@ -75194,38 +77255,31 @@ cbx_1__1_ cbx_8__6_ ( .chanx_left_in ( sb_1__1__71_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__82_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7893 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7894 ) , + .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( p1524 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5268 ) , .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[82] ) , .prog_clk_0_N_in ( prog_clk_0_wires[309] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7895 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7896 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7897 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7898 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7899 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7900 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7901 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7902 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7903 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5269 ) , + .prog_clk_1_W_in ( p1541 ) , .prog_clk_1_E_in ( p415 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5270 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5271 ) , + .prog_clk_2_E_in ( p2167 ) , .prog_clk_2_W_in ( p623 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5272 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5273 ) , .prog_clk_3_W_in ( prog_clk_3_wires[4] ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7904 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5274 ) , .prog_clk_3_E_out ( prog_clk_3_wires[5] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7905 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7906 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7907 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7908 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7909 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7910 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7911 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7912 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7913 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5275 ) , .clk_1_W_in ( p1541 ) , + .clk_1_E_in ( p1347 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5276 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5277 ) , .clk_2_E_in ( p1524 ) , + .clk_2_W_in ( p795 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5278 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5279 ) , .clk_3_W_in ( clk_3_wires[4] ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7914 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5280 ) , .clk_3_E_out ( clk_3_wires[5] ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7915 ) ) ; + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5281 ) ) ; cbx_1__1_ cbx_8__7_ ( .chanx_left_in ( sb_1__1__72_chanx_right_out ) , .chanx_right_in ( sb_1__1__83_chanx_left_out ) , .ccff_head ( sb_1__1__83_ccff_tail ) , @@ -75247,37 +77301,31 @@ cbx_1__1_ cbx_8__7_ ( .chanx_left_in ( sb_1__1__72_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__83_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7916 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7917 ) , + .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( p2606 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5282 ) , .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[83] ) , .prog_clk_0_N_in ( prog_clk_0_wires[312] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7918 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5283 ) , .prog_clk_1_W_in ( prog_clk_1_wires[148] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7919 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5284 ) , .prog_clk_1_N_out ( prog_clk_1_wires[152] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7920 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7921 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7922 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7923 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7924 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7925 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7926 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7927 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , .prog_clk_2_E_in ( p2356 ) , + .prog_clk_2_W_in ( p1166 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5285 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5286 ) , + .prog_clk_3_W_in ( p3010 ) , .prog_clk_3_E_in ( p2488 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5287 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5288 ) , .clk_1_W_in ( clk_1_wires[148] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7928 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5289 ) , .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7929 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7930 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7931 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7932 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7933 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7934 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7935 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7936 ) ) ; + .clk_2_E_in ( p2606 ) , .clk_2_W_in ( p2941 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5290 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5291 ) , .clk_3_W_in ( p3010 ) , + .clk_3_E_in ( p2195 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5292 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5293 ) ) ; cbx_1__1_ cbx_8__8_ ( .chanx_left_in ( sb_1__1__73_chanx_right_out ) , .chanx_right_in ( sb_1__1__84_chanx_left_out ) , .ccff_head ( sb_1__1__84_ccff_tail ) , @@ -75299,38 +77347,31 @@ cbx_1__1_ cbx_8__8_ ( .chanx_left_in ( sb_1__1__73_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__84_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7937 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7938 ) , + .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( p2574 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5294 ) , .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[84] ) , .prog_clk_0_N_in ( prog_clk_0_wires[315] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7939 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7940 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7941 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7942 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7943 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5295 ) , + .prog_clk_1_W_in ( p1567 ) , .prog_clk_1_E_in ( p582 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5296 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5297 ) , .prog_clk_2_E_in ( prog_clk_2_wires[93] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7944 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5298 ) , .prog_clk_2_W_out ( prog_clk_2_wires[94] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7945 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7946 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7947 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7948 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7949 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7950 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7951 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7952 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7953 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5299 ) , + .prog_clk_3_W_in ( p1723 ) , .prog_clk_3_E_in ( p2481 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5300 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5301 ) , .clk_1_W_in ( p1567 ) , + .clk_1_E_in ( p436 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5302 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5303 ) , .clk_2_E_in ( clk_2_wires[93] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7954 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5304 ) , .clk_2_W_out ( clk_2_wires[94] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7955 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7956 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7957 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7958 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7959 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5305 ) , .clk_3_W_in ( p1723 ) , + .clk_3_E_in ( p213 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5306 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5307 ) ) ; cbx_1__1_ cbx_8__9_ ( .chanx_left_in ( sb_1__1__74_chanx_right_out ) , .chanx_right_in ( sb_1__1__85_chanx_left_out ) , .ccff_head ( sb_1__1__85_ccff_tail ) , @@ -75352,37 +77393,31 @@ cbx_1__1_ cbx_8__9_ ( .chanx_left_in ( sb_1__1__74_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__85_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7960 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7961 ) , + .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( p2035 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5308 ) , .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[85] ) , .prog_clk_0_N_in ( prog_clk_0_wires[318] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7962 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5309 ) , .prog_clk_1_W_in ( prog_clk_1_wires[155] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7963 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5310 ) , .prog_clk_1_N_out ( prog_clk_1_wires[159] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7964 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7965 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7966 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7967 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7968 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7969 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7970 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7971 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , .prog_clk_2_E_in ( p2353 ) , + .prog_clk_2_W_in ( p1103 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5311 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5312 ) , + .prog_clk_3_W_in ( p1639 ) , .prog_clk_3_E_in ( p2837 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5313 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5314 ) , .clk_1_W_in ( clk_1_wires[155] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7972 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5315 ) , .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7973 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7974 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7975 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7976 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_7977 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7978 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7979 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7980 ) ) ; + .clk_2_E_in ( p2898 ) , .clk_2_W_in ( p2432 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5316 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5317 ) , .clk_3_W_in ( p2618 ) , + .clk_3_E_in ( p2214 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5318 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5319 ) ) ; cbx_1__1_ cbx_8__10_ ( .chanx_left_in ( sb_1__1__75_chanx_right_out ) , .chanx_right_in ( sb_1__1__86_chanx_left_out ) , .ccff_head ( sb_1__1__86_ccff_tail ) , @@ -75404,38 +77439,31 @@ cbx_1__1_ cbx_8__10_ ( .chanx_left_in ( sb_1__1__75_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__86_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7981 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7982 ) , + .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( p1565 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5320 ) , .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[86] ) , .prog_clk_0_N_in ( prog_clk_0_wires[321] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7983 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7984 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7985 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7986 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7987 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5321 ) , + .prog_clk_1_W_in ( p1660 ) , .prog_clk_1_E_in ( p359 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5322 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5323 ) , .prog_clk_2_E_in ( prog_clk_2_wires[106] ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_7988 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5324 ) , .prog_clk_2_W_out ( prog_clk_2_wires[107] ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7989 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_7990 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7991 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7992 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7993 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7994 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7995 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7996 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7997 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5325 ) , + .prog_clk_3_W_in ( p1676 ) , .prog_clk_3_E_in ( p740 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5326 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5327 ) , .clk_1_W_in ( p1660 ) , + .clk_1_E_in ( p1224 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5328 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5329 ) , .clk_2_E_in ( clk_2_wires[106] ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_7998 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5330 ) , .clk_2_W_out ( clk_2_wires[107] ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7999 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8000 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8001 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8002 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8003 ) ) ; + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5331 ) , .clk_3_W_in ( p1676 ) , + .clk_3_E_in ( p2240 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5332 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5333 ) ) ; cbx_1__1_ cbx_8__11_ ( .chanx_left_in ( sb_1__1__76_chanx_right_out ) , .chanx_right_in ( sb_1__1__87_chanx_left_out ) , .ccff_head ( sb_1__1__87_ccff_tail ) , @@ -75457,37 +77485,31 @@ cbx_1__1_ cbx_8__11_ ( .chanx_left_in ( sb_1__1__76_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__87_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8004 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8005 ) , + .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( p1678 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5334 ) , .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[87] ) , .prog_clk_0_N_in ( prog_clk_0_wires[324] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8006 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5335 ) , .prog_clk_1_W_in ( prog_clk_1_wires[162] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8007 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5336 ) , .prog_clk_1_N_out ( prog_clk_1_wires[166] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8008 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8009 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8010 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8011 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8012 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8013 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8014 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8015 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , .prog_clk_2_E_in ( p2603 ) , + .prog_clk_2_W_in ( p768 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5337 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5338 ) , + .prog_clk_3_W_in ( p1478 ) , .prog_clk_3_E_in ( p3158 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5339 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5340 ) , .clk_1_W_in ( clk_1_wires[162] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8016 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5341 ) , .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8017 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8018 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8019 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8020 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8021 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8022 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8023 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8024 ) ) ; + .clk_2_E_in ( p3202 ) , .clk_2_W_in ( p1135 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5342 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5343 ) , .clk_3_W_in ( p1478 ) , + .clk_3_E_in ( p2465 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5344 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5345 ) ) ; cbx_1__1_ cbx_9__1_ ( .chanx_left_in ( sb_1__1__77_chanx_right_out ) , .chanx_right_in ( sb_1__1__88_chanx_left_out ) , .ccff_head ( sb_1__1__88_ccff_tail ) , @@ -75510,36 +77532,29 @@ cbx_1__1_ cbx_9__1_ ( .chanx_left_in ( sb_1__1__77_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) , - .SC_OUT_BOT ( scff_Wires[235] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8025 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8026 ) , + .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( p1871 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5346 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) , .prog_clk_0_N_in ( prog_clk_0_wires[332] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8027 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8028 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5347 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5348 ) , .prog_clk_1_E_in ( prog_clk_1_wires[170] ) , .prog_clk_1_N_out ( prog_clk_1_wires[171] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8029 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8030 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8031 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8032 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8033 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8034 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8035 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8036 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8037 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , .prog_clk_2_E_in ( p2304 ) , + .prog_clk_2_W_in ( p1358 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5349 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5350 ) , + .prog_clk_3_W_in ( p1609 ) , .prog_clk_3_E_in ( p2265 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5351 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5352 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5353 ) , .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) , - .clk_1_S_out ( clk_1_wires[172] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8038 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8039 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8040 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8041 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8042 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8043 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8044 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8045 ) ) ; + .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( p2391 ) , + .clk_2_W_in ( p698 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5354 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5355 ) , .clk_3_W_in ( p1609 ) , + .clk_3_E_in ( p2199 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5356 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5357 ) ) ; cbx_1__1_ cbx_9__2_ ( .chanx_left_in ( sb_1__1__78_chanx_right_out ) , .chanx_right_in ( sb_1__1__89_chanx_left_out ) , .ccff_head ( sb_1__1__89_ccff_tail ) , @@ -75562,37 +77577,30 @@ cbx_1__1_ cbx_9__2_ ( .chanx_left_in ( sb_1__1__78_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) , - .SC_OUT_BOT ( scff_Wires[233] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8046 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8047 ) , + .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( p1714 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5358 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) , .prog_clk_0_N_in ( prog_clk_0_wires[335] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8048 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8049 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8050 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8051 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8052 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8053 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5359 ) , + .prog_clk_1_W_in ( p1672 ) , .prog_clk_1_E_in ( p1382 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5360 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5361 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5362 ) , .prog_clk_2_W_in ( prog_clk_2_wires[69] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8054 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8055 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8056 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8057 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8058 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8059 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8060 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8061 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8062 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8063 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5363 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , .prog_clk_3_W_in ( p1766 ) , + .prog_clk_3_E_in ( p1174 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5364 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5365 ) , .clk_1_W_in ( p1672 ) , + .clk_1_E_in ( p181 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5366 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5367 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5368 ) , .clk_2_W_in ( clk_2_wires[69] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8064 ) , - .clk_2_E_out ( clk_2_wires[70] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8065 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8066 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8067 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8068 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5369 ) , + .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1766 ) , + .clk_3_E_in ( p310 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5370 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5371 ) ) ; cbx_1__1_ cbx_9__3_ ( .chanx_left_in ( sb_1__1__79_chanx_right_out ) , .chanx_right_in ( sb_1__1__90_chanx_left_out ) , .ccff_head ( sb_1__1__90_ccff_tail ) , @@ -75615,36 +77623,29 @@ cbx_1__1_ cbx_9__3_ ( .chanx_left_in ( sb_1__1__79_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) , - .SC_OUT_BOT ( scff_Wires[231] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8069 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8070 ) , + .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( p1576 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5372 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) , .prog_clk_0_N_in ( prog_clk_0_wires[338] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8071 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8072 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5373 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5374 ) , .prog_clk_1_E_in ( prog_clk_1_wires[177] ) , .prog_clk_1_N_out ( prog_clk_1_wires[178] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8073 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8074 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8075 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8076 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8077 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8078 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8079 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8080 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8081 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , .prog_clk_2_E_in ( p2747 ) , + .prog_clk_2_W_in ( p806 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5375 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5376 ) , + .prog_clk_3_W_in ( p2558 ) , .prog_clk_3_E_in ( p3062 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5377 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5378 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5379 ) , .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) , - .clk_1_S_out ( clk_1_wires[179] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8082 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8083 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8084 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8085 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8086 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8087 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8088 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8089 ) ) ; + .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( p3115 ) , + .clk_2_W_in ( p2483 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5380 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5381 ) , .clk_3_W_in ( p2558 ) , + .clk_3_E_in ( p2701 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5382 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5383 ) ) ; cbx_1__1_ cbx_9__4_ ( .chanx_left_in ( sb_1__1__80_chanx_right_out ) , .chanx_right_in ( sb_1__1__91_chanx_left_out ) , .ccff_head ( sb_1__1__91_ccff_tail ) , @@ -75667,37 +77668,30 @@ cbx_1__1_ cbx_9__4_ ( .chanx_left_in ( sb_1__1__80_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) , - .SC_OUT_BOT ( scff_Wires[229] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8090 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8091 ) , + .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( p1872 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5384 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) , .prog_clk_0_N_in ( prog_clk_0_wires[341] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8092 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8093 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8094 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8095 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8096 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8097 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5385 ) , + .prog_clk_1_W_in ( p1312 ) , .prog_clk_1_E_in ( p1102 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5386 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5387 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5388 ) , .prog_clk_2_W_in ( prog_clk_2_wires[78] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8098 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8099 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8100 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8101 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8102 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8103 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8104 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8105 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8106 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8107 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5389 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , .prog_clk_3_W_in ( p1107 ) , + .prog_clk_3_E_in ( p1058 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5390 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5391 ) , .clk_1_W_in ( p1312 ) , + .clk_1_E_in ( p667 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5392 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5393 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5394 ) , .clk_2_W_in ( clk_2_wires[78] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8108 ) , - .clk_2_E_out ( clk_2_wires[79] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8109 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8110 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8111 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8112 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5395 ) , + .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p1510 ) , + .clk_3_E_in ( p2239 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5396 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5397 ) ) ; cbx_1__1_ cbx_9__5_ ( .chanx_left_in ( sb_1__1__81_chanx_right_out ) , .chanx_right_in ( sb_1__1__92_chanx_left_out ) , .ccff_head ( sb_1__1__92_ccff_tail ) , @@ -75720,36 +77714,29 @@ cbx_1__1_ cbx_9__5_ ( .chanx_left_in ( sb_1__1__81_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) , - .SC_OUT_BOT ( scff_Wires[227] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8113 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8114 ) , + .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( p1739 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5398 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) , .prog_clk_0_N_in ( prog_clk_0_wires[344] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8115 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8116 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5399 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5400 ) , .prog_clk_1_E_in ( prog_clk_1_wires[184] ) , .prog_clk_1_N_out ( prog_clk_1_wires[185] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8117 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8118 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8119 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8120 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8121 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8122 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8123 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8124 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8125 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , .prog_clk_2_E_in ( p2609 ) , + .prog_clk_2_W_in ( p681 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5401 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5402 ) , + .prog_clk_3_W_in ( p1832 ) , .prog_clk_3_E_in ( p2979 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5403 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5404 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5405 ) , .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) , - .clk_1_S_out ( clk_1_wires[186] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8126 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8127 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8128 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8129 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8130 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8131 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8132 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8133 ) ) ; + .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( p3039 ) , + .clk_2_W_in ( p1266 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5406 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5407 ) , .clk_3_W_in ( p1832 ) , + .clk_3_E_in ( p2493 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5408 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5409 ) ) ; cbx_1__1_ cbx_9__6_ ( .chanx_left_in ( sb_1__1__82_chanx_right_out ) , .chanx_right_in ( sb_1__1__93_chanx_left_out ) , .ccff_head ( sb_1__1__93_ccff_tail ) , @@ -75772,37 +77759,30 @@ cbx_1__1_ cbx_9__6_ ( .chanx_left_in ( sb_1__1__82_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) , - .SC_OUT_BOT ( scff_Wires[225] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8134 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8135 ) , + .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( p1734 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5410 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) , .prog_clk_0_N_in ( prog_clk_0_wires[347] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8136 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8137 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8138 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8139 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8140 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8141 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8142 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8143 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8144 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5411 ) , + .prog_clk_1_W_in ( p1411 ) , .prog_clk_1_E_in ( p563 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5412 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5413 ) , + .prog_clk_2_E_in ( p1623 ) , .prog_clk_2_W_in ( p690 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5414 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5415 ) , .prog_clk_3_W_in ( prog_clk_3_wires[44] ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8145 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5416 ) , .prog_clk_3_E_out ( prog_clk_3_wires[45] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8146 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8147 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8148 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8149 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8150 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8151 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8152 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8153 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8154 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5417 ) , .clk_1_W_in ( p1411 ) , + .clk_1_E_in ( p1360 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5418 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5419 ) , .clk_2_E_in ( p1472 ) , + .clk_2_W_in ( p514 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5421 ) , .clk_3_W_in ( clk_3_wires[44] ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8155 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5422 ) , .clk_3_E_out ( clk_3_wires[45] ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8156 ) ) ; + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5423 ) ) ; cbx_1__1_ cbx_9__7_ ( .chanx_left_in ( sb_1__1__83_chanx_right_out ) , .chanx_right_in ( sb_1__1__94_chanx_left_out ) , .ccff_head ( sb_1__1__94_ccff_tail ) , @@ -75825,36 +77805,29 @@ cbx_1__1_ cbx_9__7_ ( .chanx_left_in ( sb_1__1__83_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) , - .SC_OUT_BOT ( scff_Wires[223] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8157 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8158 ) , + .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( p1843 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5424 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) , .prog_clk_0_N_in ( prog_clk_0_wires[350] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8159 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8160 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5425 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5426 ) , .prog_clk_1_E_in ( prog_clk_1_wires[191] ) , .prog_clk_1_N_out ( prog_clk_1_wires[192] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8161 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8162 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8163 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8164 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8165 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8166 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8167 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8168 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8169 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , .prog_clk_2_E_in ( p2109 ) , + .prog_clk_2_W_in ( p546 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5427 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5428 ) , + .prog_clk_3_W_in ( p2082 ) , .prog_clk_3_E_in ( p3157 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5429 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5430 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5431 ) , .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) , - .clk_1_S_out ( clk_1_wires[193] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8170 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8171 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8172 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8173 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8174 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8175 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8176 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8177 ) ) ; + .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( p3215 ) , + .clk_2_W_in ( p1912 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5432 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5433 ) , .clk_3_W_in ( p2082 ) , + .clk_3_E_in ( p1960 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5434 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5435 ) ) ; cbx_1__1_ cbx_9__8_ ( .chanx_left_in ( sb_1__1__84_chanx_right_out ) , .chanx_right_in ( sb_1__1__95_chanx_left_out ) , .ccff_head ( sb_1__1__95_ccff_tail ) , @@ -75877,37 +77850,30 @@ cbx_1__1_ cbx_9__8_ ( .chanx_left_in ( sb_1__1__84_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) , - .SC_OUT_BOT ( scff_Wires[221] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8178 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8179 ) , + .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( p2425 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5436 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) , .prog_clk_0_N_in ( prog_clk_0_wires[353] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8180 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8181 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8182 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8183 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8184 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8185 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5437 ) , + .prog_clk_1_W_in ( p674 ) , .prog_clk_1_E_in ( p1260 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5438 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5439 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5440 ) , .prog_clk_2_W_in ( prog_clk_2_wires[91] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8186 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8187 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8188 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8189 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8190 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8191 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8192 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8193 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8194 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8195 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5441 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , .prog_clk_3_W_in ( p1600 ) , + .prog_clk_3_E_in ( p350 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5442 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5443 ) , .clk_1_W_in ( p674 ) , + .clk_1_E_in ( p2192 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5444 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5445 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5446 ) , .clk_2_W_in ( clk_2_wires[91] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8196 ) , - .clk_2_E_out ( clk_2_wires[92] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8197 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8198 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8199 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8200 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5447 ) , + .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1600 ) , + .clk_3_E_in ( p1905 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5448 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5449 ) ) ; cbx_1__1_ cbx_9__9_ ( .chanx_left_in ( sb_1__1__85_chanx_right_out ) , .chanx_right_in ( sb_1__1__96_chanx_left_out ) , .ccff_head ( sb_1__1__96_ccff_tail ) , @@ -75930,36 +77896,29 @@ cbx_1__1_ cbx_9__9_ ( .chanx_left_in ( sb_1__1__85_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) , - .SC_OUT_BOT ( scff_Wires[219] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8201 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8202 ) , + .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( p1884 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5450 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) , .prog_clk_0_N_in ( prog_clk_0_wires[356] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8203 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8204 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5451 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5452 ) , .prog_clk_1_E_in ( prog_clk_1_wires[198] ) , .prog_clk_1_N_out ( prog_clk_1_wires[199] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8205 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8206 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8207 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8208 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8209 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8210 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8211 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8212 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8213 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , .prog_clk_2_E_in ( p1839 ) , + .prog_clk_2_W_in ( p815 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5453 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5454 ) , + .prog_clk_3_W_in ( p2698 ) , .prog_clk_3_E_in ( p2266 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5455 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5456 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5457 ) , .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) , - .clk_1_S_out ( clk_1_wires[200] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8214 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8215 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8216 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8217 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8218 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8219 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8220 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8221 ) ) ; + .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( p2300 ) , + .clk_2_W_in ( p2671 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5458 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5459 ) , .clk_3_W_in ( p2698 ) , + .clk_3_E_in ( p1040 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5460 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5461 ) ) ; cbx_1__1_ cbx_9__10_ ( .chanx_left_in ( sb_1__1__86_chanx_right_out ) , .chanx_right_in ( sb_1__1__97_chanx_left_out ) , .ccff_head ( sb_1__1__97_ccff_tail ) , @@ -75982,37 +77941,30 @@ cbx_1__1_ cbx_9__10_ ( .chanx_left_in ( sb_1__1__86_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) , - .SC_OUT_BOT ( scff_Wires[217] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8222 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8223 ) , + .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( p2362 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5462 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) , .prog_clk_0_N_in ( prog_clk_0_wires[359] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8224 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8225 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8226 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8227 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8228 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8229 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5463 ) , + .prog_clk_1_W_in ( p1511 ) , .prog_clk_1_E_in ( p1476 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5464 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5465 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5466 ) , .prog_clk_2_W_in ( prog_clk_2_wires[104] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8230 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8231 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8232 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8233 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8234 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8235 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8236 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8237 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8238 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8239 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5467 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , .prog_clk_3_W_in ( p1726 ) , + .prog_clk_3_E_in ( p1322 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5468 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5469 ) , .clk_1_W_in ( p1511 ) , + .clk_1_E_in ( p2242 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5470 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5471 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5472 ) , .clk_2_W_in ( clk_2_wires[104] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8240 ) , - .clk_2_E_out ( clk_2_wires[105] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8241 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8242 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8243 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8244 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5473 ) , + .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p1726 ) , + .clk_3_E_in ( p525 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5474 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5475 ) ) ; cbx_1__1_ cbx_9__11_ ( .chanx_left_in ( sb_1__1__87_chanx_right_out ) , .chanx_right_in ( sb_1__1__98_chanx_left_out ) , .ccff_head ( sb_1__1__98_ccff_tail ) , @@ -76035,36 +77987,29 @@ cbx_1__1_ cbx_9__11_ ( .chanx_left_in ( sb_1__1__87_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) , - .SC_OUT_BOT ( scff_Wires[215] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8245 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8246 ) , + .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( p1450 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5476 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) , .prog_clk_0_N_in ( prog_clk_0_wires[362] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8247 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8248 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5477 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5478 ) , .prog_clk_1_E_in ( prog_clk_1_wires[205] ) , .prog_clk_1_N_out ( prog_clk_1_wires[206] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8249 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8250 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8251 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8252 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8253 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8254 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8255 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8256 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8257 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , .prog_clk_2_E_in ( p1727 ) , + .prog_clk_2_W_in ( p1188 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5479 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5480 ) , + .prog_clk_3_W_in ( p2526 ) , .prog_clk_3_E_in ( p3241 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5481 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5482 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5483 ) , .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) , - .clk_1_S_out ( clk_1_wires[207] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8258 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8259 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8260 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8261 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8262 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8263 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8264 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8265 ) ) ; + .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( p3285 ) , + .clk_2_W_in ( p2670 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5484 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5485 ) , .clk_3_W_in ( p2745 ) , + .clk_3_E_in ( p620 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5486 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5487 ) ) ; cbx_1__1_ cbx_10__1_ ( .chanx_left_in ( sb_1__1__88_chanx_right_out ) , .chanx_right_in ( sb_1__1__99_chanx_left_out ) , .ccff_head ( sb_1__1__99_ccff_tail ) , @@ -76086,37 +78031,31 @@ cbx_1__1_ cbx_10__1_ ( .chanx_left_in ( sb_1__1__88_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__99_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8266 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8267 ) , + .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( p1731 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5488 ) , .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[99] ) , .prog_clk_0_N_in ( prog_clk_0_wires[370] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8268 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5489 ) , .prog_clk_1_W_in ( prog_clk_1_wires[169] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8269 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5490 ) , .prog_clk_1_N_out ( prog_clk_1_wires[173] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8270 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8271 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8272 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8273 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8274 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8275 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8276 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8277 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , .prog_clk_2_E_in ( p2364 ) , + .prog_clk_2_W_in ( p2396 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5491 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5492 ) , + .prog_clk_3_W_in ( p1807 ) , .prog_clk_3_E_in ( p2076 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5493 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5494 ) , .clk_1_W_in ( clk_1_wires[169] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8278 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5495 ) , .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8279 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8280 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8281 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8282 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8283 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8284 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8285 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8286 ) ) ; + .clk_2_E_in ( p2042 ) , .clk_2_W_in ( p2259 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5496 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5497 ) , .clk_3_W_in ( p1807 ) , + .clk_3_E_in ( p2295 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5498 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5499 ) ) ; cbx_1__1_ cbx_10__2_ ( .chanx_left_in ( sb_1__1__89_chanx_right_out ) , .chanx_right_in ( sb_1__1__100_chanx_left_out ) , .ccff_head ( sb_1__1__100_ccff_tail ) , @@ -76138,38 +78077,28 @@ cbx_1__1_ cbx_10__2_ ( .chanx_left_in ( sb_1__1__89_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__100_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8287 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8288 ) , + .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( p2551 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5500 ) , .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[100] ) , .prog_clk_0_N_in ( prog_clk_0_wires[373] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8289 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8290 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8291 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8292 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8293 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8294 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8295 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8296 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8297 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8298 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8299 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8300 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8301 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8302 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8303 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8304 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8305 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8306 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8307 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8308 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8309 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8310 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8311 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8312 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8313 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5501 ) , + .prog_clk_1_W_in ( p1454 ) , .prog_clk_1_E_in ( p1689 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5502 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5503 ) , + .prog_clk_2_E_in ( p2783 ) , .prog_clk_2_W_in ( p1851 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5504 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5505 ) , + .prog_clk_3_W_in ( p1474 ) , .prog_clk_3_E_in ( p3096 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5506 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5507 ) , .clk_1_W_in ( p1454 ) , + .clk_1_E_in ( p959 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5508 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5509 ) , .clk_2_E_in ( p3097 ) , + .clk_2_W_in ( p1395 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5510 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5511 ) , .clk_3_W_in ( p1474 ) , + .clk_3_E_in ( p2693 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5512 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5513 ) ) ; cbx_1__1_ cbx_10__3_ ( .chanx_left_in ( sb_1__1__90_chanx_right_out ) , .chanx_right_in ( sb_1__1__101_chanx_left_out ) , .ccff_head ( sb_1__1__101_ccff_tail ) , @@ -76191,37 +78120,31 @@ cbx_1__1_ cbx_10__3_ ( .chanx_left_in ( sb_1__1__90_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__101_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8314 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8315 ) , + .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( p2310 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5514 ) , .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[101] ) , .prog_clk_0_N_in ( prog_clk_0_wires[376] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8316 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5515 ) , .prog_clk_1_W_in ( prog_clk_1_wires[176] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8317 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5516 ) , .prog_clk_1_N_out ( prog_clk_1_wires[180] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8318 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8319 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8320 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8321 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8322 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8323 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8324 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8325 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , .prog_clk_2_E_in ( p2387 ) , + .prog_clk_2_W_in ( p1471 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5517 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5518 ) , + .prog_clk_3_W_in ( p2110 ) , .prog_clk_3_E_in ( p2984 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5519 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5520 ) , .clk_1_W_in ( clk_1_wires[176] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8326 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5521 ) , .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8327 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8328 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8329 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8330 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8331 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8332 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8333 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8334 ) ) ; + .clk_2_E_in ( p3020 ) , .clk_2_W_in ( p1972 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5522 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5523 ) , .clk_3_W_in ( p2110 ) , + .clk_3_E_in ( p2249 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5524 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5525 ) ) ; cbx_1__1_ cbx_10__4_ ( .chanx_left_in ( sb_1__1__91_chanx_right_out ) , .chanx_right_in ( sb_1__1__102_chanx_left_out ) , .ccff_head ( sb_1__1__102_ccff_tail ) , @@ -76243,38 +78166,28 @@ cbx_1__1_ cbx_10__4_ ( .chanx_left_in ( sb_1__1__91_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__102_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8335 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8336 ) , + .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( p1738 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5526 ) , .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[102] ) , .prog_clk_0_N_in ( prog_clk_0_wires[379] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8337 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8338 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8339 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8340 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8341 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8342 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8343 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8344 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8345 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8346 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8347 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8348 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8349 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8350 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8351 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8352 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8353 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8354 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8355 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8356 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8357 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8358 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8359 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8360 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8361 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5527 ) , + .prog_clk_1_W_in ( p1651 ) , .prog_clk_1_E_in ( p1719 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5528 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5529 ) , + .prog_clk_2_E_in ( p2623 ) , .prog_clk_2_W_in ( p1278 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5530 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5531 ) , + .prog_clk_3_W_in ( p1794 ) , .prog_clk_3_E_in ( p1715 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5532 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5533 ) , .clk_1_W_in ( p1651 ) , + .clk_1_E_in ( p764 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5534 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5535 ) , .clk_2_E_in ( p1738 ) , + .clk_2_W_in ( p1232 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5536 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5537 ) , .clk_3_W_in ( p1794 ) , + .clk_3_E_in ( p2498 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5538 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5539 ) ) ; cbx_1__1_ cbx_10__5_ ( .chanx_left_in ( sb_1__1__92_chanx_right_out ) , .chanx_right_in ( sb_1__1__103_chanx_left_out ) , .ccff_head ( sb_1__1__103_ccff_tail ) , @@ -76296,37 +78209,31 @@ cbx_1__1_ cbx_10__5_ ( .chanx_left_in ( sb_1__1__92_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__103_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8362 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8363 ) , + .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( p1716 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5540 ) , .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[103] ) , .prog_clk_0_N_in ( prog_clk_0_wires[382] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8364 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5541 ) , .prog_clk_1_W_in ( prog_clk_1_wires[183] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8365 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5542 ) , .prog_clk_1_N_out ( prog_clk_1_wires[187] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8366 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8367 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8368 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8369 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8370 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8371 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8372 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8373 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , .prog_clk_2_E_in ( p2165 ) , + .prog_clk_2_W_in ( p1002 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5543 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5544 ) , + .prog_clk_3_W_in ( p2710 ) , .prog_clk_3_E_in ( p2169 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5545 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5546 ) , .clk_1_W_in ( clk_1_wires[183] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8374 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5547 ) , .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8375 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8376 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8377 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8378 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8379 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8380 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8381 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8382 ) ) ; + .clk_2_E_in ( p1716 ) , .clk_2_W_in ( p2694 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5548 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5549 ) , .clk_3_W_in ( p2752 ) , + .clk_3_E_in ( p1947 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5550 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5551 ) ) ; cbx_1__1_ cbx_10__6_ ( .chanx_left_in ( sb_1__1__93_chanx_right_out ) , .chanx_right_in ( sb_1__1__104_chanx_left_out ) , .ccff_head ( sb_1__1__104_ccff_tail ) , @@ -76348,38 +78255,31 @@ cbx_1__1_ cbx_10__6_ ( .chanx_left_in ( sb_1__1__93_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__104_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8383 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8384 ) , + .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( p1505 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5552 ) , .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[104] ) , .prog_clk_0_N_in ( prog_clk_0_wires[385] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8385 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8386 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8387 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8388 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8389 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8390 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8391 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8392 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8393 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5553 ) , + .prog_clk_1_W_in ( p1578 ) , .prog_clk_1_E_in ( p1165 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5554 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5555 ) , + .prog_clk_2_E_in ( p2531 ) , .prog_clk_2_W_in ( p1659 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5556 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5557 ) , .prog_clk_3_W_in ( prog_clk_3_wires[48] ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8394 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5558 ) , .prog_clk_3_E_out ( prog_clk_3_wires[49] ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8395 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8396 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8397 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8398 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8399 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8400 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8401 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8402 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8403 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5559 ) , .clk_1_W_in ( p1578 ) , + .clk_1_E_in ( p1822 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5560 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5561 ) , .clk_2_E_in ( p1505 ) , + .clk_2_W_in ( p1243 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5562 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5563 ) , .clk_3_W_in ( clk_3_wires[48] ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8404 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5564 ) , .clk_3_E_out ( clk_3_wires[49] ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8405 ) ) ; + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5565 ) ) ; cbx_1__1_ cbx_10__7_ ( .chanx_left_in ( sb_1__1__94_chanx_right_out ) , .chanx_right_in ( sb_1__1__105_chanx_left_out ) , .ccff_head ( sb_1__1__105_ccff_tail ) , @@ -76401,37 +78301,31 @@ cbx_1__1_ cbx_10__7_ ( .chanx_left_in ( sb_1__1__94_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__105_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8406 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8407 ) , + .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( p1729 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5566 ) , .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[105] ) , .prog_clk_0_N_in ( prog_clk_0_wires[388] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8408 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5567 ) , .prog_clk_1_W_in ( prog_clk_1_wires[190] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8409 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5568 ) , .prog_clk_1_N_out ( prog_clk_1_wires[194] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8410 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8411 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8412 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8413 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8414 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8415 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8416 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8417 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , .prog_clk_2_E_in ( p1223 ) , + .prog_clk_2_W_in ( p1975 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5569 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5570 ) , + .prog_clk_3_W_in ( p2378 ) , .prog_clk_3_E_in ( p3094 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5571 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5572 ) , .clk_1_W_in ( clk_1_wires[190] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8418 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8419 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8420 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8421 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8422 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8423 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8424 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8425 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8426 ) ) ; + .clk_2_E_in ( p3112 ) , .clk_2_W_in ( p2262 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5574 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5575 ) , .clk_3_W_in ( p2378 ) , + .clk_3_E_in ( p1614 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5576 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5577 ) ) ; cbx_1__1_ cbx_10__8_ ( .chanx_left_in ( sb_1__1__95_chanx_right_out ) , .chanx_right_in ( sb_1__1__106_chanx_left_out ) , .ccff_head ( sb_1__1__106_ccff_tail ) , @@ -76453,38 +78347,28 @@ cbx_1__1_ cbx_10__8_ ( .chanx_left_in ( sb_1__1__95_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__106_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8427 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8428 ) , + .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( p2383 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5578 ) , .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[106] ) , .prog_clk_0_N_in ( prog_clk_0_wires[391] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8429 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8430 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8431 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8432 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8433 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8434 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8435 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8436 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8437 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8438 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8439 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8440 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8441 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8442 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8443 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8444 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8445 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8446 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8447 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8448 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8449 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8450 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8451 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8452 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8453 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5579 ) , + .prog_clk_1_W_in ( p1370 ) , .prog_clk_1_E_in ( p520 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5580 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5581 ) , + .prog_clk_2_E_in ( p2622 ) , .prog_clk_2_W_in ( p1849 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5582 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5583 ) , + .prog_clk_3_W_in ( p940 ) , .prog_clk_3_E_in ( p2303 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5584 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_1_W_in ( p1370 ) , + .clk_1_E_in ( p1519 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5586 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_2_E_in ( p2383 ) , + .clk_2_W_in ( p1467 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p940 ) , + .clk_3_E_in ( p2461 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5591 ) ) ; cbx_1__1_ cbx_10__9_ ( .chanx_left_in ( sb_1__1__96_chanx_right_out ) , .chanx_right_in ( sb_1__1__107_chanx_left_out ) , .ccff_head ( sb_1__1__107_ccff_tail ) , @@ -76506,37 +78390,31 @@ cbx_1__1_ cbx_10__9_ ( .chanx_left_in ( sb_1__1__96_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__107_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8454 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8455 ) , + .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( p1573 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5592 ) , .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[107] ) , .prog_clk_0_N_in ( prog_clk_0_wires[394] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8456 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5593 ) , .prog_clk_1_W_in ( prog_clk_1_wires[197] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8457 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5594 ) , .prog_clk_1_N_out ( prog_clk_1_wires[201] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8458 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8459 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8460 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8461 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8462 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8463 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8464 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8465 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , .prog_clk_2_E_in ( p1863 ) , + .prog_clk_2_W_in ( p662 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5595 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5596 ) , + .prog_clk_3_W_in ( p1990 ) , .prog_clk_3_E_in ( p2520 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5597 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5598 ) , .clk_1_W_in ( clk_1_wires[197] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8466 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5599 ) , .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8467 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8468 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8469 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8470 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8471 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8472 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8473 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8474 ) ) ; + .clk_2_E_in ( p2503 ) , .clk_2_W_in ( p1970 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5600 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5601 ) , .clk_3_W_in ( p1990 ) , + .clk_3_E_in ( p756 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5602 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5603 ) ) ; cbx_1__1_ cbx_10__10_ ( .chanx_left_in ( sb_1__1__97_chanx_right_out ) , .chanx_right_in ( sb_1__1__108_chanx_left_out ) , .ccff_head ( sb_1__1__108_ccff_tail ) , @@ -76558,38 +78436,28 @@ cbx_1__1_ cbx_10__10_ ( .chanx_left_in ( sb_1__1__97_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__108_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8475 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8476 ) , + .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( p1995 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5604 ) , .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[108] ) , .prog_clk_0_N_in ( prog_clk_0_wires[397] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8477 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8478 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8479 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8480 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8481 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8482 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8483 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8484 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8485 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8486 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8487 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8488 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8489 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8490 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8491 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8492 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8493 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8494 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8495 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8496 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8497 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8498 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8499 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8500 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8501 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5605 ) , + .prog_clk_1_W_in ( p1371 ) , .prog_clk_1_E_in ( p946 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5606 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5607 ) , + .prog_clk_2_E_in ( p1158 ) , .prog_clk_2_W_in ( p1502 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5608 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5609 ) , + .prog_clk_3_W_in ( p1710 ) , .prog_clk_3_E_in ( p2024 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5610 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5611 ) , .clk_1_W_in ( p1371 ) , + .clk_1_E_in ( p946 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5612 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5613 ) , .clk_2_E_in ( p1995 ) , + .clk_2_W_in ( p1502 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5614 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_3_W_in ( p1710 ) , + .clk_3_E_in ( p2024 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5616 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5617 ) ) ; cbx_1__1_ cbx_10__11_ ( .chanx_left_in ( sb_1__1__98_chanx_right_out ) , .chanx_right_in ( sb_1__1__109_chanx_left_out ) , .ccff_head ( sb_1__1__109_ccff_tail ) , @@ -76611,37 +78479,31 @@ cbx_1__1_ cbx_10__11_ ( .chanx_left_in ( sb_1__1__98_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__109_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8502 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8503 ) , + .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( p2514 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5618 ) , .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[109] ) , .prog_clk_0_N_in ( prog_clk_0_wires[400] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8504 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5619 ) , .prog_clk_1_W_in ( prog_clk_1_wires[204] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8505 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5620 ) , .prog_clk_1_N_out ( prog_clk_1_wires[208] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8506 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8507 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8508 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8509 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8510 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8511 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8512 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8513 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , .prog_clk_2_E_in ( p2073 ) , + .prog_clk_2_W_in ( p2128 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5621 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5622 ) , + .prog_clk_3_W_in ( p2414 ) , .prog_clk_3_E_in ( p2514 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5623 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5624 ) , .clk_1_W_in ( clk_1_wires[204] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8514 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5625 ) , .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8515 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8516 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8517 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8518 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8519 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8520 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8521 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8522 ) ) ; + .clk_2_E_in ( p2514 ) , .clk_2_W_in ( p2283 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5626 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5627 ) , .clk_3_W_in ( p2283 ) , + .clk_3_E_in ( p2549 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5628 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5629 ) ) ; cbx_1__1_ cbx_11__1_ ( .chanx_left_in ( sb_1__1__99_chanx_right_out ) , .chanx_right_in ( sb_1__1__110_chanx_left_out ) , .ccff_head ( sb_1__1__110_ccff_tail ) , @@ -76664,36 +78526,29 @@ cbx_1__1_ cbx_11__1_ ( .chanx_left_in ( sb_1__1__99_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) , - .SC_OUT_BOT ( scff_Wires[288] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8523 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8524 ) , + .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( p1354 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5630 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) , .prog_clk_0_N_in ( prog_clk_0_wires[408] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8525 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8526 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5631 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5632 ) , .prog_clk_1_E_in ( prog_clk_1_wires[212] ) , .prog_clk_1_N_out ( prog_clk_1_wires[213] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8527 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8528 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8529 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8530 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8531 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8532 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8533 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8534 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8535 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , .prog_clk_2_E_in ( p2323 ) , + .prog_clk_2_W_in ( p993 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5633 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5634 ) , + .prog_clk_3_W_in ( p2307 ) , .prog_clk_3_E_in ( p2985 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5635 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5636 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5637 ) , .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) , - .clk_1_S_out ( clk_1_wires[214] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8536 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8537 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8538 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8539 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8540 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8541 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8542 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8543 ) ) ; + .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( p3052 ) , + .clk_2_W_in ( p2270 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5638 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5639 ) , .clk_3_W_in ( p2307 ) , + .clk_3_E_in ( p2336 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5640 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5641 ) ) ; cbx_1__1_ cbx_11__2_ ( .chanx_left_in ( sb_1__1__100_chanx_right_out ) , .chanx_right_in ( sb_1__1__111_chanx_left_out ) , .ccff_head ( sb_1__1__111_ccff_tail ) , @@ -76716,37 +78571,30 @@ cbx_1__1_ cbx_11__2_ ( .chanx_left_in ( sb_1__1__100_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) , - .SC_OUT_BOT ( scff_Wires[286] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8544 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8545 ) , + .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( p1721 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5642 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) , .prog_clk_0_N_in ( prog_clk_0_wires[411] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8546 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8547 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8548 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8549 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8550 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8551 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5643 ) , + .prog_clk_1_W_in ( p1525 ) , .prog_clk_1_E_in ( p1458 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5644 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5645 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5646 ) , .prog_clk_2_W_in ( prog_clk_2_wires[114] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8552 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8553 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8554 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8555 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8556 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8557 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8558 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8559 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8560 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8561 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5647 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , .prog_clk_3_W_in ( p2554 ) , + .prog_clk_3_E_in ( p1542 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5648 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_1_W_in ( p1525 ) , + .clk_1_E_in ( p904 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5650 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5651 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5652 ) , .clk_2_W_in ( clk_2_wires[114] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8562 ) , - .clk_2_E_out ( clk_2_wires[113] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8563 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8564 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8565 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8566 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5653 ) , + .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p2554 ) , + .clk_3_E_in ( p1971 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5654 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5655 ) ) ; cbx_1__1_ cbx_11__3_ ( .chanx_left_in ( sb_1__1__101_chanx_right_out ) , .chanx_right_in ( sb_1__1__112_chanx_left_out ) , .ccff_head ( sb_1__1__112_ccff_tail ) , @@ -76769,36 +78617,29 @@ cbx_1__1_ cbx_11__3_ ( .chanx_left_in ( sb_1__1__101_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) , - .SC_OUT_BOT ( scff_Wires[284] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8567 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8568 ) , + .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( p1621 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5656 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) , .prog_clk_0_N_in ( prog_clk_0_wires[414] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8569 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8570 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5657 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5658 ) , .prog_clk_1_E_in ( prog_clk_1_wires[219] ) , .prog_clk_1_N_out ( prog_clk_1_wires[220] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8571 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8572 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8573 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8574 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8575 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8576 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8577 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8578 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8579 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , .prog_clk_2_E_in ( p2937 ) , + .prog_clk_2_W_in ( p1071 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5659 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5660 ) , + .prog_clk_3_W_in ( p1439 ) , .prog_clk_3_E_in ( p2285 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5661 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5662 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) , - .clk_1_S_out ( clk_1_wires[221] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8580 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8581 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8582 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8583 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8584 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8585 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8586 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8587 ) ) ; + .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( p2380 ) , + .clk_2_W_in ( p1631 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5664 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5665 ) , .clk_3_W_in ( p1439 ) , + .clk_3_E_in ( p2853 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5666 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5667 ) ) ; cbx_1__1_ cbx_11__4_ ( .chanx_left_in ( sb_1__1__102_chanx_right_out ) , .chanx_right_in ( sb_1__1__113_chanx_left_out ) , .ccff_head ( sb_1__1__113_ccff_tail ) , @@ -76821,37 +78662,30 @@ cbx_1__1_ cbx_11__4_ ( .chanx_left_in ( sb_1__1__102_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) , - .SC_OUT_BOT ( scff_Wires[282] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8588 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8589 ) , + .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( p1679 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5668 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) , .prog_clk_0_N_in ( prog_clk_0_wires[417] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8590 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8591 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8592 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8593 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8594 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8595 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5669 ) , + .prog_clk_1_W_in ( p1378 ) , .prog_clk_1_E_in ( p827 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5670 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5671 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5672 ) , .prog_clk_2_W_in ( prog_clk_2_wires[119] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8596 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8597 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8598 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8599 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8600 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8601 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8602 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8603 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8604 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8605 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5673 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , .prog_clk_3_W_in ( p1393 ) , + .prog_clk_3_E_in ( p1504 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5674 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_1_W_in ( p1378 ) , + .clk_1_E_in ( p1561 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5676 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5677 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5678 ) , .clk_2_W_in ( clk_2_wires[119] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8606 ) , - .clk_2_E_out ( clk_2_wires[118] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8607 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8608 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8609 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8610 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5679 ) , + .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1393 ) , + .clk_3_E_in ( p319 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5681 ) ) ; cbx_1__1_ cbx_11__5_ ( .chanx_left_in ( sb_1__1__103_chanx_right_out ) , .chanx_right_in ( sb_1__1__114_chanx_left_out ) , .ccff_head ( sb_1__1__114_ccff_tail ) , @@ -76874,36 +78708,29 @@ cbx_1__1_ cbx_11__5_ ( .chanx_left_in ( sb_1__1__103_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) , - .SC_OUT_BOT ( scff_Wires[280] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8611 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8612 ) , + .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( p1834 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5682 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) , .prog_clk_0_N_in ( prog_clk_0_wires[420] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8613 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8614 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5683 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5684 ) , .prog_clk_1_E_in ( prog_clk_1_wires[226] ) , .prog_clk_1_N_out ( prog_clk_1_wires[227] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8615 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8616 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8617 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8618 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8619 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8620 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8621 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8622 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8623 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , .prog_clk_2_E_in ( p1421 ) , + .prog_clk_2_W_in ( p1375 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5685 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5686 ) , + .prog_clk_3_W_in ( p2086 ) , .prog_clk_3_E_in ( p2003 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5687 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5688 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5689 ) , .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) , - .clk_1_S_out ( clk_1_wires[228] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8624 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8625 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8626 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8627 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8628 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8629 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8630 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8631 ) ) ; + .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( p2083 ) , + .clk_2_W_in ( p1968 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5690 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5691 ) , .clk_3_W_in ( p2086 ) , + .clk_3_E_in ( p1311 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5692 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5693 ) ) ; cbx_1__1_ cbx_11__6_ ( .chanx_left_in ( sb_1__1__104_chanx_right_out ) , .chanx_right_in ( sb_1__1__115_chanx_left_out ) , .ccff_head ( sb_1__1__115_ccff_tail ) , @@ -76926,37 +78753,27 @@ cbx_1__1_ cbx_11__6_ ( .chanx_left_in ( sb_1__1__104_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) , - .SC_OUT_BOT ( scff_Wires[278] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8632 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8633 ) , + .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( p2056 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5694 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) , .prog_clk_0_N_in ( prog_clk_0_wires[423] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8634 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8635 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8636 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8637 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8638 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8639 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8640 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8641 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8642 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8643 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8644 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8645 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8646 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8647 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8648 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8649 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8650 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8651 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8652 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8653 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8654 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8655 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8656 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8657 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8658 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5695 ) , + .prog_clk_1_W_in ( p1400 ) , .prog_clk_1_E_in ( p156 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5696 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5697 ) , + .prog_clk_2_E_in ( p2691 ) , .prog_clk_2_W_in ( p1508 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5698 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5699 ) , + .prog_clk_3_W_in ( p1806 ) , .prog_clk_3_E_in ( p2852 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5700 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5701 ) , .clk_1_W_in ( p1400 ) , + .clk_1_E_in ( p1976 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5702 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5703 ) , .clk_2_E_in ( p2863 ) , + .clk_2_W_in ( p699 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5704 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_3_W_in ( p1340 ) , + .clk_3_E_in ( p2679 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5706 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5707 ) ) ; cbx_1__1_ cbx_11__7_ ( .chanx_left_in ( sb_1__1__105_chanx_right_out ) , .chanx_right_in ( sb_1__1__116_chanx_left_out ) , .ccff_head ( sb_1__1__116_ccff_tail ) , @@ -76979,36 +78796,29 @@ cbx_1__1_ cbx_11__7_ ( .chanx_left_in ( sb_1__1__105_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) , - .SC_OUT_BOT ( scff_Wires[276] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8659 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8660 ) , + .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( p1658 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5708 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) , .prog_clk_0_N_in ( prog_clk_0_wires[426] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8661 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8662 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5709 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5710 ) , .prog_clk_1_E_in ( prog_clk_1_wires[233] ) , .prog_clk_1_N_out ( prog_clk_1_wires[234] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8663 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8664 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8665 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8666 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8667 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8668 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8669 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8670 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8671 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , .prog_clk_2_E_in ( p2602 ) , + .prog_clk_2_W_in ( p1517 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5711 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5712 ) , + .prog_clk_3_W_in ( p1599 ) , .prog_clk_3_E_in ( p2857 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5713 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5714 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5715 ) , .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) , - .clk_1_S_out ( clk_1_wires[235] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8672 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8673 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8674 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8675 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8676 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8677 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8678 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8679 ) ) ; + .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( p2850 ) , + .clk_2_W_in ( p1143 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5716 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5717 ) , .clk_3_W_in ( p1599 ) , + .clk_3_E_in ( p2517 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5718 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5719 ) ) ; cbx_1__1_ cbx_11__8_ ( .chanx_left_in ( sb_1__1__106_chanx_right_out ) , .chanx_right_in ( sb_1__1__117_chanx_left_out ) , .ccff_head ( sb_1__1__117_ccff_tail ) , @@ -77031,37 +78841,30 @@ cbx_1__1_ cbx_11__8_ ( .chanx_left_in ( sb_1__1__106_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) , - .SC_OUT_BOT ( scff_Wires[274] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8680 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8681 ) , + .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( p2419 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5720 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) , .prog_clk_0_N_in ( prog_clk_0_wires[429] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8682 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8683 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8684 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8685 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8686 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8687 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5721 ) , + .prog_clk_1_W_in ( p1453 ) , .prog_clk_1_E_in ( p849 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5722 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5723 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5724 ) , .prog_clk_2_W_in ( prog_clk_2_wires[126] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8688 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8689 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8690 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8691 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8692 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8693 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8694 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8695 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8696 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8697 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5725 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , .prog_clk_3_W_in ( p1180 ) , + .prog_clk_3_E_in ( p1527 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5726 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5727 ) , .clk_1_W_in ( p1453 ) , + .clk_1_E_in ( p2248 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5728 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5729 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5730 ) , .clk_2_W_in ( clk_2_wires[126] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8698 ) , - .clk_2_E_out ( clk_2_wires[125] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8699 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8700 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8701 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8702 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5731 ) , + .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1180 ) , + .clk_3_E_in ( p500 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5732 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5733 ) ) ; cbx_1__1_ cbx_11__9_ ( .chanx_left_in ( sb_1__1__107_chanx_right_out ) , .chanx_right_in ( sb_1__1__118_chanx_left_out ) , .ccff_head ( sb_1__1__118_ccff_tail ) , @@ -77084,36 +78887,29 @@ cbx_1__1_ cbx_11__9_ ( .chanx_left_in ( sb_1__1__107_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) , - .SC_OUT_BOT ( scff_Wires[272] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8703 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8704 ) , + .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( p2007 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5734 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) , .prog_clk_0_N_in ( prog_clk_0_wires[432] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8705 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8706 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5735 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5736 ) , .prog_clk_1_E_in ( prog_clk_1_wires[240] ) , .prog_clk_1_N_out ( prog_clk_1_wires[241] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8707 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8708 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8709 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8710 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8711 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8712 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8713 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8714 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8715 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , .prog_clk_2_E_in ( p2351 ) , + .prog_clk_2_W_in ( p1587 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5737 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , + .prog_clk_3_W_in ( p2077 ) , .prog_clk_3_E_in ( p1779 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5740 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5741 ) , .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) , - .clk_1_S_out ( clk_1_wires[242] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8716 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8717 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8718 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8719 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8720 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8721 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8722 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8723 ) ) ; + .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( p1760 ) , + .clk_2_W_in ( p2842 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5742 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5743 ) , .clk_3_W_in ( p2864 ) , + .clk_3_E_in ( p2184 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5744 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5745 ) ) ; cbx_1__1_ cbx_11__10_ ( .chanx_left_in ( sb_1__1__108_chanx_right_out ) , .chanx_right_in ( sb_1__1__119_chanx_left_out ) , .ccff_head ( sb_1__1__119_ccff_tail ) , @@ -77136,37 +78932,30 @@ cbx_1__1_ cbx_11__10_ ( .chanx_left_in ( sb_1__1__108_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) , - .SC_OUT_BOT ( scff_Wires[270] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8724 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8725 ) , + .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( p2335 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5746 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) , .prog_clk_0_N_in ( prog_clk_0_wires[435] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8726 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8727 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8728 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8729 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8730 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8731 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5747 ) , + .prog_clk_1_W_in ( p1605 ) , .prog_clk_1_E_in ( p1529 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5748 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5749 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5750 ) , .prog_clk_2_W_in ( prog_clk_2_wires[133] ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8732 ) , - .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8733 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8734 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8735 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8736 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8737 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8738 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8739 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8740 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8741 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5751 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , .prog_clk_3_W_in ( p1881 ) , + .prog_clk_3_E_in ( p556 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5752 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5753 ) , .clk_1_W_in ( p1420 ) , + .clk_1_E_in ( p2260 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5754 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5755 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5756 ) , .clk_2_W_in ( clk_2_wires[133] ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8742 ) , - .clk_2_E_out ( clk_2_wires[132] ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8743 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8744 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8745 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8746 ) ) ; + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5757 ) , + .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1881 ) , + .clk_3_E_in ( p2492 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5758 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5759 ) ) ; cbx_1__1_ cbx_11__11_ ( .chanx_left_in ( sb_1__1__109_chanx_right_out ) , .chanx_right_in ( sb_1__1__120_chanx_left_out ) , .ccff_head ( sb_1__1__120_ccff_tail ) , @@ -77189,36 +78978,29 @@ cbx_1__1_ cbx_11__11_ ( .chanx_left_in ( sb_1__1__109_chanx_right_out ) , .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) , - .SC_OUT_BOT ( scff_Wires[268] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8747 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_8748 ) , + .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( p1642 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5760 ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) , .prog_clk_0_N_in ( prog_clk_0_wires[438] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8749 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8750 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5761 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5762 ) , .prog_clk_1_E_in ( prog_clk_1_wires[247] ) , .prog_clk_1_N_out ( prog_clk_1_wires[248] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8751 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8752 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8753 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8754 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8755 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8756 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8757 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8758 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8759 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , .prog_clk_2_E_in ( p1799 ) , + .prog_clk_2_W_in ( p1387 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5763 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5764 ) , + .prog_clk_3_W_in ( p2392 ) , .prog_clk_3_E_in ( p3189 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5765 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5766 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5767 ) , .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) , - .clk_1_S_out ( clk_1_wires[249] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8760 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8761 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8762 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8763 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8764 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8765 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8766 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8767 ) ) ; + .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( p3233 ) , + .clk_2_W_in ( p2269 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5768 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5769 ) , .clk_3_W_in ( p2392 ) , + .clk_3_E_in ( p866 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5771 ) ) ; cbx_1__1_ cbx_12__1_ ( .chanx_left_in ( sb_1__1__110_chanx_right_out ) , .chanx_right_in ( sb_12__1__0_chanx_left_out ) , .ccff_head ( sb_12__1__0_ccff_tail ) , @@ -77240,37 +79022,31 @@ cbx_1__1_ cbx_12__1_ ( .chanx_left_in ( sb_1__1__110_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__121_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8768 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8769 ) , + .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( p2162 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5772 ) , .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[121] ) , .prog_clk_0_N_in ( prog_clk_0_wires[446] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8770 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5773 ) , .prog_clk_1_W_in ( prog_clk_1_wires[211] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8771 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5774 ) , .prog_clk_1_N_out ( prog_clk_1_wires[215] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8772 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8773 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8774 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8775 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8776 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8777 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8778 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8779 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , .prog_clk_2_E_in ( p2314 ) , + .prog_clk_2_W_in ( p269 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5775 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5776 ) , + .prog_clk_3_W_in ( p2023 ) , .prog_clk_3_E_in ( p2032 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5777 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5778 ) , .clk_1_W_in ( clk_1_wires[211] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8780 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5779 ) , .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8781 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8782 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8783 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8784 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8785 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8786 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8787 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8788 ) ) ; + .clk_2_E_in ( p2162 ) , .clk_2_W_in ( p2981 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5780 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5781 ) , .clk_3_W_in ( p3051 ) , + .clk_3_E_in ( p2268 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5782 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5783 ) ) ; cbx_1__1_ cbx_12__2_ ( .chanx_left_in ( sb_1__1__111_chanx_right_out ) , .chanx_right_in ( sb_12__1__1_chanx_left_out ) , .ccff_head ( sb_12__1__1_ccff_tail ) , @@ -77292,38 +79068,28 @@ cbx_1__1_ cbx_12__2_ ( .chanx_left_in ( sb_1__1__111_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__122_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8789 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8790 ) , + .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( p1829 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5784 ) , .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[122] ) , .prog_clk_0_N_in ( prog_clk_0_wires[449] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8791 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8792 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8793 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8794 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8795 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8796 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8797 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8798 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8799 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8800 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8801 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8802 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8803 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8804 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8805 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8806 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8807 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8808 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8809 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8810 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8811 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8812 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8813 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8814 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8815 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5785 ) , + .prog_clk_1_W_in ( p1688 ) , .prog_clk_1_E_in ( p733 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5786 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5787 ) , + .prog_clk_2_E_in ( p2862 ) , .prog_clk_2_W_in ( p1344 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5788 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5789 ) , + .prog_clk_3_W_in ( p2599 ) , .prog_clk_3_E_in ( p2695 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5790 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5791 ) , .clk_1_W_in ( p1688 ) , + .clk_1_E_in ( p695 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5792 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5793 ) , .clk_2_E_in ( p2712 ) , + .clk_2_W_in ( p2428 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5794 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5795 ) , .clk_3_W_in ( p2599 ) , + .clk_3_E_in ( p2810 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5796 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5797 ) ) ; cbx_1__1_ cbx_12__3_ ( .chanx_left_in ( sb_1__1__112_chanx_right_out ) , .chanx_right_in ( sb_12__1__2_chanx_left_out ) , .ccff_head ( sb_12__1__2_ccff_tail ) , @@ -77345,37 +79111,31 @@ cbx_1__1_ cbx_12__3_ ( .chanx_left_in ( sb_1__1__112_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__123_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8816 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8817 ) , + .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( p1810 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5798 ) , .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[123] ) , .prog_clk_0_N_in ( prog_clk_0_wires[452] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8818 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5799 ) , .prog_clk_1_W_in ( prog_clk_1_wires[218] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8819 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5800 ) , .prog_clk_1_N_out ( prog_clk_1_wires[222] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8820 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8821 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8822 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8823 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8824 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8825 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8826 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8827 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , .prog_clk_2_E_in ( p2555 ) , + .prog_clk_2_W_in ( p1540 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5801 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , + .prog_clk_3_W_in ( p2087 ) , .prog_clk_3_E_in ( p1908 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) , .clk_1_W_in ( clk_1_wires[218] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8828 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5805 ) , .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8829 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8830 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8831 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8832 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8833 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8834 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8835 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8836 ) ) ; + .clk_2_E_in ( p2018 ) , .clk_2_W_in ( p2496 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5806 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5807 ) , .clk_3_W_in ( p2581 ) , + .clk_3_E_in ( p2436 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5808 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5809 ) ) ; cbx_1__1_ cbx_12__4_ ( .chanx_left_in ( sb_1__1__113_chanx_right_out ) , .chanx_right_in ( sb_12__1__3_chanx_left_out ) , .ccff_head ( sb_12__1__3_ccff_tail ) , @@ -77397,38 +79157,28 @@ cbx_1__1_ cbx_12__4_ ( .chanx_left_in ( sb_1__1__113_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__124_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8837 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8838 ) , + .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( p1878 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5810 ) , .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[124] ) , .prog_clk_0_N_in ( prog_clk_0_wires[455] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8839 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8840 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8841 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8842 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8843 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8844 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8845 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8846 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8847 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8848 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8849 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8850 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8851 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8852 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8853 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8855 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8856 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8857 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8858 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8859 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8860 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8861 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8862 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8863 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5811 ) , + .prog_clk_1_W_in ( p1570 ) , .prog_clk_1_E_in ( p1622 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5812 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5813 ) , + .prog_clk_2_E_in ( p2744 ) , .prog_clk_2_W_in ( p48 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5814 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5815 ) , + .prog_clk_3_W_in ( p1348 ) , .prog_clk_3_E_in ( p2699 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5816 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_1_W_in ( p1570 ) , + .clk_1_E_in ( p398 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5818 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_2_E_in ( p2790 ) , + .clk_2_W_in ( p1359 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5820 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5821 ) , .clk_3_W_in ( p1348 ) , + .clk_3_E_in ( p2639 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5822 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5823 ) ) ; cbx_1__1_ cbx_12__5_ ( .chanx_left_in ( sb_1__1__114_chanx_right_out ) , .chanx_right_in ( sb_12__1__4_chanx_left_out ) , .ccff_head ( sb_12__1__4_ccff_tail ) , @@ -77450,37 +79200,31 @@ cbx_1__1_ cbx_12__5_ ( .chanx_left_in ( sb_1__1__114_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__125_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8864 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8865 ) , + .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( p2084 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5824 ) , .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[125] ) , .prog_clk_0_N_in ( prog_clk_0_wires[458] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8866 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5825 ) , .prog_clk_1_W_in ( prog_clk_1_wires[225] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8867 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5826 ) , .prog_clk_1_N_out ( prog_clk_1_wires[229] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8868 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8869 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8870 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8871 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8872 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8873 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8874 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8875 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , .prog_clk_2_E_in ( p1548 ) , + .prog_clk_2_W_in ( p670 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5827 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5828 ) , + .prog_clk_3_W_in ( p1544 ) , .prog_clk_3_E_in ( p2463 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5829 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5830 ) , .clk_1_W_in ( clk_1_wires[225] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8876 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5831 ) , .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8877 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8878 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8879 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8880 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8881 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8882 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8883 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8884 ) ) ; + .clk_2_E_in ( p2552 ) , .clk_2_W_in ( p1482 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5832 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5833 ) , .clk_3_W_in ( p1628 ) , + .clk_3_E_in ( p1550 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5835 ) ) ; cbx_1__1_ cbx_12__6_ ( .chanx_left_in ( sb_1__1__115_chanx_right_out ) , .chanx_right_in ( sb_12__1__5_chanx_left_out ) , .ccff_head ( sb_12__1__5_ccff_tail ) , @@ -77502,38 +79246,28 @@ cbx_1__1_ cbx_12__6_ ( .chanx_left_in ( sb_1__1__115_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__126_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8885 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8886 ) , + .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( p1754 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5836 ) , .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[126] ) , .prog_clk_0_N_in ( prog_clk_0_wires[461] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8887 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8888 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8889 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8890 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8891 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8892 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8893 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8894 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8895 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8896 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8897 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8898 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8899 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8900 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8901 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8902 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8903 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8904 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8905 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8906 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8907 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8908 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8909 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8910 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8911 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5837 ) , + .prog_clk_1_W_in ( p1538 ) , .prog_clk_1_E_in ( p976 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5838 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5839 ) , + .prog_clk_2_E_in ( p2343 ) , .prog_clk_2_W_in ( p1070 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5840 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5841 ) , + .prog_clk_3_W_in ( p2379 ) , .prog_clk_3_E_in ( p2074 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5842 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5843 ) , .clk_1_W_in ( p1538 ) , + .clk_1_E_in ( p580 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5844 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5845 ) , .clk_2_E_in ( p2027 ) , + .clk_2_W_in ( p2480 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5846 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5847 ) , .clk_3_W_in ( p2553 ) , + .clk_3_E_in ( p2243 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5848 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5849 ) ) ; cbx_1__1_ cbx_12__7_ ( .chanx_left_in ( sb_1__1__116_chanx_right_out ) , .chanx_right_in ( sb_12__1__6_chanx_left_out ) , .ccff_head ( sb_12__1__6_ccff_tail ) , @@ -77555,37 +79289,31 @@ cbx_1__1_ cbx_12__7_ ( .chanx_left_in ( sb_1__1__116_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__127_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8912 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8913 ) , + .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( p1857 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5850 ) , .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[127] ) , .prog_clk_0_N_in ( prog_clk_0_wires[464] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8914 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5851 ) , .prog_clk_1_W_in ( prog_clk_1_wires[232] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8915 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5852 ) , .prog_clk_1_N_out ( prog_clk_1_wires[236] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8916 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8917 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8918 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8919 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8920 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8921 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8922 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8923 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , .prog_clk_2_E_in ( p2327 ) , + .prog_clk_2_W_in ( p1449 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5853 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5854 ) , + .prog_clk_3_W_in ( p1593 ) , .prog_clk_3_E_in ( p1595 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5855 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5856 ) , .clk_1_W_in ( clk_1_wires[232] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8924 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5857 ) , .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8925 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8926 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8927 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8928 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8929 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8930 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8931 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8932 ) ) ; + .clk_2_E_in ( p1857 ) , .clk_2_W_in ( p2982 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5858 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5859 ) , .clk_3_W_in ( p3025 ) , + .clk_3_E_in ( p2213 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5860 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5861 ) ) ; cbx_1__1_ cbx_12__8_ ( .chanx_left_in ( sb_1__1__117_chanx_right_out ) , .chanx_right_in ( sb_12__1__7_chanx_left_out ) , .ccff_head ( sb_12__1__7_ccff_tail ) , @@ -77607,38 +79335,28 @@ cbx_1__1_ cbx_12__8_ ( .chanx_left_in ( sb_1__1__117_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__128_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8933 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8934 ) , + .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( p2033 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5862 ) , .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[128] ) , .prog_clk_0_N_in ( prog_clk_0_wires[467] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8935 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8936 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8937 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8938 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8939 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8940 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8941 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8942 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8943 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8944 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8945 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8946 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8947 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8948 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8949 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8950 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8951 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8952 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8953 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8954 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8955 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8956 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8957 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8958 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8959 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5863 ) , + .prog_clk_1_W_in ( p1572 ) , .prog_clk_1_E_in ( p420 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5864 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5865 ) , + .prog_clk_2_E_in ( p2413 ) , .prog_clk_2_W_in ( p1153 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5866 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5867 ) , + .prog_clk_3_W_in ( p2422 ) , .prog_clk_3_E_in ( p2065 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5868 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5869 ) , .clk_1_W_in ( p1572 ) , + .clk_1_E_in ( p1374 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5870 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5871 ) , .clk_2_E_in ( p2054 ) , + .clk_2_W_in ( p2236 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5872 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5873 ) , .clk_3_W_in ( p2422 ) , + .clk_3_E_in ( p2235 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5874 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5875 ) ) ; cbx_1__1_ cbx_12__9_ ( .chanx_left_in ( sb_1__1__118_chanx_right_out ) , .chanx_right_in ( sb_12__1__8_chanx_left_out ) , .ccff_head ( sb_12__1__8_ccff_tail ) , @@ -77660,37 +79378,31 @@ cbx_1__1_ cbx_12__9_ ( .chanx_left_in ( sb_1__1__118_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__129_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8960 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8961 ) , + .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( p1841 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5876 ) , .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[129] ) , .prog_clk_0_N_in ( prog_clk_0_wires[470] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8962 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5877 ) , .prog_clk_1_W_in ( prog_clk_1_wires[239] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8963 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5878 ) , .prog_clk_1_N_out ( prog_clk_1_wires[243] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8964 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8965 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8966 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8967 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8968 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8969 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8970 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8971 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , .prog_clk_2_E_in ( p1655 ) , + .prog_clk_2_W_in ( p1248 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5879 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5880 ) , + .prog_clk_3_W_in ( p2297 ) , .prog_clk_3_E_in ( p2215 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5881 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5882 ) , .clk_1_W_in ( clk_1_wires[239] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8972 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_8973 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_8974 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_8975 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_8976 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_8977 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_8978 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_8979 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_8980 ) ) ; + .clk_2_E_in ( p2373 ) , .clk_2_W_in ( p2252 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5884 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5885 ) , .clk_3_W_in ( p2297 ) , + .clk_3_E_in ( p1437 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5886 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5887 ) ) ; cbx_1__1_ cbx_12__10_ ( .chanx_left_in ( sb_1__1__119_chanx_right_out ) , .chanx_right_in ( sb_12__1__9_chanx_left_out ) , .ccff_head ( sb_12__1__9_ccff_tail ) , @@ -77712,38 +79424,28 @@ cbx_1__1_ cbx_12__10_ ( .chanx_left_in ( sb_1__1__119_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__130_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_8981 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8982 ) , + .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( p2338 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5888 ) , .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[130] ) , .prog_clk_0_N_in ( prog_clk_0_wires[473] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_8983 ) , - .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_8984 ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_8985 ) , - .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_8986 ) , - .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_8987 ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_8988 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_8989 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_8990 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_8991 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_8992 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_8993 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_8994 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_8995 ) , - .clk_1_W_in ( SYNOPSYS_UNCONNECTED_8996 ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_8997 ) , - .clk_1_N_out ( SYNOPSYS_UNCONNECTED_8998 ) , - .clk_1_S_out ( SYNOPSYS_UNCONNECTED_8999 ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_9000 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_9001 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_9002 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_9003 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_9004 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_9005 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_9006 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_9007 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5889 ) , + .prog_clk_1_W_in ( p1585 ) , .prog_clk_1_E_in ( p1282 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5890 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5891 ) , + .prog_clk_2_E_in ( p2702 ) , .prog_clk_2_W_in ( p450 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5892 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5893 ) , + .prog_clk_3_W_in ( p1798 ) , .prog_clk_3_E_in ( p2280 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5894 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5895 ) , .clk_1_W_in ( p1585 ) , + .clk_1_E_in ( p344 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5896 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5897 ) , .clk_2_E_in ( p2333 ) , + .clk_2_W_in ( p1337 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5898 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5899 ) , .clk_3_W_in ( p1798 ) , + .clk_3_E_in ( p2673 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5900 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5901 ) ) ; cbx_1__1_ cbx_12__11_ ( .chanx_left_in ( sb_1__1__120_chanx_right_out ) , .chanx_right_in ( sb_12__1__10_chanx_left_out ) , .ccff_head ( sb_12__1__10_ccff_tail ) , @@ -77765,37 +79467,31 @@ cbx_1__1_ cbx_12__11_ ( .chanx_left_in ( sb_1__1__120_chanx_right_out ) , .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__131_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_9008 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_9009 ) , + .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( p1848 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5902 ) , .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) , .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) , .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[131] ) , .prog_clk_0_N_in ( prog_clk_0_wires[476] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9010 ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5903 ) , .prog_clk_1_W_in ( prog_clk_1_wires[246] ) , - .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_9011 ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5904 ) , .prog_clk_1_N_out ( prog_clk_1_wires[250] ) , - .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , - .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_9012 ) , - .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_9013 ) , - .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_9014 ) , - .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_9015 ) , - .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_9016 ) , - .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_9017 ) , - .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_9018 ) , - .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_9019 ) , + .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , .prog_clk_2_E_in ( p1468 ) , + .prog_clk_2_W_in ( p11 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5905 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5906 ) , + .prog_clk_3_W_in ( p2312 ) , .prog_clk_3_E_in ( p1492 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5907 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5908 ) , .clk_1_W_in ( clk_1_wires[246] ) , - .clk_1_E_in ( SYNOPSYS_UNCONNECTED_9020 ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5909 ) , .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) , - .clk_2_E_in ( SYNOPSYS_UNCONNECTED_9021 ) , - .clk_2_W_in ( SYNOPSYS_UNCONNECTED_9022 ) , - .clk_2_W_out ( SYNOPSYS_UNCONNECTED_9023 ) , - .clk_2_E_out ( SYNOPSYS_UNCONNECTED_9024 ) , - .clk_3_W_in ( SYNOPSYS_UNCONNECTED_9025 ) , - .clk_3_E_in ( SYNOPSYS_UNCONNECTED_9026 ) , - .clk_3_E_out ( SYNOPSYS_UNCONNECTED_9027 ) , - .clk_3_W_out ( SYNOPSYS_UNCONNECTED_9028 ) ) ; + .clk_2_E_in ( p1673 ) , .clk_2_W_in ( p2254 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5910 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5911 ) , .clk_3_W_in ( p2312 ) , + .clk_3_E_in ( p523 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5912 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5913 ) ) ; cbx_1__2_ cbx_1__12_ ( .chanx_left_in ( sb_0__12__0_chanx_right_out ) , .chanx_right_in ( sb_1__12__0_chanx_left_out ) , .ccff_head ( sb_1__12__0_ccff_tail ) , @@ -77826,8 +79522,7 @@ cbx_1__2_ cbx_1__12_ ( .chanx_left_in ( sb_0__12__0_chanx_right_out ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9029 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9030 ) , + .SC_IN_BOT ( p1368 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5914 ) , .prog_clk_0_S_in ( prog_clk_0_wires[59] ) , .prog_clk_0_W_out ( prog_clk_0_wires[62] ) ) ; cbx_1__2_ cbx_2__12_ ( .chanx_left_in ( sb_1__12__0_chanx_right_out ) , @@ -77859,11 +79554,10 @@ cbx_1__2_ cbx_2__12_ ( .chanx_left_in ( sb_1__12__0_chanx_right_out ) , .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_9031 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_9032 ) , + .SC_IN_TOP ( p1698 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5915 ) , .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) , .prog_clk_0_S_in ( prog_clk_0_wires[99] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9033 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5916 ) ) ; cbx_1__2_ cbx_3__12_ ( .chanx_left_in ( sb_1__12__1_chanx_right_out ) , .chanx_right_in ( sb_1__12__2_chanx_left_out ) , .ccff_head ( sb_1__12__2_ccff_tail ) , @@ -77894,10 +79588,9 @@ cbx_1__2_ cbx_3__12_ ( .chanx_left_in ( sb_1__12__1_chanx_right_out ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9034 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9035 ) , + .SC_IN_BOT ( p1422 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5917 ) , .prog_clk_0_S_in ( prog_clk_0_wires[137] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9036 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5918 ) ) ; cbx_1__2_ cbx_4__12_ ( .chanx_left_in ( sb_1__12__2_chanx_right_out ) , .chanx_right_in ( sb_1__12__3_chanx_left_out ) , .ccff_head ( sb_1__12__3_ccff_tail ) , @@ -77927,11 +79620,10 @@ cbx_1__2_ cbx_4__12_ ( .chanx_left_in ( sb_1__12__2_chanx_right_out ) , .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_9037 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_9038 ) , + .SC_IN_TOP ( p2029 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5919 ) , .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) , .prog_clk_0_S_in ( prog_clk_0_wires[175] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9039 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5920 ) ) ; cbx_1__2_ cbx_5__12_ ( .chanx_left_in ( sb_1__12__3_chanx_right_out ) , .chanx_right_in ( sb_1__12__4_chanx_left_out ) , .ccff_head ( sb_1__12__4_ccff_tail ) , @@ -77962,10 +79654,9 @@ cbx_1__2_ cbx_5__12_ ( .chanx_left_in ( sb_1__12__3_chanx_right_out ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9040 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9041 ) , + .SC_IN_BOT ( p1788 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5921 ) , .prog_clk_0_S_in ( prog_clk_0_wires[213] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9042 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5922 ) ) ; cbx_1__2_ cbx_6__12_ ( .chanx_left_in ( sb_1__12__4_chanx_right_out ) , .chanx_right_in ( sb_1__12__5_chanx_left_out ) , .ccff_head ( sb_1__12__5_ccff_tail ) , @@ -77995,11 +79686,10 @@ cbx_1__2_ cbx_6__12_ ( .chanx_left_in ( sb_1__12__4_chanx_right_out ) , .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_9043 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_9044 ) , + .SC_IN_TOP ( p1736 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5923 ) , .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) , .prog_clk_0_S_in ( prog_clk_0_wires[251] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9045 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5924 ) ) ; cbx_1__2_ cbx_7__12_ ( .chanx_left_in ( sb_1__12__5_chanx_right_out ) , .chanx_right_in ( sb_1__12__6_chanx_left_out ) , .ccff_head ( sb_1__12__6_ccff_tail ) , @@ -78030,10 +79720,9 @@ cbx_1__2_ cbx_7__12_ ( .chanx_left_in ( sb_1__12__5_chanx_right_out ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9046 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9047 ) , + .SC_IN_BOT ( p1652 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5925 ) , .prog_clk_0_S_in ( prog_clk_0_wires[289] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9048 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5926 ) ) ; cbx_1__2_ cbx_8__12_ ( .chanx_left_in ( sb_1__12__6_chanx_right_out ) , .chanx_right_in ( sb_1__12__7_chanx_left_out ) , .ccff_head ( sb_1__12__7_ccff_tail ) , @@ -78063,11 +79752,10 @@ cbx_1__2_ cbx_8__12_ ( .chanx_left_in ( sb_1__12__6_chanx_right_out ) , .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_9049 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_9050 ) , + .SC_IN_TOP ( p1720 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5927 ) , .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) , .prog_clk_0_S_in ( prog_clk_0_wires[327] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9051 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5928 ) ) ; cbx_1__2_ cbx_9__12_ ( .chanx_left_in ( sb_1__12__7_chanx_right_out ) , .chanx_right_in ( sb_1__12__8_chanx_left_out ) , .ccff_head ( sb_1__12__8_ccff_tail ) , @@ -78098,10 +79786,9 @@ cbx_1__2_ cbx_9__12_ ( .chanx_left_in ( sb_1__12__7_chanx_right_out ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9052 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9053 ) , + .SC_IN_BOT ( p1523 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5929 ) , .prog_clk_0_S_in ( prog_clk_0_wires[365] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9054 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5930 ) ) ; cbx_1__2_ cbx_10__12_ ( .chanx_left_in ( sb_1__12__8_chanx_right_out ) , .chanx_right_in ( sb_1__12__9_chanx_left_out ) , .ccff_head ( sb_1__12__9_ccff_tail ) , @@ -78131,11 +79818,10 @@ cbx_1__2_ cbx_10__12_ ( .chanx_left_in ( sb_1__12__8_chanx_right_out ) , .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_9055 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_9056 ) , + .SC_IN_TOP ( p1787 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5931 ) , .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) , .prog_clk_0_S_in ( prog_clk_0_wires[403] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9057 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5932 ) ) ; cbx_1__2_ cbx_11__12_ ( .chanx_left_in ( sb_1__12__9_chanx_right_out ) , .chanx_right_in ( sb_1__12__10_chanx_left_out ) , .ccff_head ( sb_1__12__10_ccff_tail ) , @@ -78166,10 +79852,9 @@ cbx_1__2_ cbx_11__12_ ( .chanx_left_in ( sb_1__12__9_chanx_right_out ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9058 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9059 ) , + .SC_IN_BOT ( p1533 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5933 ) , .prog_clk_0_S_in ( prog_clk_0_wires[441] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9060 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5934 ) ) ; cbx_1__2_ cbx_12__12_ ( .chanx_left_in ( sb_1__12__10_chanx_right_out ) , .chanx_right_in ( sb_12__12__0_chanx_left_out ) , .ccff_head ( sb_12__12__0_ccff_tail ) , @@ -78199,11 +79884,10 @@ cbx_1__2_ cbx_12__12_ ( .chanx_left_in ( sb_1__12__10_chanx_right_out ) , .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_9061 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_9062 ) , + .SC_IN_TOP ( p2161 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5935 ) , .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) , .prog_clk_0_S_in ( prog_clk_0_wires[479] ) , - .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_9063 ) ) ; + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5936 ) ) ; cby_0__1_ cby_0__1_ ( .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , @@ -78394,31 +80078,25 @@ cby_1__1_ cby_1__1_ ( .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__0_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9064 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5937 ) , .Test_en_E_in ( Test_enWires[26] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9065 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9066 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5938 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5939 ) , .Test_en_W_out ( Test_enWires[24] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9067 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5940 ) , .prog_clk_0_W_in ( prog_clk_0_wires[1] ) , .prog_clk_0_S_out ( prog_clk_0_wires[2] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9068 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9069 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9070 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9071 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9072 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9073 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9074 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9075 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9076 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9077 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9078 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9081 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9082 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9083 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9084 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5941 ) , + .prog_clk_2_N_in ( p3425 ) , .prog_clk_2_S_in ( p2824 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5942 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5943 ) , + .prog_clk_3_S_in ( p2930 ) , .prog_clk_3_N_in ( p3401 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5944 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_2_N_in ( p3200 ) , + .clk_2_S_in ( p2187 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5946 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5947 ) , .clk_3_S_in ( p2277 ) , + .clk_3_N_in ( p766 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5948 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5949 ) ) ; cby_1__1_ cby_1__2_ ( .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__1__1_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , @@ -78441,31 +80119,28 @@ cby_1__1_ cby_1__2_ ( .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__1_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9085 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5950 ) , .Test_en_E_in ( Test_enWires[48] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9086 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9087 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5951 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5952 ) , .Test_en_W_out ( Test_enWires[46] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9088 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5953 ) , .prog_clk_0_W_in ( prog_clk_0_wires[7] ) , .prog_clk_0_S_out ( prog_clk_0_wires[8] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9089 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5954 ) , .prog_clk_2_N_in ( prog_clk_2_wires[3] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9090 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5955 ) , .prog_clk_2_S_out ( prog_clk_2_wires[4] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9091 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9092 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9093 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9094 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9095 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5956 ) , + .prog_clk_3_S_in ( p1604 ) , .prog_clk_3_N_in ( p480 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5957 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_2_N_in ( clk_2_wires[3] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9096 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5959 ) , .clk_2_S_out ( clk_2_wires[4] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9097 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9098 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9099 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9101 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_3_S_in ( p2037 ) , + .clk_3_N_in ( p1261 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5961 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5962 ) ) ; cby_1__1_ cby_1__3_ ( .chany_bottom_in ( sb_1__1__1_chany_top_out ) , .chany_top_in ( sb_1__1__2_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , @@ -78488,31 +80163,25 @@ cby_1__1_ cby_1__3_ ( .chany_bottom_in ( sb_1__1__1_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__2_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9102 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5963 ) , .Test_en_E_in ( Test_enWires[70] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9103 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9104 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5964 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5965 ) , .Test_en_W_out ( Test_enWires[68] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9105 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5966 ) , .prog_clk_0_W_in ( prog_clk_0_wires[12] ) , .prog_clk_0_S_out ( prog_clk_0_wires[13] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9106 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9107 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9108 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9109 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9110 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9111 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9112 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9113 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9114 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9115 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9116 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9117 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9118 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9119 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9120 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9121 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9122 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5967 ) , + .prog_clk_2_N_in ( p3265 ) , .prog_clk_2_S_in ( p2200 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5968 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5969 ) , + .prog_clk_3_S_in ( p2350 ) , .prog_clk_3_N_in ( p3240 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5970 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5971 ) , .clk_2_N_in ( p3139 ) , + .clk_2_S_in ( p153 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5972 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5973 ) , .clk_3_S_in ( p2061 ) , + .clk_3_N_in ( p106 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5974 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5975 ) ) ; cby_1__1_ cby_1__4_ ( .chany_bottom_in ( sb_1__1__2_chany_top_out ) , .chany_top_in ( sb_1__1__3_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , @@ -78535,31 +80204,28 @@ cby_1__1_ cby_1__4_ ( .chany_bottom_in ( sb_1__1__2_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__3_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9123 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5976 ) , .Test_en_E_in ( Test_enWires[92] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9124 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9125 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5977 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5978 ) , .Test_en_W_out ( Test_enWires[90] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9126 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5979 ) , .prog_clk_0_W_in ( prog_clk_0_wires[17] ) , .prog_clk_0_S_out ( prog_clk_0_wires[18] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9127 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5980 ) , .prog_clk_2_N_in ( prog_clk_2_wires[10] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9128 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5981 ) , .prog_clk_2_S_out ( prog_clk_2_wires[11] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9129 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9130 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9131 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9132 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9133 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5982 ) , + .prog_clk_3_S_in ( p1632 ) , .prog_clk_3_N_in ( p908 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5983 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5984 ) , .clk_2_N_in ( clk_2_wires[10] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9134 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5985 ) , .clk_2_S_out ( clk_2_wires[11] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9135 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9136 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9137 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9139 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5986 ) , .clk_3_S_in ( p1632 ) , + .clk_3_N_in ( p476 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5987 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5988 ) ) ; cby_1__1_ cby_1__5_ ( .chany_bottom_in ( sb_1__1__3_chany_top_out ) , .chany_top_in ( sb_1__1__4_chany_bottom_out ) , .ccff_head ( grid_clb_4_ccff_tail ) , @@ -78582,31 +80248,28 @@ cby_1__1_ cby_1__5_ ( .chany_bottom_in ( sb_1__1__3_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__4_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9140 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_5989 ) , .Test_en_E_in ( Test_enWires[114] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9141 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9142 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_5990 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5991 ) , .Test_en_W_out ( Test_enWires[112] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9143 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_5992 ) , .prog_clk_0_W_in ( prog_clk_0_wires[22] ) , .prog_clk_0_S_out ( prog_clk_0_wires[23] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9144 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9145 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_5993 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5994 ) , .prog_clk_2_S_in ( prog_clk_2_wires[8] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9146 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9147 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9148 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9149 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9150 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9151 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5995 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( p2125 ) , + .prog_clk_3_N_in ( p1073 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5996 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5997 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5998 ) , .clk_2_S_in ( clk_2_wires[8] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9152 ) , - .clk_2_N_out ( clk_2_wires[9] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9153 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9154 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9155 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9156 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5999 ) , + .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p2125 ) , + .clk_3_N_in ( p630 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6000 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6001 ) ) ; cby_1__1_ cby_1__6_ ( .chany_bottom_in ( sb_1__1__4_chany_top_out ) , .chany_top_in ( sb_1__1__5_chany_bottom_out ) , .ccff_head ( grid_clb_5_ccff_tail ) , @@ -78629,31 +80292,25 @@ cby_1__1_ cby_1__6_ ( .chany_bottom_in ( sb_1__1__4_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__5_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9157 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6002 ) , .Test_en_E_in ( Test_enWires[136] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9158 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9159 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6003 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6004 ) , .Test_en_W_out ( Test_enWires[134] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9160 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6005 ) , .prog_clk_0_W_in ( prog_clk_0_wires[27] ) , .prog_clk_0_S_out ( prog_clk_0_wires[28] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9161 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9162 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9163 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9164 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9165 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9166 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9167 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9168 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9169 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9170 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9171 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9172 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9173 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9174 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9175 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9177 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6006 ) , + .prog_clk_2_N_in ( p3388 ) , .prog_clk_2_S_in ( p2484 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6007 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6008 ) , + .prog_clk_3_S_in ( p2610 ) , .prog_clk_3_N_in ( p3354 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6009 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6010 ) , .clk_2_N_in ( p2288 ) , + .clk_2_S_in ( p897 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6011 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6012 ) , .clk_3_S_in ( p2164 ) , + .clk_3_N_in ( p862 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6013 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6014 ) ) ; cby_1__1_ cby_1__7_ ( .chany_bottom_in ( sb_1__1__5_chany_top_out ) , .chany_top_in ( sb_1__1__6_chany_bottom_out ) , .ccff_head ( grid_clb_6_ccff_tail ) , @@ -78676,31 +80333,25 @@ cby_1__1_ cby_1__7_ ( .chany_bottom_in ( sb_1__1__5_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__6_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9178 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6015 ) , .Test_en_E_in ( Test_enWires[158] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9179 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9180 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6016 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6017 ) , .Test_en_W_out ( Test_enWires[156] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9181 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6018 ) , .prog_clk_0_W_in ( prog_clk_0_wires[32] ) , .prog_clk_0_S_out ( prog_clk_0_wires[33] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9182 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9183 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9184 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9185 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9186 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9187 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9188 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9189 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9190 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9191 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9192 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9193 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9194 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9195 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9196 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9197 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9198 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6019 ) , + .prog_clk_2_N_in ( p1681 ) , .prog_clk_2_S_in ( p1945 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6020 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6021 ) , + .prog_clk_3_S_in ( p2120 ) , .prog_clk_3_N_in ( p3187 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6022 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6023 ) , .clk_2_N_in ( p3216 ) , + .clk_2_S_in ( p566 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6024 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6025 ) , .clk_3_S_in ( p1820 ) , + .clk_3_N_in ( p1003 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6026 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6027 ) ) ; cby_1__1_ cby_1__8_ ( .chany_bottom_in ( sb_1__1__6_chany_top_out ) , .chany_top_in ( sb_1__1__7_chany_bottom_out ) , .ccff_head ( grid_clb_7_ccff_tail ) , @@ -78723,31 +80374,28 @@ cby_1__1_ cby_1__8_ ( .chany_bottom_in ( sb_1__1__6_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__7_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9199 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6028 ) , .Test_en_E_in ( Test_enWires[180] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9200 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9201 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6029 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6030 ) , .Test_en_W_out ( Test_enWires[178] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9202 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6031 ) , .prog_clk_0_W_in ( prog_clk_0_wires[37] ) , .prog_clk_0_S_out ( prog_clk_0_wires[38] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9203 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6032 ) , .prog_clk_2_N_in ( prog_clk_2_wires[17] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9204 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6033 ) , .prog_clk_2_S_out ( prog_clk_2_wires[18] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9205 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9206 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9207 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9208 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9209 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6034 ) , + .prog_clk_3_S_in ( p1503 ) , .prog_clk_3_N_in ( p27 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6035 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6036 ) , .clk_2_N_in ( clk_2_wires[17] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9210 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6037 ) , .clk_2_S_out ( clk_2_wires[18] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9211 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9212 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9213 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9215 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6038 ) , .clk_3_S_in ( p1635 ) , + .clk_3_N_in ( p814 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6039 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6040 ) ) ; cby_1__1_ cby_1__9_ ( .chany_bottom_in ( sb_1__1__7_chany_top_out ) , .chany_top_in ( sb_1__1__8_chany_bottom_out ) , .ccff_head ( grid_clb_8_ccff_tail ) , @@ -78770,31 +80418,28 @@ cby_1__1_ cby_1__9_ ( .chany_bottom_in ( sb_1__1__7_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__8_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9216 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6041 ) , .Test_en_E_in ( Test_enWires[202] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9217 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9218 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6042 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6043 ) , .Test_en_W_out ( Test_enWires[200] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9219 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6044 ) , .prog_clk_0_W_in ( prog_clk_0_wires[42] ) , .prog_clk_0_S_out ( prog_clk_0_wires[43] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9220 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9221 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6045 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6046 ) , .prog_clk_2_S_in ( prog_clk_2_wires[15] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9222 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9223 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9224 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9225 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9226 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9227 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6047 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , .prog_clk_3_S_in ( p1590 ) , + .prog_clk_3_N_in ( p1170 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6048 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6049 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6050 ) , .clk_2_S_in ( clk_2_wires[15] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9228 ) , - .clk_2_N_out ( clk_2_wires[16] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9229 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9230 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9231 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9232 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6051 ) , + .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p2158 ) , + .clk_3_N_in ( p586 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6052 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6053 ) ) ; cby_1__1_ cby_1__10_ ( .chany_bottom_in ( sb_1__1__8_chany_top_out ) , .chany_top_in ( sb_1__1__9_chany_bottom_out ) , .ccff_head ( grid_clb_9_ccff_tail ) , @@ -78817,31 +80462,25 @@ cby_1__1_ cby_1__10_ ( .chany_bottom_in ( sb_1__1__8_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__9_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9233 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6054 ) , .Test_en_E_in ( Test_enWires[224] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9234 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9235 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6055 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6056 ) , .Test_en_W_out ( Test_enWires[222] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9236 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6057 ) , .prog_clk_0_W_in ( prog_clk_0_wires[47] ) , .prog_clk_0_S_out ( prog_clk_0_wires[48] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9237 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9238 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9239 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9240 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9241 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9242 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9243 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9244 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9245 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9246 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9247 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9248 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9249 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9250 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9251 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9252 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9253 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6058 ) , + .prog_clk_2_N_in ( p2704 ) , .prog_clk_2_S_in ( p3081 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6059 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6060 ) , + .prog_clk_3_S_in ( p3149 ) , .prog_clk_3_N_in ( p3076 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6061 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6062 ) , .clk_2_N_in ( p3099 ) , + .clk_2_S_in ( p229 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6063 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6064 ) , .clk_3_S_in ( p1579 ) , + .clk_3_N_in ( p813 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6065 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6066 ) ) ; cby_1__1_ cby_1__11_ ( .chany_bottom_in ( sb_1__1__9_chany_top_out ) , .chany_top_in ( sb_1__1__10_chany_bottom_out ) , .ccff_head ( grid_clb_10_ccff_tail ) , @@ -78864,31 +80503,28 @@ cby_1__1_ cby_1__11_ ( .chany_bottom_in ( sb_1__1__9_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__10_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9254 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6067 ) , .Test_en_E_in ( Test_enWires[246] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9255 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9256 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6068 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6069 ) , .Test_en_W_out ( Test_enWires[244] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9257 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6070 ) , .prog_clk_0_W_in ( prog_clk_0_wires[52] ) , .prog_clk_0_S_out ( prog_clk_0_wires[53] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9258 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9259 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6071 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6072 ) , .prog_clk_2_S_in ( prog_clk_2_wires[22] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9260 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9261 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9262 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9263 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9264 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9265 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6073 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , .prog_clk_3_S_in ( p1858 ) , + .prog_clk_3_N_in ( p708 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6074 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6075 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6076 ) , .clk_2_S_in ( clk_2_wires[22] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9266 ) , - .clk_2_N_out ( clk_2_wires[23] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9267 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9268 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9270 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6077 ) , + .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1390 ) , + .clk_3_N_in ( p353 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6078 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6079 ) ) ; cby_1__1_ cby_1__12_ ( .chany_bottom_in ( sb_1__1__10_chany_top_out ) , .chany_top_in ( sb_1__12__0_chany_bottom_out ) , .ccff_head ( grid_clb_11_ccff_tail ) , @@ -78911,31 +80547,25 @@ cby_1__1_ cby_1__12_ ( .chany_bottom_in ( sb_1__1__10_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__11_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9271 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6080 ) , .Test_en_E_in ( Test_enWires[268] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9272 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9273 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6081 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6082 ) , .Test_en_W_out ( Test_enWires[266] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9274 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6083 ) , .prog_clk_0_W_in ( prog_clk_0_wires[57] ) , .prog_clk_0_S_out ( prog_clk_0_wires[58] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9275 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9276 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9277 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9278 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9279 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9280 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9281 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9282 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9283 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9284 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9285 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9286 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9287 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9288 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9290 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , .prog_clk_2_N_in ( p2040 ) , + .prog_clk_2_S_in ( p3242 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6084 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6085 ) , + .prog_clk_3_S_in ( p3266 ) , .prog_clk_3_N_in ( p2453 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6086 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6087 ) , .clk_2_N_in ( p2535 ) , + .clk_2_S_in ( p672 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6088 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6089 ) , .clk_3_S_in ( p2404 ) , + .clk_3_N_in ( p202 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6090 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6091 ) ) ; cby_1__1_ cby_2__1_ ( .chany_bottom_in ( sb_1__0__1_chany_top_out ) , .chany_top_in ( sb_1__1__11_chany_bottom_out ) , .ccff_head ( grid_clb_12_ccff_tail ) , @@ -78958,31 +80588,25 @@ cby_1__1_ cby_2__1_ ( .chany_bottom_in ( sb_1__0__1_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__12_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9291 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6092 ) , .Test_en_E_in ( Test_enWires[28] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9292 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9293 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6093 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6094 ) , .Test_en_W_out ( Test_enWires[25] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9294 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6095 ) , .prog_clk_0_W_in ( prog_clk_0_wires[64] ) , .prog_clk_0_S_out ( prog_clk_0_wires[65] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9295 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9296 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9297 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9298 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9299 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9300 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9301 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9302 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9303 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9304 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9305 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9306 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9307 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9308 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9309 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9310 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9311 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6096 ) , + .prog_clk_2_N_in ( p2595 ) , .prog_clk_2_S_in ( p2956 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6097 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6098 ) , + .prog_clk_3_S_in ( p3054 ) , .prog_clk_3_N_in ( p2967 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6099 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6100 ) , .clk_2_N_in ( p3001 ) , + .clk_2_S_in ( p1 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6101 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6102 ) , .clk_3_S_in ( p1859 ) , + .clk_3_N_in ( p1230 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6103 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6104 ) ) ; cby_1__1_ cby_2__2_ ( .chany_bottom_in ( sb_1__1__11_chany_top_out ) , .chany_top_in ( sb_1__1__12_chany_bottom_out ) , .ccff_head ( grid_clb_13_ccff_tail ) , @@ -79005,31 +80629,25 @@ cby_1__1_ cby_2__2_ ( .chany_bottom_in ( sb_1__1__11_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__13_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9312 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6105 ) , .Test_en_E_in ( Test_enWires[50] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9313 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9314 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6106 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6107 ) , .Test_en_W_out ( Test_enWires[47] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9315 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6108 ) , .prog_clk_0_W_in ( prog_clk_0_wires[67] ) , .prog_clk_0_S_out ( prog_clk_0_wires[68] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9316 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9317 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9318 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9319 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9320 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9321 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9322 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9323 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9324 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9325 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9326 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9327 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9328 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9329 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9330 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9331 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9332 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6109 ) , + .prog_clk_2_N_in ( p2572 ) , .prog_clk_2_S_in ( p2490 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6110 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6111 ) , + .prog_clk_3_S_in ( p2524 ) , .prog_clk_3_N_in ( p3154 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6112 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6113 ) , .clk_2_N_in ( p3232 ) , + .clk_2_S_in ( p824 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6114 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6115 ) , .clk_3_S_in ( p2289 ) , + .clk_3_N_in ( p167 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6116 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6117 ) ) ; cby_1__1_ cby_2__3_ ( .chany_bottom_in ( sb_1__1__12_chany_top_out ) , .chany_top_in ( sb_1__1__13_chany_bottom_out ) , .ccff_head ( grid_clb_14_ccff_tail ) , @@ -79052,30 +80670,27 @@ cby_1__1_ cby_2__3_ ( .chany_bottom_in ( sb_1__1__12_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__14_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9333 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6118 ) , .Test_en_E_in ( Test_enWires[72] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9334 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9335 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6119 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6120 ) , .Test_en_W_out ( Test_enWires[69] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9336 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6121 ) , .prog_clk_0_W_in ( prog_clk_0_wires[70] ) , .prog_clk_0_S_out ( prog_clk_0_wires[71] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9337 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9338 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9339 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9340 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9341 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9342 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6122 ) , + .prog_clk_2_N_in ( p1846 ) , .prog_clk_2_S_in ( p591 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6123 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6124 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6125 ) , .prog_clk_3_N_in ( prog_clk_3_wires[68] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9343 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9344 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9345 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9346 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9347 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9348 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6126 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( p1846 ) , + .clk_2_S_in ( p1088 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6127 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6128 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6129 ) , .clk_3_N_in ( clk_3_wires[68] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9349 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6130 ) , .clk_3_S_out ( clk_3_wires[69] ) ) ; cby_1__1_ cby_2__4_ ( .chany_bottom_in ( sb_1__1__13_chany_top_out ) , .chany_top_in ( sb_1__1__14_chany_bottom_out ) , @@ -79099,30 +80714,27 @@ cby_1__1_ cby_2__4_ ( .chany_bottom_in ( sb_1__1__13_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__15_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9350 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6131 ) , .Test_en_E_in ( Test_enWires[94] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9351 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9352 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6132 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6133 ) , .Test_en_W_out ( Test_enWires[91] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9353 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6134 ) , .prog_clk_0_W_in ( prog_clk_0_wires[73] ) , .prog_clk_0_S_out ( prog_clk_0_wires[74] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9354 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9355 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9356 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9357 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9358 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9359 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6135 ) , + .prog_clk_2_N_in ( p1627 ) , .prog_clk_2_S_in ( p400 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6136 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6137 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6138 ) , .prog_clk_3_N_in ( prog_clk_3_wires[64] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9360 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9361 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9362 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9363 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9364 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9365 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6139 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( p1627 ) , + .clk_2_S_in ( p868 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6140 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6141 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6142 ) , .clk_3_N_in ( clk_3_wires[64] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9366 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6143 ) , .clk_3_S_out ( clk_3_wires[65] ) ) ; cby_1__1_ cby_2__5_ ( .chany_bottom_in ( sb_1__1__14_chany_top_out ) , .chany_top_in ( sb_1__1__15_chany_bottom_out ) , @@ -79146,30 +80758,27 @@ cby_1__1_ cby_2__5_ ( .chany_bottom_in ( sb_1__1__14_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__16_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9367 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6144 ) , .Test_en_E_in ( Test_enWires[116] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9368 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9369 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6145 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6146 ) , .Test_en_W_out ( Test_enWires[113] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9370 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6147 ) , .prog_clk_0_W_in ( prog_clk_0_wires[76] ) , .prog_clk_0_S_out ( prog_clk_0_wires[77] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9371 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9372 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9373 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9374 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9375 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9376 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6148 ) , + .prog_clk_2_N_in ( p2130 ) , .prog_clk_2_S_in ( p273 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6149 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6150 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6151 ) , .prog_clk_3_N_in ( prog_clk_3_wires[58] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9377 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9378 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9379 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9380 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9381 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9382 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6152 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( p2071 ) , + .clk_2_S_in ( p637 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6153 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6154 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6155 ) , .clk_3_N_in ( clk_3_wires[58] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9383 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6156 ) , .clk_3_S_out ( clk_3_wires[59] ) ) ; cby_1__1_ cby_2__6_ ( .chany_bottom_in ( sb_1__1__15_chany_top_out ) , .chany_top_in ( sb_1__1__16_chany_bottom_out ) , @@ -79193,30 +80802,27 @@ cby_1__1_ cby_2__6_ ( .chany_bottom_in ( sb_1__1__15_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__17_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9384 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6157 ) , .Test_en_E_in ( Test_enWires[138] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9385 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9386 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6158 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6159 ) , .Test_en_W_out ( Test_enWires[135] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9387 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6160 ) , .prog_clk_0_W_in ( prog_clk_0_wires[79] ) , .prog_clk_0_S_out ( prog_clk_0_wires[80] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9388 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9389 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9390 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9391 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9392 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9393 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6161 ) , + .prog_clk_2_N_in ( p2136 ) , .prog_clk_2_S_in ( p485 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6162 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6163 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6164 ) , .prog_clk_3_N_in ( prog_clk_3_wires[54] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9394 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9395 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9396 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9397 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9398 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9399 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6165 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( p2136 ) , + .clk_2_S_in ( p994 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6166 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6167 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6168 ) , .clk_3_N_in ( clk_3_wires[54] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9400 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6169 ) , .clk_3_S_out ( clk_3_wires[55] ) ) ; cby_1__1_ cby_2__7_ ( .chany_bottom_in ( sb_1__1__16_chany_top_out ) , .chany_top_in ( sb_1__1__17_chany_bottom_out ) , @@ -79240,31 +80846,28 @@ cby_1__1_ cby_2__7_ ( .chany_bottom_in ( sb_1__1__16_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__18_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9401 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6170 ) , .Test_en_E_in ( Test_enWires[160] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9402 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9403 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6171 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6172 ) , .Test_en_W_out ( Test_enWires[157] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9404 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6173 ) , .prog_clk_0_W_in ( prog_clk_0_wires[82] ) , .prog_clk_0_S_out ( prog_clk_0_wires[83] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9405 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9406 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9407 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9408 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9409 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6174 ) , + .prog_clk_2_N_in ( p2357 ) , .prog_clk_2_S_in ( p536 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6175 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6176 ) , .prog_clk_3_S_in ( prog_clk_3_wires[52] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9410 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6177 ) , .prog_clk_3_N_out ( prog_clk_3_wires[53] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9411 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9412 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9413 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9414 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9415 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6178 ) , .clk_2_N_in ( p2357 ) , + .clk_2_S_in ( p93 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6179 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6180 ) , .clk_3_S_in ( clk_3_wires[52] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9416 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6181 ) , .clk_3_N_out ( clk_3_wires[53] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9417 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6182 ) ) ; cby_1__1_ cby_2__8_ ( .chany_bottom_in ( sb_1__1__17_chany_top_out ) , .chany_top_in ( sb_1__1__18_chany_bottom_out ) , .ccff_head ( grid_clb_19_ccff_tail ) , @@ -79287,31 +80890,28 @@ cby_1__1_ cby_2__8_ ( .chany_bottom_in ( sb_1__1__17_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__19_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9418 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6183 ) , .Test_en_E_in ( Test_enWires[182] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9419 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9420 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6184 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6185 ) , .Test_en_W_out ( Test_enWires[179] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9421 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6186 ) , .prog_clk_0_W_in ( prog_clk_0_wires[85] ) , .prog_clk_0_S_out ( prog_clk_0_wires[86] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9422 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9423 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9424 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9425 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9426 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6187 ) , + .prog_clk_2_N_in ( p1869 ) , .prog_clk_2_S_in ( p250 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6188 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6189 ) , .prog_clk_3_S_in ( prog_clk_3_wires[56] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9427 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6190 ) , .prog_clk_3_N_out ( prog_clk_3_wires[57] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9428 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9429 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9430 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9431 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9432 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6191 ) , .clk_2_N_in ( p1869 ) , + .clk_2_S_in ( p880 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6192 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6193 ) , .clk_3_S_in ( clk_3_wires[56] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9433 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6194 ) , .clk_3_N_out ( clk_3_wires[57] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9434 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6195 ) ) ; cby_1__1_ cby_2__9_ ( .chany_bottom_in ( sb_1__1__18_chany_top_out ) , .chany_top_in ( sb_1__1__19_chany_bottom_out ) , .ccff_head ( grid_clb_20_ccff_tail ) , @@ -79334,31 +80934,28 @@ cby_1__1_ cby_2__9_ ( .chany_bottom_in ( sb_1__1__18_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__20_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9435 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6196 ) , .Test_en_E_in ( Test_enWires[204] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9436 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9437 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6197 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6198 ) , .Test_en_W_out ( Test_enWires[201] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9438 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6199 ) , .prog_clk_0_W_in ( prog_clk_0_wires[88] ) , .prog_clk_0_S_out ( prog_clk_0_wires[89] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9439 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9440 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9441 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9442 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9443 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6200 ) , + .prog_clk_2_N_in ( p1507 ) , .prog_clk_2_S_in ( p180 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6201 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6202 ) , .prog_clk_3_S_in ( prog_clk_3_wires[62] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9444 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6203 ) , .prog_clk_3_N_out ( prog_clk_3_wires[63] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9445 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9446 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9447 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9448 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9449 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6204 ) , .clk_2_N_in ( p1507 ) , + .clk_2_S_in ( p729 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6205 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6206 ) , .clk_3_S_in ( clk_3_wires[62] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9450 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6207 ) , .clk_3_N_out ( clk_3_wires[63] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9451 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6208 ) ) ; cby_1__1_ cby_2__10_ ( .chany_bottom_in ( sb_1__1__19_chany_top_out ) , .chany_top_in ( sb_1__1__20_chany_bottom_out ) , .ccff_head ( grid_clb_21_ccff_tail ) , @@ -79381,31 +80978,28 @@ cby_1__1_ cby_2__10_ ( .chany_bottom_in ( sb_1__1__19_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__21_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9452 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6209 ) , .Test_en_E_in ( Test_enWires[226] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9453 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9454 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6210 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6211 ) , .Test_en_W_out ( Test_enWires[223] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9455 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6212 ) , .prog_clk_0_W_in ( prog_clk_0_wires[91] ) , .prog_clk_0_S_out ( prog_clk_0_wires[92] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9456 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9457 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9458 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9459 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9460 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6213 ) , + .prog_clk_2_N_in ( p1399 ) , .prog_clk_2_S_in ( p323 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6214 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6215 ) , .prog_clk_3_S_in ( prog_clk_3_wires[66] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9461 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6216 ) , .prog_clk_3_N_out ( prog_clk_3_wires[67] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9462 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9463 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9464 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9465 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9466 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6217 ) , .clk_2_N_in ( p1399 ) , + .clk_2_S_in ( p774 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6218 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6219 ) , .clk_3_S_in ( clk_3_wires[66] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9467 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6220 ) , .clk_3_N_out ( clk_3_wires[67] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9468 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6221 ) ) ; cby_1__1_ cby_2__11_ ( .chany_bottom_in ( sb_1__1__20_chany_top_out ) , .chany_top_in ( sb_1__1__21_chany_bottom_out ) , .ccff_head ( grid_clb_22_ccff_tail ) , @@ -79428,31 +81022,25 @@ cby_1__1_ cby_2__11_ ( .chany_bottom_in ( sb_1__1__20_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__22_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9469 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6222 ) , .Test_en_E_in ( Test_enWires[248] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9470 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9471 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6223 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6224 ) , .Test_en_W_out ( Test_enWires[245] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9472 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6225 ) , .prog_clk_0_W_in ( prog_clk_0_wires[94] ) , .prog_clk_0_S_out ( prog_clk_0_wires[95] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9473 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9474 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9475 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9478 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9479 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9480 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9481 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9482 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9483 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9484 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9485 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9486 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9487 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9488 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9489 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6226 ) , + .prog_clk_2_N_in ( p3279 ) , .prog_clk_2_S_in ( p3262 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6227 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6228 ) , + .prog_clk_3_S_in ( p3270 ) , .prog_clk_3_N_in ( p3254 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6229 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6230 ) , .clk_2_N_in ( p2153 ) , + .clk_2_S_in ( p895 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6231 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6232 ) , .clk_3_S_in ( p2590 ) , + .clk_3_N_in ( p1186 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6233 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6234 ) ) ; cby_1__1_ cby_2__12_ ( .chany_bottom_in ( sb_1__1__21_chany_top_out ) , .chany_top_in ( sb_1__12__1_chany_bottom_out ) , .ccff_head ( grid_clb_23_ccff_tail ) , @@ -79475,31 +81063,25 @@ cby_1__1_ cby_2__12_ ( .chany_bottom_in ( sb_1__1__21_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__23_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9490 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6235 ) , .Test_en_E_in ( Test_enWires[270] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9491 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9492 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6236 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6237 ) , .Test_en_W_out ( Test_enWires[267] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9493 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6238 ) , .prog_clk_0_W_in ( prog_clk_0_wires[97] ) , .prog_clk_0_S_out ( prog_clk_0_wires[98] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9494 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9495 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9496 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9497 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9498 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9499 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9500 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9501 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9502 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9503 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9504 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9505 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9506 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9507 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9508 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9509 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , .prog_clk_2_N_in ( p1724 ) , + .prog_clk_2_S_in ( p2832 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6239 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6240 ) , + .prog_clk_3_S_in ( p2866 ) , .prog_clk_3_N_in ( p2965 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6241 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6242 ) , .clk_2_N_in ( p2994 ) , + .clk_2_S_in ( p555 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6243 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6244 ) , .clk_3_S_in ( p1288 ) , + .clk_3_N_in ( p1017 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6245 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6246 ) ) ; cby_1__1_ cby_3__1_ ( .chany_bottom_in ( sb_1__0__2_chany_top_out ) , .chany_top_in ( sb_1__1__22_chany_bottom_out ) , .ccff_head ( grid_clb_24_ccff_tail ) , @@ -79522,31 +81104,25 @@ cby_1__1_ cby_3__1_ ( .chany_bottom_in ( sb_1__0__2_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__24_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9510 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6247 ) , .Test_en_E_in ( Test_enWires[30] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9511 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9512 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6248 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6249 ) , .Test_en_W_out ( Test_enWires[27] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9513 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6250 ) , .prog_clk_0_W_in ( prog_clk_0_wires[102] ) , .prog_clk_0_S_out ( prog_clk_0_wires[103] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9514 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9515 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9516 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9517 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9518 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9519 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9520 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9521 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9522 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9523 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9524 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9525 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9526 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9527 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9528 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9529 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9530 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6251 ) , + .prog_clk_2_N_in ( p2328 ) , .prog_clk_2_S_in ( p3084 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6252 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6253 ) , + .prog_clk_3_S_in ( p3129 ) , .prog_clk_3_N_in ( p3159 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6254 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6255 ) , .clk_2_N_in ( p3231 ) , + .clk_2_S_in ( p1038 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6256 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6257 ) , .clk_3_S_in ( p1530 ) , + .clk_3_N_in ( p49 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6258 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6259 ) ) ; cby_1__1_ cby_3__2_ ( .chany_bottom_in ( sb_1__1__22_chany_top_out ) , .chany_top_in ( sb_1__1__23_chany_bottom_out ) , .ccff_head ( grid_clb_25_ccff_tail ) , @@ -79569,31 +81145,28 @@ cby_1__1_ cby_3__2_ ( .chany_bottom_in ( sb_1__1__22_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__25_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9531 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6260 ) , .Test_en_E_in ( Test_enWires[52] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9532 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9533 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6261 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6262 ) , .Test_en_W_out ( Test_enWires[49] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9534 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .prog_clk_0_W_in ( prog_clk_0_wires[105] ) , .prog_clk_0_S_out ( prog_clk_0_wires[106] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9535 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6264 ) , .prog_clk_2_N_in ( prog_clk_2_wires[29] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9536 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6265 ) , .prog_clk_2_S_out ( prog_clk_2_wires[30] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9537 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9538 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9539 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9540 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9541 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6266 ) , + .prog_clk_3_S_in ( p1845 ) , .prog_clk_3_N_in ( p944 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6267 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6268 ) , .clk_2_N_in ( clk_2_wires[29] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9542 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6269 ) , .clk_2_S_out ( clk_2_wires[30] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9543 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9544 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9545 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9546 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9547 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6270 ) , .clk_3_S_in ( p1845 ) , + .clk_3_N_in ( p173 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6271 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6272 ) ) ; cby_1__1_ cby_3__3_ ( .chany_bottom_in ( sb_1__1__23_chany_top_out ) , .chany_top_in ( sb_1__1__24_chany_bottom_out ) , .ccff_head ( grid_clb_26_ccff_tail ) , @@ -79616,31 +81189,25 @@ cby_1__1_ cby_3__3_ ( .chany_bottom_in ( sb_1__1__23_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__26_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9548 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6273 ) , .Test_en_E_in ( Test_enWires[74] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9549 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9550 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6274 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6275 ) , .Test_en_W_out ( Test_enWires[71] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9551 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6276 ) , .prog_clk_0_W_in ( prog_clk_0_wires[108] ) , .prog_clk_0_S_out ( prog_clk_0_wires[109] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9552 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9553 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9554 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9555 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9556 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9557 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9558 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9559 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9560 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9561 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9562 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9563 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9564 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9565 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9566 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9567 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9568 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6277 ) , + .prog_clk_2_N_in ( p2716 ) , .prog_clk_2_S_in ( p2449 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6278 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6279 ) , + .prog_clk_3_S_in ( p2627 ) , .prog_clk_3_N_in ( p2662 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6280 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6281 ) , .clk_2_N_in ( p2374 ) , + .clk_2_S_in ( p373 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6282 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6283 ) , .clk_3_S_in ( p1664 ) , + .clk_3_N_in ( p1150 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6284 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6285 ) ) ; cby_1__1_ cby_3__4_ ( .chany_bottom_in ( sb_1__1__24_chany_top_out ) , .chany_top_in ( sb_1__1__25_chany_bottom_out ) , .ccff_head ( grid_clb_27_ccff_tail ) , @@ -79663,31 +81230,28 @@ cby_1__1_ cby_3__4_ ( .chany_bottom_in ( sb_1__1__24_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__27_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9569 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6286 ) , .Test_en_E_in ( Test_enWires[96] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9570 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9571 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6287 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6288 ) , .Test_en_W_out ( Test_enWires[93] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9572 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6289 ) , .prog_clk_0_W_in ( prog_clk_0_wires[111] ) , .prog_clk_0_S_out ( prog_clk_0_wires[112] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9573 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6290 ) , .prog_clk_2_N_in ( prog_clk_2_wires[40] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9574 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6291 ) , .prog_clk_2_S_out ( prog_clk_2_wires[41] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9575 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9576 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9577 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9578 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9579 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6292 ) , + .prog_clk_3_S_in ( p1675 ) , .prog_clk_3_N_in ( p742 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6293 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6294 ) , .clk_2_N_in ( clk_2_wires[40] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9580 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_2_S_out ( clk_2_wires[41] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9581 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9582 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9583 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9584 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9585 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6296 ) , .clk_3_S_in ( p2053 ) , + .clk_3_N_in ( p360 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6297 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6298 ) ) ; cby_1__1_ cby_3__5_ ( .chany_bottom_in ( sb_1__1__25_chany_top_out ) , .chany_top_in ( sb_1__1__26_chany_bottom_out ) , .ccff_head ( grid_clb_28_ccff_tail ) , @@ -79710,31 +81274,28 @@ cby_1__1_ cby_3__5_ ( .chany_bottom_in ( sb_1__1__25_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__28_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9586 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6299 ) , .Test_en_E_in ( Test_enWires[118] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9587 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9588 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6300 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6301 ) , .Test_en_W_out ( Test_enWires[115] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9589 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6302 ) , .prog_clk_0_W_in ( prog_clk_0_wires[114] ) , .prog_clk_0_S_out ( prog_clk_0_wires[115] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9590 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9591 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6303 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6304 ) , .prog_clk_2_S_in ( prog_clk_2_wires[38] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9592 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9593 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9594 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9595 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9596 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9597 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6305 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , .prog_clk_3_S_in ( p1356 ) , + .prog_clk_3_N_in ( p493 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6306 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6307 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6308 ) , .clk_2_S_in ( clk_2_wires[38] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9598 ) , - .clk_2_N_out ( clk_2_wires[39] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9599 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9600 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9601 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9602 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6309 ) , + .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p2369 ) , + .clk_3_N_in ( p1099 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6310 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6311 ) ) ; cby_1__1_ cby_3__6_ ( .chany_bottom_in ( sb_1__1__26_chany_top_out ) , .chany_top_in ( sb_1__1__27_chany_bottom_out ) , .ccff_head ( grid_clb_29_ccff_tail ) , @@ -79757,31 +81318,25 @@ cby_1__1_ cby_3__6_ ( .chany_bottom_in ( sb_1__1__26_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__29_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9603 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6312 ) , .Test_en_E_in ( Test_enWires[140] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9604 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9605 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6313 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6314 ) , .Test_en_W_out ( Test_enWires[137] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9606 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6315 ) , .prog_clk_0_W_in ( prog_clk_0_wires[117] ) , .prog_clk_0_S_out ( prog_clk_0_wires[118] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9607 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9608 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9609 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9610 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9611 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9612 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9613 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9614 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9615 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9616 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9617 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9618 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9619 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9620 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9621 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9622 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9623 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6316 ) , + .prog_clk_2_N_in ( p3414 ) , .prog_clk_2_S_in ( p2813 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6317 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6318 ) , + .prog_clk_3_S_in ( p2871 ) , .prog_clk_3_N_in ( p3397 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6319 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6320 ) , .clk_2_N_in ( p3288 ) , + .clk_2_S_in ( p721 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6321 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6322 ) , .clk_3_S_in ( p1817 ) , + .clk_3_N_in ( p368 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6323 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6324 ) ) ; cby_1__1_ cby_3__7_ ( .chany_bottom_in ( sb_1__1__27_chany_top_out ) , .chany_top_in ( sb_1__1__28_chany_bottom_out ) , .ccff_head ( grid_clb_30_ccff_tail ) , @@ -79804,31 +81359,25 @@ cby_1__1_ cby_3__7_ ( .chany_bottom_in ( sb_1__1__27_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__30_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9624 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6325 ) , .Test_en_E_in ( Test_enWires[162] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9625 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9626 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6326 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6327 ) , .Test_en_W_out ( Test_enWires[159] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9627 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6328 ) , .prog_clk_0_W_in ( prog_clk_0_wires[120] ) , .prog_clk_0_S_out ( prog_clk_0_wires[121] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9628 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9629 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9630 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9631 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9632 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9633 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9634 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9635 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9636 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9637 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9638 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9639 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9640 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9641 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9642 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9643 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9644 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6329 ) , + .prog_clk_2_N_in ( p2890 ) , .prog_clk_2_S_in ( p2441 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6330 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6331 ) , + .prog_clk_3_S_in ( p2619 ) , .prog_clk_3_N_in ( p3079 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6332 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6333 ) , .clk_2_N_in ( p3137 ) , + .clk_2_S_in ( p1072 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6334 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6335 ) , .clk_3_S_in ( p1597 ) , + .clk_3_N_in ( p68 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6336 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6337 ) ) ; cby_1__1_ cby_3__8_ ( .chany_bottom_in ( sb_1__1__28_chany_top_out ) , .chany_top_in ( sb_1__1__29_chany_bottom_out ) , .ccff_head ( grid_clb_31_ccff_tail ) , @@ -79851,31 +81400,28 @@ cby_1__1_ cby_3__8_ ( .chany_bottom_in ( sb_1__1__28_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__31_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9645 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6338 ) , .Test_en_E_in ( Test_enWires[184] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9646 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9647 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6339 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6340 ) , .Test_en_W_out ( Test_enWires[181] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9648 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6341 ) , .prog_clk_0_W_in ( prog_clk_0_wires[123] ) , .prog_clk_0_S_out ( prog_clk_0_wires[124] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9649 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6342 ) , .prog_clk_2_N_in ( prog_clk_2_wires[53] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9650 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6343 ) , .prog_clk_2_S_out ( prog_clk_2_wires[54] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9651 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9652 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9653 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9654 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9655 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6344 ) , + .prog_clk_3_S_in ( p1860 ) , .prog_clk_3_N_in ( p554 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6345 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6346 ) , .clk_2_N_in ( clk_2_wires[53] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9656 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6347 ) , .clk_2_S_out ( clk_2_wires[54] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9657 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9658 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9659 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9660 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9661 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6348 ) , .clk_3_S_in ( p2597 ) , + .clk_3_N_in ( p406 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6349 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6350 ) ) ; cby_1__1_ cby_3__9_ ( .chany_bottom_in ( sb_1__1__29_chany_top_out ) , .chany_top_in ( sb_1__1__30_chany_bottom_out ) , .ccff_head ( grid_clb_32_ccff_tail ) , @@ -79898,31 +81444,28 @@ cby_1__1_ cby_3__9_ ( .chany_bottom_in ( sb_1__1__29_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__32_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9662 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6351 ) , .Test_en_E_in ( Test_enWires[206] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9663 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9664 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6352 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6353 ) , .Test_en_W_out ( Test_enWires[203] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9665 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6354 ) , .prog_clk_0_W_in ( prog_clk_0_wires[126] ) , .prog_clk_0_S_out ( prog_clk_0_wires[127] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9666 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9667 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6355 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6356 ) , .prog_clk_2_S_in ( prog_clk_2_wires[51] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9668 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9669 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9670 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9671 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9672 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9673 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6357 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , .prog_clk_3_S_in ( p2015 ) , + .prog_clk_3_N_in ( p750 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6358 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6359 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6360 ) , .clk_2_S_in ( clk_2_wires[51] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9674 ) , - .clk_2_N_out ( clk_2_wires[52] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9675 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9676 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9677 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9678 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6361 ) , + .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p2608 ) , + .clk_3_N_in ( p653 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6362 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6363 ) ) ; cby_1__1_ cby_3__10_ ( .chany_bottom_in ( sb_1__1__30_chany_top_out ) , .chany_top_in ( sb_1__1__31_chany_bottom_out ) , .ccff_head ( grid_clb_33_ccff_tail ) , @@ -79945,31 +81488,25 @@ cby_1__1_ cby_3__10_ ( .chany_bottom_in ( sb_1__1__30_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__33_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9679 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6364 ) , .Test_en_E_in ( Test_enWires[228] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9680 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9681 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6365 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6366 ) , .Test_en_W_out ( Test_enWires[225] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9682 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6367 ) , .prog_clk_0_W_in ( prog_clk_0_wires[129] ) , .prog_clk_0_S_out ( prog_clk_0_wires[130] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9683 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9684 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9685 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9686 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9687 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9688 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9689 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9690 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9691 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9692 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9693 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9694 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9695 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9696 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9697 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9698 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9699 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6368 ) , + .prog_clk_2_N_in ( p2709 ) , .prog_clk_2_S_in ( p2437 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6369 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6370 ) , + .prog_clk_3_S_in ( p2616 ) , .prog_clk_3_N_in ( p3303 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6371 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6372 ) , .clk_2_N_in ( p3343 ) , + .clk_2_S_in ( p90 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6373 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6374 ) , .clk_3_S_in ( p1481 ) , + .clk_3_N_in ( p941 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6375 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6376 ) ) ; cby_1__1_ cby_3__11_ ( .chany_bottom_in ( sb_1__1__31_chany_top_out ) , .chany_top_in ( sb_1__1__32_chany_bottom_out ) , .ccff_head ( grid_clb_34_ccff_tail ) , @@ -79992,31 +81529,28 @@ cby_1__1_ cby_3__11_ ( .chany_bottom_in ( sb_1__1__31_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__34_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9700 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6377 ) , .Test_en_E_in ( Test_enWires[250] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9701 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9702 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6378 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6379 ) , .Test_en_W_out ( Test_enWires[247] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9703 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6380 ) , .prog_clk_0_W_in ( prog_clk_0_wires[132] ) , .prog_clk_0_S_out ( prog_clk_0_wires[133] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9705 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6381 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6382 ) , .prog_clk_2_S_in ( prog_clk_2_wires[64] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9706 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9707 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9708 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9709 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9710 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9711 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6383 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , .prog_clk_3_S_in ( p1485 ) , + .prog_clk_3_N_in ( p1034 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6384 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6385 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6386 ) , .clk_2_S_in ( clk_2_wires[64] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9712 ) , - .clk_2_N_out ( clk_2_wires[65] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9713 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9714 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9715 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9716 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6387 ) , + .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p1795 ) , + .clk_3_N_in ( p254 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6388 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6389 ) ) ; cby_1__1_ cby_3__12_ ( .chany_bottom_in ( sb_1__1__32_chany_top_out ) , .chany_top_in ( sb_1__12__2_chany_bottom_out ) , .ccff_head ( grid_clb_35_ccff_tail ) , @@ -80039,31 +81573,25 @@ cby_1__1_ cby_3__12_ ( .chany_bottom_in ( sb_1__1__32_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__35_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9717 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6390 ) , .Test_en_E_in ( Test_enWires[272] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9718 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9719 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6391 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6392 ) , .Test_en_W_out ( Test_enWires[269] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9720 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6393 ) , .prog_clk_0_W_in ( prog_clk_0_wires[135] ) , .prog_clk_0_S_out ( prog_clk_0_wires[136] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9721 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9722 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9723 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9724 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9725 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9726 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9727 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9728 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9729 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9730 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9731 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9732 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9733 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9734 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9735 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9736 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , .prog_clk_2_N_in ( p2575 ) , + .prog_clk_2_S_in ( p3321 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6394 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6395 ) , + .prog_clk_3_S_in ( p3330 ) , .prog_clk_3_N_in ( p3152 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6396 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6397 ) , .clk_2_N_in ( p3211 ) , + .clk_2_S_in ( p516 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6398 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6399 ) , .clk_3_S_in ( p2539 ) , + .clk_3_N_in ( p1974 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6400 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6401 ) ) ; cby_1__1_ cby_4__1_ ( .chany_bottom_in ( sb_1__0__3_chany_top_out ) , .chany_top_in ( sb_1__1__33_chany_bottom_out ) , .ccff_head ( grid_clb_36_ccff_tail ) , @@ -80086,31 +81614,25 @@ cby_1__1_ cby_4__1_ ( .chany_bottom_in ( sb_1__0__3_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__36_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9737 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6402 ) , .Test_en_E_in ( Test_enWires[32] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9738 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9739 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6403 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6404 ) , .Test_en_W_out ( Test_enWires[29] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9740 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6405 ) , .prog_clk_0_W_in ( prog_clk_0_wires[140] ) , .prog_clk_0_S_out ( prog_clk_0_wires[141] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9741 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9742 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9743 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9744 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9745 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9746 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9747 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9748 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9749 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9750 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9751 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9752 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9753 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9754 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9755 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9756 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9757 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6406 ) , + .prog_clk_2_N_in ( p2604 ) , .prog_clk_2_S_in ( p1909 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6407 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6408 ) , + .prog_clk_3_S_in ( p2157 ) , .prog_clk_3_N_in ( p3179 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6409 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6410 ) , .clk_2_N_in ( p3235 ) , + .clk_2_S_in ( p60 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6411 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6412 ) , .clk_3_S_in ( p1775 ) , + .clk_3_N_in ( p1270 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6413 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6414 ) ) ; cby_1__1_ cby_4__2_ ( .chany_bottom_in ( sb_1__1__33_chany_top_out ) , .chany_top_in ( sb_1__1__34_chany_bottom_out ) , .ccff_head ( grid_clb_37_ccff_tail ) , @@ -80133,31 +81655,25 @@ cby_1__1_ cby_4__2_ ( .chany_bottom_in ( sb_1__1__33_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__37_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9758 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6415 ) , .Test_en_E_in ( Test_enWires[54] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9759 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9760 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6416 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6417 ) , .Test_en_W_out ( Test_enWires[51] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9761 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6418 ) , .prog_clk_0_W_in ( prog_clk_0_wires[143] ) , .prog_clk_0_S_out ( prog_clk_0_wires[144] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9762 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9763 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9764 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9765 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9766 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9767 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9768 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9769 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9770 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9771 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9772 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9773 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9774 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9775 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9776 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9777 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9778 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6419 ) , + .prog_clk_2_N_in ( p3338 ) , .prog_clk_2_S_in ( p3064 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6420 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6421 ) , + .prog_clk_3_S_in ( p3117 ) , .prog_clk_3_N_in ( p3305 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6422 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_2_N_in ( p3283 ) , + .clk_2_S_in ( p727 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6424 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6425 ) , .clk_3_S_in ( p2100 ) , + .clk_3_N_in ( p0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6426 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6427 ) ) ; cby_1__1_ cby_4__3_ ( .chany_bottom_in ( sb_1__1__34_chany_top_out ) , .chany_top_in ( sb_1__1__35_chany_bottom_out ) , .ccff_head ( grid_clb_38_ccff_tail ) , @@ -80180,30 +81696,27 @@ cby_1__1_ cby_4__3_ ( .chany_bottom_in ( sb_1__1__34_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__38_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9779 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6428 ) , .Test_en_E_in ( Test_enWires[76] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9780 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9781 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6429 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6430 ) , .Test_en_W_out ( Test_enWires[73] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9782 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6431 ) , .prog_clk_0_W_in ( prog_clk_0_wires[146] ) , .prog_clk_0_S_out ( prog_clk_0_wires[147] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9783 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9784 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9785 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9786 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9787 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9788 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6432 ) , + .prog_clk_2_N_in ( p1865 ) , .prog_clk_2_S_in ( p1078 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6433 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6434 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6435 ) , .prog_clk_3_N_in ( prog_clk_3_wires[24] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9789 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9790 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9791 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9792 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9793 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9794 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6436 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( p1865 ) , + .clk_2_S_in ( p378 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6437 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6438 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6439 ) , .clk_3_N_in ( clk_3_wires[24] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9795 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6440 ) , .clk_3_S_out ( clk_3_wires[25] ) ) ; cby_1__1_ cby_4__4_ ( .chany_bottom_in ( sb_1__1__35_chany_top_out ) , .chany_top_in ( sb_1__1__36_chany_bottom_out ) , @@ -80227,30 +81740,27 @@ cby_1__1_ cby_4__4_ ( .chany_bottom_in ( sb_1__1__35_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__39_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9796 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6441 ) , .Test_en_E_in ( Test_enWires[98] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9797 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9798 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6442 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6443 ) , .Test_en_W_out ( Test_enWires[95] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9799 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6444 ) , .prog_clk_0_W_in ( prog_clk_0_wires[149] ) , .prog_clk_0_S_out ( prog_clk_0_wires[150] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9800 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9801 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9802 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9803 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9804 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9805 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6445 ) , + .prog_clk_2_N_in ( p1768 ) , .prog_clk_2_S_in ( p65 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6446 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6447 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6448 ) , .prog_clk_3_N_in ( prog_clk_3_wires[20] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9806 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9807 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9808 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9809 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9810 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9811 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6449 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( p1768 ) , + .clk_2_S_in ( p374 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6450 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6451 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6452 ) , .clk_3_N_in ( clk_3_wires[20] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9812 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_3_S_out ( clk_3_wires[21] ) ) ; cby_1__1_ cby_4__5_ ( .chany_bottom_in ( sb_1__1__36_chany_top_out ) , .chany_top_in ( sb_1__1__37_chany_bottom_out ) , @@ -80274,30 +81784,27 @@ cby_1__1_ cby_4__5_ ( .chany_bottom_in ( sb_1__1__36_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__40_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9813 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6454 ) , .Test_en_E_in ( Test_enWires[120] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9814 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9815 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6455 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6456 ) , .Test_en_W_out ( Test_enWires[117] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9816 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6457 ) , .prog_clk_0_W_in ( prog_clk_0_wires[152] ) , .prog_clk_0_S_out ( prog_clk_0_wires[153] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9817 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9818 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9819 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9820 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9821 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9822 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6458 ) , + .prog_clk_2_N_in ( p1840 ) , .prog_clk_2_S_in ( p968 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6459 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6460 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6461 ) , .prog_clk_3_N_in ( prog_clk_3_wires[14] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9823 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9824 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9825 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9826 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9827 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9828 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6462 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( p1840 ) , + .clk_2_S_in ( p1938 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6463 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6464 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6465 ) , .clk_3_N_in ( clk_3_wires[14] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9829 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6466 ) , .clk_3_S_out ( clk_3_wires[15] ) ) ; cby_1__1_ cby_4__6_ ( .chany_bottom_in ( sb_1__1__37_chany_top_out ) , .chany_top_in ( sb_1__1__38_chany_bottom_out ) , @@ -80321,30 +81828,27 @@ cby_1__1_ cby_4__6_ ( .chany_bottom_in ( sb_1__1__37_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__41_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9830 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6467 ) , .Test_en_E_in ( Test_enWires[142] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9831 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9832 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6468 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6469 ) , .Test_en_W_out ( Test_enWires[139] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9833 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .prog_clk_0_W_in ( prog_clk_0_wires[155] ) , .prog_clk_0_S_out ( prog_clk_0_wires[156] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9834 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9835 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9836 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9837 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9838 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9839 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6471 ) , + .prog_clk_2_N_in ( p1805 ) , .prog_clk_2_S_in ( p411 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6472 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6473 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_6474 ) , .prog_clk_3_N_in ( prog_clk_3_wires[10] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9840 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9841 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9842 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9843 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9844 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9845 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6475 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( p1805 ) , + .clk_2_S_in ( p857 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6476 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6477 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_6478 ) , .clk_3_N_in ( clk_3_wires[10] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9846 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6479 ) , .clk_3_S_out ( clk_3_wires[11] ) ) ; cby_1__1_ cby_4__7_ ( .chany_bottom_in ( sb_1__1__38_chany_top_out ) , .chany_top_in ( sb_1__1__39_chany_bottom_out ) , @@ -80368,31 +81872,28 @@ cby_1__1_ cby_4__7_ ( .chany_bottom_in ( sb_1__1__38_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__42_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9847 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6480 ) , .Test_en_E_in ( Test_enWires[164] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9848 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9849 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6481 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6482 ) , .Test_en_W_out ( Test_enWires[161] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9850 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6483 ) , .prog_clk_0_W_in ( prog_clk_0_wires[158] ) , .prog_clk_0_S_out ( prog_clk_0_wires[159] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9851 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9852 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9853 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9854 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9855 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6484 ) , + .prog_clk_2_N_in ( p1647 ) , .prog_clk_2_S_in ( p240 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6485 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6486 ) , .prog_clk_3_S_in ( prog_clk_3_wires[8] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9856 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6487 ) , .prog_clk_3_N_out ( prog_clk_3_wires[9] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9857 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9858 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9859 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9860 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9861 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6488 ) , .clk_2_N_in ( p1647 ) , + .clk_2_S_in ( p645 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6489 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6490 ) , .clk_3_S_in ( clk_3_wires[8] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9862 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6491 ) , .clk_3_N_out ( clk_3_wires[9] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9863 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6492 ) ) ; cby_1__1_ cby_4__8_ ( .chany_bottom_in ( sb_1__1__39_chany_top_out ) , .chany_top_in ( sb_1__1__40_chany_bottom_out ) , .ccff_head ( grid_clb_43_ccff_tail ) , @@ -80415,31 +81916,28 @@ cby_1__1_ cby_4__8_ ( .chany_bottom_in ( sb_1__1__39_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__43_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9864 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6493 ) , .Test_en_E_in ( Test_enWires[186] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9865 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9866 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6494 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6495 ) , .Test_en_W_out ( Test_enWires[183] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9867 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6496 ) , .prog_clk_0_W_in ( prog_clk_0_wires[161] ) , .prog_clk_0_S_out ( prog_clk_0_wires[162] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9868 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9869 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9870 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9871 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9872 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6497 ) , + .prog_clk_2_N_in ( p1792 ) , .prog_clk_2_S_in ( p635 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6498 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6499 ) , .prog_clk_3_S_in ( prog_clk_3_wires[12] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9873 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6500 ) , .prog_clk_3_N_out ( prog_clk_3_wires[13] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9874 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9875 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9876 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9877 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9878 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6501 ) , .clk_2_N_in ( p1792 ) , + .clk_2_S_in ( p224 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6502 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6503 ) , .clk_3_S_in ( clk_3_wires[12] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9879 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6504 ) , .clk_3_N_out ( clk_3_wires[13] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9880 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6505 ) ) ; cby_1__1_ cby_4__9_ ( .chany_bottom_in ( sb_1__1__40_chany_top_out ) , .chany_top_in ( sb_1__1__41_chany_bottom_out ) , .ccff_head ( grid_clb_44_ccff_tail ) , @@ -80462,31 +81960,28 @@ cby_1__1_ cby_4__9_ ( .chany_bottom_in ( sb_1__1__40_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__44_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9881 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6506 ) , .Test_en_E_in ( Test_enWires[208] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9882 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9883 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6507 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6508 ) , .Test_en_W_out ( Test_enWires[205] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9884 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6509 ) , .prog_clk_0_W_in ( prog_clk_0_wires[164] ) , .prog_clk_0_S_out ( prog_clk_0_wires[165] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9885 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9886 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9887 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9888 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9889 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6510 ) , + .prog_clk_2_N_in ( p2102 ) , .prog_clk_2_S_in ( p855 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6511 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6512 ) , .prog_clk_3_S_in ( prog_clk_3_wires[18] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9890 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6513 ) , .prog_clk_3_N_out ( prog_clk_3_wires[19] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9891 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9892 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9893 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9894 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9895 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6514 ) , .clk_2_N_in ( p2102 ) , + .clk_2_S_in ( p166 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6515 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6516 ) , .clk_3_S_in ( clk_3_wires[18] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9896 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6517 ) , .clk_3_N_out ( clk_3_wires[19] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9897 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6518 ) ) ; cby_1__1_ cby_4__10_ ( .chany_bottom_in ( sb_1__1__41_chany_top_out ) , .chany_top_in ( sb_1__1__42_chany_bottom_out ) , .ccff_head ( grid_clb_45_ccff_tail ) , @@ -80509,31 +82004,28 @@ cby_1__1_ cby_4__10_ ( .chany_bottom_in ( sb_1__1__41_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__45_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9898 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6519 ) , .Test_en_E_in ( Test_enWires[230] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9899 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9900 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6520 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6521 ) , .Test_en_W_out ( Test_enWires[227] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9901 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6522 ) , .prog_clk_0_W_in ( prog_clk_0_wires[167] ) , .prog_clk_0_S_out ( prog_clk_0_wires[168] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9902 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9903 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9904 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9905 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9906 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6523 ) , + .prog_clk_2_N_in ( p1352 ) , .prog_clk_2_S_in ( p212 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6524 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6525 ) , .prog_clk_3_S_in ( prog_clk_3_wires[22] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9907 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6526 ) , .prog_clk_3_N_out ( prog_clk_3_wires[23] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9908 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9909 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9910 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9911 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9912 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6527 ) , .clk_2_N_in ( p1352 ) , + .clk_2_S_in ( p550 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6528 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6529 ) , .clk_3_S_in ( clk_3_wires[22] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9913 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6530 ) , .clk_3_N_out ( clk_3_wires[23] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9914 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6531 ) ) ; cby_1__1_ cby_4__11_ ( .chany_bottom_in ( sb_1__1__42_chany_top_out ) , .chany_top_in ( sb_1__1__43_chany_bottom_out ) , .ccff_head ( grid_clb_46_ccff_tail ) , @@ -80556,31 +82048,25 @@ cby_1__1_ cby_4__11_ ( .chany_bottom_in ( sb_1__1__42_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__46_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9915 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6532 ) , .Test_en_E_in ( Test_enWires[252] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9916 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9917 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6533 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6534 ) , .Test_en_W_out ( Test_enWires[249] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9918 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6535 ) , .prog_clk_0_W_in ( prog_clk_0_wires[170] ) , .prog_clk_0_S_out ( prog_clk_0_wires[171] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9919 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9920 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9921 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9922 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9923 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9924 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9925 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9926 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9927 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9928 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9929 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9932 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9933 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9934 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9935 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6536 ) , + .prog_clk_2_N_in ( p3230 ) , .prog_clk_2_S_in ( p2958 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6537 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6538 ) , + .prog_clk_3_S_in ( p2993 ) , .prog_clk_3_N_in ( p3161 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6539 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6540 ) , .clk_2_N_in ( p1782 ) , + .clk_2_S_in ( p443 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6541 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6542 ) , .clk_3_S_in ( p1477 ) , + .clk_3_N_in ( p1074 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6543 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6544 ) ) ; cby_1__1_ cby_4__12_ ( .chany_bottom_in ( sb_1__1__43_chany_top_out ) , .chany_top_in ( sb_1__12__3_chany_bottom_out ) , .ccff_head ( grid_clb_47_ccff_tail ) , @@ -80603,31 +82089,25 @@ cby_1__1_ cby_4__12_ ( .chany_bottom_in ( sb_1__1__43_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__47_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9936 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6545 ) , .Test_en_E_in ( Test_enWires[274] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9937 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9938 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6546 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6547 ) , .Test_en_W_out ( Test_enWires[271] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9939 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6548 ) , .prog_clk_0_W_in ( prog_clk_0_wires[173] ) , .prog_clk_0_S_out ( prog_clk_0_wires[174] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9940 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9941 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9942 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9943 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9944 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9945 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9946 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9947 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9948 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9949 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9950 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9951 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9952 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9953 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9954 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9955 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , .prog_clk_2_N_in ( p2723 ) , + .prog_clk_2_S_in ( p1895 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6549 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6550 ) , + .prog_clk_3_S_in ( p1986 ) , .prog_clk_3_N_in ( p2644 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6551 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6552 ) , .clk_2_N_in ( p2329 ) , + .clk_2_S_in ( p547 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6553 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6554 ) , .clk_3_S_in ( p2529 ) , + .clk_3_N_in ( p861 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6555 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6556 ) ) ; cby_1__1_ cby_5__1_ ( .chany_bottom_in ( sb_1__0__4_chany_top_out ) , .chany_top_in ( sb_1__1__44_chany_bottom_out ) , .ccff_head ( grid_clb_48_ccff_tail ) , @@ -80650,31 +82130,25 @@ cby_1__1_ cby_5__1_ ( .chany_bottom_in ( sb_1__0__4_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__48_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9956 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6557 ) , .Test_en_E_in ( Test_enWires[34] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9957 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9958 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6558 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6559 ) , .Test_en_W_out ( Test_enWires[31] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9959 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6560 ) , .prog_clk_0_W_in ( prog_clk_0_wires[178] ) , .prog_clk_0_S_out ( prog_clk_0_wires[179] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9960 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9961 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9962 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9963 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9964 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9965 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9966 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9967 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9968 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9969 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9970 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9971 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9972 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9973 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9974 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9975 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9976 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6561 ) , + .prog_clk_2_N_in ( p3199 ) , .prog_clk_2_S_in ( p2938 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6562 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6563 ) , + .prog_clk_3_S_in ( p2995 ) , .prog_clk_3_N_in ( p3180 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6564 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6565 ) , .clk_2_N_in ( p2931 ) , + .clk_2_S_in ( p2225 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6566 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6567 ) , .clk_3_S_in ( p2321 ) , + .clk_3_N_in ( p749 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6568 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6569 ) ) ; cby_1__1_ cby_5__2_ ( .chany_bottom_in ( sb_1__1__44_chany_top_out ) , .chany_top_in ( sb_1__1__45_chany_bottom_out ) , .ccff_head ( grid_clb_49_ccff_tail ) , @@ -80697,31 +82171,28 @@ cby_1__1_ cby_5__2_ ( .chany_bottom_in ( sb_1__1__44_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__49_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9977 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6570 ) , .Test_en_E_in ( Test_enWires[56] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9978 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9979 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6571 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6572 ) , .Test_en_W_out ( Test_enWires[53] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9980 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6573 ) , .prog_clk_0_W_in ( prog_clk_0_wires[181] ) , .prog_clk_0_S_out ( prog_clk_0_wires[182] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9981 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6574 ) , .prog_clk_2_N_in ( prog_clk_2_wires[31] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9982 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6575 ) , .prog_clk_2_S_out ( prog_clk_2_wires[32] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9983 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9984 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9985 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9986 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9987 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6576 ) , + .prog_clk_3_S_in ( p1706 ) , .prog_clk_3_N_in ( p1259 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6577 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6578 ) , .clk_2_N_in ( clk_2_wires[31] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9988 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_2_S_out ( clk_2_wires[32] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9989 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9990 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9991 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9992 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9993 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6580 ) , .clk_3_S_in ( p2174 ) , + .clk_3_N_in ( p417 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6581 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6582 ) ) ; cby_1__1_ cby_5__3_ ( .chany_bottom_in ( sb_1__1__45_chany_top_out ) , .chany_top_in ( sb_1__1__46_chany_bottom_out ) , .ccff_head ( grid_clb_50_ccff_tail ) , @@ -80744,31 +82215,25 @@ cby_1__1_ cby_5__3_ ( .chany_bottom_in ( sb_1__1__45_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__50_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9994 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6583 ) , .Test_en_E_in ( Test_enWires[78] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9995 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9996 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6584 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6585 ) , .Test_en_W_out ( Test_enWires[75] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9997 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6586 ) , .prog_clk_0_W_in ( prog_clk_0_wires[184] ) , .prog_clk_0_S_out ( prog_clk_0_wires[185] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9998 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9999 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10000 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10001 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10002 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10003 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10004 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10005 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10006 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10007 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10008 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10009 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10010 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10011 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10012 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10013 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10014 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6587 ) , + .prog_clk_2_N_in ( p3030 ) , .prog_clk_2_S_in ( p2202 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6588 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6589 ) , + .prog_clk_3_S_in ( p2331 ) , .prog_clk_3_N_in ( p3185 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6590 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6591 ) , .clk_2_N_in ( p3221 ) , + .clk_2_S_in ( p102 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6592 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6593 ) , .clk_3_S_in ( p2160 ) , + .clk_3_N_in ( p731 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6594 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6595 ) ) ; cby_1__1_ cby_5__4_ ( .chany_bottom_in ( sb_1__1__46_chany_top_out ) , .chany_top_in ( sb_1__1__47_chany_bottom_out ) , .ccff_head ( grid_clb_51_ccff_tail ) , @@ -80791,31 +82256,28 @@ cby_1__1_ cby_5__4_ ( .chany_bottom_in ( sb_1__1__46_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__51_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10015 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6596 ) , .Test_en_E_in ( Test_enWires[100] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10016 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10017 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6597 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6598 ) , .Test_en_W_out ( Test_enWires[97] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_10018 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6599 ) , .prog_clk_0_W_in ( prog_clk_0_wires[187] ) , .prog_clk_0_S_out ( prog_clk_0_wires[188] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10019 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6600 ) , .prog_clk_2_N_in ( prog_clk_2_wires[44] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10020 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6601 ) , .prog_clk_2_S_out ( prog_clk_2_wires[45] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10021 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10022 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10023 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10024 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10025 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6602 ) , + .prog_clk_3_S_in ( p1877 ) , .prog_clk_3_N_in ( p1026 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6603 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6604 ) , .clk_2_N_in ( clk_2_wires[44] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10026 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6605 ) , .clk_2_S_out ( clk_2_wires[45] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10027 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10028 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10029 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10030 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10031 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6606 ) , .clk_3_S_in ( p2794 ) , + .clk_3_N_in ( p639 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6607 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6608 ) ) ; cby_1__1_ cby_5__5_ ( .chany_bottom_in ( sb_1__1__47_chany_top_out ) , .chany_top_in ( sb_1__1__48_chany_bottom_out ) , .ccff_head ( grid_clb_52_ccff_tail ) , @@ -80838,31 +82300,28 @@ cby_1__1_ cby_5__5_ ( .chany_bottom_in ( sb_1__1__47_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__52_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10032 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6609 ) , .Test_en_E_in ( Test_enWires[122] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10033 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10034 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6610 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6611 ) , .Test_en_W_out ( Test_enWires[119] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_10035 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6612 ) , .prog_clk_0_W_in ( prog_clk_0_wires[190] ) , .prog_clk_0_S_out ( prog_clk_0_wires[191] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10036 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10037 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6613 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6614 ) , .prog_clk_2_S_in ( prog_clk_2_wires[42] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10038 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10039 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10040 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10041 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10042 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10043 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6615 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , .prog_clk_3_S_in ( p2592 ) , + .prog_clk_3_N_in ( p779 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6616 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6617 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6618 ) , .clk_2_S_in ( clk_2_wires[42] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) , - .clk_2_N_out ( clk_2_wires[43] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10045 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10046 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10047 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10048 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6619 ) , + .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p2861 ) , + .clk_3_N_in ( p1313 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6620 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6621 ) ) ; cby_1__1_ cby_5__6_ ( .chany_bottom_in ( sb_1__1__48_chany_top_out ) , .chany_top_in ( sb_1__1__49_chany_bottom_out ) , .ccff_head ( grid_clb_53_ccff_tail ) , @@ -80885,31 +82344,25 @@ cby_1__1_ cby_5__6_ ( .chany_bottom_in ( sb_1__1__48_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__53_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10049 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6622 ) , .Test_en_E_in ( Test_enWires[144] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10050 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10051 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6623 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6624 ) , .Test_en_W_out ( Test_enWires[141] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_10052 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6625 ) , .prog_clk_0_W_in ( prog_clk_0_wires[193] ) , .prog_clk_0_S_out ( prog_clk_0_wires[194] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10053 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10054 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10055 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10056 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10057 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10058 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10059 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10060 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10061 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10062 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10063 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10064 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10065 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10066 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10067 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10068 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10069 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6626 ) , + .prog_clk_2_N_in ( p3298 ) , .prog_clk_2_S_in ( p2828 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6627 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6628 ) , + .prog_clk_3_S_in ( p2924 ) , .prog_clk_3_N_in ( p3259 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6629 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_2_N_in ( p2388 ) , + .clk_2_S_in ( p357 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6631 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6632 ) , .clk_3_S_in ( p1633 ) , + .clk_3_N_in ( p714 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6633 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6634 ) ) ; cby_1__1_ cby_5__7_ ( .chany_bottom_in ( sb_1__1__49_chany_top_out ) , .chany_top_in ( sb_1__1__50_chany_bottom_out ) , .ccff_head ( grid_clb_54_ccff_tail ) , @@ -80932,31 +82385,25 @@ cby_1__1_ cby_5__7_ ( .chany_bottom_in ( sb_1__1__49_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__54_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10070 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6635 ) , .Test_en_E_in ( Test_enWires[166] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10071 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10072 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6636 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6637 ) , .Test_en_W_out ( Test_enWires[163] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_10073 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6638 ) , .prog_clk_0_W_in ( prog_clk_0_wires[196] ) , .prog_clk_0_S_out ( prog_clk_0_wires[197] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10074 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10075 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10076 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10077 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10078 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10079 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10080 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10081 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10082 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10083 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10084 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10085 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10086 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10087 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10088 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10089 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10090 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6639 ) , + .prog_clk_2_N_in ( p2922 ) , .prog_clk_2_S_in ( p2440 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6640 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6641 ) , + .prog_clk_3_S_in ( p2540 ) , .prog_clk_3_N_in ( p2816 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6642 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6643 ) , .clk_2_N_in ( p2936 ) , + .clk_2_S_in ( p1925 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6644 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_S_in ( p2145 ) , + .clk_3_N_in ( p706 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6646 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6647 ) ) ; cby_1__1_ cby_5__8_ ( .chany_bottom_in ( sb_1__1__50_chany_top_out ) , .chany_top_in ( sb_1__1__51_chany_bottom_out ) , .ccff_head ( grid_clb_55_ccff_tail ) , @@ -80979,31 +82426,28 @@ cby_1__1_ cby_5__8_ ( .chany_bottom_in ( sb_1__1__50_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__55_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10091 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6648 ) , .Test_en_E_in ( Test_enWires[188] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10092 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10093 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6649 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6650 ) , .Test_en_W_out ( Test_enWires[185] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_10094 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6651 ) , .prog_clk_0_W_in ( prog_clk_0_wires[199] ) , .prog_clk_0_S_out ( prog_clk_0_wires[200] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10095 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6652 ) , .prog_clk_2_N_in ( prog_clk_2_wires[57] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10096 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6653 ) , .prog_clk_2_S_out ( prog_clk_2_wires[58] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10097 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10098 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10099 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10100 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10101 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6654 ) , + .prog_clk_3_S_in ( p1708 ) , .prog_clk_3_N_in ( p445 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6655 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6656 ) , .clk_2_N_in ( clk_2_wires[57] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10102 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6657 ) , .clk_2_S_out ( clk_2_wires[58] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10103 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10104 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10105 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10106 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10107 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_3_S_in ( p2156 ) , + .clk_3_N_in ( p1036 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6659 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6660 ) ) ; cby_1__1_ cby_5__9_ ( .chany_bottom_in ( sb_1__1__51_chany_top_out ) , .chany_top_in ( sb_1__1__52_chany_bottom_out ) , .ccff_head ( grid_clb_56_ccff_tail ) , @@ -81026,31 +82470,28 @@ cby_1__1_ cby_5__9_ ( .chany_bottom_in ( sb_1__1__51_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__56_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10108 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6661 ) , .Test_en_E_in ( Test_enWires[210] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10109 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10110 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6662 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6663 ) , .Test_en_W_out ( Test_enWires[207] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_10111 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6664 ) , .prog_clk_0_W_in ( prog_clk_0_wires[202] ) , .prog_clk_0_S_out ( prog_clk_0_wires[203] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10112 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10113 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6665 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6666 ) , .prog_clk_2_S_in ( prog_clk_2_wires[55] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10114 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10115 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10116 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10117 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10118 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10119 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6667 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , .prog_clk_3_S_in ( p1745 ) , + .prog_clk_3_N_in ( p1201 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6668 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6669 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6670 ) , .clk_2_S_in ( clk_2_wires[55] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) , - .clk_2_N_out ( clk_2_wires[56] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10121 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10122 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10123 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10124 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6671 ) , + .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1745 ) , + .clk_3_N_in ( p887 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6672 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6673 ) ) ; cby_1__1_ cby_5__10_ ( .chany_bottom_in ( sb_1__1__52_chany_top_out ) , .chany_top_in ( sb_1__1__53_chany_bottom_out ) , .ccff_head ( grid_clb_57_ccff_tail ) , @@ -81073,31 +82514,25 @@ cby_1__1_ cby_5__10_ ( .chany_bottom_in ( sb_1__1__52_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__57_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10125 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6674 ) , .Test_en_E_in ( Test_enWires[232] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10126 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10127 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6675 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6676 ) , .Test_en_W_out ( Test_enWires[229] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_10128 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .prog_clk_0_W_in ( prog_clk_0_wires[205] ) , .prog_clk_0_S_out ( prog_clk_0_wires[206] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10129 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10130 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10131 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10132 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10133 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10134 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10135 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10136 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10137 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10138 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10139 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10140 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10141 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10142 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10143 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10144 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10145 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6678 ) , + .prog_clk_2_N_in ( p3228 ) , .prog_clk_2_S_in ( p3299 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6679 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6680 ) , + .prog_clk_3_S_in ( p3336 ) , .prog_clk_3_N_in ( p3251 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6681 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6682 ) , .clk_2_N_in ( p3289 ) , + .clk_2_S_in ( p503 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6683 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6684 ) , .clk_3_S_in ( p2014 ) , + .clk_3_N_in ( p124 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6685 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6686 ) ) ; cby_1__1_ cby_5__11_ ( .chany_bottom_in ( sb_1__1__53_chany_top_out ) , .chany_top_in ( sb_1__1__54_chany_bottom_out ) , .ccff_head ( grid_clb_58_ccff_tail ) , @@ -81120,31 +82555,28 @@ cby_1__1_ cby_5__11_ ( .chany_bottom_in ( sb_1__1__53_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__58_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10146 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6687 ) , .Test_en_E_in ( Test_enWires[254] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10147 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10148 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6688 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6689 ) , .Test_en_W_out ( Test_enWires[251] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_10149 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6690 ) , .prog_clk_0_W_in ( prog_clk_0_wires[208] ) , .prog_clk_0_S_out ( prog_clk_0_wires[209] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10150 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10151 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6691 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6692 ) , .prog_clk_2_S_in ( prog_clk_2_wires[66] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10152 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10153 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10154 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10155 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10156 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10157 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6693 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , .prog_clk_3_S_in ( p2330 ) , + .prog_clk_3_N_in ( p194 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6694 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6695 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6696 ) , .clk_2_S_in ( clk_2_wires[66] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10158 ) , - .clk_2_N_out ( clk_2_wires[67] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10159 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10160 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10161 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10162 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6697 ) , + .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p2330 ) , + .clk_3_N_in ( p1031 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6698 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6699 ) ) ; cby_1__1_ cby_5__12_ ( .chany_bottom_in ( sb_1__1__54_chany_top_out ) , .chany_top_in ( sb_1__12__4_chany_bottom_out ) , .ccff_head ( grid_clb_59_ccff_tail ) , @@ -81167,31 +82599,25 @@ cby_1__1_ cby_5__12_ ( .chany_bottom_in ( sb_1__1__54_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__59_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10163 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6700 ) , .Test_en_E_in ( Test_enWires[276] ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10164 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10165 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6701 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6702 ) , .Test_en_W_out ( Test_enWires[273] ) , - .Test_en_E_out ( SYNOPSYS_UNCONNECTED_10166 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_6703 ) , .prog_clk_0_W_in ( prog_clk_0_wires[211] ) , .prog_clk_0_S_out ( prog_clk_0_wires[212] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10167 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10168 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10169 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10170 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10171 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10172 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10173 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10174 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10175 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10176 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10177 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10178 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10179 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10180 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10181 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10182 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , .prog_clk_2_N_in ( p2780 ) , + .prog_clk_2_S_in ( p3319 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6704 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6705 ) , + .prog_clk_3_S_in ( p3326 ) , .prog_clk_3_N_in ( p2657 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6706 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6707 ) , .clk_2_N_in ( p2111 ) , + .clk_2_S_in ( p24 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6708 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_S_in ( p1596 ) , + .clk_3_N_in ( p498 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6710 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6711 ) ) ; cby_1__1_ cby_6__1_ ( .chany_bottom_in ( sb_1__0__5_chany_top_out ) , .chany_top_in ( sb_1__1__55_chany_bottom_out ) , .ccff_head ( grid_clb_60_ccff_tail ) , @@ -81215,29 +82641,26 @@ cby_1__1_ cby_6__1_ ( .chany_bottom_in ( sb_1__0__5_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__60_ccff_tail ) , .Test_en_S_in ( Test_enWires[1] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10183 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10184 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6712 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6713 ) , .Test_en_N_out ( Test_enWires[2] ) , .Test_en_W_out ( Test_enWires[33] ) , .Test_en_E_out ( Test_enWires[35] ) , .prog_clk_0_W_in ( prog_clk_0_wires[216] ) , .prog_clk_0_S_out ( prog_clk_0_wires[217] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10185 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10186 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10187 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10188 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10189 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6714 ) , + .prog_clk_2_N_in ( p2049 ) , .prog_clk_2_S_in ( p1900 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6715 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6716 ) , .prog_clk_3_S_in ( prog_clk_3_wires[90] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10190 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6717 ) , .prog_clk_3_N_out ( prog_clk_3_wires[89] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10191 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10192 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10193 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10194 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10195 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6718 ) , .clk_2_N_in ( p2049 ) , + .clk_2_S_in ( p88 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6719 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6720 ) , .clk_3_S_in ( clk_3_wires[90] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10196 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6721 ) , .clk_3_N_out ( clk_3_wires[89] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10197 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6722 ) ) ; cby_1__1_ cby_6__2_ ( .chany_bottom_in ( sb_1__1__55_chany_top_out ) , .chany_top_in ( sb_1__1__56_chany_bottom_out ) , .ccff_head ( grid_clb_61_ccff_tail ) , @@ -81261,29 +82684,26 @@ cby_1__1_ cby_6__2_ ( .chany_bottom_in ( sb_1__1__55_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__61_ccff_tail ) , .Test_en_S_in ( Test_enWires[3] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10198 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10199 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6723 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6724 ) , .Test_en_N_out ( Test_enWires[4] ) , .Test_en_W_out ( Test_enWires[55] ) , .Test_en_E_out ( Test_enWires[57] ) , .prog_clk_0_W_in ( prog_clk_0_wires[219] ) , .prog_clk_0_S_out ( prog_clk_0_wires[220] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10200 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10201 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10202 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10203 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10204 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6725 ) , + .prog_clk_2_N_in ( p2062 ) , .prog_clk_2_S_in ( p233 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6726 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6727 ) , .prog_clk_3_S_in ( prog_clk_3_wires[92] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10205 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6728 ) , .prog_clk_3_N_out ( prog_clk_3_wires[91] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10206 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10207 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10208 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10209 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10210 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6729 ) , .clk_2_N_in ( p2062 ) , + .clk_2_S_in ( p995 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6730 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6731 ) , .clk_3_S_in ( clk_3_wires[92] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10211 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6732 ) , .clk_3_N_out ( clk_3_wires[91] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10212 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6733 ) ) ; cby_1__1_ cby_6__3_ ( .chany_bottom_in ( sb_1__1__56_chany_top_out ) , .chany_top_in ( sb_1__1__57_chany_bottom_out ) , .ccff_head ( grid_clb_62_ccff_tail ) , @@ -81307,29 +82727,26 @@ cby_1__1_ cby_6__3_ ( .chany_bottom_in ( sb_1__1__56_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__62_ccff_tail ) , .Test_en_S_in ( Test_enWires[5] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10213 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10214 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6734 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6735 ) , .Test_en_N_out ( Test_enWires[6] ) , .Test_en_W_out ( Test_enWires[77] ) , .Test_en_E_out ( Test_enWires[79] ) , .prog_clk_0_W_in ( prog_clk_0_wires[222] ) , .prog_clk_0_S_out ( prog_clk_0_wires[223] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10215 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10216 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10217 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10218 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10219 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6736 ) , + .prog_clk_2_N_in ( p1707 ) , .prog_clk_2_S_in ( p144 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6737 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6738 ) , .prog_clk_3_S_in ( prog_clk_3_wires[94] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10220 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6739 ) , .prog_clk_3_N_out ( prog_clk_3_wires[93] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10221 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10222 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10223 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10224 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10225 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6740 ) , .clk_2_N_in ( p1707 ) , + .clk_2_S_in ( p421 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6741 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6742 ) , .clk_3_S_in ( clk_3_wires[94] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10226 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6743 ) , .clk_3_N_out ( clk_3_wires[93] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10227 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6744 ) ) ; cby_1__1_ cby_6__4_ ( .chany_bottom_in ( sb_1__1__57_chany_top_out ) , .chany_top_in ( sb_1__1__58_chany_bottom_out ) , .ccff_head ( grid_clb_63_ccff_tail ) , @@ -81353,29 +82770,26 @@ cby_1__1_ cby_6__4_ ( .chany_bottom_in ( sb_1__1__57_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__63_ccff_tail ) , .Test_en_S_in ( Test_enWires[7] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10228 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10229 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6745 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6746 ) , .Test_en_N_out ( Test_enWires[8] ) , .Test_en_W_out ( Test_enWires[99] ) , .Test_en_E_out ( Test_enWires[101] ) , .prog_clk_0_W_in ( prog_clk_0_wires[225] ) , .prog_clk_0_S_out ( prog_clk_0_wires[226] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10230 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10231 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10232 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10233 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10234 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6747 ) , + .prog_clk_2_N_in ( p2349 ) , .prog_clk_2_S_in ( p739 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6748 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6749 ) , .prog_clk_3_S_in ( prog_clk_3_wires[96] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10235 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6750 ) , .prog_clk_3_N_out ( prog_clk_3_wires[95] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10236 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10237 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10238 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10239 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10240 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6751 ) , .clk_2_N_in ( p2349 ) , + .clk_2_S_in ( p433 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6752 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6753 ) , .clk_3_S_in ( clk_3_wires[96] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10241 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_3_N_out ( clk_3_wires[95] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10242 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6755 ) ) ; cby_1__1_ cby_6__5_ ( .chany_bottom_in ( sb_1__1__58_chany_top_out ) , .chany_top_in ( sb_1__1__59_chany_bottom_out ) , .ccff_head ( grid_clb_64_ccff_tail ) , @@ -81399,30 +82813,27 @@ cby_1__1_ cby_6__5_ ( .chany_bottom_in ( sb_1__1__58_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__64_ccff_tail ) , .Test_en_S_in ( Test_enWires[9] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10243 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10244 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6756 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6757 ) , .Test_en_N_out ( Test_enWires[10] ) , .Test_en_W_out ( Test_enWires[121] ) , .Test_en_E_out ( Test_enWires[123] ) , .prog_clk_0_W_in ( prog_clk_0_wires[228] ) , .prog_clk_0_S_out ( prog_clk_0_wires[229] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10245 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10246 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10247 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10248 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10249 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6758 ) , + .prog_clk_2_N_in ( p2360 ) , .prog_clk_2_S_in ( p1023 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6759 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6760 ) , .prog_clk_3_S_in ( prog_clk_3_wires[98] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10250 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6761 ) , .prog_clk_3_N_out ( prog_clk_3_wires[97] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10251 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10252 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10253 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10254 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10255 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6762 ) , .clk_2_N_in ( p2360 ) , + .clk_2_S_in ( p58 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6763 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6764 ) , .clk_3_S_in ( clk_3_wires[98] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10256 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6765 ) , .clk_3_N_out ( clk_3_wires[97] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10257 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6766 ) ) ; cby_1__1_ cby_6__6_ ( .chany_bottom_in ( sb_1__1__59_chany_top_out ) , .chany_top_in ( sb_1__1__60_chany_bottom_out ) , .ccff_head ( grid_clb_65_ccff_tail ) , @@ -81446,30 +82857,27 @@ cby_1__1_ cby_6__6_ ( .chany_bottom_in ( sb_1__1__59_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__65_ccff_tail ) , .Test_en_S_in ( Test_enWires[11] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10258 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10259 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6767 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6768 ) , .Test_en_N_out ( Test_enWires[12] ) , .Test_en_W_out ( Test_enWires[143] ) , .Test_en_E_out ( Test_enWires[145] ) , .prog_clk_0_W_in ( prog_clk_0_wires[231] ) , .prog_clk_0_S_out ( prog_clk_0_wires[232] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10260 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10261 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10262 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10263 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10264 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6769 ) , + .prog_clk_2_N_in ( p2104 ) , .prog_clk_2_S_in ( p113 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6770 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6771 ) , .prog_clk_3_S_in ( prog_clk_3_wires[100] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10265 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_6772 ) , .prog_clk_3_N_out ( prog_clk_3_wires[99] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10266 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10267 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10268 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10269 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10270 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_2_N_in ( p2104 ) , + .clk_2_S_in ( p1929 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6774 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6775 ) , .clk_3_S_in ( clk_3_wires[100] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10271 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_6776 ) , .clk_3_N_out ( clk_3_wires[99] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10272 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6777 ) ) ; cby_1__1_ cby_6__7_ ( .chany_bottom_in ( sb_1__1__60_chany_top_out ) , .chany_top_in ( sb_1__1__61_chany_bottom_out ) , .ccff_head ( grid_clb_66_ccff_tail ) , @@ -81493,30 +82901,24 @@ cby_1__1_ cby_6__7_ ( .chany_bottom_in ( sb_1__1__60_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__66_ccff_tail ) , .Test_en_S_in ( Test_enWires[13] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10273 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10274 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6778 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6779 ) , .Test_en_N_out ( Test_enWires[14] ) , .Test_en_W_out ( Test_enWires[165] ) , .Test_en_E_out ( Test_enWires[167] ) , .prog_clk_0_W_in ( prog_clk_0_wires[234] ) , .prog_clk_0_S_out ( prog_clk_0_wires[235] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10275 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10276 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10277 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10278 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10279 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10280 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10281 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10282 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10283 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10284 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10285 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10286 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10287 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10288 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10289 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10290 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10291 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6780 ) , + .prog_clk_2_N_in ( p2914 ) , .prog_clk_2_S_in ( p3070 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6781 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6782 ) , + .prog_clk_3_S_in ( p3110 ) , .prog_clk_3_N_in ( p2801 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6783 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6784 ) , .clk_2_N_in ( p2721 ) , + .clk_2_S_in ( p911 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6785 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6786 ) , .clk_3_S_in ( p1617 ) , + .clk_3_N_in ( p115 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6787 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6788 ) ) ; cby_1__1_ cby_6__8_ ( .chany_bottom_in ( sb_1__1__61_chany_top_out ) , .chany_top_in ( sb_1__1__62_chany_bottom_out ) , .ccff_head ( grid_clb_67_ccff_tail ) , @@ -81540,30 +82942,24 @@ cby_1__1_ cby_6__8_ ( .chany_bottom_in ( sb_1__1__61_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__67_ccff_tail ) , .Test_en_S_in ( Test_enWires[15] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10292 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10293 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6789 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6790 ) , .Test_en_N_out ( Test_enWires[16] ) , .Test_en_W_out ( Test_enWires[187] ) , .Test_en_E_out ( Test_enWires[189] ) , .prog_clk_0_W_in ( prog_clk_0_wires[237] ) , .prog_clk_0_S_out ( prog_clk_0_wires[238] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10294 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10295 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10296 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10297 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10298 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10299 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10300 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10301 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10302 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10303 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10304 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10305 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10306 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10307 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10308 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10309 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10310 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6791 ) , + .prog_clk_2_N_in ( p2538 ) , .prog_clk_2_S_in ( p79 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6792 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6793 ) , + .prog_clk_3_S_in ( p1671 ) , .prog_clk_3_N_in ( p2636 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6794 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6795 ) , .clk_2_N_in ( p2763 ) , + .clk_2_S_in ( p1013 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6796 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6797 ) , .clk_3_S_in ( p2097 ) , + .clk_3_N_in ( p363 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6798 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6799 ) ) ; cby_1__1_ cby_6__9_ ( .chany_bottom_in ( sb_1__1__62_chany_top_out ) , .chany_top_in ( sb_1__1__63_chany_bottom_out ) , .ccff_head ( grid_clb_68_ccff_tail ) , @@ -81587,30 +82983,24 @@ cby_1__1_ cby_6__9_ ( .chany_bottom_in ( sb_1__1__62_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__68_ccff_tail ) , .Test_en_S_in ( Test_enWires[17] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10311 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10312 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6800 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6801 ) , .Test_en_N_out ( Test_enWires[18] ) , .Test_en_W_out ( Test_enWires[209] ) , .Test_en_E_out ( Test_enWires[211] ) , .prog_clk_0_W_in ( prog_clk_0_wires[240] ) , .prog_clk_0_S_out ( prog_clk_0_wires[241] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10313 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10314 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10315 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10316 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10317 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10318 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10319 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10320 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10321 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10322 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10323 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10324 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10325 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10326 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10327 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10328 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10329 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6802 ) , + .prog_clk_2_N_in ( p3016 ) , .prog_clk_2_S_in ( p2802 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6803 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6804 ) , + .prog_clk_3_S_in ( p2917 ) , .prog_clk_3_N_in ( p2950 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6805 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6806 ) , .clk_2_N_in ( p2394 ) , + .clk_2_S_in ( p470 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6807 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6808 ) , .clk_3_S_in ( p2105 ) , + .clk_3_N_in ( p1083 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6809 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6810 ) ) ; cby_1__1_ cby_6__10_ ( .chany_bottom_in ( sb_1__1__63_chany_top_out ) , .chany_top_in ( sb_1__1__64_chany_bottom_out ) , .ccff_head ( grid_clb_69_ccff_tail ) , @@ -81634,30 +83024,24 @@ cby_1__1_ cby_6__10_ ( .chany_bottom_in ( sb_1__1__63_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__69_ccff_tail ) , .Test_en_S_in ( Test_enWires[19] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10330 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10331 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6811 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6812 ) , .Test_en_N_out ( Test_enWires[20] ) , .Test_en_W_out ( Test_enWires[231] ) , .Test_en_E_out ( Test_enWires[233] ) , .prog_clk_0_W_in ( prog_clk_0_wires[243] ) , .prog_clk_0_S_out ( prog_clk_0_wires[244] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10332 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10333 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10334 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10335 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10336 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10337 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10338 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10339 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10340 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10341 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10342 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10343 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10344 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10345 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10346 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10347 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10348 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6813 ) , + .prog_clk_2_N_in ( p2741 ) , .prog_clk_2_S_in ( p74 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6814 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6815 ) , + .prog_clk_3_S_in ( p1823 ) , .prog_clk_3_N_in ( p3074 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6816 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6817 ) , .clk_2_N_in ( p3105 ) , + .clk_2_S_in ( p818 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6818 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6819 ) , .clk_3_S_in ( p1592 ) , + .clk_3_N_in ( p460 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6820 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6821 ) ) ; cby_1__1_ cby_6__11_ ( .chany_bottom_in ( sb_1__1__64_chany_top_out ) , .chany_top_in ( sb_1__1__65_chany_bottom_out ) , .ccff_head ( grid_clb_70_ccff_tail ) , @@ -81681,30 +83065,24 @@ cby_1__1_ cby_6__11_ ( .chany_bottom_in ( sb_1__1__64_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__70_ccff_tail ) , .Test_en_S_in ( Test_enWires[21] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10349 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10350 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6822 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6823 ) , .Test_en_N_out ( Test_enWires[22] ) , .Test_en_W_out ( Test_enWires[253] ) , .Test_en_E_out ( Test_enWires[255] ) , .prog_clk_0_W_in ( prog_clk_0_wires[246] ) , .prog_clk_0_S_out ( prog_clk_0_wires[247] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10351 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10352 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10353 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10354 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10355 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10356 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10357 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10358 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10359 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10360 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10361 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10362 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10363 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10364 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10365 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10366 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10367 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6824 ) , + .prog_clk_2_N_in ( p3000 ) , .prog_clk_2_S_in ( p2244 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6825 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6826 ) , + .prog_clk_3_S_in ( p2293 ) , .prog_clk_3_N_in ( p3178 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6827 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6828 ) , .clk_2_N_in ( p3224 ) , + .clk_2_S_in ( p518 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6829 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6830 ) , .clk_3_S_in ( p1602 ) , + .clk_3_N_in ( p1095 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6831 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6832 ) ) ; cby_1__1_ cby_6__12_ ( .chany_bottom_in ( sb_1__1__65_chany_top_out ) , .chany_top_in ( sb_1__12__5_chany_bottom_out ) , .ccff_head ( grid_clb_71_ccff_tail ) , @@ -81728,30 +83106,24 @@ cby_1__1_ cby_6__12_ ( .chany_bottom_in ( sb_1__1__65_chany_top_out ) , .left_grid_pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__71_ccff_tail ) , .Test_en_S_in ( Test_enWires[23] ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10368 ) , - .Test_en_W_in ( SYNOPSYS_UNCONNECTED_10369 ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10370 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6833 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_6834 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6835 ) , .Test_en_W_out ( Test_enWires[275] ) , .Test_en_E_out ( Test_enWires[277] ) , .prog_clk_0_W_in ( prog_clk_0_wires[249] ) , .prog_clk_0_S_out ( prog_clk_0_wires[250] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10371 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10372 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10373 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10374 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10375 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10376 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10377 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10378 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10379 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10380 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10381 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10382 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10383 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10384 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10385 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10386 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , .prog_clk_2_N_in ( p2887 ) , + .prog_clk_2_S_in ( p3082 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6836 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6837 ) , + .prog_clk_3_S_in ( p3111 ) , .prog_clk_3_N_in ( p2803 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6838 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6839 ) , .clk_2_N_in ( p2726 ) , + .clk_2_S_in ( p442 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6840 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6841 ) , .clk_3_S_in ( p2038 ) , + .clk_3_N_in ( p675 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6842 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6843 ) ) ; cby_1__1_ cby_7__1_ ( .chany_bottom_in ( sb_1__0__6_chany_top_out ) , .chany_top_in ( sb_1__1__66_chany_bottom_out ) , .ccff_head ( grid_clb_72_ccff_tail ) , @@ -81774,31 +83146,25 @@ cby_1__1_ cby_7__1_ ( .chany_bottom_in ( sb_1__0__6_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__72_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10387 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10388 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6844 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6845 ) , .Test_en_W_in ( Test_enWires[36] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10389 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10390 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6846 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6847 ) , .Test_en_E_out ( Test_enWires[37] ) , .prog_clk_0_W_in ( prog_clk_0_wires[254] ) , .prog_clk_0_S_out ( prog_clk_0_wires[255] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10391 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10392 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10393 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10394 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10395 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10396 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10397 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10398 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10399 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10400 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10401 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10402 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10403 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10404 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10405 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10406 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10407 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6848 ) , + .prog_clk_2_N_in ( p2501 ) , .prog_clk_2_S_in ( p2943 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6849 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6850 ) , + .prog_clk_3_S_in ( p3050 ) , .prog_clk_3_N_in ( p2961 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6851 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_2_N_in ( p3046 ) , + .clk_2_S_in ( p384 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6853 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6854 ) , .clk_3_S_in ( p1682 ) , + .clk_3_N_in ( p538 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6855 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6856 ) ) ; cby_1__1_ cby_7__2_ ( .chany_bottom_in ( sb_1__1__66_chany_top_out ) , .chany_top_in ( sb_1__1__67_chany_bottom_out ) , .ccff_head ( grid_clb_73_ccff_tail ) , @@ -81821,31 +83187,28 @@ cby_1__1_ cby_7__2_ ( .chany_bottom_in ( sb_1__1__66_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__73_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10408 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10409 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6857 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6858 ) , .Test_en_W_in ( Test_enWires[58] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10410 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10411 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6859 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6860 ) , .Test_en_E_out ( Test_enWires[59] ) , .prog_clk_0_W_in ( prog_clk_0_wires[257] ) , .prog_clk_0_S_out ( prog_clk_0_wires[258] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10412 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6861 ) , .prog_clk_2_N_in ( prog_clk_2_wires[73] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10413 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6862 ) , .prog_clk_2_S_out ( prog_clk_2_wires[74] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10414 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10415 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10416 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10417 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10418 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6863 ) , + .prog_clk_3_S_in ( p1430 ) , .prog_clk_3_N_in ( p298 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6864 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_2_N_in ( clk_2_wires[73] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10419 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6866 ) , .clk_2_S_out ( clk_2_wires[74] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10420 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10421 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10422 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10423 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10424 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6867 ) , .clk_3_S_in ( p1376 ) , + .clk_3_N_in ( p1162 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6868 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6869 ) ) ; cby_1__1_ cby_7__3_ ( .chany_bottom_in ( sb_1__1__67_chany_top_out ) , .chany_top_in ( sb_1__1__68_chany_bottom_out ) , .ccff_head ( grid_clb_74_ccff_tail ) , @@ -81868,31 +83231,25 @@ cby_1__1_ cby_7__3_ ( .chany_bottom_in ( sb_1__1__67_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__74_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10425 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10426 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6870 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6871 ) , .Test_en_W_in ( Test_enWires[80] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10427 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10428 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6872 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6873 ) , .Test_en_E_out ( Test_enWires[81] ) , .prog_clk_0_W_in ( prog_clk_0_wires[260] ) , .prog_clk_0_S_out ( prog_clk_0_wires[261] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10429 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10430 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10431 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10432 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10433 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10434 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10435 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10436 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10437 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10438 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10439 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10440 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10441 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10442 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10443 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10444 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10445 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6874 ) , + .prog_clk_2_N_in ( p2777 ) , .prog_clk_2_S_in ( p3153 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6875 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6876 ) , + .prog_clk_3_S_in ( p3206 ) , .prog_clk_3_N_in ( p2676 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6877 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6878 ) , .clk_2_N_in ( p2545 ) , + .clk_2_S_in ( p509 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6879 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6880 ) , .clk_3_S_in ( p2146 ) , + .clk_3_N_in ( p342 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6881 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6882 ) ) ; cby_1__1_ cby_7__4_ ( .chany_bottom_in ( sb_1__1__68_chany_top_out ) , .chany_top_in ( sb_1__1__69_chany_bottom_out ) , .ccff_head ( grid_clb_75_ccff_tail ) , @@ -81915,31 +83272,28 @@ cby_1__1_ cby_7__4_ ( .chany_bottom_in ( sb_1__1__68_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__75_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10446 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10447 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6883 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6884 ) , .Test_en_W_in ( Test_enWires[102] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10448 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10449 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6885 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6886 ) , .Test_en_E_out ( Test_enWires[103] ) , .prog_clk_0_W_in ( prog_clk_0_wires[263] ) , .prog_clk_0_S_out ( prog_clk_0_wires[264] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10450 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6887 ) , .prog_clk_2_N_in ( prog_clk_2_wires[84] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10451 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6888 ) , .prog_clk_2_S_out ( prog_clk_2_wires[85] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10452 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10453 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10454 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10455 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10456 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6889 ) , + .prog_clk_3_S_in ( p1815 ) , .prog_clk_3_N_in ( p1246 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6890 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6891 ) , .clk_2_N_in ( clk_2_wires[84] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10457 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6892 ) , .clk_2_S_out ( clk_2_wires[85] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10458 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10459 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10460 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10461 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10462 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6893 ) , .clk_3_S_in ( p1415 ) , + .clk_3_N_in ( p33 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6894 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6895 ) ) ; cby_1__1_ cby_7__5_ ( .chany_bottom_in ( sb_1__1__69_chany_top_out ) , .chany_top_in ( sb_1__1__70_chany_bottom_out ) , .ccff_head ( grid_clb_76_ccff_tail ) , @@ -81962,31 +83316,28 @@ cby_1__1_ cby_7__5_ ( .chany_bottom_in ( sb_1__1__69_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__76_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10463 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10464 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6896 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6897 ) , .Test_en_W_in ( Test_enWires[124] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10465 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10466 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6898 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6899 ) , .Test_en_E_out ( Test_enWires[125] ) , .prog_clk_0_W_in ( prog_clk_0_wires[266] ) , .prog_clk_0_S_out ( prog_clk_0_wires[267] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10467 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10468 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6900 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6901 ) , .prog_clk_2_S_in ( prog_clk_2_wires[82] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10469 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10470 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10471 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10472 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10473 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10474 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6902 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , .prog_clk_3_S_in ( p1516 ) , + .prog_clk_3_N_in ( p528 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6903 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6904 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6905 ) , .clk_2_S_in ( clk_2_wires[82] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10475 ) , - .clk_2_N_out ( clk_2_wires[83] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10476 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10477 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10478 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10479 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6906 ) , + .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p1516 ) , + .clk_3_N_in ( p1079 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6907 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6908 ) ) ; cby_1__1_ cby_7__6_ ( .chany_bottom_in ( sb_1__1__70_chany_top_out ) , .chany_top_in ( sb_1__1__71_chany_bottom_out ) , .ccff_head ( grid_clb_77_ccff_tail ) , @@ -82009,31 +83360,25 @@ cby_1__1_ cby_7__6_ ( .chany_bottom_in ( sb_1__1__70_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__77_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10480 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10481 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6909 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6910 ) , .Test_en_W_in ( Test_enWires[146] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10482 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10483 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6911 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6912 ) , .Test_en_E_out ( Test_enWires[147] ) , .prog_clk_0_W_in ( prog_clk_0_wires[269] ) , .prog_clk_0_S_out ( prog_clk_0_wires[270] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10484 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10485 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10486 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10487 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10488 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10489 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10490 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10491 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10492 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10493 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10494 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10495 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10496 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10497 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10498 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10499 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10500 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6913 ) , + .prog_clk_2_N_in ( p2598 ) , .prog_clk_2_S_in ( p2806 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6914 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6915 ) , + .prog_clk_3_S_in ( p2911 ) , .prog_clk_3_N_in ( p3456 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6916 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6917 ) , .clk_2_N_in ( p3465 ) , + .clk_2_S_in ( p763 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6918 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6919 ) , .clk_3_S_in ( p2045 ) , + .clk_3_N_in ( p1217 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6920 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6921 ) ) ; cby_1__1_ cby_7__7_ ( .chany_bottom_in ( sb_1__1__71_chany_top_out ) , .chany_top_in ( sb_1__1__72_chany_bottom_out ) , .ccff_head ( grid_clb_78_ccff_tail ) , @@ -82056,31 +83401,25 @@ cby_1__1_ cby_7__7_ ( .chany_bottom_in ( sb_1__1__71_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__78_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10501 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10502 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6922 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6923 ) , .Test_en_W_in ( Test_enWires[168] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10503 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10504 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6924 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6925 ) , .Test_en_E_out ( Test_enWires[169] ) , .prog_clk_0_W_in ( prog_clk_0_wires[272] ) , .prog_clk_0_S_out ( prog_clk_0_wires[273] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10505 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10506 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10507 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10508 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10509 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10510 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10511 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10512 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10513 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10514 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10515 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10516 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10517 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10518 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10519 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10520 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10521 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6926 ) , + .prog_clk_2_N_in ( p3027 ) , .prog_clk_2_S_in ( p2203 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6927 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6928 ) , + .prog_clk_3_S_in ( p2299 ) , .prog_clk_3_N_in ( p2968 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6929 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6930 ) , .clk_2_N_in ( p3029 ) , + .clk_2_S_in ( p596 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6931 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6932 ) , .clk_3_S_in ( p1838 ) , + .clk_3_N_in ( p821 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6933 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6934 ) ) ; cby_1__1_ cby_7__8_ ( .chany_bottom_in ( sb_1__1__72_chany_top_out ) , .chany_top_in ( sb_1__1__73_chany_bottom_out ) , .ccff_head ( grid_clb_79_ccff_tail ) , @@ -82103,31 +83442,28 @@ cby_1__1_ cby_7__8_ ( .chany_bottom_in ( sb_1__1__72_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__79_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10522 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10523 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6935 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6936 ) , .Test_en_W_in ( Test_enWires[190] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10524 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10525 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6937 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6938 ) , .Test_en_E_out ( Test_enWires[191] ) , .prog_clk_0_W_in ( prog_clk_0_wires[275] ) , .prog_clk_0_S_out ( prog_clk_0_wires[276] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10526 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6939 ) , .prog_clk_2_N_in ( prog_clk_2_wires[97] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10527 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_6940 ) , .prog_clk_2_S_out ( prog_clk_2_wires[98] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10528 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10529 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10530 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10531 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10532 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6941 ) , + .prog_clk_3_S_in ( p1784 ) , .prog_clk_3_N_in ( p627 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6942 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6943 ) , .clk_2_N_in ( clk_2_wires[97] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10533 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_6944 ) , .clk_2_S_out ( clk_2_wires[98] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10534 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10535 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10536 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10537 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10538 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6945 ) , .clk_3_S_in ( p2129 ) , + .clk_3_N_in ( p1116 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6946 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6947 ) ) ; cby_1__1_ cby_7__9_ ( .chany_bottom_in ( sb_1__1__73_chany_top_out ) , .chany_top_in ( sb_1__1__74_chany_bottom_out ) , .ccff_head ( grid_clb_80_ccff_tail ) , @@ -82150,31 +83486,28 @@ cby_1__1_ cby_7__9_ ( .chany_bottom_in ( sb_1__1__73_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__80_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10539 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10540 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6948 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6949 ) , .Test_en_W_in ( Test_enWires[212] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10541 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10542 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6950 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6951 ) , .Test_en_E_out ( Test_enWires[213] ) , .prog_clk_0_W_in ( prog_clk_0_wires[278] ) , .prog_clk_0_S_out ( prog_clk_0_wires[279] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10543 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10544 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6952 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6953 ) , .prog_clk_2_S_in ( prog_clk_2_wires[95] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10545 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10546 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10547 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10548 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10549 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10550 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6954 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , .prog_clk_3_S_in ( p2172 ) , + .prog_clk_3_N_in ( p386 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6955 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6956 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6957 ) , .clk_2_S_in ( clk_2_wires[95] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10551 ) , - .clk_2_N_out ( clk_2_wires[96] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10552 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10553 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10554 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10555 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6958 ) , + .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p2009 ) , + .clk_3_N_in ( p1169 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6959 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6960 ) ) ; cby_1__1_ cby_7__10_ ( .chany_bottom_in ( sb_1__1__74_chany_top_out ) , .chany_top_in ( sb_1__1__75_chany_bottom_out ) , .ccff_head ( grid_clb_81_ccff_tail ) , @@ -82197,31 +83530,25 @@ cby_1__1_ cby_7__10_ ( .chany_bottom_in ( sb_1__1__74_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__81_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10556 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10557 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6961 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6962 ) , .Test_en_W_in ( Test_enWires[234] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10558 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10559 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6963 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6964 ) , .Test_en_E_out ( Test_enWires[235] ) , .prog_clk_0_W_in ( prog_clk_0_wires[281] ) , .prog_clk_0_S_out ( prog_clk_0_wires[282] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10560 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10561 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10562 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10563 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10564 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10565 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10566 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10567 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10568 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10569 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10570 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10571 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10572 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10573 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10574 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10575 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10576 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6965 ) , + .prog_clk_2_N_in ( p3332 ) , .prog_clk_2_S_in ( p2224 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6966 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6967 ) , + .prog_clk_3_S_in ( p2352 ) , .prog_clk_3_N_in ( p3310 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6968 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6969 ) , .clk_2_N_in ( p3005 ) , + .clk_2_S_in ( p922 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6970 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6971 ) , .clk_3_S_in ( p2346 ) , + .clk_3_N_in ( p537 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6972 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6973 ) ) ; cby_1__1_ cby_7__11_ ( .chany_bottom_in ( sb_1__1__75_chany_top_out ) , .chany_top_in ( sb_1__1__76_chany_bottom_out ) , .ccff_head ( grid_clb_82_ccff_tail ) , @@ -82244,31 +83571,28 @@ cby_1__1_ cby_7__11_ ( .chany_bottom_in ( sb_1__1__75_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__82_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10577 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10578 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6974 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6975 ) , .Test_en_W_in ( Test_enWires[256] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10579 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10580 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6976 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6977 ) , .Test_en_E_out ( Test_enWires[257] ) , .prog_clk_0_W_in ( prog_clk_0_wires[284] ) , .prog_clk_0_S_out ( prog_clk_0_wires[285] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10581 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10582 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_6978 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_6979 ) , .prog_clk_2_S_in ( prog_clk_2_wires[108] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10583 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10584 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10585 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10586 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10587 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10588 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6980 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , .prog_clk_3_S_in ( p1831 ) , + .prog_clk_3_N_in ( p691 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6981 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6982 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_6983 ) , .clk_2_S_in ( clk_2_wires[108] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10589 ) , - .clk_2_N_out ( clk_2_wires[109] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10590 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10591 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10592 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10593 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6984 ) , + .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p2341 ) , + .clk_3_N_in ( p875 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6985 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6986 ) ) ; cby_1__1_ cby_7__12_ ( .chany_bottom_in ( sb_1__1__76_chany_top_out ) , .chany_top_in ( sb_1__12__6_chany_bottom_out ) , .ccff_head ( grid_clb_83_ccff_tail ) , @@ -82291,31 +83615,25 @@ cby_1__1_ cby_7__12_ ( .chany_bottom_in ( sb_1__1__76_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__83_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10594 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10595 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6987 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_6988 ) , .Test_en_W_in ( Test_enWires[278] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10596 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10597 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_6989 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_6990 ) , .Test_en_E_out ( Test_enWires[279] ) , .prog_clk_0_W_in ( prog_clk_0_wires[287] ) , .prog_clk_0_S_out ( prog_clk_0_wires[288] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10598 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10599 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10600 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10601 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10602 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10603 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10604 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10605 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10606 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10607 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10608 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10609 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10610 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10611 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10612 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10613 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , .prog_clk_2_N_in ( p3293 ) , + .prog_clk_2_S_in ( p2491 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_6991 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_6992 ) , + .prog_clk_3_S_in ( p2582 ) , .prog_clk_3_N_in ( p3244 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_6993 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_6994 ) , .clk_2_N_in ( p2778 ) , + .clk_2_S_in ( p660 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_6995 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_6996 ) , .clk_3_S_in ( p1830 ) , + .clk_3_N_in ( p996 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_6997 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_6998 ) ) ; cby_1__1_ cby_8__1_ ( .chany_bottom_in ( sb_1__0__7_chany_top_out ) , .chany_top_in ( sb_1__1__77_chany_bottom_out ) , .ccff_head ( grid_clb_84_ccff_tail ) , @@ -82338,31 +83656,25 @@ cby_1__1_ cby_8__1_ ( .chany_bottom_in ( sb_1__0__7_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__84_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10614 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10615 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_6999 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7000 ) , .Test_en_W_in ( Test_enWires[38] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10616 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10617 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7001 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7002 ) , .Test_en_E_out ( Test_enWires[39] ) , .prog_clk_0_W_in ( prog_clk_0_wires[292] ) , .prog_clk_0_S_out ( prog_clk_0_wires[293] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10618 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10619 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10620 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10621 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10622 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10623 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10624 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10625 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10626 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10627 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10628 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10629 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10630 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10631 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10632 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10633 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10634 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7003 ) , + .prog_clk_2_N_in ( p3386 ) , .prog_clk_2_S_in ( p3077 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7004 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7005 ) , + .prog_clk_3_S_in ( p3107 ) , .prog_clk_3_N_in ( p3359 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7006 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7007 ) , .clk_2_N_in ( p2106 ) , + .clk_2_S_in ( p2685 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7008 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7009 ) , .clk_3_S_in ( p2746 ) , + .clk_3_N_in ( p801 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7010 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7011 ) ) ; cby_1__1_ cby_8__2_ ( .chany_bottom_in ( sb_1__1__77_chany_top_out ) , .chany_top_in ( sb_1__1__78_chany_bottom_out ) , .ccff_head ( grid_clb_85_ccff_tail ) , @@ -82385,31 +83697,25 @@ cby_1__1_ cby_8__2_ ( .chany_bottom_in ( sb_1__1__77_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__85_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10635 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10636 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7012 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7013 ) , .Test_en_W_in ( Test_enWires[60] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10637 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10638 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7014 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7015 ) , .Test_en_E_out ( Test_enWires[61] ) , .prog_clk_0_W_in ( prog_clk_0_wires[295] ) , .prog_clk_0_S_out ( prog_clk_0_wires[296] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10639 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10640 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10641 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10642 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10643 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10644 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10645 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10646 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10647 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10648 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10649 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10650 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10651 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10652 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10653 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10654 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10655 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7016 ) , + .prog_clk_2_N_in ( p3193 ) , .prog_clk_2_S_in ( p979 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7017 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7018 ) , + .prog_clk_3_S_in ( p1713 ) , .prog_clk_3_N_in ( p3176 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7019 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7020 ) , .clk_2_N_in ( p2918 ) , + .clk_2_S_in ( p34 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7021 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7022 ) , .clk_3_S_in ( p1856 ) , + .clk_3_N_in ( p710 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7023 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7024 ) ) ; cby_1__1_ cby_8__3_ ( .chany_bottom_in ( sb_1__1__78_chany_top_out ) , .chany_top_in ( sb_1__1__79_chany_bottom_out ) , .ccff_head ( grid_clb_86_ccff_tail ) , @@ -82432,30 +83738,27 @@ cby_1__1_ cby_8__3_ ( .chany_bottom_in ( sb_1__1__78_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__86_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10656 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10657 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7025 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7026 ) , .Test_en_W_in ( Test_enWires[82] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10658 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10659 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7027 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7028 ) , .Test_en_E_out ( Test_enWires[83] ) , .prog_clk_0_W_in ( prog_clk_0_wires[298] ) , .prog_clk_0_S_out ( prog_clk_0_wires[299] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10660 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10661 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10662 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10663 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10664 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10665 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7029 ) , + .prog_clk_2_N_in ( p2085 ) , .prog_clk_2_S_in ( p146 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7030 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7031 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7032 ) , .prog_clk_3_N_in ( prog_clk_3_wires[42] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10666 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10667 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10668 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10669 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10670 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10671 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7033 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( p2085 ) , + .clk_2_S_in ( p468 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7034 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7035 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7036 ) , .clk_3_N_in ( clk_3_wires[42] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10672 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7037 ) , .clk_3_S_out ( clk_3_wires[43] ) ) ; cby_1__1_ cby_8__4_ ( .chany_bottom_in ( sb_1__1__79_chany_top_out ) , .chany_top_in ( sb_1__1__80_chany_bottom_out ) , @@ -82479,30 +83782,27 @@ cby_1__1_ cby_8__4_ ( .chany_bottom_in ( sb_1__1__79_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__87_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10673 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10674 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7038 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7039 ) , .Test_en_W_in ( Test_enWires[104] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10675 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10676 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7040 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7041 ) , .Test_en_E_out ( Test_enWires[105] ) , .prog_clk_0_W_in ( prog_clk_0_wires[301] ) , .prog_clk_0_S_out ( prog_clk_0_wires[302] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10677 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10678 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10679 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10680 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10681 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10682 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7042 ) , + .prog_clk_2_N_in ( p1225 ) , .prog_clk_2_S_in ( p243 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7043 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7044 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7045 ) , .prog_clk_3_N_in ( prog_clk_3_wires[38] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10683 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10684 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10685 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10686 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10687 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10688 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7046 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( p1225 ) , + .clk_2_S_in ( p1893 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7047 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7048 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7049 ) , .clk_3_N_in ( clk_3_wires[38] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10689 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7050 ) , .clk_3_S_out ( clk_3_wires[39] ) ) ; cby_1__1_ cby_8__5_ ( .chany_bottom_in ( sb_1__1__80_chany_top_out ) , .chany_top_in ( sb_1__1__81_chany_bottom_out ) , @@ -82526,30 +83826,27 @@ cby_1__1_ cby_8__5_ ( .chany_bottom_in ( sb_1__1__80_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__88_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10690 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10691 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7051 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7052 ) , .Test_en_W_in ( Test_enWires[126] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10692 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10693 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7053 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7054 ) , .Test_en_E_out ( Test_enWires[127] ) , .prog_clk_0_W_in ( prog_clk_0_wires[304] ) , .prog_clk_0_S_out ( prog_clk_0_wires[305] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10694 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10695 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10696 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10697 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10698 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10699 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7055 ) , + .prog_clk_2_N_in ( p1873 ) , .prog_clk_2_S_in ( p143 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7056 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7057 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7058 ) , .prog_clk_3_N_in ( prog_clk_3_wires[32] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10700 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10701 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10702 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10703 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10704 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10705 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7059 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( p1873 ) , + .clk_2_S_in ( p1918 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7060 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7061 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7062 ) , .clk_3_N_in ( clk_3_wires[32] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10706 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7063 ) , .clk_3_S_out ( clk_3_wires[33] ) ) ; cby_1__1_ cby_8__6_ ( .chany_bottom_in ( sb_1__1__81_chany_top_out ) , .chany_top_in ( sb_1__1__82_chany_bottom_out ) , @@ -82573,30 +83870,27 @@ cby_1__1_ cby_8__6_ ( .chany_bottom_in ( sb_1__1__81_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__89_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10707 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10708 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7064 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7065 ) , .Test_en_W_in ( Test_enWires[148] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10709 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10710 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7066 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7067 ) , .Test_en_E_out ( Test_enWires[149] ) , .prog_clk_0_W_in ( prog_clk_0_wires[307] ) , .prog_clk_0_S_out ( prog_clk_0_wires[308] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10711 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10712 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10713 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10714 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10715 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10716 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7068 ) , + .prog_clk_2_N_in ( p2287 ) , .prog_clk_2_S_in ( p474 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7069 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7070 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7071 ) , .prog_clk_3_N_in ( prog_clk_3_wires[28] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10717 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10718 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10719 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10720 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10721 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10722 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7072 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( p2381 ) , + .clk_2_S_in ( p1004 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7073 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7074 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7075 ) , .clk_3_N_in ( clk_3_wires[28] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10723 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7076 ) , .clk_3_S_out ( clk_3_wires[29] ) ) ; cby_1__1_ cby_8__7_ ( .chany_bottom_in ( sb_1__1__82_chany_top_out ) , .chany_top_in ( sb_1__1__83_chany_bottom_out ) , @@ -82620,31 +83914,28 @@ cby_1__1_ cby_8__7_ ( .chany_bottom_in ( sb_1__1__82_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__90_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10724 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10725 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7077 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7078 ) , .Test_en_W_in ( Test_enWires[170] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10726 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10727 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7079 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7080 ) , .Test_en_E_out ( Test_enWires[171] ) , .prog_clk_0_W_in ( prog_clk_0_wires[310] ) , .prog_clk_0_S_out ( prog_clk_0_wires[311] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10728 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10729 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10730 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10731 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10732 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7081 ) , + .prog_clk_2_N_in ( p2584 ) , .prog_clk_2_S_in ( p292 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7082 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7083 ) , .prog_clk_3_S_in ( prog_clk_3_wires[26] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10733 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7084 ) , .prog_clk_3_N_out ( prog_clk_3_wires[27] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10734 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10735 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10736 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10737 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10738 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7085 ) , .clk_2_N_in ( p2508 ) , + .clk_2_S_in ( p1051 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7086 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7087 ) , .clk_3_S_in ( clk_3_wires[26] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10739 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7088 ) , .clk_3_N_out ( clk_3_wires[27] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10740 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7089 ) ) ; cby_1__1_ cby_8__8_ ( .chany_bottom_in ( sb_1__1__83_chany_top_out ) , .chany_top_in ( sb_1__1__84_chany_bottom_out ) , .ccff_head ( grid_clb_91_ccff_tail ) , @@ -82667,31 +83958,28 @@ cby_1__1_ cby_8__8_ ( .chany_bottom_in ( sb_1__1__83_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__91_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10741 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10742 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7090 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7091 ) , .Test_en_W_in ( Test_enWires[192] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10743 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10744 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7092 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7093 ) , .Test_en_E_out ( Test_enWires[193] ) , .prog_clk_0_W_in ( prog_clk_0_wires[313] ) , .prog_clk_0_S_out ( prog_clk_0_wires[314] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10745 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10746 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10747 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10748 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10749 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7094 ) , + .prog_clk_2_N_in ( p1586 ) , .prog_clk_2_S_in ( p469 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7095 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7096 ) , .prog_clk_3_S_in ( prog_clk_3_wires[30] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10750 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7097 ) , .prog_clk_3_N_out ( prog_clk_3_wires[31] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10751 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10752 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10753 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10754 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10755 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7098 ) , .clk_2_N_in ( p1586 ) , + .clk_2_S_in ( p980 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7099 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7100 ) , .clk_3_S_in ( clk_3_wires[30] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10756 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7101 ) , .clk_3_N_out ( clk_3_wires[31] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10757 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7102 ) ) ; cby_1__1_ cby_8__9_ ( .chany_bottom_in ( sb_1__1__84_chany_top_out ) , .chany_top_in ( sb_1__1__85_chany_bottom_out ) , .ccff_head ( grid_clb_92_ccff_tail ) , @@ -82714,31 +84002,28 @@ cby_1__1_ cby_8__9_ ( .chany_bottom_in ( sb_1__1__84_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__92_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10758 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10759 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7103 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7104 ) , .Test_en_W_in ( Test_enWires[214] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10760 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10761 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7105 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7106 ) , .Test_en_E_out ( Test_enWires[215] ) , .prog_clk_0_W_in ( prog_clk_0_wires[316] ) , .prog_clk_0_S_out ( prog_clk_0_wires[317] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10762 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10763 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10764 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10765 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10766 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7107 ) , + .prog_clk_2_N_in ( p1645 ) , .prog_clk_2_S_in ( p388 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7108 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7109 ) , .prog_clk_3_S_in ( prog_clk_3_wires[36] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10767 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7110 ) , .prog_clk_3_N_out ( prog_clk_3_wires[37] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10768 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10769 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10770 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10771 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10772 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7111 ) , .clk_2_N_in ( p1645 ) , + .clk_2_S_in ( p1033 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7112 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7113 ) , .clk_3_S_in ( clk_3_wires[36] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10773 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7114 ) , .clk_3_N_out ( clk_3_wires[37] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10774 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7115 ) ) ; cby_1__1_ cby_8__10_ ( .chany_bottom_in ( sb_1__1__85_chany_top_out ) , .chany_top_in ( sb_1__1__86_chany_bottom_out ) , .ccff_head ( grid_clb_93_ccff_tail ) , @@ -82761,31 +84046,28 @@ cby_1__1_ cby_8__10_ ( .chany_bottom_in ( sb_1__1__85_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__93_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10775 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10776 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7116 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7117 ) , .Test_en_W_in ( Test_enWires[236] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10777 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10778 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7118 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7119 ) , .Test_en_E_out ( Test_enWires[237] ) , .prog_clk_0_W_in ( prog_clk_0_wires[319] ) , .prog_clk_0_S_out ( prog_clk_0_wires[320] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10779 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10780 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10781 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10782 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10783 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7120 ) , + .prog_clk_2_N_in ( p1850 ) , .prog_clk_2_S_in ( p1141 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7121 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7122 ) , .prog_clk_3_S_in ( prog_clk_3_wires[40] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10784 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7123 ) , .prog_clk_3_N_out ( prog_clk_3_wires[41] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10785 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10786 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10787 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10788 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10789 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7124 ) , .clk_2_N_in ( p1695 ) , + .clk_2_S_in ( p313 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7125 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7126 ) , .clk_3_S_in ( clk_3_wires[40] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10790 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7127 ) , .clk_3_N_out ( clk_3_wires[41] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10791 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7128 ) ) ; cby_1__1_ cby_8__11_ ( .chany_bottom_in ( sb_1__1__86_chany_top_out ) , .chany_top_in ( sb_1__1__87_chany_bottom_out ) , .ccff_head ( grid_clb_94_ccff_tail ) , @@ -82808,31 +84090,25 @@ cby_1__1_ cby_8__11_ ( .chany_bottom_in ( sb_1__1__86_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__94_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10792 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10793 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7129 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7130 ) , .Test_en_W_in ( Test_enWires[258] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10794 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10795 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7131 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7132 ) , .Test_en_E_out ( Test_enWires[259] ) , .prog_clk_0_W_in ( prog_clk_0_wires[322] ) , .prog_clk_0_S_out ( prog_clk_0_wires[323] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10796 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10797 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10798 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10799 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10800 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10801 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10802 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10803 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10804 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10805 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10806 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10807 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10808 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10809 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10810 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10811 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10812 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7133 ) , + .prog_clk_2_N_in ( p2733 ) , .prog_clk_2_S_in ( p3184 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7134 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7135 ) , + .prog_clk_3_S_in ( p3198 ) , .prog_clk_3_N_in ( p2661 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7136 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7137 ) , .clk_2_N_in ( p2754 ) , + .clk_2_S_in ( p473 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7138 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7139 ) , .clk_3_S_in ( p2301 ) , + .clk_3_N_in ( p1151 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7140 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7141 ) ) ; cby_1__1_ cby_8__12_ ( .chany_bottom_in ( sb_1__1__87_chany_top_out ) , .chany_top_in ( sb_1__12__7_chany_bottom_out ) , .ccff_head ( grid_clb_95_ccff_tail ) , @@ -82855,31 +84131,25 @@ cby_1__1_ cby_8__12_ ( .chany_bottom_in ( sb_1__1__87_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__95_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10813 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10814 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7142 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7143 ) , .Test_en_W_in ( Test_enWires[280] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10815 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10816 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7144 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7145 ) , .Test_en_E_out ( Test_enWires[281] ) , .prog_clk_0_W_in ( prog_clk_0_wires[325] ) , .prog_clk_0_S_out ( prog_clk_0_wires[326] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10817 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10818 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10819 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10820 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10821 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10822 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10823 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10824 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10825 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10826 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10827 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10828 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10829 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10830 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10831 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10832 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , .prog_clk_2_N_in ( p3103 ) , + .prog_clk_2_S_in ( p2650 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7146 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7147 ) , + .prog_clk_3_S_in ( p2740 ) , .prog_clk_3_N_in ( p3063 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7148 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7149 ) , .clk_2_N_in ( p2888 ) , + .clk_2_S_in ( p712 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7150 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_3_S_in ( p1451 ) , + .clk_3_N_in ( p35 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7152 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7153 ) ) ; cby_1__1_ cby_9__1_ ( .chany_bottom_in ( sb_1__0__8_chany_top_out ) , .chany_top_in ( sb_1__1__88_chany_bottom_out ) , .ccff_head ( grid_clb_96_ccff_tail ) , @@ -82902,31 +84172,25 @@ cby_1__1_ cby_9__1_ ( .chany_bottom_in ( sb_1__0__8_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__96_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10833 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10834 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7154 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7155 ) , .Test_en_W_in ( Test_enWires[40] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10835 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10836 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7156 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7157 ) , .Test_en_E_out ( Test_enWires[41] ) , .prog_clk_0_W_in ( prog_clk_0_wires[330] ) , .prog_clk_0_S_out ( prog_clk_0_wires[331] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10837 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10838 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10839 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10840 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10841 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10842 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10843 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10844 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10845 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10846 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10847 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10848 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10849 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10850 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10851 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10852 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10853 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7158 ) , + .prog_clk_2_N_in ( p3220 ) , .prog_clk_2_S_in ( p2827 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7159 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7160 ) , + .prog_clk_3_S_in ( p2869 ) , .prog_clk_3_N_in ( p3169 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7161 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7162 ) , .clk_2_N_in ( p2705 ) , + .clk_2_S_in ( p72 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7163 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7164 ) , .clk_3_S_in ( p1813 ) , + .clk_3_N_in ( p616 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7165 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7166 ) ) ; cby_1__1_ cby_9__2_ ( .chany_bottom_in ( sb_1__1__88_chany_top_out ) , .chany_top_in ( sb_1__1__89_chany_bottom_out ) , .ccff_head ( grid_clb_97_ccff_tail ) , @@ -82949,31 +84213,28 @@ cby_1__1_ cby_9__2_ ( .chany_bottom_in ( sb_1__1__88_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__97_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10854 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10855 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7167 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7168 ) , .Test_en_W_in ( Test_enWires[62] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10856 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10857 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7169 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7170 ) , .Test_en_E_out ( Test_enWires[63] ) , .prog_clk_0_W_in ( prog_clk_0_wires[333] ) , .prog_clk_0_S_out ( prog_clk_0_wires[334] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10858 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7171 ) , .prog_clk_2_N_in ( prog_clk_2_wires[75] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10859 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7172 ) , .prog_clk_2_S_out ( prog_clk_2_wires[76] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10860 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10861 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10862 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10863 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10864 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7173 ) , + .prog_clk_3_S_in ( p1998 ) , .prog_clk_3_N_in ( p1327 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7174 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7175 ) , .clk_2_N_in ( clk_2_wires[75] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10865 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7176 ) , .clk_2_S_out ( clk_2_wires[76] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10866 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10867 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10868 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10869 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10870 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7177 ) , .clk_3_S_in ( p1998 ) , + .clk_3_N_in ( p713 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7178 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7179 ) ) ; cby_1__1_ cby_9__3_ ( .chany_bottom_in ( sb_1__1__89_chany_top_out ) , .chany_top_in ( sb_1__1__90_chany_bottom_out ) , .ccff_head ( grid_clb_98_ccff_tail ) , @@ -82996,31 +84257,25 @@ cby_1__1_ cby_9__3_ ( .chany_bottom_in ( sb_1__1__89_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__98_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10871 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10872 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7180 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7181 ) , .Test_en_W_in ( Test_enWires[84] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10873 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10874 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7182 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7183 ) , .Test_en_E_out ( Test_enWires[85] ) , .prog_clk_0_W_in ( prog_clk_0_wires[336] ) , .prog_clk_0_S_out ( prog_clk_0_wires[337] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10875 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10876 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10877 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10878 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10879 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10880 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10881 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10882 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10883 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10884 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10885 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10886 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10887 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10888 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10889 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10890 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10891 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7184 ) , + .prog_clk_2_N_in ( p3229 ) , .prog_clk_2_S_in ( p3236 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7185 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7186 ) , + .prog_clk_3_S_in ( p3282 ) , .prog_clk_3_N_in ( p3188 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7187 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7188 ) , .clk_2_N_in ( p3098 ) , + .clk_2_S_in ( p351 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7189 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7190 ) , .clk_3_S_in ( p2370 ) , + .clk_3_N_in ( p1315 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7191 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7192 ) ) ; cby_1__1_ cby_9__4_ ( .chany_bottom_in ( sb_1__1__90_chany_top_out ) , .chany_top_in ( sb_1__1__91_chany_bottom_out ) , .ccff_head ( grid_clb_99_ccff_tail ) , @@ -83043,31 +84298,28 @@ cby_1__1_ cby_9__4_ ( .chany_bottom_in ( sb_1__1__90_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__99_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10892 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10893 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7193 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7194 ) , .Test_en_W_in ( Test_enWires[106] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10894 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10895 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7195 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7196 ) , .Test_en_E_out ( Test_enWires[107] ) , .prog_clk_0_W_in ( prog_clk_0_wires[339] ) , .prog_clk_0_S_out ( prog_clk_0_wires[340] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10896 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7197 ) , .prog_clk_2_N_in ( prog_clk_2_wires[88] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10897 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7198 ) , .prog_clk_2_S_out ( prog_clk_2_wires[89] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10898 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10899 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10900 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10901 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10902 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7199 ) , + .prog_clk_3_S_in ( p793 ) , .prog_clk_3_N_in ( p1041 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7200 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7201 ) , .clk_2_N_in ( clk_2_wires[88] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10903 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_2_S_out ( clk_2_wires[89] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10904 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10905 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10906 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10907 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10908 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7203 ) , .clk_3_S_in ( p1603 ) , + .clk_3_N_in ( p66 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7204 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7205 ) ) ; cby_1__1_ cby_9__5_ ( .chany_bottom_in ( sb_1__1__91_chany_top_out ) , .chany_top_in ( sb_1__1__92_chany_bottom_out ) , .ccff_head ( grid_clb_100_ccff_tail ) , @@ -83090,31 +84342,28 @@ cby_1__1_ cby_9__5_ ( .chany_bottom_in ( sb_1__1__91_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__100_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10909 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10910 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7206 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7207 ) , .Test_en_W_in ( Test_enWires[128] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10911 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10912 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7208 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7209 ) , .Test_en_E_out ( Test_enWires[129] ) , .prog_clk_0_W_in ( prog_clk_0_wires[342] ) , .prog_clk_0_S_out ( prog_clk_0_wires[343] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10913 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10914 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7210 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7211 ) , .prog_clk_2_S_in ( prog_clk_2_wires[86] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10915 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10916 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10917 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10918 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10919 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10920 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7212 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , .prog_clk_3_S_in ( p1479 ) , + .prog_clk_3_N_in ( p1179 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7213 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7214 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_2_S_in ( clk_2_wires[86] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10921 ) , - .clk_2_N_out ( clk_2_wires[87] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10922 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10923 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10924 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10925 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7216 ) , + .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p1479 ) , + .clk_3_N_in ( p15 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7217 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7218 ) ) ; cby_1__1_ cby_9__6_ ( .chany_bottom_in ( sb_1__1__92_chany_top_out ) , .chany_top_in ( sb_1__1__93_chany_bottom_out ) , .ccff_head ( grid_clb_101_ccff_tail ) , @@ -83137,31 +84386,25 @@ cby_1__1_ cby_9__6_ ( .chany_bottom_in ( sb_1__1__92_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__101_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10926 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10927 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7219 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7220 ) , .Test_en_W_in ( Test_enWires[150] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10928 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10929 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7221 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7222 ) , .Test_en_E_out ( Test_enWires[151] ) , .prog_clk_0_W_in ( prog_clk_0_wires[345] ) , .prog_clk_0_S_out ( prog_clk_0_wires[346] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10930 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10931 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10932 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10933 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10934 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10935 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10936 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10937 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10938 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10939 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10940 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10941 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10942 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10943 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10944 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10945 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10946 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7223 ) , + .prog_clk_2_N_in ( p3109 ) , .prog_clk_2_S_in ( p2946 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7224 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7225 ) , + .prog_clk_3_S_in ( p3002 ) , .prog_clk_3_N_in ( p3080 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7226 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7227 ) , .clk_2_N_in ( p2585 ) , + .clk_2_S_in ( p440 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7228 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7229 ) , .clk_3_S_in ( p2717 ) , + .clk_3_N_in ( p1233 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7230 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7231 ) ) ; cby_1__1_ cby_9__7_ ( .chany_bottom_in ( sb_1__1__93_chany_top_out ) , .chany_top_in ( sb_1__1__94_chany_bottom_out ) , .ccff_head ( grid_clb_102_ccff_tail ) , @@ -83184,31 +84427,25 @@ cby_1__1_ cby_9__7_ ( .chany_bottom_in ( sb_1__1__93_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__102_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10947 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10948 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7232 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7233 ) , .Test_en_W_in ( Test_enWires[172] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10949 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10950 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7234 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7235 ) , .Test_en_E_out ( Test_enWires[173] ) , .prog_clk_0_W_in ( prog_clk_0_wires[348] ) , .prog_clk_0_S_out ( prog_clk_0_wires[349] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10951 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10952 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10953 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10954 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10955 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10956 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10957 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10958 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10959 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10960 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10961 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10962 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10963 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10964 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10965 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10966 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10967 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7236 ) , + .prog_clk_2_N_in ( p3297 ) , .prog_clk_2_S_in ( p2954 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7237 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7238 ) , + .prog_clk_3_S_in ( p3019 ) , .prog_clk_3_N_in ( p3356 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7239 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7240 ) , .clk_2_N_in ( p3377 ) , + .clk_2_S_in ( p522 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7241 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7242 ) , .clk_3_S_in ( p1852 ) , + .clk_3_N_in ( p632 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7243 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7244 ) ) ; cby_1__1_ cby_9__8_ ( .chany_bottom_in ( sb_1__1__94_chany_top_out ) , .chany_top_in ( sb_1__1__95_chany_bottom_out ) , .ccff_head ( grid_clb_103_ccff_tail ) , @@ -83231,31 +84468,28 @@ cby_1__1_ cby_9__8_ ( .chany_bottom_in ( sb_1__1__94_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__103_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10968 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10969 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7245 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7246 ) , .Test_en_W_in ( Test_enWires[194] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10970 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10971 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7247 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7248 ) , .Test_en_E_out ( Test_enWires[195] ) , .prog_clk_0_W_in ( prog_clk_0_wires[351] ) , .prog_clk_0_S_out ( prog_clk_0_wires[352] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10972 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7249 ) , .prog_clk_2_N_in ( prog_clk_2_wires[101] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10973 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7250 ) , .prog_clk_2_S_out ( prog_clk_2_wires[102] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10974 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10975 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10976 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10977 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10978 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7251 ) , + .prog_clk_3_S_in ( p1624 ) , .prog_clk_3_N_in ( p69 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7252 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7253 ) , .clk_2_N_in ( clk_2_wires[101] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10979 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7254 ) , .clk_2_S_out ( clk_2_wires[102] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10980 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10981 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10982 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10983 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10984 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7255 ) , .clk_3_S_in ( p2515 ) , + .clk_3_N_in ( p1258 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7256 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7257 ) ) ; cby_1__1_ cby_9__9_ ( .chany_bottom_in ( sb_1__1__95_chany_top_out ) , .chany_top_in ( sb_1__1__96_chany_bottom_out ) , .ccff_head ( grid_clb_104_ccff_tail ) , @@ -83278,31 +84512,28 @@ cby_1__1_ cby_9__9_ ( .chany_bottom_in ( sb_1__1__95_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__104_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10985 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10986 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7258 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7259 ) , .Test_en_W_in ( Test_enWires[216] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10987 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10988 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7260 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7261 ) , .Test_en_E_out ( Test_enWires[217] ) , .prog_clk_0_W_in ( prog_clk_0_wires[354] ) , .prog_clk_0_S_out ( prog_clk_0_wires[355] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10989 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10990 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7262 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7263 ) , .prog_clk_2_S_in ( prog_clk_2_wires[99] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10991 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_10992 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_10993 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10994 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10995 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10996 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7264 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , .prog_clk_3_S_in ( p1757 ) , + .prog_clk_3_N_in ( p479 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7265 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7266 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7267 ) , .clk_2_S_in ( clk_2_wires[99] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10997 ) , - .clk_2_N_out ( clk_2_wires[100] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_10998 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_10999 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11000 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11001 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7268 ) , + .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1987 ) , + .clk_3_N_in ( p562 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7269 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7270 ) ) ; cby_1__1_ cby_9__10_ ( .chany_bottom_in ( sb_1__1__96_chany_top_out ) , .chany_top_in ( sb_1__1__97_chany_bottom_out ) , .ccff_head ( grid_clb_105_ccff_tail ) , @@ -83325,31 +84556,25 @@ cby_1__1_ cby_9__10_ ( .chany_bottom_in ( sb_1__1__96_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__105_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11002 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11003 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7271 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7272 ) , .Test_en_W_in ( Test_enWires[238] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11004 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11005 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7273 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7274 ) , .Test_en_E_out ( Test_enWires[239] ) , .prog_clk_0_W_in ( prog_clk_0_wires[357] ) , .prog_clk_0_S_out ( prog_clk_0_wires[358] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11006 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11007 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11008 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11009 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11010 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11011 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11012 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11013 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11014 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11015 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11016 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11017 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11018 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11019 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11020 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11021 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11022 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7275 ) , + .prog_clk_2_N_in ( p3119 ) , .prog_clk_2_S_in ( p3255 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7276 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7277 ) , + .prog_clk_3_S_in ( p3295 ) , .prog_clk_3_N_in ( p3307 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7278 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_2_N_in ( p3335 ) , + .clk_2_S_in ( p251 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7280 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_3_S_in ( p2547 ) , + .clk_3_N_in ( p294 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7282 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7283 ) ) ; cby_1__1_ cby_9__11_ ( .chany_bottom_in ( sb_1__1__97_chany_top_out ) , .chany_top_in ( sb_1__1__98_chany_bottom_out ) , .ccff_head ( grid_clb_106_ccff_tail ) , @@ -83372,31 +84597,28 @@ cby_1__1_ cby_9__11_ ( .chany_bottom_in ( sb_1__1__97_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__106_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11023 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11024 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7284 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7285 ) , .Test_en_W_in ( Test_enWires[260] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11025 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11026 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7286 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7287 ) , .Test_en_E_out ( Test_enWires[261] ) , .prog_clk_0_W_in ( prog_clk_0_wires[360] ) , .prog_clk_0_S_out ( prog_clk_0_wires[361] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11027 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11028 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7288 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7289 ) , .prog_clk_2_S_in ( prog_clk_2_wires[110] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11029 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11030 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11031 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11032 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11033 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11034 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7290 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , .prog_clk_3_S_in ( p1880 ) , + .prog_clk_3_N_in ( p819 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7291 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7292 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7293 ) , .clk_2_S_in ( clk_2_wires[110] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11035 ) , - .clk_2_N_out ( clk_2_wires[111] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11036 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11037 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11038 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11039 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7294 ) , + .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p2760 ) , + .clk_3_N_in ( p829 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7295 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7296 ) ) ; cby_1__1_ cby_9__12_ ( .chany_bottom_in ( sb_1__1__98_chany_top_out ) , .chany_top_in ( sb_1__12__8_chany_bottom_out ) , .ccff_head ( grid_clb_107_ccff_tail ) , @@ -83419,31 +84641,25 @@ cby_1__1_ cby_9__12_ ( .chany_bottom_in ( sb_1__1__98_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__107_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11040 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11041 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7297 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7298 ) , .Test_en_W_in ( Test_enWires[282] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11042 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11043 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7299 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7300 ) , .Test_en_E_out ( Test_enWires[283] ) , .prog_clk_0_W_in ( prog_clk_0_wires[363] ) , .prog_clk_0_S_out ( prog_clk_0_wires[364] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11044 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11045 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11046 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11047 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11048 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11049 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11050 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11051 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11052 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11053 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11054 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11055 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11056 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11057 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11058 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11059 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , .prog_clk_2_N_in ( p2021 ) , + .prog_clk_2_S_in ( p2473 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7301 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7302 ) , + .prog_clk_3_S_in ( p2525 ) , .prog_clk_3_N_in ( p2814 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7303 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7304 ) , .clk_2_N_in ( p2916 ) , + .clk_2_S_in ( p619 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7305 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7306 ) , .clk_3_S_in ( p1693 ) , + .clk_3_N_in ( p816 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7307 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7308 ) ) ; cby_1__1_ cby_10__1_ ( .chany_bottom_in ( sb_1__0__9_chany_top_out ) , .chany_top_in ( sb_1__1__99_chany_bottom_out ) , .ccff_head ( grid_clb_108_ccff_tail ) , @@ -83466,31 +84682,25 @@ cby_1__1_ cby_10__1_ ( .chany_bottom_in ( sb_1__0__9_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__108_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11060 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11061 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7309 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7310 ) , .Test_en_W_in ( Test_enWires[42] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11062 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11063 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7311 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7312 ) , .Test_en_E_out ( Test_enWires[43] ) , .prog_clk_0_W_in ( prog_clk_0_wires[368] ) , .prog_clk_0_S_out ( prog_clk_0_wires[369] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11064 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11065 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11066 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11067 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11068 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11069 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11070 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11071 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11072 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11073 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11074 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11075 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11076 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11077 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11078 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11079 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11080 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7313 ) , + .prog_clk_2_N_in ( p3281 ) , .prog_clk_2_S_in ( p1891 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7314 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7315 ) , + .prog_clk_3_S_in ( p1740 ) , .prog_clk_3_N_in ( p3239 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7316 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7317 ) , .clk_2_N_in ( p2766 ) , + .clk_2_S_in ( p1988 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7318 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7319 ) , .clk_3_S_in ( p1996 ) , + .clk_3_N_in ( p752 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7320 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7321 ) ) ; cby_1__1_ cby_10__2_ ( .chany_bottom_in ( sb_1__1__99_chany_top_out ) , .chany_top_in ( sb_1__1__100_chany_bottom_out ) , .ccff_head ( grid_clb_109_ccff_tail ) , @@ -83513,31 +84723,25 @@ cby_1__1_ cby_10__2_ ( .chany_bottom_in ( sb_1__1__99_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__109_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11081 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11082 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7322 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7323 ) , .Test_en_W_in ( Test_enWires[64] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11083 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11084 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7324 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7325 ) , .Test_en_E_out ( Test_enWires[65] ) , .prog_clk_0_W_in ( prog_clk_0_wires[371] ) , .prog_clk_0_S_out ( prog_clk_0_wires[372] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11085 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11086 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11087 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11088 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11089 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11090 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11091 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11092 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11093 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11094 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11095 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11096 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11097 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11098 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11099 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11100 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11101 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7326 ) , + .prog_clk_2_N_in ( p3133 ) , .prog_clk_2_S_in ( p2218 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7327 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7328 ) , + .prog_clk_3_S_in ( p2395 ) , .prog_clk_3_N_in ( p3060 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7329 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7330 ) , .clk_2_N_in ( p2886 ) , + .clk_2_S_in ( p1018 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7331 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7332 ) , .clk_3_S_in ( p2043 ) , + .clk_3_N_in ( p985 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7333 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7334 ) ) ; cby_1__1_ cby_10__3_ ( .chany_bottom_in ( sb_1__1__100_chany_top_out ) , .chany_top_in ( sb_1__1__101_chany_bottom_out ) , .ccff_head ( grid_clb_110_ccff_tail ) , @@ -83560,30 +84764,27 @@ cby_1__1_ cby_10__3_ ( .chany_bottom_in ( sb_1__1__100_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__110_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11102 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11103 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7335 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7336 ) , .Test_en_W_in ( Test_enWires[86] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11104 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11105 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7337 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7338 ) , .Test_en_E_out ( Test_enWires[87] ) , .prog_clk_0_W_in ( prog_clk_0_wires[374] ) , .prog_clk_0_S_out ( prog_clk_0_wires[375] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11106 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11107 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11108 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11109 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11110 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11111 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7339 ) , + .prog_clk_2_N_in ( p2093 ) , .prog_clk_2_S_in ( p506 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7340 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7341 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7342 ) , .prog_clk_3_N_in ( prog_clk_3_wires[86] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11112 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11113 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11114 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11115 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11116 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11117 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7343 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( p2093 ) , + .clk_2_S_in ( p171 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7344 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7345 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7346 ) , .clk_3_N_in ( clk_3_wires[86] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11118 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7347 ) , .clk_3_S_out ( clk_3_wires[87] ) ) ; cby_1__1_ cby_10__4_ ( .chany_bottom_in ( sb_1__1__101_chany_top_out ) , .chany_top_in ( sb_1__1__102_chany_bottom_out ) , @@ -83607,30 +84808,27 @@ cby_1__1_ cby_10__4_ ( .chany_bottom_in ( sb_1__1__101_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__111_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11119 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11120 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7348 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7349 ) , .Test_en_W_in ( Test_enWires[108] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11121 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11122 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7350 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7351 ) , .Test_en_E_out ( Test_enWires[109] ) , .prog_clk_0_W_in ( prog_clk_0_wires[377] ) , .prog_clk_0_S_out ( prog_clk_0_wires[378] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11123 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11124 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11125 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11126 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11127 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11128 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7352 ) , + .prog_clk_2_N_in ( p1557 ) , .prog_clk_2_S_in ( p487 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7353 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7354 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7355 ) , .prog_clk_3_N_in ( prog_clk_3_wires[82] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11129 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11130 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11131 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11132 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11133 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11134 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7356 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( p1557 ) , + .clk_2_S_in ( p597 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7357 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7358 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7359 ) , .clk_3_N_in ( clk_3_wires[82] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11135 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7360 ) , .clk_3_S_out ( clk_3_wires[83] ) ) ; cby_1__1_ cby_10__5_ ( .chany_bottom_in ( sb_1__1__102_chany_top_out ) , .chany_top_in ( sb_1__1__103_chany_bottom_out ) , @@ -83654,30 +84852,27 @@ cby_1__1_ cby_10__5_ ( .chany_bottom_in ( sb_1__1__102_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__112_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11136 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11137 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7361 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7362 ) , .Test_en_W_in ( Test_enWires[130] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11138 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11139 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7363 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7364 ) , .Test_en_E_out ( Test_enWires[131] ) , .prog_clk_0_W_in ( prog_clk_0_wires[380] ) , .prog_clk_0_S_out ( prog_clk_0_wires[381] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11140 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11141 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11142 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11143 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11144 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11145 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7365 ) , + .prog_clk_2_N_in ( p1875 ) , .prog_clk_2_S_in ( p717 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7366 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7367 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7368 ) , .prog_clk_3_N_in ( prog_clk_3_wires[76] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11146 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11147 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11148 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11149 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11150 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11151 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7369 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( p1875 ) , + .clk_2_S_in ( p186 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7370 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7371 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7372 ) , .clk_3_N_in ( clk_3_wires[76] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11152 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7373 ) , .clk_3_S_out ( clk_3_wires[77] ) ) ; cby_1__1_ cby_10__6_ ( .chany_bottom_in ( sb_1__1__103_chany_top_out ) , .chany_top_in ( sb_1__1__104_chany_bottom_out ) , @@ -83701,30 +84896,27 @@ cby_1__1_ cby_10__6_ ( .chany_bottom_in ( sb_1__1__103_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__113_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11153 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11154 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7374 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7375 ) , .Test_en_W_in ( Test_enWires[152] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11155 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11156 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7376 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7377 ) , .Test_en_E_out ( Test_enWires[153] ) , .prog_clk_0_W_in ( prog_clk_0_wires[383] ) , .prog_clk_0_S_out ( prog_clk_0_wires[384] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11157 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11158 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11159 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11160 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11161 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11162 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7378 ) , + .prog_clk_2_N_in ( p2389 ) , .prog_clk_2_S_in ( p1283 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7379 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7380 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7381 ) , .prog_clk_3_N_in ( prog_clk_3_wires[72] ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11163 ) , - .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11164 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11165 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11166 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11167 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11168 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7382 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( p2389 ) , + .clk_2_S_in ( p478 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7383 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7384 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_7385 ) , .clk_3_N_in ( clk_3_wires[72] ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11169 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7386 ) , .clk_3_S_out ( clk_3_wires[73] ) ) ; cby_1__1_ cby_10__7_ ( .chany_bottom_in ( sb_1__1__104_chany_top_out ) , .chany_top_in ( sb_1__1__105_chany_bottom_out ) , @@ -83748,31 +84940,28 @@ cby_1__1_ cby_10__7_ ( .chany_bottom_in ( sb_1__1__104_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__114_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11170 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11171 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7387 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7388 ) , .Test_en_W_in ( Test_enWires[174] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11172 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11173 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7389 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7390 ) , .Test_en_E_out ( Test_enWires[175] ) , .prog_clk_0_W_in ( prog_clk_0_wires[386] ) , .prog_clk_0_S_out ( prog_clk_0_wires[387] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11174 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11175 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11176 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11177 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11178 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7391 ) , + .prog_clk_2_N_in ( p2420 ) , .prog_clk_2_S_in ( p741 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7392 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7393 ) , .prog_clk_3_S_in ( prog_clk_3_wires[70] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11179 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7394 ) , .prog_clk_3_N_out ( prog_clk_3_wires[71] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11180 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11181 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11182 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11183 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11184 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7395 ) , .clk_2_N_in ( p2420 ) , + .clk_2_S_in ( p308 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7396 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7397 ) , .clk_3_S_in ( clk_3_wires[70] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11185 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7398 ) , .clk_3_N_out ( clk_3_wires[71] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11186 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7399 ) ) ; cby_1__1_ cby_10__8_ ( .chany_bottom_in ( sb_1__1__105_chany_top_out ) , .chany_top_in ( sb_1__1__106_chany_bottom_out ) , .ccff_head ( grid_clb_115_ccff_tail ) , @@ -83795,31 +84984,28 @@ cby_1__1_ cby_10__8_ ( .chany_bottom_in ( sb_1__1__105_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__115_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11187 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11188 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7400 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7401 ) , .Test_en_W_in ( Test_enWires[196] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11189 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11190 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7402 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7403 ) , .Test_en_E_out ( Test_enWires[197] ) , .prog_clk_0_W_in ( prog_clk_0_wires[389] ) , .prog_clk_0_S_out ( prog_clk_0_wires[390] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11191 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11192 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11193 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11194 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11195 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7404 ) , + .prog_clk_2_N_in ( p1825 ) , .prog_clk_2_S_in ( p1177 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7405 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7406 ) , .prog_clk_3_S_in ( prog_clk_3_wires[74] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11196 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7407 ) , .prog_clk_3_N_out ( prog_clk_3_wires[75] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11197 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11198 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11199 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11200 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11201 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7408 ) , .clk_2_N_in ( p1774 ) , + .clk_2_S_in ( p345 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7409 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7410 ) , .clk_3_S_in ( clk_3_wires[74] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11202 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7411 ) , .clk_3_N_out ( clk_3_wires[75] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11203 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7412 ) ) ; cby_1__1_ cby_10__9_ ( .chany_bottom_in ( sb_1__1__106_chany_top_out ) , .chany_top_in ( sb_1__1__107_chany_bottom_out ) , .ccff_head ( grid_clb_116_ccff_tail ) , @@ -83842,31 +85028,28 @@ cby_1__1_ cby_10__9_ ( .chany_bottom_in ( sb_1__1__106_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__116_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11204 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11205 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7413 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7414 ) , .Test_en_W_in ( Test_enWires[218] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11206 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11207 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7415 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7416 ) , .Test_en_E_out ( Test_enWires[219] ) , .prog_clk_0_W_in ( prog_clk_0_wires[392] ) , .prog_clk_0_S_out ( prog_clk_0_wires[393] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11208 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11209 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11210 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11211 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11212 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7417 ) , + .prog_clk_2_N_in ( p2094 ) , .prog_clk_2_S_in ( p260 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7418 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7419 ) , .prog_clk_3_S_in ( prog_clk_3_wires[80] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11213 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7420 ) , .prog_clk_3_N_out ( prog_clk_3_wires[81] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11214 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11215 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11216 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11217 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11218 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7421 ) , .clk_2_N_in ( p2094 ) , + .clk_2_S_in ( p907 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7422 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7423 ) , .clk_3_S_in ( clk_3_wires[80] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11219 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7424 ) , .clk_3_N_out ( clk_3_wires[81] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11220 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7425 ) ) ; cby_1__1_ cby_10__10_ ( .chany_bottom_in ( sb_1__1__107_chany_top_out ) , .chany_top_in ( sb_1__1__108_chany_bottom_out ) , .ccff_head ( grid_clb_117_ccff_tail ) , @@ -83889,31 +85072,28 @@ cby_1__1_ cby_10__10_ ( .chany_bottom_in ( sb_1__1__107_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__117_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11221 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11222 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7426 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7427 ) , .Test_en_W_in ( Test_enWires[240] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11223 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11224 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7428 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7429 ) , .Test_en_E_out ( Test_enWires[241] ) , .prog_clk_0_W_in ( prog_clk_0_wires[395] ) , .prog_clk_0_S_out ( prog_clk_0_wires[396] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11225 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11226 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11227 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11228 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11229 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7430 ) , + .prog_clk_2_N_in ( p1606 ) , .prog_clk_2_S_in ( p77 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7431 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7432 ) , .prog_clk_3_S_in ( prog_clk_3_wires[84] ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11230 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_7433 ) , .prog_clk_3_N_out ( prog_clk_3_wires[85] ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11231 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11232 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11233 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11234 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11235 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7434 ) , .clk_2_N_in ( p1606 ) , + .clk_2_S_in ( p770 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7435 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7436 ) , .clk_3_S_in ( clk_3_wires[84] ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11236 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_7437 ) , .clk_3_N_out ( clk_3_wires[85] ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11237 ) ) ; + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7438 ) ) ; cby_1__1_ cby_10__11_ ( .chany_bottom_in ( sb_1__1__108_chany_top_out ) , .chany_top_in ( sb_1__1__109_chany_bottom_out ) , .ccff_head ( grid_clb_118_ccff_tail ) , @@ -83936,31 +85116,25 @@ cby_1__1_ cby_10__11_ ( .chany_bottom_in ( sb_1__1__108_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__118_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11238 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11239 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7439 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7440 ) , .Test_en_W_in ( Test_enWires[262] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11240 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11241 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7441 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7442 ) , .Test_en_E_out ( Test_enWires[263] ) , .prog_clk_0_W_in ( prog_clk_0_wires[398] ) , .prog_clk_0_S_out ( prog_clk_0_wires[399] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11242 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11243 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11244 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11245 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11246 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11247 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11248 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11249 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11250 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11251 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11252 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11253 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11254 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11255 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11256 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11257 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11258 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7443 ) , + .prog_clk_2_N_in ( p2865 ) , .prog_clk_2_S_in ( p2687 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7444 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7445 ) , + .prog_clk_3_S_in ( p2718 ) , .prog_clk_3_N_in ( p2851 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7446 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7447 ) , .clk_2_N_in ( p2907 ) , + .clk_2_S_in ( p936 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7448 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7449 ) , .clk_3_S_in ( p2142 ) , + .clk_3_N_in ( p560 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7450 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7451 ) ) ; cby_1__1_ cby_10__12_ ( .chany_bottom_in ( sb_1__1__109_chany_top_out ) , .chany_top_in ( sb_1__12__9_chany_bottom_out ) , .ccff_head ( grid_clb_119_ccff_tail ) , @@ -83983,31 +85157,25 @@ cby_1__1_ cby_10__12_ ( .chany_bottom_in ( sb_1__1__109_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__119_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11259 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11260 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7452 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7453 ) , .Test_en_W_in ( Test_enWires[284] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11261 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11262 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7454 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7455 ) , .Test_en_E_out ( Test_enWires[285] ) , .prog_clk_0_W_in ( prog_clk_0_wires[401] ) , .prog_clk_0_S_out ( prog_clk_0_wires[402] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11263 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11264 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11265 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11266 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11267 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11268 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11269 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11270 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11271 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11272 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11273 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11274 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11275 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11276 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11277 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11278 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , .prog_clk_2_N_in ( p3108 ) , + .prog_clk_2_S_in ( p3093 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7456 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7457 ) , + .prog_clk_3_S_in ( p3128 ) , .prog_clk_3_N_in ( p3056 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7458 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7459 ) , .clk_2_N_in ( p2882 ) , + .clk_2_S_in ( p134 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7460 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7461 ) , .clk_3_S_in ( p2533 ) , + .clk_3_N_in ( p322 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7462 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7463 ) ) ; cby_1__1_ cby_11__1_ ( .chany_bottom_in ( sb_1__0__10_chany_top_out ) , .chany_top_in ( sb_1__1__110_chany_bottom_out ) , .ccff_head ( grid_clb_120_ccff_tail ) , @@ -84030,31 +85198,25 @@ cby_1__1_ cby_11__1_ ( .chany_bottom_in ( sb_1__0__10_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__120_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11279 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11280 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7464 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7465 ) , .Test_en_W_in ( Test_enWires[44] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11281 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11282 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7466 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7467 ) , .Test_en_E_out ( Test_enWires[45] ) , .prog_clk_0_W_in ( prog_clk_0_wires[406] ) , .prog_clk_0_S_out ( prog_clk_0_wires[407] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11283 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11284 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11285 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11286 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11287 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11288 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11289 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11290 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11291 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11292 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11293 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11294 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11295 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11296 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11297 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11298 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11299 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7468 ) , + .prog_clk_2_N_in ( p3126 ) , .prog_clk_2_S_in ( p2647 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7469 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7470 ) , + .prog_clk_3_S_in ( p2762 ) , .prog_clk_3_N_in ( p3258 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7471 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7472 ) , .clk_2_N_in ( p3277 ) , + .clk_2_S_in ( p2185 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7473 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7474 ) , .clk_3_S_in ( p2390 ) , + .clk_3_N_in ( p1306 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7475 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7476 ) ) ; cby_1__1_ cby_11__2_ ( .chany_bottom_in ( sb_1__1__110_chany_top_out ) , .chany_top_in ( sb_1__1__111_chany_bottom_out ) , .ccff_head ( grid_clb_121_ccff_tail ) , @@ -84077,31 +85239,28 @@ cby_1__1_ cby_11__2_ ( .chany_bottom_in ( sb_1__1__110_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__121_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11300 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11301 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7477 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7478 ) , .Test_en_W_in ( Test_enWires[66] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11302 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11303 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7479 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7480 ) , .Test_en_E_out ( Test_enWires[67] ) , .prog_clk_0_W_in ( prog_clk_0_wires[409] ) , .prog_clk_0_S_out ( prog_clk_0_wires[410] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11304 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7481 ) , .prog_clk_2_N_in ( prog_clk_2_wires[115] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11305 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7482 ) , .prog_clk_2_S_out ( prog_clk_2_wires[116] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11306 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11307 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11308 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11309 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11310 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7483 ) , + .prog_clk_3_S_in ( p1674 ) , .prog_clk_3_N_in ( p1087 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7484 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7485 ) , .clk_2_N_in ( clk_2_wires[115] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11311 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7486 ) , .clk_2_S_out ( clk_2_wires[116] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11312 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11313 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11314 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11315 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11316 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7487 ) , .clk_3_S_in ( p2397 ) , + .clk_3_N_in ( p464 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7488 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7489 ) ) ; cby_1__1_ cby_11__3_ ( .chany_bottom_in ( sb_1__1__111_chany_top_out ) , .chany_top_in ( sb_1__1__112_chany_bottom_out ) , .ccff_head ( grid_clb_122_ccff_tail ) , @@ -84124,31 +85283,25 @@ cby_1__1_ cby_11__3_ ( .chany_bottom_in ( sb_1__1__111_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__122_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11317 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11318 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7490 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7491 ) , .Test_en_W_in ( Test_enWires[88] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11319 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11320 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7492 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7493 ) , .Test_en_E_out ( Test_enWires[89] ) , .prog_clk_0_W_in ( prog_clk_0_wires[412] ) , .prog_clk_0_S_out ( prog_clk_0_wires[413] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11321 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11322 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11323 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11324 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11325 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11326 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11327 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11328 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11329 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11330 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11331 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11332 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11333 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11334 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11335 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11336 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11337 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7494 ) , + .prog_clk_2_N_in ( p2895 ) , .prog_clk_2_S_in ( p2659 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7495 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7496 ) , + .prog_clk_3_S_in ( p2749 ) , .prog_clk_3_N_in ( p2964 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7497 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7498 ) , .clk_2_N_in ( p2998 ) , + .clk_2_S_in ( p45 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7499 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7500 ) , .clk_3_S_in ( p2055 ) , + .clk_3_N_in ( p1249 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7501 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7502 ) ) ; cby_1__1_ cby_11__4_ ( .chany_bottom_in ( sb_1__1__112_chany_top_out ) , .chany_top_in ( sb_1__1__113_chany_bottom_out ) , .ccff_head ( grid_clb_123_ccff_tail ) , @@ -84171,31 +85324,28 @@ cby_1__1_ cby_11__4_ ( .chany_bottom_in ( sb_1__1__112_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__123_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11338 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11339 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7503 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7504 ) , .Test_en_W_in ( Test_enWires[110] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11340 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11341 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7505 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7506 ) , .Test_en_E_out ( Test_enWires[111] ) , .prog_clk_0_W_in ( prog_clk_0_wires[415] ) , .prog_clk_0_S_out ( prog_clk_0_wires[416] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11342 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7507 ) , .prog_clk_2_N_in ( prog_clk_2_wires[122] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11343 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7508 ) , .prog_clk_2_S_out ( prog_clk_2_wires[123] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11344 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11345 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11346 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11347 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11348 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7509 ) , + .prog_clk_3_S_in ( p1634 ) , .prog_clk_3_N_in ( p724 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7510 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7511 ) , .clk_2_N_in ( clk_2_wires[122] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11349 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7512 ) , .clk_2_S_out ( clk_2_wires[123] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11350 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11351 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11352 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11353 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11354 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7513 ) , .clk_3_S_in ( p2334 ) , + .clk_3_N_in ( p316 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7514 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7515 ) ) ; cby_1__1_ cby_11__5_ ( .chany_bottom_in ( sb_1__1__113_chany_top_out ) , .chany_top_in ( sb_1__1__114_chany_bottom_out ) , .ccff_head ( grid_clb_124_ccff_tail ) , @@ -84218,31 +85368,28 @@ cby_1__1_ cby_11__5_ ( .chany_bottom_in ( sb_1__1__113_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__124_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11355 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11356 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7516 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7517 ) , .Test_en_W_in ( Test_enWires[132] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11357 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11358 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7518 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7519 ) , .Test_en_E_out ( Test_enWires[133] ) , .prog_clk_0_W_in ( prog_clk_0_wires[418] ) , .prog_clk_0_S_out ( prog_clk_0_wires[419] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11359 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11360 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7520 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7521 ) , .prog_clk_2_S_in ( prog_clk_2_wires[120] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11361 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11362 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11363 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11364 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11365 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11366 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7522 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , .prog_clk_3_S_in ( p1700 ) , + .prog_clk_3_N_in ( p1053 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7523 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7524 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7525 ) , .clk_2_S_in ( clk_2_wires[120] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11367 ) , - .clk_2_N_out ( clk_2_wires[121] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11368 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11369 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11370 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11371 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7526 ) , + .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1700 ) , + .clk_3_N_in ( p548 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7527 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7528 ) ) ; cby_1__1_ cby_11__6_ ( .chany_bottom_in ( sb_1__1__114_chany_top_out ) , .chany_top_in ( sb_1__1__115_chany_bottom_out ) , .ccff_head ( grid_clb_125_ccff_tail ) , @@ -84265,31 +85412,25 @@ cby_1__1_ cby_11__6_ ( .chany_bottom_in ( sb_1__1__114_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__125_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11372 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11373 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7529 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7530 ) , .Test_en_W_in ( Test_enWires[154] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11374 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11375 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7531 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7532 ) , .Test_en_E_out ( Test_enWires[155] ) , .prog_clk_0_W_in ( prog_clk_0_wires[421] ) , .prog_clk_0_S_out ( prog_clk_0_wires[422] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11376 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11377 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11378 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11379 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11380 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11381 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11382 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11383 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11384 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11385 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11386 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11387 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11388 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11389 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11390 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11391 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11392 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7533 ) , + .prog_clk_2_N_in ( p3219 ) , .prog_clk_2_S_in ( p3065 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7534 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7535 ) , + .prog_clk_3_S_in ( p3136 ) , .prog_clk_3_N_in ( p3186 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7536 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_2_N_in ( p3124 ) , + .clk_2_S_in ( p286 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7538 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7539 ) , .clk_3_S_in ( p1761 ) , + .clk_3_N_in ( p1090 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7540 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7541 ) ) ; cby_1__1_ cby_11__7_ ( .chany_bottom_in ( sb_1__1__115_chany_top_out ) , .chany_top_in ( sb_1__1__116_chany_bottom_out ) , .ccff_head ( grid_clb_126_ccff_tail ) , @@ -84312,31 +85453,25 @@ cby_1__1_ cby_11__7_ ( .chany_bottom_in ( sb_1__1__115_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__126_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11393 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11394 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7542 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7543 ) , .Test_en_W_in ( Test_enWires[176] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11395 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11396 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7544 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7545 ) , .Test_en_E_out ( Test_enWires[177] ) , .prog_clk_0_W_in ( prog_clk_0_wires[424] ) , .prog_clk_0_S_out ( prog_clk_0_wires[425] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11397 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11398 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11399 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11400 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11401 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11402 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11403 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11404 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11405 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11406 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11407 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11408 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11409 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11410 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11411 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11412 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11413 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7546 ) , + .prog_clk_2_N_in ( p3340 ) , .prog_clk_2_S_in ( p2633 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7547 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7548 ) , + .prog_clk_3_S_in ( p2796 ) , .prog_clk_3_N_in ( p3306 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7549 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7550 ) , .clk_2_N_in ( p3294 ) , + .clk_2_S_in ( p242 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7551 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_S_in ( p1730 ) , + .clk_3_N_in ( p1029 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7553 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7554 ) ) ; cby_1__1_ cby_11__8_ ( .chany_bottom_in ( sb_1__1__116_chany_top_out ) , .chany_top_in ( sb_1__1__117_chany_bottom_out ) , .ccff_head ( grid_clb_127_ccff_tail ) , @@ -84359,31 +85494,28 @@ cby_1__1_ cby_11__8_ ( .chany_bottom_in ( sb_1__1__116_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__127_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11414 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11415 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7555 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7556 ) , .Test_en_W_in ( Test_enWires[198] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11416 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11417 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7557 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7558 ) , .Test_en_E_out ( Test_enWires[199] ) , .prog_clk_0_W_in ( prog_clk_0_wires[427] ) , .prog_clk_0_S_out ( prog_clk_0_wires[428] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11418 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7559 ) , .prog_clk_2_N_in ( prog_clk_2_wires[129] ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11419 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7560 ) , .prog_clk_2_S_out ( prog_clk_2_wires[130] ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11420 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11421 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11422 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11423 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11424 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7561 ) , + .prog_clk_3_S_in ( p1521 ) , .prog_clk_3_N_in ( p508 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7562 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7563 ) , .clk_2_N_in ( clk_2_wires[129] ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11425 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7564 ) , .clk_2_S_out ( clk_2_wires[130] ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11426 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11427 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11428 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11429 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11430 ) ) ; + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_3_S_in ( p2720 ) , + .clk_3_N_in ( p1062 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7566 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7567 ) ) ; cby_1__1_ cby_11__9_ ( .chany_bottom_in ( sb_1__1__117_chany_top_out ) , .chany_top_in ( sb_1__1__118_chany_bottom_out ) , .ccff_head ( grid_clb_128_ccff_tail ) , @@ -84406,31 +85538,28 @@ cby_1__1_ cby_11__9_ ( .chany_bottom_in ( sb_1__1__117_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__128_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11431 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11432 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7568 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7569 ) , .Test_en_W_in ( Test_enWires[220] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11433 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11434 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7570 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7571 ) , .Test_en_E_out ( Test_enWires[221] ) , .prog_clk_0_W_in ( prog_clk_0_wires[430] ) , .prog_clk_0_S_out ( prog_clk_0_wires[431] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11435 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11436 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7572 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7573 ) , .prog_clk_2_S_in ( prog_clk_2_wires[127] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11437 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11438 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11439 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11440 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11441 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11442 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7574 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , .prog_clk_3_S_in ( p1722 ) , + .prog_clk_3_N_in ( p401 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7575 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7576 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7577 ) , .clk_2_S_in ( clk_2_wires[127] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11443 ) , - .clk_2_N_out ( clk_2_wires[128] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11444 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11445 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11446 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11447 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7578 ) , + .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p2075 ) , + .clk_3_N_in ( p974 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7579 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7580 ) ) ; cby_1__1_ cby_11__10_ ( .chany_bottom_in ( sb_1__1__118_chany_top_out ) , .chany_top_in ( sb_1__1__119_chany_bottom_out ) , .ccff_head ( grid_clb_129_ccff_tail ) , @@ -84453,31 +85582,25 @@ cby_1__1_ cby_11__10_ ( .chany_bottom_in ( sb_1__1__118_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__129_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11448 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11449 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7581 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7582 ) , .Test_en_W_in ( Test_enWires[242] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11450 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11451 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7583 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7584 ) , .Test_en_E_out ( Test_enWires[243] ) , .prog_clk_0_W_in ( prog_clk_0_wires[433] ) , .prog_clk_0_S_out ( prog_clk_0_wires[434] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11452 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11453 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11454 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11455 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11456 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11457 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11458 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11459 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11460 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11461 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11462 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11463 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11464 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11465 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11466 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11467 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11468 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7585 ) , + .prog_clk_2_N_in ( p3418 ) , .prog_clk_2_S_in ( p3058 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7586 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7587 ) , + .prog_clk_3_S_in ( p3150 ) , .prog_clk_3_N_in ( p3400 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7588 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7589 ) , .clk_2_N_in ( p3274 ) , + .clk_2_S_in ( p651 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7590 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7591 ) , .clk_3_S_in ( p1776 ) , + .clk_3_N_in ( p1329 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7592 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7593 ) ) ; cby_1__1_ cby_11__11_ ( .chany_bottom_in ( sb_1__1__119_chany_top_out ) , .chany_top_in ( sb_1__1__120_chany_bottom_out ) , .ccff_head ( grid_clb_130_ccff_tail ) , @@ -84500,31 +85623,28 @@ cby_1__1_ cby_11__11_ ( .chany_bottom_in ( sb_1__1__119_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__130_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11469 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11470 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7594 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7595 ) , .Test_en_W_in ( Test_enWires[264] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11471 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11472 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7596 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7597 ) , .Test_en_E_out ( Test_enWires[265] ) , .prog_clk_0_W_in ( prog_clk_0_wires[436] ) , .prog_clk_0_S_out ( prog_clk_0_wires[437] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11473 ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11474 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7598 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7599 ) , .prog_clk_2_S_in ( prog_clk_2_wires[134] ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11475 ) , - .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11476 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11477 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11478 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11479 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11480 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7600 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , .prog_clk_3_S_in ( p1252 ) , + .prog_clk_3_N_in ( p1244 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7601 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7602 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7603 ) , .clk_2_S_in ( clk_2_wires[134] ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11481 ) , - .clk_2_N_out ( clk_2_wires[135] ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11482 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11483 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11484 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11485 ) ) ; + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7604 ) , + .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p2308 ) , + .clk_3_N_in ( p644 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7605 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7606 ) ) ; cby_1__1_ cby_11__12_ ( .chany_bottom_in ( sb_1__1__120_chany_top_out ) , .chany_top_in ( sb_1__12__10_chany_bottom_out ) , .ccff_head ( grid_clb_131_ccff_tail ) , @@ -84547,31 +85667,25 @@ cby_1__1_ cby_11__12_ ( .chany_bottom_in ( sb_1__1__120_chany_top_out ) , .left_grid_pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) , .ccff_tail ( cby_1__1__131_ccff_tail ) , - .Test_en_S_in ( SYNOPSYS_UNCONNECTED_11486 ) , - .Test_en_E_in ( SYNOPSYS_UNCONNECTED_11487 ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7607 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_7608 ) , .Test_en_W_in ( Test_enWires[286] ) , - .Test_en_N_out ( SYNOPSYS_UNCONNECTED_11488 ) , - .Test_en_W_out ( SYNOPSYS_UNCONNECTED_11489 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7609 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_7610 ) , .Test_en_E_out ( Test_enWires[287] ) , .prog_clk_0_W_in ( prog_clk_0_wires[439] ) , .prog_clk_0_S_out ( prog_clk_0_wires[440] ) , - .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , - .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_11490 ) , - .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_11491 ) , - .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_11492 ) , - .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_11493 ) , - .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_11494 ) , - .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_11495 ) , - .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_11496 ) , - .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_11497 ) , - .clk_2_N_in ( SYNOPSYS_UNCONNECTED_11498 ) , - .clk_2_S_in ( SYNOPSYS_UNCONNECTED_11499 ) , - .clk_2_S_out ( SYNOPSYS_UNCONNECTED_11500 ) , - .clk_2_N_out ( SYNOPSYS_UNCONNECTED_11501 ) , - .clk_3_S_in ( SYNOPSYS_UNCONNECTED_11502 ) , - .clk_3_N_in ( SYNOPSYS_UNCONNECTED_11503 ) , - .clk_3_N_out ( SYNOPSYS_UNCONNECTED_11504 ) , - .clk_3_S_out ( SYNOPSYS_UNCONNECTED_11505 ) ) ; + .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , .prog_clk_2_N_in ( p3345 ) , + .prog_clk_2_S_in ( p3304 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7611 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7612 ) , + .prog_clk_3_S_in ( p3327 ) , .prog_clk_3_N_in ( p3313 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7613 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7614 ) , .clk_2_N_in ( p2904 ) , + .clk_2_S_in ( p828 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7615 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_S_in ( p2322 ) , + .clk_3_N_in ( p2002 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7617 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7618 ) ) ; cby_2__1_ cby_12__1_ ( .chany_bottom_in ( sb_12__0__0_chany_top_out ) , .chany_top_in ( sb_12__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_132_ccff_tail ) , @@ -84603,7 +85717,7 @@ cby_2__1_ cby_12__1_ ( .chany_bottom_in ( sb_12__0__0_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[444] ) , .prog_clk_0_S_out ( prog_clk_0_wires[445] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11506 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7619 ) ) ; cby_2__1_ cby_12__2_ ( .chany_bottom_in ( sb_12__1__0_chany_top_out ) , .chany_top_in ( sb_12__1__1_chany_bottom_out ) , .ccff_head ( grid_clb_133_ccff_tail ) , @@ -84635,7 +85749,7 @@ cby_2__1_ cby_12__2_ ( .chany_bottom_in ( sb_12__1__0_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[447] ) , .prog_clk_0_S_out ( prog_clk_0_wires[448] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11507 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7620 ) ) ; cby_2__1_ cby_12__3_ ( .chany_bottom_in ( sb_12__1__1_chany_top_out ) , .chany_top_in ( sb_12__1__2_chany_bottom_out ) , .ccff_head ( grid_clb_134_ccff_tail ) , @@ -84667,7 +85781,7 @@ cby_2__1_ cby_12__3_ ( .chany_bottom_in ( sb_12__1__1_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[450] ) , .prog_clk_0_S_out ( prog_clk_0_wires[451] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11508 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7621 ) ) ; cby_2__1_ cby_12__4_ ( .chany_bottom_in ( sb_12__1__2_chany_top_out ) , .chany_top_in ( sb_12__1__3_chany_bottom_out ) , .ccff_head ( grid_clb_135_ccff_tail ) , @@ -84699,7 +85813,7 @@ cby_2__1_ cby_12__4_ ( .chany_bottom_in ( sb_12__1__2_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[453] ) , .prog_clk_0_S_out ( prog_clk_0_wires[454] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11509 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7622 ) ) ; cby_2__1_ cby_12__5_ ( .chany_bottom_in ( sb_12__1__3_chany_top_out ) , .chany_top_in ( sb_12__1__4_chany_bottom_out ) , .ccff_head ( grid_clb_136_ccff_tail ) , @@ -84731,7 +85845,7 @@ cby_2__1_ cby_12__5_ ( .chany_bottom_in ( sb_12__1__3_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[456] ) , .prog_clk_0_S_out ( prog_clk_0_wires[457] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11510 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7623 ) ) ; cby_2__1_ cby_12__6_ ( .chany_bottom_in ( sb_12__1__4_chany_top_out ) , .chany_top_in ( sb_12__1__5_chany_bottom_out ) , .ccff_head ( grid_clb_137_ccff_tail ) , @@ -84763,7 +85877,7 @@ cby_2__1_ cby_12__6_ ( .chany_bottom_in ( sb_12__1__4_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[459] ) , .prog_clk_0_S_out ( prog_clk_0_wires[460] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11511 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7624 ) ) ; cby_2__1_ cby_12__7_ ( .chany_bottom_in ( sb_12__1__5_chany_top_out ) , .chany_top_in ( sb_12__1__6_chany_bottom_out ) , .ccff_head ( grid_clb_138_ccff_tail ) , @@ -84795,7 +85909,7 @@ cby_2__1_ cby_12__7_ ( .chany_bottom_in ( sb_12__1__5_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[462] ) , .prog_clk_0_S_out ( prog_clk_0_wires[463] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11512 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7625 ) ) ; cby_2__1_ cby_12__8_ ( .chany_bottom_in ( sb_12__1__6_chany_top_out ) , .chany_top_in ( sb_12__1__7_chany_bottom_out ) , .ccff_head ( grid_clb_139_ccff_tail ) , @@ -84827,7 +85941,7 @@ cby_2__1_ cby_12__8_ ( .chany_bottom_in ( sb_12__1__6_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[465] ) , .prog_clk_0_S_out ( prog_clk_0_wires[466] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11513 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7626 ) ) ; cby_2__1_ cby_12__9_ ( .chany_bottom_in ( sb_12__1__7_chany_top_out ) , .chany_top_in ( sb_12__1__8_chany_bottom_out ) , .ccff_head ( grid_clb_140_ccff_tail ) , @@ -84859,7 +85973,7 @@ cby_2__1_ cby_12__9_ ( .chany_bottom_in ( sb_12__1__7_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[468] ) , .prog_clk_0_S_out ( prog_clk_0_wires[469] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11514 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7627 ) ) ; cby_2__1_ cby_12__10_ ( .chany_bottom_in ( sb_12__1__8_chany_top_out ) , .chany_top_in ( sb_12__1__9_chany_bottom_out ) , .ccff_head ( grid_clb_141_ccff_tail ) , @@ -84891,7 +86005,7 @@ cby_2__1_ cby_12__10_ ( .chany_bottom_in ( sb_12__1__8_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[471] ) , .prog_clk_0_S_out ( prog_clk_0_wires[472] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11515 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7628 ) ) ; cby_2__1_ cby_12__11_ ( .chany_bottom_in ( sb_12__1__9_chany_top_out ) , .chany_top_in ( sb_12__1__10_chany_bottom_out ) , .ccff_head ( grid_clb_142_ccff_tail ) , @@ -84923,7 +86037,7 @@ cby_2__1_ cby_12__11_ ( .chany_bottom_in ( sb_12__1__9_chany_top_out ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , .prog_clk_0_W_in ( prog_clk_0_wires[474] ) , .prog_clk_0_S_out ( prog_clk_0_wires[475] ) , - .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_11516 ) ) ; + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7629 ) ) ; cby_2__1_ cby_12__12_ ( .chany_bottom_in ( sb_12__1__10_chany_top_out ) , .chany_top_in ( sb_12__12__0_chany_bottom_out ) , .ccff_head ( grid_clb_143_ccff_tail ) , @@ -85261,22 +86375,6 @@ assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ; assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ; assign sc_head = io_in[26] ; assign wb_la_switch = io_in[25] ; -assign io_out[37] = 1'b0 ; -assign io_out[36] = 1'b0 ; -assign io_out[26] = 1'b0 ; -assign io_out[25] = 1'b0 ; -assign io_out[12] = 1'b0 ; -assign io_out[1] = 1'b0 ; -assign io_out[0] = 1'b0 ; -assign io_oeb[37] = 1'b1 ; -assign io_oeb[36] = 1'b1 ; -assign io_oeb[35] = 1'b0 ; -assign io_oeb[26] = 1'b1 ; -assign io_oeb[25] = 1'b1 ; -assign io_oeb[12] = 1'b1 ; -assign io_oeb[11] = 1'b0 ; -assign io_oeb[1] = 1'b1 ; -assign io_oeb[0] = 1'b1 ; sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[13] ) , .A1 ( wb_clk_i ) , .S ( io_in[25] ) , @@ -85979,7 +87077,8831 @@ fpga_core fpga_core_uut ( .prog_clk ( io_in[37] ) , .Test_en ( io_in[0] ) , io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] , io_oeb[27] } ) , .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) , - .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) ) ; + .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) , + .h_incr0 ( SYNOPSYS_UNCONNECTED_1 ) , .p0 ( optlc_net_16 ) , + .p1 ( optlc_net_17 ) , .p2 ( optlc_net_18 ) , .p3 ( optlc_net_19 ) , + .p4 ( optlc_net_20 ) , .p5 ( optlc_net_21 ) , .p6 ( optlc_net_22 ) , + .p7 ( optlc_net_23 ) , .p8 ( optlc_net_24 ) , .p9 ( optlc_net_25 ) , + .p10 ( optlc_net_26 ) , .p11 ( optlc_net_27 ) , .p12 ( optlc_net_28 ) , + .p13 ( optlc_net_29 ) , .p14 ( optlc_net_30 ) , .p15 ( optlc_net_31 ) , + .p16 ( optlc_net_32 ) , .p17 ( optlc_net_33 ) , .p18 ( optlc_net_34 ) , + .p19 ( optlc_net_35 ) , .p20 ( optlc_net_36 ) , .p21 ( optlc_net_37 ) , + .p22 ( optlc_net_38 ) , .p23 ( optlc_net_39 ) , .p24 ( optlc_net_40 ) , + .p25 ( optlc_net_41 ) , .p26 ( optlc_net_42 ) , .p27 ( optlc_net_43 ) , + .p28 ( optlc_net_44 ) , .p29 ( optlc_net_45 ) , .p30 ( optlc_net_46 ) , + .p31 ( optlc_net_47 ) , .p32 ( optlc_net_48 ) , .p33 ( optlc_net_49 ) , + .p34 ( optlc_net_50 ) , .p35 ( optlc_net_51 ) , .p36 ( optlc_net_52 ) , + .p37 ( optlc_net_53 ) , .p38 ( optlc_net_54 ) , .p39 ( optlc_net_55 ) , + .p40 ( optlc_net_56 ) , .p41 ( optlc_net_57 ) , .p42 ( optlc_net_58 ) , + .p43 ( optlc_net_59 ) , .p44 ( optlc_net_60 ) , .p45 ( optlc_net_61 ) , + .p46 ( optlc_net_62 ) , .p47 ( optlc_net_63 ) , .p48 ( optlc_net_64 ) , + .p49 ( optlc_net_65 ) , .p50 ( optlc_net_66 ) , .p51 ( optlc_net_67 ) , + .p52 ( optlc_net_68 ) , .p53 ( optlc_net_69 ) , .p54 ( optlc_net_70 ) , + .p55 ( optlc_net_71 ) , .p56 ( optlc_net_72 ) , .p57 ( optlc_net_73 ) , + .p58 ( optlc_net_74 ) , .p59 ( optlc_net_75 ) , .p60 ( optlc_net_76 ) , + .p61 ( optlc_net_77 ) , .p62 ( optlc_net_78 ) , .p63 ( optlc_net_79 ) , + .p64 ( optlc_net_80 ) , .p65 ( optlc_net_81 ) , .p66 ( optlc_net_82 ) , + .p67 ( optlc_net_83 ) , .p68 ( optlc_net_84 ) , .p69 ( optlc_net_85 ) , + .p70 ( optlc_net_86 ) , .p71 ( optlc_net_87 ) , .p72 ( optlc_net_88 ) , + .p73 ( optlc_net_89 ) , .p74 ( optlc_net_90 ) , .p75 ( optlc_net_91 ) , + .p76 ( optlc_net_92 ) , .p77 ( optlc_net_93 ) , .p78 ( optlc_net_94 ) , + .p79 ( optlc_net_95 ) , .p80 ( optlc_net_96 ) , .p81 ( optlc_net_97 ) , + .p82 ( optlc_net_98 ) , .p83 ( optlc_net_99 ) , .p84 ( optlc_net_100 ) , + .p85 ( optlc_net_101 ) , .p86 ( optlc_net_102 ) , .p87 ( optlc_net_103 ) , + .p88 ( optlc_net_104 ) , .p89 ( optlc_net_105 ) , .p90 ( optlc_net_106 ) , + .p91 ( optlc_net_107 ) , .p92 ( optlc_net_108 ) , .p93 ( optlc_net_109 ) , + .p94 ( optlc_net_110 ) , .p95 ( optlc_net_111 ) , .p96 ( optlc_net_112 ) , + .p97 ( optlc_net_113 ) , .p98 ( optlc_net_114 ) , .p99 ( optlc_net_115 ) , + .p100 ( optlc_net_116 ) , .p101 ( optlc_net_117 ) , + .p102 ( optlc_net_118 ) , .p103 ( optlc_net_119 ) , + .p104 ( optlc_net_120 ) , .p105 ( optlc_net_121 ) , + .p106 ( optlc_net_122 ) , .p107 ( optlc_net_123 ) , + .p108 ( optlc_net_124 ) , .p109 ( optlc_net_125 ) , + .p110 ( optlc_net_126 ) , .p111 ( optlc_net_127 ) , + .p112 ( optlc_net_128 ) , .p113 ( optlc_net_129 ) , + .p114 ( optlc_net_130 ) , .p115 ( optlc_net_131 ) , + .p116 ( optlc_net_132 ) , .p117 ( optlc_net_133 ) , + .p118 ( optlc_net_134 ) , .p119 ( optlc_net_135 ) , + .p120 ( optlc_net_136 ) , .p121 ( optlc_net_137 ) , + .p122 ( optlc_net_138 ) , .p123 ( optlc_net_139 ) , + .p124 ( optlc_net_140 ) , .p125 ( optlc_net_141 ) , + .p126 ( optlc_net_142 ) , .p127 ( optlc_net_143 ) , + .p128 ( optlc_net_144 ) , .p129 ( optlc_net_145 ) , + .p130 ( optlc_net_146 ) , .p131 ( optlc_net_147 ) , + .p132 ( optlc_net_148 ) , .p133 ( optlc_net_149 ) , + .p134 ( optlc_net_150 ) , .p135 ( optlc_net_151 ) , + .p136 ( optlc_net_152 ) , .p137 ( optlc_net_153 ) , + .p138 ( optlc_net_154 ) , .p139 ( optlc_net_155 ) , + .p140 ( optlc_net_156 ) , .p141 ( optlc_net_157 ) , + .p142 ( optlc_net_158 ) , .p143 ( optlc_net_159 ) , + .p144 ( optlc_net_160 ) , .p145 ( optlc_net_161 ) , + .p146 ( optlc_net_162 ) , .p147 ( optlc_net_163 ) , + .p148 ( optlc_net_164 ) , .p149 ( optlc_net_165 ) , + .p150 ( optlc_net_166 ) , .p151 ( optlc_net_167 ) , + .p152 ( optlc_net_168 ) , .p153 ( optlc_net_169 ) , + .p154 ( optlc_net_170 ) , .p155 ( optlc_net_171 ) , + .p156 ( optlc_net_172 ) , .p157 ( optlc_net_173 ) , + .p158 ( optlc_net_174 ) , .p159 ( optlc_net_175 ) , + .p160 ( optlc_net_176 ) , .p161 ( optlc_net_177 ) , + .p162 ( optlc_net_178 ) , .p163 ( optlc_net_179 ) , + .p164 ( optlc_net_180 ) , .p165 ( optlc_net_181 ) , + .p166 ( optlc_net_182 ) , .p167 ( optlc_net_183 ) , + .p168 ( optlc_net_184 ) , .p169 ( optlc_net_185 ) , + .p170 ( optlc_net_186 ) , .p171 ( optlc_net_187 ) , + .p172 ( optlc_net_188 ) , .p173 ( optlc_net_189 ) , + .p174 ( optlc_net_190 ) , .p175 ( optlc_net_191 ) , + .p176 ( optlc_net_192 ) , .p177 ( optlc_net_193 ) , + .p178 ( optlc_net_194 ) , .p179 ( optlc_net_195 ) , + .p180 ( optlc_net_196 ) , .p181 ( optlc_net_197 ) , + .p182 ( optlc_net_198 ) , .p183 ( optlc_net_199 ) , + .p184 ( optlc_net_200 ) , .p185 ( optlc_net_201 ) , + .p186 ( optlc_net_202 ) , .p187 ( optlc_net_203 ) , + .p188 ( optlc_net_204 ) , .p189 ( optlc_net_205 ) , + .p190 ( optlc_net_206 ) , .p191 ( optlc_net_207 ) , + .p192 ( optlc_net_208 ) , .p193 ( optlc_net_209 ) , + .p194 ( optlc_net_210 ) , .p195 ( optlc_net_211 ) , + .p196 ( optlc_net_212 ) , .p197 ( optlc_net_213 ) , + .p198 ( optlc_net_214 ) , .p199 ( optlc_net_215 ) , + .p200 ( optlc_net_216 ) , .p201 ( optlc_net_217 ) , + .p202 ( optlc_net_218 ) , .p203 ( optlc_net_219 ) , + .p204 ( optlc_net_220 ) , .p205 ( optlc_net_221 ) , + .p206 ( optlc_net_222 ) , .p207 ( optlc_net_223 ) , + .p208 ( optlc_net_224 ) , .p209 ( optlc_net_225 ) , + .p210 ( optlc_net_226 ) , .p211 ( optlc_net_227 ) , + .p212 ( optlc_net_228 ) , .p213 ( optlc_net_229 ) , + .p214 ( optlc_net_230 ) , .p215 ( optlc_net_231 ) , + .p216 ( optlc_net_232 ) , .p217 ( optlc_net_233 ) , + .p218 ( optlc_net_234 ) , .p219 ( optlc_net_235 ) , + .p220 ( optlc_net_236 ) , .p221 ( optlc_net_237 ) , + .p222 ( optlc_net_238 ) , .p223 ( optlc_net_239 ) , + .p224 ( optlc_net_240 ) , .p225 ( optlc_net_241 ) , + .p226 ( optlc_net_242 ) , .p227 ( optlc_net_243 ) , + .p228 ( optlc_net_244 ) , .p229 ( optlc_net_245 ) , + .p230 ( optlc_net_246 ) , .p231 ( optlc_net_247 ) , + .p232 ( optlc_net_248 ) , .p233 ( optlc_net_249 ) , + .p234 ( optlc_net_250 ) , .p235 ( optlc_net_251 ) , + .p236 ( optlc_net_252 ) , .p237 ( optlc_net_253 ) , + .p238 ( optlc_net_254 ) , .p239 ( optlc_net_255 ) , + .p240 ( optlc_net_256 ) , .p241 ( optlc_net_257 ) , + .p242 ( optlc_net_258 ) , .p243 ( optlc_net_259 ) , + .p244 ( optlc_net_260 ) , .p245 ( optlc_net_261 ) , + .p246 ( optlc_net_262 ) , .p247 ( optlc_net_263 ) , + .p248 ( optlc_net_264 ) , .p249 ( optlc_net_265 ) , + .p250 ( optlc_net_266 ) , .p251 ( optlc_net_267 ) , + .p252 ( optlc_net_268 ) , .p253 ( optlc_net_269 ) , + .p254 ( optlc_net_270 ) , .p255 ( optlc_net_271 ) , + .p256 ( optlc_net_272 ) , .p257 ( optlc_net_273 ) , + .p258 ( optlc_net_274 ) , .p259 ( optlc_net_275 ) , + .p260 ( optlc_net_276 ) , .p261 ( optlc_net_277 ) , + .p262 ( optlc_net_278 ) , .p263 ( optlc_net_279 ) , + .p264 ( optlc_net_280 ) , .p265 ( optlc_net_281 ) , + .p266 ( optlc_net_282 ) , .p267 ( optlc_net_283 ) , + .p268 ( optlc_net_284 ) , .p269 ( optlc_net_285 ) , + .p270 ( optlc_net_286 ) , .p271 ( optlc_net_287 ) , + .p272 ( optlc_net_288 ) , .p273 ( optlc_net_289 ) , + .p274 ( optlc_net_290 ) , .p275 ( optlc_net_291 ) , + .p276 ( optlc_net_292 ) , .p277 ( optlc_net_293 ) , + .p278 ( optlc_net_294 ) , .p279 ( optlc_net_295 ) , + .p280 ( optlc_net_296 ) , .p281 ( optlc_net_297 ) , + .p282 ( optlc_net_298 ) , .p283 ( optlc_net_299 ) , + .p284 ( optlc_net_300 ) , .p285 ( optlc_net_301 ) , + .p286 ( optlc_net_302 ) , .p287 ( optlc_net_303 ) , + .p288 ( optlc_net_304 ) , .p289 ( optlc_net_305 ) , + .p290 ( optlc_net_306 ) , .p291 ( optlc_net_307 ) , + .p292 ( optlc_net_308 ) , .p293 ( optlc_net_309 ) , + .p294 ( optlc_net_310 ) , .p295 ( optlc_net_311 ) , + .p296 ( optlc_net_312 ) , .p297 ( optlc_net_313 ) , + .p298 ( optlc_net_314 ) , .p299 ( optlc_net_315 ) , + .p300 ( optlc_net_316 ) , .p301 ( optlc_net_317 ) , + .p302 ( optlc_net_318 ) , .p303 ( optlc_net_319 ) , + .p304 ( optlc_net_320 ) , .p305 ( optlc_net_321 ) , + .p306 ( optlc_net_322 ) , .p307 ( optlc_net_323 ) , + .p308 ( optlc_net_324 ) , .p309 ( optlc_net_325 ) , + .p310 ( optlc_net_326 ) , .p311 ( optlc_net_327 ) , + .p312 ( optlc_net_328 ) , .p313 ( optlc_net_329 ) , + .p314 ( optlc_net_330 ) , .p315 ( optlc_net_331 ) , + .p316 ( optlc_net_332 ) , .p317 ( optlc_net_333 ) , + .p318 ( optlc_net_334 ) , .p319 ( optlc_net_335 ) , + .p320 ( optlc_net_336 ) , .p321 ( optlc_net_337 ) , + .p322 ( optlc_net_338 ) , .p323 ( optlc_net_339 ) , + .p324 ( optlc_net_340 ) , .p325 ( optlc_net_341 ) , + .p326 ( optlc_net_342 ) , .p327 ( optlc_net_343 ) , + .p328 ( optlc_net_344 ) , .p329 ( optlc_net_345 ) , + .p330 ( optlc_net_346 ) , .p331 ( optlc_net_347 ) , + .p332 ( optlc_net_348 ) , .p333 ( optlc_net_349 ) , + .p334 ( optlc_net_350 ) , .p335 ( optlc_net_351 ) , + .p336 ( optlc_net_352 ) , .p337 ( optlc_net_353 ) , + .p338 ( optlc_net_354 ) , .p339 ( optlc_net_355 ) , + .p340 ( optlc_net_356 ) , .p341 ( optlc_net_357 ) , + .p342 ( optlc_net_358 ) , .p343 ( optlc_net_359 ) , + .p344 ( optlc_net_360 ) , .p345 ( optlc_net_361 ) , + .p346 ( optlc_net_362 ) , .p347 ( optlc_net_363 ) , + .p348 ( optlc_net_364 ) , .p349 ( optlc_net_365 ) , + .p350 ( optlc_net_366 ) , .p351 ( optlc_net_367 ) , + .p352 ( optlc_net_368 ) , .p353 ( optlc_net_369 ) , + .p354 ( optlc_net_370 ) , .p355 ( optlc_net_371 ) , + .p356 ( optlc_net_372 ) , .p357 ( optlc_net_373 ) , + .p358 ( optlc_net_374 ) , .p359 ( optlc_net_375 ) , + .p360 ( optlc_net_376 ) , .p361 ( optlc_net_377 ) , + .p362 ( optlc_net_378 ) , .p363 ( optlc_net_379 ) , + .p364 ( optlc_net_380 ) , .p365 ( optlc_net_381 ) , + .p366 ( optlc_net_382 ) , .p367 ( optlc_net_383 ) , + .p368 ( optlc_net_384 ) , .p369 ( optlc_net_385 ) , + .p370 ( optlc_net_386 ) , .p371 ( optlc_net_387 ) , + .p372 ( optlc_net_388 ) , .p373 ( optlc_net_389 ) , + .p374 ( optlc_net_390 ) , .p375 ( optlc_net_391 ) , + .p376 ( optlc_net_392 ) , .p377 ( optlc_net_393 ) , + .p378 ( optlc_net_394 ) , .p379 ( optlc_net_395 ) , + .p380 ( optlc_net_396 ) , .p381 ( optlc_net_397 ) , + .p382 ( optlc_net_398 ) , .p383 ( optlc_net_399 ) , + .p384 ( optlc_net_400 ) , .p385 ( optlc_net_401 ) , + .p386 ( optlc_net_402 ) , .p387 ( optlc_net_403 ) , + .p388 ( optlc_net_404 ) , .p389 ( optlc_net_405 ) , + .p390 ( optlc_net_406 ) , .p391 ( optlc_net_407 ) , + .p392 ( optlc_net_408 ) , .p393 ( optlc_net_409 ) , + .p394 ( optlc_net_410 ) , .p395 ( optlc_net_411 ) , + .p396 ( optlc_net_412 ) , .p397 ( optlc_net_413 ) , + .p398 ( optlc_net_414 ) , .p399 ( optlc_net_415 ) , + .p400 ( optlc_net_416 ) , .p401 ( optlc_net_417 ) , + .p402 ( optlc_net_418 ) , .p403 ( optlc_net_419 ) , + .p404 ( optlc_net_420 ) , .p405 ( optlc_net_421 ) , + .p406 ( optlc_net_422 ) , .p407 ( optlc_net_423 ) , + .p408 ( optlc_net_424 ) , .p409 ( optlc_net_425 ) , + .p410 ( optlc_net_426 ) , .p411 ( optlc_net_427 ) , + .p412 ( optlc_net_428 ) , .p413 ( optlc_net_429 ) , + .p414 ( optlc_net_430 ) , .p415 ( optlc_net_431 ) , + .p416 ( optlc_net_432 ) , .p417 ( optlc_net_433 ) , + .p418 ( optlc_net_434 ) , .p419 ( optlc_net_435 ) , + .p420 ( optlc_net_436 ) , .p421 ( optlc_net_437 ) , + .p422 ( optlc_net_438 ) , .p423 ( optlc_net_439 ) , + .p424 ( optlc_net_440 ) , .p425 ( optlc_net_441 ) , + .p426 ( optlc_net_442 ) , .p427 ( optlc_net_443 ) , + .p428 ( optlc_net_444 ) , .p429 ( optlc_net_445 ) , + .p430 ( optlc_net_446 ) , .p431 ( optlc_net_447 ) , + .p432 ( optlc_net_448 ) , .p433 ( optlc_net_449 ) , + .p434 ( optlc_net_450 ) , .p435 ( optlc_net_451 ) , + .p436 ( optlc_net_452 ) , .p437 ( optlc_net_453 ) , + .p438 ( optlc_net_454 ) , .p439 ( optlc_net_455 ) , + .p440 ( optlc_net_456 ) , .p441 ( optlc_net_457 ) , + .p442 ( optlc_net_458 ) , .p443 ( optlc_net_459 ) , + .p444 ( optlc_net_460 ) , .p445 ( optlc_net_461 ) , + .p446 ( optlc_net_462 ) , .p447 ( optlc_net_463 ) , + .p448 ( optlc_net_464 ) , .p449 ( optlc_net_465 ) , + .p450 ( optlc_net_466 ) , .p451 ( optlc_net_467 ) , + .p452 ( optlc_net_468 ) , .p453 ( optlc_net_469 ) , + .p454 ( optlc_net_470 ) , .p455 ( optlc_net_471 ) , + .p456 ( optlc_net_472 ) , .p457 ( optlc_net_473 ) , + .p458 ( optlc_net_474 ) , .p459 ( optlc_net_475 ) , + .p460 ( optlc_net_476 ) , .p461 ( optlc_net_477 ) , + .p462 ( optlc_net_478 ) , .p463 ( optlc_net_479 ) , + .p464 ( optlc_net_480 ) , .p465 ( optlc_net_481 ) , + .p466 ( optlc_net_482 ) , .p467 ( optlc_net_483 ) , + .p468 ( optlc_net_484 ) , .p469 ( optlc_net_485 ) , + .p470 ( optlc_net_486 ) , .p471 ( optlc_net_487 ) , + .p472 ( optlc_net_488 ) , .p473 ( optlc_net_489 ) , + .p474 ( optlc_net_490 ) , .p475 ( optlc_net_491 ) , + .p476 ( optlc_net_492 ) , .p477 ( optlc_net_493 ) , + .p478 ( optlc_net_494 ) , .p479 ( optlc_net_495 ) , + .p480 ( optlc_net_496 ) , .p481 ( optlc_net_497 ) , + .p482 ( optlc_net_498 ) , .p483 ( optlc_net_499 ) , + .p484 ( optlc_net_500 ) , .p485 ( optlc_net_501 ) , + .p486 ( optlc_net_502 ) , .p487 ( optlc_net_503 ) , + .p488 ( optlc_net_504 ) , .p489 ( optlc_net_505 ) , + .p490 ( optlc_net_506 ) , .p491 ( optlc_net_507 ) , + .p492 ( optlc_net_508 ) , .p493 ( optlc_net_509 ) , + .p494 ( optlc_net_510 ) , .p495 ( optlc_net_511 ) , + .p496 ( optlc_net_512 ) , .p497 ( optlc_net_513 ) , + .p498 ( optlc_net_514 ) , .p499 ( optlc_net_515 ) , + .p500 ( optlc_net_516 ) , .p501 ( optlc_net_517 ) , + .p502 ( optlc_net_518 ) , .p503 ( optlc_net_519 ) , + .p504 ( optlc_net_520 ) , .p505 ( optlc_net_521 ) , + .p506 ( optlc_net_522 ) , .p507 ( optlc_net_523 ) , + .p508 ( optlc_net_524 ) , .p509 ( optlc_net_525 ) , + .p510 ( optlc_net_526 ) , .p511 ( optlc_net_527 ) , + .p512 ( optlc_net_528 ) , .p513 ( optlc_net_529 ) , + .p514 ( optlc_net_530 ) , .p515 ( optlc_net_531 ) , + .p516 ( optlc_net_532 ) , .p517 ( optlc_net_533 ) , + .p518 ( optlc_net_534 ) , .p519 ( optlc_net_535 ) , + .p520 ( optlc_net_536 ) , .p521 ( optlc_net_537 ) , + .p522 ( optlc_net_538 ) , .p523 ( optlc_net_539 ) , + .p524 ( optlc_net_540 ) , .p525 ( optlc_net_541 ) , + .p526 ( optlc_net_542 ) , .p527 ( optlc_net_543 ) , + .p528 ( optlc_net_544 ) , .p529 ( optlc_net_545 ) , + .p530 ( optlc_net_546 ) , .p531 ( optlc_net_547 ) , + .p532 ( optlc_net_548 ) , .p533 ( optlc_net_549 ) , + .p534 ( optlc_net_550 ) , .p535 ( optlc_net_551 ) , + .p536 ( optlc_net_552 ) , .p537 ( optlc_net_553 ) , + .p538 ( optlc_net_554 ) , .p539 ( optlc_net_555 ) , + .p540 ( optlc_net_556 ) , .p541 ( optlc_net_557 ) , + .p542 ( optlc_net_558 ) , .p543 ( optlc_net_559 ) , + .p544 ( optlc_net_560 ) , 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.p582 ( optlc_net_598 ) , .p583 ( optlc_net_599 ) , + .p584 ( optlc_net_600 ) , .p585 ( optlc_net_601 ) , + .p586 ( optlc_net_602 ) , .p587 ( optlc_net_603 ) , + .p588 ( optlc_net_604 ) , .p589 ( optlc_net_605 ) , + .p590 ( optlc_net_606 ) , .p591 ( optlc_net_607 ) , + .p592 ( optlc_net_608 ) , .p593 ( optlc_net_609 ) , + .p594 ( optlc_net_610 ) , .p595 ( optlc_net_611 ) , + .p596 ( optlc_net_612 ) , .p597 ( optlc_net_613 ) , + .p598 ( optlc_net_614 ) , .p599 ( optlc_net_615 ) , + .p600 ( optlc_net_616 ) , .p601 ( optlc_net_617 ) , + .p602 ( optlc_net_618 ) , .p603 ( optlc_net_619 ) , + .p604 ( optlc_net_620 ) , .p605 ( optlc_net_621 ) , + .p606 ( optlc_net_622 ) , .p607 ( optlc_net_623 ) , + .p608 ( optlc_net_624 ) , .p609 ( optlc_net_625 ) , + .p610 ( optlc_net_626 ) , .p611 ( optlc_net_627 ) , + .p612 ( optlc_net_628 ) , .p613 ( optlc_net_629 ) , + .p614 ( optlc_net_630 ) , .p615 ( optlc_net_631 ) , + .p616 ( optlc_net_632 ) , .p617 ( optlc_net_633 ) , + .p618 ( optlc_net_634 ) , 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optlc_net_1143 ) , + .p1128 ( optlc_net_1144 ) , .p1129 ( optlc_net_1145 ) , + .p1130 ( optlc_net_1146 ) , .p1131 ( optlc_net_1147 ) , + .p1132 ( optlc_net_1148 ) , .p1133 ( optlc_net_1149 ) , + .p1134 ( optlc_net_1150 ) , .p1135 ( optlc_net_1151 ) , + .p1136 ( optlc_net_1152 ) , .p1137 ( optlc_net_1153 ) , + .p1138 ( optlc_net_1154 ) , .p1139 ( optlc_net_1155 ) , + .p1140 ( optlc_net_1156 ) , .p1141 ( optlc_net_1157 ) , + .p1142 ( optlc_net_1158 ) , .p1143 ( optlc_net_1159 ) , + .p1144 ( optlc_net_1160 ) , .p1145 ( optlc_net_1161 ) , + .p1146 ( optlc_net_1162 ) , .p1147 ( optlc_net_1163 ) , + .p1148 ( optlc_net_1164 ) , .p1149 ( optlc_net_1165 ) , + .p1150 ( optlc_net_1166 ) , .p1151 ( optlc_net_1167 ) , + .p1152 ( optlc_net_1168 ) , .p1153 ( optlc_net_1169 ) , + .p1154 ( optlc_net_1170 ) , .p1155 ( optlc_net_1171 ) , + .p1156 ( optlc_net_1172 ) , .p1157 ( optlc_net_1173 ) , + .p1158 ( optlc_net_1174 ) , .p1159 ( optlc_net_1175 ) , + .p1160 ( optlc_net_1176 ) , .p1161 ( optlc_net_1177 ) , + .p1162 ( optlc_net_1178 ) , .p1163 ( optlc_net_1179 ) , + .p1164 ( optlc_net_1180 ) , .p1165 ( optlc_net_1181 ) , + .p1166 ( optlc_net_1182 ) , .p1167 ( optlc_net_1183 ) , + .p1168 ( optlc_net_1184 ) , .p1169 ( optlc_net_1185 ) , + .p1170 ( optlc_net_1186 ) , .p1171 ( optlc_net_1187 ) , + .p1172 ( optlc_net_1188 ) , .p1173 ( optlc_net_1189 ) , + .p1174 ( optlc_net_1190 ) , .p1175 ( optlc_net_1191 ) , + .p1176 ( optlc_net_1192 ) , .p1177 ( optlc_net_1193 ) , + .p1178 ( optlc_net_1194 ) , .p1179 ( optlc_net_1195 ) , + .p1180 ( optlc_net_1196 ) , .p1181 ( optlc_net_1197 ) , + .p1182 ( optlc_net_1198 ) , .p1183 ( optlc_net_1199 ) , + .p1184 ( optlc_net_1200 ) , .p1185 ( optlc_net_1201 ) , + .p1186 ( optlc_net_1202 ) , .p1187 ( optlc_net_1203 ) , + .p1188 ( optlc_net_1204 ) , .p1189 ( optlc_net_1205 ) , + .p1190 ( optlc_net_1206 ) , .p1191 ( optlc_net_1207 ) , + .p1192 ( optlc_net_1208 ) , .p1193 ( optlc_net_1209 ) , + .p1194 ( optlc_net_1210 ) , .p1195 ( optlc_net_1211 ) , + .p1196 ( optlc_net_1212 ) , .p1197 ( optlc_net_1213 ) , + .p1198 ( optlc_net_1214 ) , .p1199 ( optlc_net_1215 ) , + .p1200 ( optlc_net_1216 ) , .p1201 ( optlc_net_1217 ) , + .p1202 ( optlc_net_1218 ) , .p1203 ( optlc_net_1219 ) , + .p1204 ( optlc_net_1220 ) , .p1205 ( optlc_net_1221 ) , + .p1206 ( optlc_net_1222 ) , .p1207 ( optlc_net_1223 ) , + .p1208 ( optlc_net_1224 ) , .p1209 ( optlc_net_1225 ) , + .p1210 ( optlc_net_1226 ) , .p1211 ( optlc_net_1227 ) , + .p1212 ( optlc_net_1228 ) , .p1213 ( optlc_net_1229 ) , + .p1214 ( optlc_net_1230 ) , .p1215 ( optlc_net_1231 ) , + .p1216 ( optlc_net_1232 ) , .p1217 ( optlc_net_1233 ) , + .p1218 ( optlc_net_1234 ) , .p1219 ( optlc_net_1235 ) , + .p1220 ( optlc_net_1236 ) , .p1221 ( optlc_net_1237 ) , + .p1222 ( optlc_net_1238 ) , .p1223 ( optlc_net_1239 ) , + .p1224 ( optlc_net_1240 ) , .p1225 ( optlc_net_1241 ) , + .p1226 ( optlc_net_1242 ) , .p1227 ( optlc_net_1243 ) , + .p1228 ( optlc_net_1244 ) , .p1229 ( optlc_net_1245 ) , + .p1230 ( optlc_net_1246 ) , .p1231 ( optlc_net_1247 ) , + .p1232 ( optlc_net_1248 ) , .p1233 ( optlc_net_1249 ) , + .p1234 ( optlc_net_1250 ) , .p1235 ( optlc_net_1251 ) , + .p1236 ( optlc_net_1252 ) , .p1237 ( optlc_net_1253 ) , + .p1238 ( optlc_net_1254 ) , .p1239 ( optlc_net_1255 ) , + .p1240 ( optlc_net_1256 ) , .p1241 ( optlc_net_1257 ) , + .p1242 ( optlc_net_1258 ) , .p1243 ( optlc_net_1259 ) , + .p1244 ( optlc_net_1260 ) , .p1245 ( optlc_net_1261 ) , + .p1246 ( optlc_net_1262 ) , .p1247 ( optlc_net_1263 ) , + .p1248 ( optlc_net_1264 ) , .p1249 ( optlc_net_1265 ) , + .p1250 ( optlc_net_1266 ) , .p1251 ( optlc_net_1267 ) , + .p1252 ( optlc_net_1268 ) , .p1253 ( optlc_net_1269 ) , + .p1254 ( optlc_net_1270 ) , .p1255 ( optlc_net_1271 ) , + .p1256 ( optlc_net_1272 ) , .p1257 ( optlc_net_1273 ) , + .p1258 ( optlc_net_1274 ) , .p1259 ( optlc_net_1275 ) , + .p1260 ( optlc_net_1276 ) , .p1261 ( optlc_net_1277 ) , + .p1262 ( optlc_net_1278 ) , .p1263 ( optlc_net_1279 ) , + .p1264 ( optlc_net_1280 ) , .p1265 ( optlc_net_1281 ) , + .p1266 ( optlc_net_1282 ) , .p1267 ( optlc_net_1283 ) , + .p1268 ( optlc_net_1284 ) , .p1269 ( optlc_net_1285 ) , + .p1270 ( optlc_net_1286 ) , .p1271 ( optlc_net_1287 ) , + .p1272 ( optlc_net_1288 ) , .p1273 ( optlc_net_1289 ) , + .p1274 ( optlc_net_1290 ) , .p1275 ( optlc_net_1291 ) , + .p1276 ( optlc_net_1292 ) , .p1277 ( optlc_net_1293 ) , + .p1278 ( optlc_net_1294 ) , .p1279 ( optlc_net_1295 ) , + .p1280 ( optlc_net_1296 ) , .p1281 ( optlc_net_1297 ) , + .p1282 ( optlc_net_1298 ) , .p1283 ( optlc_net_1299 ) , + .p1284 ( optlc_net_1300 ) , .p1285 ( optlc_net_1301 ) , + .p1286 ( optlc_net_1302 ) , .p1287 ( optlc_net_1303 ) , + .p1288 ( optlc_net_1304 ) , .p1289 ( optlc_net_1305 ) , + .p1290 ( optlc_net_1306 ) , .p1291 ( optlc_net_1307 ) , + .p1292 ( optlc_net_1308 ) , .p1293 ( optlc_net_1309 ) , + .p1294 ( optlc_net_1310 ) , .p1295 ( optlc_net_1311 ) , + .p1296 ( optlc_net_1312 ) , .p1297 ( optlc_net_1313 ) , + .p1298 ( optlc_net_1314 ) , .p1299 ( optlc_net_1315 ) , + .p1300 ( optlc_net_1316 ) , .p1301 ( optlc_net_1317 ) , + .p1302 ( optlc_net_1318 ) , .p1303 ( optlc_net_1319 ) , + .p1304 ( optlc_net_1320 ) , .p1305 ( optlc_net_1321 ) , + .p1306 ( optlc_net_1322 ) , .p1307 ( optlc_net_1323 ) , + .p1308 ( optlc_net_1324 ) , .p1309 ( optlc_net_1325 ) , + .p1310 ( optlc_net_1326 ) , .p1311 ( optlc_net_1327 ) , + .p1312 ( optlc_net_1328 ) , .p1313 ( optlc_net_1329 ) , + .p1314 ( optlc_net_1330 ) , .p1315 ( optlc_net_1331 ) , + .p1316 ( optlc_net_1332 ) , .p1317 ( optlc_net_1333 ) , + .p1318 ( optlc_net_1334 ) , .p1319 ( optlc_net_1335 ) , + .p1320 ( optlc_net_1336 ) , .p1321 ( optlc_net_1337 ) , + .p1322 ( optlc_net_1338 ) , .p1323 ( optlc_net_1339 ) , + .p1324 ( optlc_net_1340 ) , .p1325 ( optlc_net_1341 ) , + .p1326 ( optlc_net_1342 ) , .p1327 ( optlc_net_1343 ) , + .p1328 ( optlc_net_1344 ) , .p1329 ( optlc_net_1345 ) , + .p1330 ( optlc_net_1346 ) , .p1331 ( optlc_net_1347 ) , + .p1332 ( optlc_net_1348 ) , .p1333 ( optlc_net_1349 ) , + .p1334 ( optlc_net_1350 ) , .p1335 ( optlc_net_1351 ) , + .p1336 ( optlc_net_1352 ) , .p1337 ( optlc_net_1353 ) , + .p1338 ( optlc_net_1354 ) , .p1339 ( optlc_net_1355 ) , + .p1340 ( optlc_net_1356 ) , .p1341 ( optlc_net_1357 ) , + .p1342 ( optlc_net_1358 ) , .p1343 ( optlc_net_1359 ) , + .p1344 ( optlc_net_1360 ) , .p1345 ( optlc_net_1361 ) , + .p1346 ( optlc_net_1362 ) , .p1347 ( optlc_net_1363 ) , + .p1348 ( optlc_net_1364 ) , .p1349 ( optlc_net_1365 ) , + .p1350 ( optlc_net_1366 ) , .p1351 ( optlc_net_1367 ) , + .p1352 ( optlc_net_1368 ) , .p1353 ( optlc_net_1369 ) , + .p1354 ( optlc_net_1370 ) , .p1355 ( optlc_net_1371 ) , + .p1356 ( optlc_net_1372 ) , .p1357 ( optlc_net_1373 ) , + .p1358 ( optlc_net_1374 ) , .p1359 ( optlc_net_1375 ) , + .p1360 ( optlc_net_1376 ) , .p1361 ( optlc_net_1377 ) , + .p1362 ( optlc_net_1378 ) , .p1363 ( optlc_net_1379 ) , + .p1364 ( optlc_net_1380 ) , .p1365 ( optlc_net_1381 ) , + .p1366 ( optlc_net_1382 ) , .p1367 ( optlc_net_1383 ) , + .p1368 ( optlc_net_1384 ) , .p1369 ( optlc_net_1385 ) , + .p1370 ( optlc_net_1386 ) , .p1371 ( optlc_net_1387 ) , + .p1372 ( optlc_net_1388 ) , .p1373 ( optlc_net_1389 ) , + .p1374 ( optlc_net_1390 ) , .p1375 ( optlc_net_1391 ) , + .p1376 ( optlc_net_1392 ) , .p1377 ( optlc_net_1393 ) , + .p1378 ( optlc_net_1394 ) , .p1379 ( optlc_net_1395 ) , + .p1380 ( optlc_net_1396 ) , .p1381 ( optlc_net_1397 ) , + .p1382 ( optlc_net_1398 ) , .p1383 ( optlc_net_1399 ) , + .p1384 ( optlc_net_1400 ) , .p1385 ( optlc_net_1401 ) , + .p1386 ( optlc_net_1402 ) , .p1387 ( optlc_net_1403 ) , + .p1388 ( optlc_net_1404 ) , .p1389 ( optlc_net_1405 ) , + .p1390 ( optlc_net_1406 ) , .p1391 ( optlc_net_1407 ) , + .p1392 ( optlc_net_1408 ) , .p1393 ( optlc_net_1409 ) , + .p1394 ( optlc_net_1410 ) , .p1395 ( optlc_net_1411 ) , + .p1396 ( optlc_net_1412 ) , .p1397 ( optlc_net_1413 ) , + .p1398 ( optlc_net_1414 ) , .p1399 ( optlc_net_1415 ) , + .p1400 ( optlc_net_1416 ) , .p1401 ( optlc_net_1417 ) , + .p1402 ( optlc_net_1418 ) , .p1403 ( optlc_net_1419 ) , + .p1404 ( optlc_net_1420 ) , .p1405 ( optlc_net_1421 ) , + .p1406 ( optlc_net_1422 ) , .p1407 ( optlc_net_1423 ) , + .p1408 ( optlc_net_1424 ) , .p1409 ( optlc_net_1425 ) , + .p1410 ( optlc_net_1426 ) , .p1411 ( optlc_net_1427 ) , + .p1412 ( optlc_net_1428 ) , .p1413 ( optlc_net_1429 ) , + .p1414 ( optlc_net_1430 ) , .p1415 ( optlc_net_1431 ) , + .p1416 ( optlc_net_1432 ) , .p1417 ( optlc_net_1433 ) , + .p1418 ( optlc_net_1434 ) , .p1419 ( optlc_net_1435 ) , + .p1420 ( optlc_net_1436 ) , .p1421 ( optlc_net_1437 ) , + .p1422 ( optlc_net_1438 ) , .p1423 ( optlc_net_1439 ) , + .p1424 ( optlc_net_1440 ) , .p1425 ( optlc_net_1441 ) , + .p1426 ( optlc_net_1442 ) , .p1427 ( optlc_net_1443 ) , + .p1428 ( optlc_net_1444 ) , .p1429 ( optlc_net_1445 ) , + .p1430 ( optlc_net_1446 ) , .p1431 ( optlc_net_1447 ) , + .p1432 ( optlc_net_1448 ) , .p1433 ( optlc_net_1449 ) , + .p1434 ( optlc_net_1450 ) , .p1435 ( optlc_net_1451 ) , + .p1436 ( optlc_net_1452 ) , .p1437 ( optlc_net_1453 ) , + .p1438 ( optlc_net_1454 ) , .p1439 ( optlc_net_1455 ) , + .p1440 ( optlc_net_1456 ) , .p1441 ( optlc_net_1457 ) , + .p1442 ( optlc_net_1458 ) , .p1443 ( optlc_net_1459 ) , + .p1444 ( optlc_net_1460 ) , .p1445 ( optlc_net_1461 ) , + .p1446 ( optlc_net_1462 ) , .p1447 ( optlc_net_1463 ) , + .p1448 ( optlc_net_1464 ) , .p1449 ( optlc_net_1465 ) , + .p1450 ( optlc_net_1466 ) , .p1451 ( optlc_net_1467 ) , + .p1452 ( optlc_net_1468 ) , .p1453 ( optlc_net_1469 ) , + .p1454 ( optlc_net_1470 ) , .p1455 ( optlc_net_1471 ) , + .p1456 ( optlc_net_1472 ) , .p1457 ( optlc_net_1473 ) , + .p1458 ( optlc_net_1474 ) , .p1459 ( optlc_net_1475 ) , + .p1460 ( optlc_net_1476 ) , .p1461 ( optlc_net_1477 ) , + .p1462 ( optlc_net_1478 ) , .p1463 ( optlc_net_1479 ) , + .p1464 ( optlc_net_1480 ) , .p1465 ( optlc_net_1481 ) , + .p1466 ( optlc_net_1482 ) , .p1467 ( optlc_net_1483 ) , + .p1468 ( optlc_net_1484 ) , .p1469 ( optlc_net_1485 ) , + .p1470 ( optlc_net_1486 ) , .p1471 ( optlc_net_1487 ) , + .p1472 ( optlc_net_1488 ) , .p1473 ( optlc_net_1489 ) , + .p1474 ( optlc_net_1490 ) , .p1475 ( optlc_net_1491 ) , + .p1476 ( optlc_net_1492 ) , .p1477 ( optlc_net_1493 ) , + .p1478 ( optlc_net_1494 ) , .p1479 ( optlc_net_1495 ) , + .p1480 ( optlc_net_1496 ) , .p1481 ( optlc_net_1497 ) , + .p1482 ( optlc_net_1498 ) , .p1483 ( optlc_net_1499 ) , + .p1484 ( optlc_net_1500 ) , .p1485 ( optlc_net_1501 ) , + .p1486 ( optlc_net_1502 ) , .p1487 ( optlc_net_1503 ) , + .p1488 ( optlc_net_1504 ) , .p1489 ( optlc_net_1505 ) , + .p1490 ( optlc_net_1506 ) , .p1491 ( optlc_net_1507 ) , + .p1492 ( optlc_net_1508 ) , .p1493 ( optlc_net_1509 ) , + .p1494 ( optlc_net_1510 ) , .p1495 ( optlc_net_1511 ) , + .p1496 ( optlc_net_1512 ) , .p1497 ( optlc_net_1513 ) , + .p1498 ( optlc_net_1514 ) , .p1499 ( optlc_net_1515 ) , + .p1500 ( optlc_net_1516 ) , .p1501 ( optlc_net_1517 ) , + .p1502 ( optlc_net_1518 ) , .p1503 ( optlc_net_1519 ) , + .p1504 ( optlc_net_1520 ) , .p1505 ( optlc_net_1521 ) , + .p1506 ( optlc_net_1522 ) , .p1507 ( optlc_net_1523 ) , + .p1508 ( optlc_net_1524 ) , .p1509 ( optlc_net_1525 ) , + .p1510 ( optlc_net_1526 ) , .p1511 ( optlc_net_1527 ) , + .p1512 ( optlc_net_1528 ) , .p1513 ( optlc_net_1529 ) , + .p1514 ( optlc_net_1530 ) , .p1515 ( optlc_net_1531 ) , + .p1516 ( optlc_net_1532 ) , .p1517 ( optlc_net_1533 ) , + .p1518 ( optlc_net_1534 ) , .p1519 ( optlc_net_1535 ) , + .p1520 ( optlc_net_1536 ) , .p1521 ( optlc_net_1537 ) , + .p1522 ( optlc_net_1538 ) , .p1523 ( optlc_net_1539 ) , + .p1524 ( optlc_net_1540 ) , .p1525 ( optlc_net_1541 ) , + .p1526 ( optlc_net_1542 ) , .p1527 ( optlc_net_1543 ) , + .p1528 ( optlc_net_1544 ) , .p1529 ( optlc_net_1545 ) , + .p1530 ( optlc_net_1546 ) , .p1531 ( optlc_net_1547 ) , + .p1532 ( optlc_net_1548 ) , .p1533 ( optlc_net_1549 ) , + .p1534 ( optlc_net_1550 ) , .p1535 ( optlc_net_1551 ) , + .p1536 ( optlc_net_1552 ) , .p1537 ( optlc_net_1553 ) , + .p1538 ( optlc_net_1554 ) , .p1539 ( optlc_net_1555 ) , + .p1540 ( optlc_net_1556 ) , .p1541 ( optlc_net_1557 ) , + .p1542 ( optlc_net_1558 ) , .p1543 ( optlc_net_1559 ) , + .p1544 ( optlc_net_1560 ) , .p1545 ( optlc_net_1561 ) , + .p1546 ( optlc_net_1562 ) , .p1547 ( optlc_net_1563 ) , + .p1548 ( optlc_net_1564 ) , .p1549 ( optlc_net_1565 ) , + .p1550 ( optlc_net_1566 ) , .p1551 ( optlc_net_1567 ) , + .p1552 ( optlc_net_1568 ) , .p1553 ( optlc_net_1569 ) , + .p1554 ( optlc_net_1570 ) , .p1555 ( optlc_net_1571 ) , + .p1556 ( optlc_net_1572 ) , .p1557 ( optlc_net_1573 ) , + .p1558 ( optlc_net_1574 ) , .p1559 ( optlc_net_1575 ) , + .p1560 ( optlc_net_1576 ) , .p1561 ( optlc_net_1577 ) , + .p1562 ( optlc_net_1578 ) , .p1563 ( optlc_net_1579 ) , + .p1564 ( optlc_net_1580 ) , .p1565 ( optlc_net_1581 ) , + .p1566 ( optlc_net_1582 ) , .p1567 ( optlc_net_1583 ) , + .p1568 ( optlc_net_1584 ) , .p1569 ( optlc_net_1585 ) , + .p1570 ( optlc_net_1586 ) , .p1571 ( optlc_net_1587 ) , + .p1572 ( optlc_net_1588 ) , .p1573 ( optlc_net_1589 ) , + .p1574 ( optlc_net_1590 ) , .p1575 ( optlc_net_1591 ) , + .p1576 ( optlc_net_1592 ) , .p1577 ( optlc_net_1593 ) , + .p1578 ( optlc_net_1594 ) , .p1579 ( optlc_net_1595 ) , + .p1580 ( optlc_net_1596 ) , .p1581 ( optlc_net_1597 ) , + .p1582 ( optlc_net_1598 ) , .p1583 ( optlc_net_1599 ) , + .p1584 ( optlc_net_1600 ) , .p1585 ( optlc_net_1601 ) , + .p1586 ( optlc_net_1602 ) , .p1587 ( optlc_net_1603 ) , + .p1588 ( optlc_net_1604 ) , .p1589 ( optlc_net_1605 ) , + .p1590 ( optlc_net_1606 ) , .p1591 ( optlc_net_1607 ) , + .p1592 ( optlc_net_1608 ) , .p1593 ( optlc_net_1609 ) , + .p1594 ( optlc_net_1610 ) , .p1595 ( optlc_net_1611 ) , + .p1596 ( optlc_net_1612 ) , .p1597 ( optlc_net_1613 ) , + .p1598 ( optlc_net_1614 ) , .p1599 ( optlc_net_1615 ) , + .p1600 ( optlc_net_1616 ) , .p1601 ( optlc_net_1617 ) , + .p1602 ( optlc_net_1618 ) , .p1603 ( optlc_net_1619 ) , + .p1604 ( optlc_net_1620 ) , .p1605 ( optlc_net_1621 ) , + .p1606 ( optlc_net_1622 ) , .p1607 ( optlc_net_1623 ) , + .p1608 ( optlc_net_1624 ) , .p1609 ( optlc_net_1625 ) , + .p1610 ( optlc_net_1626 ) , .p1611 ( optlc_net_1627 ) , + .p1612 ( optlc_net_1628 ) , .p1613 ( optlc_net_1629 ) , + .p1614 ( optlc_net_1630 ) , .p1615 ( optlc_net_1631 ) , + .p1616 ( optlc_net_1632 ) , .p1617 ( optlc_net_1633 ) , + .p1618 ( optlc_net_1634 ) , .p1619 ( optlc_net_1635 ) , + .p1620 ( optlc_net_1636 ) , .p1621 ( optlc_net_1637 ) , + .p1622 ( optlc_net_1638 ) , .p1623 ( optlc_net_1639 ) , + .p1624 ( optlc_net_1640 ) , .p1625 ( optlc_net_1641 ) , + .p1626 ( optlc_net_1642 ) , .p1627 ( optlc_net_1643 ) , + .p1628 ( optlc_net_1644 ) , .p1629 ( optlc_net_1645 ) , + .p1630 ( optlc_net_1646 ) , .p1631 ( optlc_net_1647 ) , + .p1632 ( optlc_net_1648 ) , .p1633 ( optlc_net_1649 ) , + .p1634 ( optlc_net_1650 ) , .p1635 ( optlc_net_1651 ) , + .p1636 ( optlc_net_1652 ) , .p1637 ( optlc_net_1653 ) , + .p1638 ( optlc_net_1654 ) , .p1639 ( optlc_net_1655 ) , + .p1640 ( optlc_net_1656 ) , .p1641 ( optlc_net_1657 ) , + .p1642 ( optlc_net_1658 ) , .p1643 ( optlc_net_1659 ) , + .p1644 ( optlc_net_1660 ) , .p1645 ( optlc_net_1661 ) , + .p1646 ( optlc_net_1662 ) , .p1647 ( optlc_net_1663 ) , + .p1648 ( optlc_net_1664 ) , .p1649 ( optlc_net_1665 ) , + .p1650 ( optlc_net_1666 ) , .p1651 ( optlc_net_1667 ) , + .p1652 ( optlc_net_1668 ) , .p1653 ( optlc_net_1669 ) , + .p1654 ( optlc_net_1670 ) , .p1655 ( optlc_net_1671 ) , + .p1656 ( optlc_net_1672 ) , .p1657 ( optlc_net_1673 ) , + .p1658 ( optlc_net_1674 ) , .p1659 ( optlc_net_1675 ) , + .p1660 ( optlc_net_1676 ) , .p1661 ( optlc_net_1677 ) , + .p1662 ( optlc_net_1678 ) , .p1663 ( optlc_net_1679 ) , + .p1664 ( optlc_net_1680 ) , .p1665 ( optlc_net_1681 ) , + .p1666 ( optlc_net_1682 ) , .p1667 ( optlc_net_1683 ) , + .p1668 ( optlc_net_1684 ) , .p1669 ( optlc_net_1685 ) , + .p1670 ( optlc_net_1686 ) , .p1671 ( optlc_net_1687 ) , + .p1672 ( optlc_net_1688 ) , .p1673 ( optlc_net_1689 ) , + .p1674 ( optlc_net_1690 ) , .p1675 ( optlc_net_1691 ) , + .p1676 ( optlc_net_1692 ) , .p1677 ( optlc_net_1693 ) , + .p1678 ( optlc_net_1694 ) , .p1679 ( optlc_net_1695 ) , + .p1680 ( optlc_net_1696 ) , .p1681 ( optlc_net_1697 ) , + .p1682 ( optlc_net_1698 ) , .p1683 ( optlc_net_1699 ) , + .p1684 ( optlc_net_1700 ) , .p1685 ( optlc_net_1701 ) , + .p1686 ( optlc_net_1702 ) , .p1687 ( optlc_net_1703 ) , + .p1688 ( optlc_net_1704 ) , .p1689 ( optlc_net_1705 ) , + .p1690 ( optlc_net_1706 ) , .p1691 ( optlc_net_1707 ) , + .p1692 ( optlc_net_1708 ) , .p1693 ( optlc_net_1709 ) , + .p1694 ( optlc_net_1710 ) , .p1695 ( optlc_net_1711 ) , + .p1696 ( optlc_net_1712 ) , .p1697 ( optlc_net_1713 ) , + .p1698 ( optlc_net_1714 ) , .p1699 ( optlc_net_1715 ) , + .p1700 ( optlc_net_1716 ) , .p1701 ( optlc_net_1717 ) , + .p1702 ( optlc_net_1718 ) , .p1703 ( optlc_net_1719 ) , + .p1704 ( optlc_net_1720 ) , .p1705 ( optlc_net_1721 ) , + .p1706 ( optlc_net_1722 ) , .p1707 ( optlc_net_1723 ) , + .p1708 ( optlc_net_1724 ) , .p1709 ( optlc_net_1725 ) , + .p1710 ( optlc_net_1726 ) , .p1711 ( optlc_net_1727 ) , + .p1712 ( optlc_net_1728 ) , .p1713 ( optlc_net_1729 ) , + .p1714 ( optlc_net_1730 ) , .p1715 ( optlc_net_1731 ) , + .p1716 ( optlc_net_1732 ) , .p1717 ( optlc_net_1733 ) , + .p1718 ( optlc_net_1734 ) , .p1719 ( optlc_net_1735 ) , + .p1720 ( optlc_net_1736 ) , .p1721 ( optlc_net_1737 ) , + .p1722 ( optlc_net_1738 ) , .p1723 ( optlc_net_1739 ) , + .p1724 ( optlc_net_1740 ) , .p1725 ( optlc_net_1741 ) , + .p1726 ( optlc_net_1742 ) , .p1727 ( optlc_net_1743 ) , + .p1728 ( optlc_net_1744 ) , .p1729 ( optlc_net_1745 ) , + .p1730 ( optlc_net_1746 ) , .p1731 ( optlc_net_1747 ) , + .p1732 ( optlc_net_1748 ) , .p1733 ( optlc_net_1749 ) , + .p1734 ( optlc_net_1750 ) , .p1735 ( optlc_net_1751 ) , + .p1736 ( optlc_net_1752 ) , .p1737 ( optlc_net_1753 ) , + .p1738 ( optlc_net_1754 ) , .p1739 ( optlc_net_1755 ) , + .p1740 ( optlc_net_1756 ) , .p1741 ( optlc_net_1757 ) , + .p1742 ( optlc_net_1758 ) , .p1743 ( optlc_net_1759 ) , + .p1744 ( optlc_net_1760 ) , .p1745 ( optlc_net_1761 ) , + .p1746 ( optlc_net_1762 ) , .p1747 ( optlc_net_1763 ) , + .p1748 ( optlc_net_1764 ) , .p1749 ( optlc_net_1765 ) , + .p1750 ( optlc_net_1766 ) , .p1751 ( optlc_net_1767 ) , + .p1752 ( optlc_net_1768 ) , .p1753 ( optlc_net_1769 ) , + .p1754 ( optlc_net_1770 ) , .p1755 ( optlc_net_1771 ) , + .p1756 ( optlc_net_1772 ) , .p1757 ( optlc_net_1773 ) , + .p1758 ( optlc_net_1774 ) , .p1759 ( optlc_net_1775 ) , + .p1760 ( optlc_net_1776 ) , .p1761 ( optlc_net_1777 ) , + .p1762 ( optlc_net_1778 ) , .p1763 ( optlc_net_1779 ) , + .p1764 ( optlc_net_1780 ) , .p1765 ( optlc_net_1781 ) , + .p1766 ( optlc_net_1782 ) , .p1767 ( optlc_net_1783 ) , + .p1768 ( optlc_net_1784 ) , .p1769 ( optlc_net_1785 ) , + .p1770 ( optlc_net_1786 ) , .p1771 ( optlc_net_1787 ) , + .p1772 ( optlc_net_1788 ) , .p1773 ( optlc_net_1789 ) , + .p1774 ( optlc_net_1790 ) , .p1775 ( optlc_net_1791 ) , + .p1776 ( optlc_net_1792 ) , .p1777 ( optlc_net_1793 ) , + .p1778 ( optlc_net_1794 ) , .p1779 ( optlc_net_1795 ) , + .p1780 ( optlc_net_1796 ) , .p1781 ( optlc_net_1797 ) , + .p1782 ( optlc_net_1798 ) , .p1783 ( optlc_net_1799 ) , + .p1784 ( optlc_net_1800 ) , .p1785 ( optlc_net_1801 ) , + .p1786 ( optlc_net_1802 ) , .p1787 ( optlc_net_1803 ) , + .p1788 ( optlc_net_1804 ) , .p1789 ( optlc_net_1805 ) , + .p1790 ( optlc_net_1806 ) , .p1791 ( optlc_net_1807 ) , + .p1792 ( optlc_net_1808 ) , .p1793 ( optlc_net_1809 ) , + .p1794 ( optlc_net_1810 ) , .p1795 ( optlc_net_1811 ) , + .p1796 ( optlc_net_1812 ) , .p1797 ( optlc_net_1813 ) , + .p1798 ( optlc_net_1814 ) , .p1799 ( optlc_net_1815 ) , + .p1800 ( optlc_net_1816 ) , .p1801 ( optlc_net_1817 ) , + .p1802 ( optlc_net_1818 ) , .p1803 ( optlc_net_1819 ) , + .p1804 ( optlc_net_1820 ) , .p1805 ( optlc_net_1821 ) , + .p1806 ( optlc_net_1822 ) , .p1807 ( optlc_net_1823 ) , + .p1808 ( optlc_net_1824 ) , .p1809 ( optlc_net_1825 ) , + .p1810 ( optlc_net_1826 ) , .p1811 ( optlc_net_1827 ) , + .p1812 ( optlc_net_1828 ) , .p1813 ( optlc_net_1829 ) , + .p1814 ( optlc_net_1830 ) , .p1815 ( optlc_net_1831 ) , + .p1816 ( optlc_net_1832 ) , .p1817 ( optlc_net_1833 ) , + .p1818 ( optlc_net_1834 ) , .p1819 ( optlc_net_1835 ) , + .p1820 ( optlc_net_1836 ) , .p1821 ( optlc_net_1837 ) , + .p1822 ( optlc_net_1838 ) , .p1823 ( optlc_net_1839 ) , + .p1824 ( optlc_net_1840 ) , .p1825 ( optlc_net_1841 ) , + .p1826 ( optlc_net_1842 ) , .p1827 ( optlc_net_1843 ) , + .p1828 ( optlc_net_1844 ) , .p1829 ( optlc_net_1845 ) , + .p1830 ( optlc_net_1846 ) , .p1831 ( optlc_net_1847 ) , + .p1832 ( optlc_net_1848 ) , .p1833 ( optlc_net_1849 ) , + .p1834 ( optlc_net_1850 ) , .p1835 ( optlc_net_1851 ) , + .p1836 ( optlc_net_1852 ) , .p1837 ( optlc_net_1853 ) , + .p1838 ( optlc_net_1854 ) , .p1839 ( optlc_net_1855 ) , + .p1840 ( optlc_net_1856 ) , .p1841 ( optlc_net_1857 ) , + .p1842 ( optlc_net_1858 ) , .p1843 ( optlc_net_1859 ) , + .p1844 ( optlc_net_1860 ) , .p1845 ( optlc_net_1861 ) , + .p1846 ( optlc_net_1862 ) , .p1847 ( optlc_net_1863 ) , + .p1848 ( optlc_net_1864 ) , .p1849 ( optlc_net_1865 ) , + .p1850 ( optlc_net_1866 ) , .p1851 ( optlc_net_1867 ) , + .p1852 ( optlc_net_1868 ) , .p1853 ( optlc_net_1869 ) , + .p1854 ( optlc_net_1870 ) , .p1855 ( optlc_net_1871 ) , + .p1856 ( optlc_net_1872 ) , .p1857 ( optlc_net_1873 ) , + .p1858 ( optlc_net_1874 ) , .p1859 ( optlc_net_1875 ) , + .p1860 ( optlc_net_1876 ) , .p1861 ( optlc_net_1877 ) , + .p1862 ( optlc_net_1878 ) , .p1863 ( optlc_net_1879 ) , + .p1864 ( optlc_net_1880 ) , .p1865 ( optlc_net_1881 ) , + .p1866 ( optlc_net_1882 ) , .p1867 ( optlc_net_1883 ) , + .p1868 ( optlc_net_1884 ) , .p1869 ( optlc_net_1885 ) , + .p1870 ( optlc_net_1886 ) , .p1871 ( optlc_net_1887 ) , + .p1872 ( optlc_net_1888 ) , .p1873 ( optlc_net_1889 ) , + .p1874 ( optlc_net_1890 ) , .p1875 ( optlc_net_1891 ) , + .p1876 ( optlc_net_1892 ) , .p1877 ( optlc_net_1893 ) , + .p1878 ( optlc_net_1894 ) , .p1879 ( optlc_net_1895 ) , + .p1880 ( optlc_net_1896 ) , .p1881 ( optlc_net_1897 ) , + .p1882 ( optlc_net_1898 ) , .p1883 ( optlc_net_1899 ) , + .p1884 ( optlc_net_1900 ) , .p1885 ( optlc_net_1901 ) , + .p1886 ( optlc_net_1902 ) , .p1887 ( optlc_net_1903 ) , + .p1888 ( optlc_net_1904 ) , .p1889 ( optlc_net_1905 ) , + .p1890 ( optlc_net_1906 ) , .p1891 ( optlc_net_1907 ) , + .p1892 ( optlc_net_1908 ) , .p1893 ( optlc_net_1909 ) , + .p1894 ( optlc_net_1910 ) , .p1895 ( optlc_net_1911 ) , + .p1896 ( optlc_net_1912 ) , .p1897 ( optlc_net_1913 ) , + .p1898 ( optlc_net_1914 ) , .p1899 ( optlc_net_1915 ) , + .p1900 ( optlc_net_1916 ) , .p1901 ( optlc_net_1917 ) , + .p1902 ( optlc_net_1918 ) , .p1903 ( optlc_net_1919 ) , + .p1904 ( optlc_net_1920 ) , .p1905 ( optlc_net_1921 ) , + .p1906 ( optlc_net_1922 ) , .p1907 ( optlc_net_1923 ) , + .p1908 ( optlc_net_1924 ) , .p1909 ( optlc_net_1925 ) , + .p1910 ( optlc_net_1926 ) , .p1911 ( optlc_net_1927 ) , + .p1912 ( optlc_net_1928 ) , .p1913 ( optlc_net_1929 ) , + .p1914 ( optlc_net_1930 ) , .p1915 ( optlc_net_1931 ) , + .p1916 ( optlc_net_1932 ) , .p1917 ( optlc_net_1933 ) , + .p1918 ( optlc_net_1934 ) , .p1919 ( optlc_net_1935 ) , + .p1920 ( optlc_net_1936 ) , .p1921 ( optlc_net_1937 ) , + .p1922 ( optlc_net_1938 ) , .p1923 ( optlc_net_1939 ) , + .p1924 ( optlc_net_1940 ) , .p1925 ( optlc_net_1941 ) , + .p1926 ( optlc_net_1942 ) , .p1927 ( optlc_net_1943 ) , + .p1928 ( optlc_net_1944 ) , .p1929 ( optlc_net_1945 ) , + .p1930 ( optlc_net_1946 ) , .p1931 ( optlc_net_1947 ) , + .p1932 ( optlc_net_1948 ) , .p1933 ( optlc_net_1949 ) , + .p1934 ( optlc_net_1950 ) , .p1935 ( optlc_net_1951 ) , + .p1936 ( optlc_net_1952 ) , .p1937 ( optlc_net_1953 ) , + .p1938 ( optlc_net_1954 ) , .p1939 ( optlc_net_1955 ) , + .p1940 ( optlc_net_1956 ) , .p1941 ( optlc_net_1957 ) , + .p1942 ( optlc_net_1958 ) , .p1943 ( optlc_net_1959 ) , + .p1944 ( optlc_net_1960 ) , .p1945 ( optlc_net_1961 ) , + .p1946 ( optlc_net_1962 ) , .p1947 ( optlc_net_1963 ) , + .p1948 ( optlc_net_1964 ) , .p1949 ( optlc_net_1965 ) , + .p1950 ( optlc_net_1966 ) , .p1951 ( optlc_net_1967 ) , + .p1952 ( optlc_net_1968 ) , .p1953 ( optlc_net_1969 ) , + .p1954 ( optlc_net_1970 ) , .p1955 ( optlc_net_1971 ) , + .p1956 ( optlc_net_1972 ) , .p1957 ( optlc_net_1973 ) , + .p1958 ( optlc_net_1974 ) , .p1959 ( optlc_net_1975 ) , + .p1960 ( optlc_net_1976 ) , .p1961 ( optlc_net_1977 ) , + .p1962 ( optlc_net_1978 ) , .p1963 ( optlc_net_1979 ) , + .p1964 ( optlc_net_1980 ) , .p1965 ( optlc_net_1981 ) , + .p1966 ( optlc_net_1982 ) , .p1967 ( optlc_net_1983 ) , + .p1968 ( optlc_net_1984 ) , .p1969 ( optlc_net_1985 ) , + .p1970 ( optlc_net_1986 ) , .p1971 ( optlc_net_1987 ) , + .p1972 ( optlc_net_1988 ) , .p1973 ( optlc_net_1989 ) , + .p1974 ( optlc_net_1990 ) , .p1975 ( optlc_net_1991 ) , + .p1976 ( optlc_net_1992 ) , .p1977 ( optlc_net_1993 ) , + .p1978 ( optlc_net_1994 ) , .p1979 ( optlc_net_1995 ) , + .p1980 ( optlc_net_1996 ) , .p1981 ( optlc_net_1997 ) , + .p1982 ( optlc_net_1998 ) , .p1983 ( optlc_net_1999 ) , + .p1984 ( optlc_net_2000 ) , .p1985 ( optlc_net_2001 ) , + .p1986 ( optlc_net_2002 ) , .p1987 ( optlc_net_2003 ) , + .p1988 ( optlc_net_2004 ) , .p1989 ( optlc_net_2005 ) , + .p1990 ( optlc_net_2006 ) , .p1991 ( optlc_net_2007 ) , + .p1992 ( optlc_net_2008 ) , .p1993 ( optlc_net_2009 ) , + .p1994 ( optlc_net_2010 ) , .p1995 ( optlc_net_2011 ) , + .p1996 ( optlc_net_2012 ) , .p1997 ( optlc_net_2013 ) , + .p1998 ( optlc_net_2014 ) , .p1999 ( optlc_net_2015 ) , + .p2000 ( optlc_net_2016 ) , .p2001 ( optlc_net_2017 ) , + .p2002 ( optlc_net_2018 ) , .p2003 ( optlc_net_2019 ) , + .p2004 ( optlc_net_2020 ) , .p2005 ( optlc_net_2021 ) , + .p2006 ( optlc_net_2022 ) , .p2007 ( optlc_net_2023 ) , + .p2008 ( optlc_net_2024 ) , .p2009 ( optlc_net_2025 ) , + .p2010 ( optlc_net_2026 ) , .p2011 ( optlc_net_2027 ) , + .p2012 ( optlc_net_2028 ) , .p2013 ( optlc_net_2029 ) , + .p2014 ( optlc_net_2030 ) , .p2015 ( optlc_net_2031 ) , + .p2016 ( optlc_net_2032 ) , .p2017 ( optlc_net_2033 ) , + .p2018 ( optlc_net_2034 ) , .p2019 ( optlc_net_2035 ) , + .p2020 ( optlc_net_2036 ) , .p2021 ( optlc_net_2037 ) , + .p2022 ( optlc_net_2038 ) , .p2023 ( optlc_net_2039 ) , + .p2024 ( optlc_net_2040 ) , .p2025 ( optlc_net_2041 ) , + .p2026 ( optlc_net_2042 ) , .p2027 ( optlc_net_2043 ) , + .p2028 ( optlc_net_2044 ) , .p2029 ( optlc_net_2045 ) , + .p2030 ( optlc_net_2046 ) , .p2031 ( optlc_net_2047 ) , + .p2032 ( optlc_net_2048 ) , .p2033 ( optlc_net_2049 ) , + .p2034 ( optlc_net_2050 ) , .p2035 ( optlc_net_2051 ) , + .p2036 ( optlc_net_2052 ) , .p2037 ( optlc_net_2053 ) , + .p2038 ( optlc_net_2054 ) , .p2039 ( optlc_net_2055 ) , + .p2040 ( optlc_net_2056 ) , .p2041 ( optlc_net_2057 ) , + .p2042 ( optlc_net_2058 ) , .p2043 ( optlc_net_2059 ) , + .p2044 ( optlc_net_2060 ) , .p2045 ( optlc_net_2061 ) , + .p2046 ( optlc_net_2062 ) , .p2047 ( optlc_net_2063 ) , + .p2048 ( optlc_net_2064 ) , .p2049 ( optlc_net_2065 ) , + .p2050 ( optlc_net_2066 ) , .p2051 ( optlc_net_2067 ) , + .p2052 ( optlc_net_2068 ) , .p2053 ( optlc_net_2069 ) , + .p2054 ( optlc_net_2070 ) , .p2055 ( optlc_net_2071 ) , + .p2056 ( optlc_net_2072 ) , .p2057 ( optlc_net_2073 ) , + .p2058 ( optlc_net_2074 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) , + .p2128 ( optlc_net_2144 ) , .p2129 ( optlc_net_2145 ) , + .p2130 ( optlc_net_2146 ) , .p2131 ( optlc_net_2147 ) , + .p2132 ( optlc_net_2148 ) , .p2133 ( optlc_net_2149 ) , + .p2134 ( optlc_net_2150 ) , .p2135 ( optlc_net_2151 ) , + .p2136 ( optlc_net_2152 ) , .p2137 ( optlc_net_2153 ) , + .p2138 ( optlc_net_2154 ) , .p2139 ( optlc_net_2155 ) , + .p2140 ( optlc_net_2156 ) , .p2141 ( optlc_net_2157 ) , + .p2142 ( optlc_net_2158 ) , .p2143 ( optlc_net_2159 ) , + .p2144 ( optlc_net_2160 ) , .p2145 ( optlc_net_2161 ) , + .p2146 ( optlc_net_2162 ) , .p2147 ( optlc_net_2163 ) , + .p2148 ( optlc_net_2164 ) , .p2149 ( optlc_net_2165 ) , + .p2150 ( optlc_net_2166 ) , .p2151 ( optlc_net_2167 ) , + .p2152 ( optlc_net_2168 ) , .p2153 ( optlc_net_2169 ) , + .p2154 ( optlc_net_2170 ) , .p2155 ( optlc_net_2171 ) , + .p2156 ( optlc_net_2172 ) , .p2157 ( optlc_net_2173 ) , + .p2158 ( optlc_net_2174 ) , .p2159 ( optlc_net_2175 ) , + .p2160 ( optlc_net_2176 ) , .p2161 ( optlc_net_2177 ) , + .p2162 ( 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optlc_net_3006 ) , .p2991 ( optlc_net_3007 ) , + .p2992 ( optlc_net_3008 ) , .p2993 ( optlc_net_3009 ) , + .p2994 ( optlc_net_3010 ) , .p2995 ( optlc_net_3011 ) , + .p2996 ( optlc_net_3012 ) , .p2997 ( optlc_net_3013 ) , + .p2998 ( optlc_net_3014 ) , .p2999 ( optlc_net_3015 ) , + .p3000 ( optlc_net_3016 ) , .p3001 ( optlc_net_3017 ) , + .p3002 ( optlc_net_3018 ) , .p3003 ( optlc_net_3019 ) , + .p3004 ( optlc_net_3020 ) , .p3005 ( optlc_net_3021 ) , + .p3006 ( optlc_net_3022 ) , .p3007 ( optlc_net_3023 ) , + .p3008 ( optlc_net_3024 ) , .p3009 ( optlc_net_3025 ) , + .p3010 ( optlc_net_3026 ) , .p3011 ( optlc_net_3027 ) , + .p3012 ( optlc_net_3028 ) , .p3013 ( optlc_net_3029 ) , + .p3014 ( optlc_net_3030 ) , .p3015 ( optlc_net_3031 ) , + .p3016 ( optlc_net_3032 ) , .p3017 ( optlc_net_3033 ) , + .p3018 ( optlc_net_3034 ) , .p3019 ( optlc_net_3035 ) , + .p3020 ( optlc_net_3036 ) , .p3021 ( optlc_net_3037 ) , + .p3022 ( optlc_net_3038 ) , .p3023 ( optlc_net_3039 ) , + .p3024 ( optlc_net_3040 ) , .p3025 ( optlc_net_3041 ) , + .p3026 ( optlc_net_3042 ) , .p3027 ( optlc_net_3043 ) , + .p3028 ( optlc_net_3044 ) , .p3029 ( optlc_net_3045 ) , + .p3030 ( optlc_net_3046 ) , .p3031 ( optlc_net_3047 ) , + .p3032 ( optlc_net_3048 ) , .p3033 ( optlc_net_3049 ) , + .p3034 ( optlc_net_3050 ) , .p3035 ( optlc_net_3051 ) , + .p3036 ( optlc_net_3052 ) , .p3037 ( optlc_net_3053 ) , + .p3038 ( optlc_net_3054 ) , .p3039 ( optlc_net_3055 ) , + .p3040 ( optlc_net_3056 ) , .p3041 ( optlc_net_3057 ) , + .p3042 ( optlc_net_3058 ) , .p3043 ( optlc_net_3059 ) , + .p3044 ( optlc_net_3060 ) , .p3045 ( optlc_net_3061 ) , + .p3046 ( optlc_net_3062 ) , .p3047 ( optlc_net_3063 ) , + .p3048 ( optlc_net_3064 ) , .p3049 ( optlc_net_3065 ) , + .p3050 ( optlc_net_3066 ) , .p3051 ( optlc_net_3067 ) , + .p3052 ( optlc_net_3068 ) , .p3053 ( optlc_net_3069 ) , + .p3054 ( optlc_net_3070 ) , .p3055 ( optlc_net_3071 ) , + .p3056 ( optlc_net_3072 ) , .p3057 ( optlc_net_3073 ) , + .p3058 ( optlc_net_3074 ) , .p3059 ( optlc_net_3075 ) , + .p3060 ( optlc_net_3076 ) , .p3061 ( optlc_net_3077 ) , + .p3062 ( optlc_net_3078 ) , .p3063 ( optlc_net_3079 ) , + .p3064 ( optlc_net_3080 ) , .p3065 ( optlc_net_3081 ) , + .p3066 ( optlc_net_3082 ) , .p3067 ( optlc_net_3083 ) , + .p3068 ( optlc_net_3084 ) , .p3069 ( optlc_net_3085 ) , + .p3070 ( optlc_net_3086 ) , .p3071 ( optlc_net_3087 ) , + .p3072 ( optlc_net_3088 ) , .p3073 ( optlc_net_3089 ) , + .p3074 ( optlc_net_3090 ) , .p3075 ( optlc_net_3091 ) , + .p3076 ( optlc_net_3092 ) , .p3077 ( optlc_net_3093 ) , + .p3078 ( optlc_net_3094 ) , .p3079 ( optlc_net_3095 ) , + .p3080 ( optlc_net_3096 ) , .p3081 ( optlc_net_3097 ) , + .p3082 ( optlc_net_3098 ) , .p3083 ( optlc_net_3099 ) , + .p3084 ( optlc_net_3100 ) , .p3085 ( optlc_net_3101 ) , + .p3086 ( optlc_net_3102 ) , .p3087 ( optlc_net_3103 ) , + .p3088 ( optlc_net_3104 ) , .p3089 ( optlc_net_3105 ) , + .p3090 ( optlc_net_3106 ) , .p3091 ( optlc_net_3107 ) , + .p3092 ( optlc_net_3108 ) , .p3093 ( optlc_net_3109 ) , + .p3094 ( optlc_net_3110 ) , .p3095 ( optlc_net_3111 ) , + .p3096 ( optlc_net_3112 ) , .p3097 ( optlc_net_3113 ) , + .p3098 ( optlc_net_3114 ) , .p3099 ( optlc_net_3115 ) , + .p3100 ( optlc_net_3116 ) , .p3101 ( optlc_net_3117 ) , + .p3102 ( optlc_net_3118 ) , .p3103 ( optlc_net_3119 ) , + .p3104 ( optlc_net_3120 ) , .p3105 ( optlc_net_3121 ) , + .p3106 ( optlc_net_3122 ) , .p3107 ( optlc_net_3123 ) , + .p3108 ( optlc_net_3124 ) , .p3109 ( optlc_net_3125 ) , + .p3110 ( optlc_net_3126 ) , .p3111 ( optlc_net_3127 ) , + .p3112 ( optlc_net_3128 ) , .p3113 ( optlc_net_3129 ) , + .p3114 ( optlc_net_3130 ) , .p3115 ( optlc_net_3131 ) , + .p3116 ( optlc_net_3132 ) , .p3117 ( optlc_net_3133 ) , + .p3118 ( optlc_net_3134 ) , .p3119 ( optlc_net_3135 ) , + .p3120 ( optlc_net_3136 ) , .p3121 ( optlc_net_3137 ) , + .p3122 ( optlc_net_3138 ) , .p3123 ( optlc_net_3139 ) , + .p3124 ( optlc_net_3140 ) , .p3125 ( optlc_net_3141 ) , + .p3126 ( optlc_net_3142 ) , .p3127 ( optlc_net_3143 ) , + .p3128 ( optlc_net_3144 ) , .p3129 ( optlc_net_3145 ) , + .p3130 ( optlc_net_3146 ) , .p3131 ( optlc_net_3147 ) , + .p3132 ( optlc_net_3148 ) , .p3133 ( optlc_net_3149 ) , + .p3134 ( optlc_net_3150 ) , .p3135 ( optlc_net_3151 ) , + .p3136 ( optlc_net_3152 ) , .p3137 ( optlc_net_3153 ) , + .p3138 ( optlc_net_3154 ) , .p3139 ( optlc_net_3155 ) , + .p3140 ( optlc_net_3156 ) , .p3141 ( optlc_net_3157 ) , + .p3142 ( optlc_net_3158 ) , .p3143 ( optlc_net_3159 ) , + .p3144 ( optlc_net_3160 ) , .p3145 ( optlc_net_3161 ) , + .p3146 ( optlc_net_3162 ) , .p3147 ( optlc_net_3163 ) , + .p3148 ( optlc_net_3164 ) , .p3149 ( optlc_net_3165 ) , + .p3150 ( optlc_net_3166 ) , .p3151 ( optlc_net_3167 ) , + .p3152 ( optlc_net_3168 ) , .p3153 ( optlc_net_3169 ) , + .p3154 ( optlc_net_3170 ) , .p3155 ( optlc_net_3171 ) , + .p3156 ( optlc_net_3172 ) , .p3157 ( optlc_net_3173 ) , + .p3158 ( optlc_net_3174 ) , .p3159 ( optlc_net_3175 ) , + .p3160 ( optlc_net_3176 ) , .p3161 ( optlc_net_3177 ) , + .p3162 ( optlc_net_3178 ) , .p3163 ( optlc_net_3179 ) , + .p3164 ( optlc_net_3180 ) , .p3165 ( optlc_net_3181 ) , + .p3166 ( optlc_net_3182 ) , .p3167 ( optlc_net_3183 ) , + .p3168 ( optlc_net_3184 ) , .p3169 ( optlc_net_3185 ) , + .p3170 ( optlc_net_3186 ) , .p3171 ( optlc_net_3187 ) , + .p3172 ( optlc_net_3188 ) , .p3173 ( optlc_net_3189 ) , + .p3174 ( optlc_net_3190 ) , .p3175 ( optlc_net_3191 ) , + .p3176 ( optlc_net_3192 ) , .p3177 ( optlc_net_3193 ) , + .p3178 ( optlc_net_3194 ) , .p3179 ( optlc_net_3195 ) , + .p3180 ( optlc_net_3196 ) , .p3181 ( optlc_net_3197 ) , + .p3182 ( optlc_net_3198 ) , .p3183 ( optlc_net_3199 ) , + .p3184 ( optlc_net_3200 ) , .p3185 ( optlc_net_3201 ) , + .p3186 ( optlc_net_3202 ) , .p3187 ( optlc_net_3203 ) , + .p3188 ( optlc_net_3204 ) , .p3189 ( optlc_net_3205 ) , + .p3190 ( optlc_net_3206 ) , .p3191 ( optlc_net_3207 ) , + .p3192 ( optlc_net_3208 ) , .p3193 ( optlc_net_3209 ) , + .p3194 ( optlc_net_3210 ) , .p3195 ( optlc_net_3211 ) , + .p3196 ( optlc_net_3212 ) , .p3197 ( optlc_net_3213 ) , + .p3198 ( optlc_net_3214 ) , .p3199 ( optlc_net_3215 ) , + .p3200 ( optlc_net_3216 ) , .p3201 ( optlc_net_3217 ) , + .p3202 ( optlc_net_3218 ) , .p3203 ( optlc_net_3219 ) , + .p3204 ( optlc_net_3220 ) , .p3205 ( optlc_net_3221 ) , + .p3206 ( optlc_net_3222 ) , .p3207 ( optlc_net_3223 ) , + .p3208 ( optlc_net_3224 ) , .p3209 ( optlc_net_3225 ) , + .p3210 ( optlc_net_3226 ) , .p3211 ( optlc_net_3227 ) , + .p3212 ( optlc_net_3228 ) , .p3213 ( optlc_net_3229 ) , + .p3214 ( optlc_net_3230 ) , .p3215 ( optlc_net_3231 ) , + .p3216 ( optlc_net_3232 ) , .p3217 ( optlc_net_3233 ) , + .p3218 ( optlc_net_3234 ) , .p3219 ( optlc_net_3235 ) , + .p3220 ( optlc_net_3236 ) , .p3221 ( optlc_net_3237 ) , + .p3222 ( optlc_net_3238 ) , .p3223 ( optlc_net_3239 ) , + .p3224 ( optlc_net_3240 ) , .p3225 ( optlc_net_3241 ) , + .p3226 ( optlc_net_3242 ) , .p3227 ( optlc_net_3243 ) , + .p3228 ( optlc_net_3244 ) , .p3229 ( optlc_net_3245 ) , + .p3230 ( optlc_net_3246 ) , .p3231 ( optlc_net_3247 ) , + .p3232 ( optlc_net_3248 ) , .p3233 ( optlc_net_3249 ) , + .p3234 ( optlc_net_3250 ) , .p3235 ( optlc_net_3251 ) , + .p3236 ( optlc_net_3252 ) , .p3237 ( optlc_net_3253 ) , + .p3238 ( optlc_net_3254 ) , .p3239 ( optlc_net_3255 ) , + .p3240 ( optlc_net_3256 ) , .p3241 ( optlc_net_3257 ) , + .p3242 ( optlc_net_3258 ) , .p3243 ( optlc_net_3259 ) , + .p3244 ( optlc_net_3260 ) , .p3245 ( optlc_net_3261 ) , + .p3246 ( optlc_net_3262 ) , .p3247 ( optlc_net_3263 ) , + .p3248 ( optlc_net_3264 ) , .p3249 ( optlc_net_3265 ) , + .p3250 ( optlc_net_3266 ) , .p3251 ( optlc_net_3267 ) , + .p3252 ( optlc_net_3268 ) , .p3253 ( optlc_net_3269 ) , + .p3254 ( optlc_net_3270 ) , .p3255 ( optlc_net_3271 ) , + .p3256 ( optlc_net_3272 ) , .p3257 ( optlc_net_3273 ) , + .p3258 ( optlc_net_3274 ) , .p3259 ( optlc_net_3275 ) , + .p3260 ( optlc_net_3276 ) , .p3261 ( optlc_net_3277 ) , + .p3262 ( optlc_net_3278 ) , .p3263 ( optlc_net_3279 ) , + .p3264 ( optlc_net_3280 ) , .p3265 ( optlc_net_3281 ) , + .p3266 ( optlc_net_3282 ) , .p3267 ( optlc_net_3283 ) , + .p3268 ( optlc_net_3284 ) , .p3269 ( optlc_net_3285 ) , + .p3270 ( optlc_net_3286 ) , .p3271 ( optlc_net_3287 ) , + .p3272 ( optlc_net_3288 ) , .p3273 ( optlc_net_3289 ) , + .p3274 ( optlc_net_3290 ) , .p3275 ( optlc_net_3291 ) , + .p3276 ( optlc_net_3292 ) , .p3277 ( optlc_net_3293 ) , + .p3278 ( optlc_net_3294 ) , .p3279 ( optlc_net_3295 ) , + .p3280 ( optlc_net_3296 ) , .p3281 ( optlc_net_3297 ) , + .p3282 ( optlc_net_3298 ) , .p3283 ( optlc_net_3299 ) , + .p3284 ( optlc_net_3300 ) , .p3285 ( optlc_net_3301 ) , + .p3286 ( optlc_net_3302 ) , .p3287 ( optlc_net_3303 ) , + .p3288 ( optlc_net_3304 ) , .p3289 ( optlc_net_3305 ) , + .p3290 ( optlc_net_3306 ) , .p3291 ( optlc_net_3307 ) , + .p3292 ( optlc_net_3308 ) , .p3293 ( optlc_net_3309 ) , + .p3294 ( optlc_net_3310 ) , .p3295 ( optlc_net_3311 ) , + .p3296 ( optlc_net_3312 ) , .p3297 ( optlc_net_3313 ) , + .p3298 ( optlc_net_3314 ) , .p3299 ( optlc_net_3315 ) , + .p3300 ( optlc_net_3316 ) , .p3301 ( optlc_net_3317 ) , + .p3302 ( optlc_net_3318 ) , .p3303 ( optlc_net_3319 ) , + .p3304 ( optlc_net_3320 ) , .p3305 ( optlc_net_3321 ) , + .p3306 ( optlc_net_3322 ) , .p3307 ( optlc_net_3323 ) , + .p3308 ( optlc_net_3324 ) , .p3309 ( optlc_net_3325 ) , + .p3310 ( optlc_net_3326 ) , .p3311 ( optlc_net_3327 ) , + .p3312 ( optlc_net_3328 ) , .p3313 ( optlc_net_3329 ) , + .p3314 ( optlc_net_3330 ) , .p3315 ( optlc_net_3331 ) , + .p3316 ( optlc_net_3332 ) , .p3317 ( optlc_net_3333 ) , + .p3318 ( optlc_net_3334 ) , .p3319 ( optlc_net_3335 ) , + .p3320 ( optlc_net_3336 ) , .p3321 ( optlc_net_3337 ) , + .p3322 ( optlc_net_3338 ) , .p3323 ( optlc_net_3339 ) , + .p3324 ( optlc_net_3340 ) , .p3325 ( optlc_net_3341 ) , + .p3326 ( optlc_net_3342 ) , .p3327 ( optlc_net_3343 ) , + .p3328 ( optlc_net_3344 ) , .p3329 ( optlc_net_3345 ) , + .p3330 ( optlc_net_3346 ) , .p3331 ( optlc_net_3347 ) , + .p3332 ( optlc_net_3348 ) , .p3333 ( optlc_net_3349 ) , + .p3334 ( optlc_net_3350 ) , .p3335 ( optlc_net_3351 ) , + .p3336 ( optlc_net_3352 ) , .p3337 ( optlc_net_3353 ) , + .p3338 ( optlc_net_3354 ) , .p3339 ( optlc_net_3355 ) , + .p3340 ( optlc_net_3356 ) , .p3341 ( optlc_net_3357 ) , + .p3342 ( optlc_net_3358 ) , .p3343 ( optlc_net_3359 ) , + .p3344 ( optlc_net_3360 ) , .p3345 ( optlc_net_3361 ) , + .p3346 ( optlc_net_3362 ) , .p3347 ( optlc_net_3363 ) , + .p3348 ( optlc_net_3364 ) , .p3349 ( optlc_net_3365 ) , + .p3350 ( optlc_net_3366 ) , .p3351 ( optlc_net_3367 ) , + .p3352 ( optlc_net_3368 ) , .p3353 ( optlc_net_3369 ) , + .p3354 ( optlc_net_3370 ) , .p3355 ( optlc_net_3371 ) , + .p3356 ( optlc_net_3372 ) , .p3357 ( optlc_net_3373 ) , + .p3358 ( optlc_net_3374 ) , .p3359 ( optlc_net_3375 ) , + .p3360 ( optlc_net_3376 ) , .p3361 ( optlc_net_3377 ) , + .p3362 ( optlc_net_3378 ) , .p3363 ( optlc_net_3379 ) , + .p3364 ( optlc_net_3380 ) , .p3365 ( optlc_net_3381 ) , + .p3366 ( optlc_net_3382 ) , .p3367 ( optlc_net_3383 ) , + .p3368 ( optlc_net_3384 ) , .p3369 ( optlc_net_3385 ) , + .p3370 ( optlc_net_3386 ) , .p3371 ( optlc_net_3387 ) , + .p3372 ( optlc_net_3388 ) , .p3373 ( optlc_net_3389 ) , + .p3374 ( optlc_net_3390 ) , .p3375 ( optlc_net_3391 ) , + .p3376 ( optlc_net_3392 ) , .p3377 ( optlc_net_3393 ) , + .p3378 ( optlc_net_3394 ) , .p3379 ( optlc_net_3395 ) , + .p3380 ( optlc_net_3396 ) , .p3381 ( optlc_net_3397 ) , + .p3382 ( optlc_net_3398 ) , .p3383 ( optlc_net_3399 ) , + .p3384 ( optlc_net_3400 ) , .p3385 ( optlc_net_3401 ) , + .p3386 ( optlc_net_3402 ) , .p3387 ( optlc_net_3403 ) , + .p3388 ( optlc_net_3404 ) , .p3389 ( optlc_net_3405 ) , + .p3390 ( optlc_net_3406 ) , .p3391 ( optlc_net_3407 ) , + .p3392 ( optlc_net_3408 ) , .p3393 ( optlc_net_3409 ) , + .p3394 ( optlc_net_3410 ) , .p3395 ( optlc_net_3411 ) , + .p3396 ( optlc_net_3412 ) , .p3397 ( optlc_net_3413 ) , + .p3398 ( optlc_net_3414 ) , .p3399 ( optlc_net_3415 ) , + .p3400 ( optlc_net_3416 ) , .p3401 ( optlc_net_3417 ) , + .p3402 ( optlc_net_3418 ) , .p3403 ( optlc_net_3419 ) , + .p3404 ( optlc_net_3420 ) , .p3405 ( optlc_net_3421 ) , + .p3406 ( optlc_net_3422 ) , .p3407 ( optlc_net_3423 ) , + .p3408 ( optlc_net_3424 ) , .p3409 ( optlc_net_3425 ) , + .p3410 ( optlc_net_3426 ) , .p3411 ( optlc_net_3427 ) , + .p3412 ( optlc_net_3428 ) , .p3413 ( optlc_net_3429 ) , + .p3414 ( optlc_net_3430 ) , .p3415 ( optlc_net_3431 ) , + .p3416 ( optlc_net_3432 ) , .p3417 ( optlc_net_3433 ) , + .p3418 ( optlc_net_3434 ) , .p3419 ( optlc_net_3435 ) , + .p3420 ( optlc_net_3436 ) , .p3421 ( optlc_net_3437 ) , + .p3422 ( optlc_net_3438 ) , .p3423 ( optlc_net_3439 ) , + .p3424 ( optlc_net_3440 ) , .p3425 ( optlc_net_3441 ) , + .p3426 ( optlc_net_3442 ) , .p3427 ( optlc_net_3443 ) , + .p3428 ( optlc_net_3444 ) , .p3429 ( optlc_net_3445 ) , + .p3430 ( optlc_net_3446 ) , .p3431 ( optlc_net_3447 ) , + .p3432 ( optlc_net_3448 ) , .p3433 ( optlc_net_3449 ) , + .p3434 ( optlc_net_3450 ) , .p3435 ( optlc_net_3451 ) , + .p3436 ( optlc_net_3452 ) , .p3437 ( optlc_net_3453 ) , + .p3438 ( optlc_net_3454 ) , .p3439 ( optlc_net_3455 ) , + .p3440 ( optlc_net_3456 ) , .p3441 ( optlc_net_3457 ) , + .p3442 ( optlc_net_3458 ) , .p3443 ( optlc_net_3459 ) , + .p3444 ( optlc_net_3460 ) , .p3445 ( optlc_net_3461 ) , + .p3446 ( optlc_net_3462 ) , .p3447 ( optlc_net_3463 ) , + .p3448 ( optlc_net_3464 ) , .p3449 ( optlc_net_3465 ) , + .p3450 ( optlc_net_3466 ) , .p3451 ( optlc_net_3467 ) , + .p3452 ( optlc_net_3468 ) , .p3453 ( optlc_net_3469 ) , + .p3454 ( optlc_net_3470 ) , .p3455 ( optlc_net_3471 ) , + .p3456 ( optlc_net_3472 ) , .p3457 ( optlc_net_3473 ) , + .p3458 ( optlc_net_3474 ) , .p3459 ( optlc_net_3475 ) , + .p3460 ( optlc_net_3476 ) , .p3461 ( optlc_net_3477 ) , + .p3462 ( optlc_net_3478 ) , .p3463 ( optlc_net_3479 ) , + .p3464 ( optlc_net_3480 ) , .p3465 ( optlc_net_3481 ) , + .p3466 ( optlc_net_3482 ) , .p3467 ( optlc_net_3483 ) , + .p3468 ( optlc_net_3484 ) , .p3469 ( optlc_net_3485 ) , + .p3470 ( optlc_net_3486 ) , .p3471 ( optlc_net_3487 ) , + .p3472 ( optlc_net_3488 ) , .p3473 ( optlc_net_3489 ) , + .p3474 ( optlc_net_3490 ) , .p3475 ( optlc_net_3491 ) , + .p3476 ( optlc_net_3492 ) , .p3477 ( optlc_net_3493 ) , + .p3478 ( optlc_net_3494 ) , .p3479 ( optlc_net_3495 ) , + .p3480 ( optlc_net_3496 ) , .p3481 ( optlc_net_3497 ) , + .p3482 ( optlc_net_3498 ) , .p3483 ( optlc_net_3499 ) , + .p3484 ( optlc_net_3500 ) , .p3485 ( optlc_net_3501 ) , + .p3486 ( optlc_net_3502 ) , .p3487 ( optlc_net_3503 ) , + .p3488 ( optlc_net_3504 ) , .p3489 ( optlc_net_3505 ) , + .p3490 ( optlc_net_3506 ) , .p3491 ( optlc_net_3507 ) , + .p3492 ( optlc_net_3508 ) , .p3493 ( optlc_net_3509 ) , + .p3494 ( optlc_net_3510 ) , .p3495 ( optlc_net_3511 ) , + .p3496 ( optlc_net_3512 ) , .p3497 ( optlc_net_3513 ) , + .p3498 ( optlc_net_3514 ) , .p3499 ( optlc_net_3515 ) , + .p3500 ( optlc_net_3516 ) , .p3501 ( optlc_net_3517 ) , + .p3502 ( optlc_net_3518 ) , .p3503 ( optlc_net_3519 ) , + .p3504 ( optlc_net_3520 ) , .p3505 ( optlc_net_3521 ) , + .p3506 ( optlc_net_3522 ) , .p3507 ( optlc_net_3523 ) , + .p3508 ( optlc_net_3524 ) , .p3509 ( optlc_net_3525 ) , + .p3510 ( optlc_net_3526 ) , .p3511 ( optlc_net_3527 ) , + .p3512 ( optlc_net_3528 ) , .p3513 ( optlc_net_3529 ) , + .p3514 ( optlc_net_3530 ) , .p3515 ( optlc_net_3531 ) , + .p3516 ( optlc_net_3532 ) , .p3517 ( optlc_net_3533 ) , + .p3518 ( optlc_net_3534 ) , .p3519 ( optlc_net_3535 ) , + .p3520 ( optlc_net_3536 ) , .p3521 ( optlc_net_3537 ) , + .p3522 ( optlc_net_3538 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( io_oeb[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( io_oeb[1] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( io_oeb[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( io_oeb[25] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( io_oeb[26] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( io_oeb[36] ) ) ; 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+ .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( optlc_net_17 ) , + .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( optlc_net_18 ) , + .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_20 ( .LO ( optlc_net_19 ) , + .HI ( SYNOPSYS_UNCONNECTED_21 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) , + .HI ( SYNOPSYS_UNCONNECTED_22 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) , + .HI ( SYNOPSYS_UNCONNECTED_23 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) , + .HI ( SYNOPSYS_UNCONNECTED_24 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) , + .HI ( SYNOPSYS_UNCONNECTED_25 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) , + .HI ( SYNOPSYS_UNCONNECTED_26 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) , + .HI ( SYNOPSYS_UNCONNECTED_27 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) , + .HI ( SYNOPSYS_UNCONNECTED_28 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) , + .HI ( SYNOPSYS_UNCONNECTED_29 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) , + .HI ( SYNOPSYS_UNCONNECTED_30 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) , + .HI ( SYNOPSYS_UNCONNECTED_31 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) , + .HI ( SYNOPSYS_UNCONNECTED_32 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) , + .HI ( SYNOPSYS_UNCONNECTED_33 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) , + .HI ( SYNOPSYS_UNCONNECTED_34 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) , + .HI ( SYNOPSYS_UNCONNECTED_35 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) , + .HI ( SYNOPSYS_UNCONNECTED_36 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) , + .HI ( SYNOPSYS_UNCONNECTED_37 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) , + .HI ( SYNOPSYS_UNCONNECTED_38 ) ) ; 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optlc_48 ( .LO ( optlc_net_47 ) , + .HI ( SYNOPSYS_UNCONNECTED_49 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) , + .HI ( SYNOPSYS_UNCONNECTED_50 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_49 ) , + .HI ( SYNOPSYS_UNCONNECTED_51 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_50 ) , + .HI ( SYNOPSYS_UNCONNECTED_52 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_51 ) , + .HI ( SYNOPSYS_UNCONNECTED_53 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_52 ) , + .HI ( SYNOPSYS_UNCONNECTED_54 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_53 ) , + .HI ( SYNOPSYS_UNCONNECTED_55 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_54 ) , + .HI ( SYNOPSYS_UNCONNECTED_56 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_55 ) , + .HI ( SYNOPSYS_UNCONNECTED_57 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_56 ) , + .HI ( SYNOPSYS_UNCONNECTED_58 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_57 ) , + .HI ( SYNOPSYS_UNCONNECTED_59 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_58 ) , + .HI ( SYNOPSYS_UNCONNECTED_60 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_59 ) , + .HI ( SYNOPSYS_UNCONNECTED_61 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_60 ) , + .HI ( SYNOPSYS_UNCONNECTED_62 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_61 ) , + .HI ( SYNOPSYS_UNCONNECTED_63 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_62 ) , + .HI ( SYNOPSYS_UNCONNECTED_64 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_63 ) , + .HI ( SYNOPSYS_UNCONNECTED_65 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_64 ) , + .HI ( SYNOPSYS_UNCONNECTED_66 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_65 ) , + .HI ( SYNOPSYS_UNCONNECTED_67 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_66 ) , + .HI ( SYNOPSYS_UNCONNECTED_68 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_67 ) , + .HI ( SYNOPSYS_UNCONNECTED_69 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_68 ) , + .HI ( SYNOPSYS_UNCONNECTED_70 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_69 ) , + .HI ( SYNOPSYS_UNCONNECTED_71 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_70 ) , + .HI ( SYNOPSYS_UNCONNECTED_72 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_71 ) , + .HI ( SYNOPSYS_UNCONNECTED_73 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_72 ) , + .HI ( SYNOPSYS_UNCONNECTED_74 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_73 ) , + .HI ( SYNOPSYS_UNCONNECTED_75 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( optlc_net_74 ) , + .HI ( SYNOPSYS_UNCONNECTED_76 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( optlc_net_75 ) , + .HI ( SYNOPSYS_UNCONNECTED_77 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( optlc_net_76 ) , + .HI ( SYNOPSYS_UNCONNECTED_78 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( optlc_net_77 ) , + .HI ( SYNOPSYS_UNCONNECTED_79 ) ) ; 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optlc_89 ( .LO ( optlc_net_88 ) , + .HI ( SYNOPSYS_UNCONNECTED_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( optlc_net_89 ) , + .HI ( SYNOPSYS_UNCONNECTED_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( optlc_net_90 ) , + .HI ( SYNOPSYS_UNCONNECTED_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( optlc_net_91 ) , + .HI ( SYNOPSYS_UNCONNECTED_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( optlc_net_92 ) , + .HI ( SYNOPSYS_UNCONNECTED_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( optlc_net_93 ) , + .HI ( SYNOPSYS_UNCONNECTED_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( optlc_net_94 ) , + .HI ( SYNOPSYS_UNCONNECTED_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( optlc_net_95 ) , + .HI ( SYNOPSYS_UNCONNECTED_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( optlc_net_96 ) , + .HI ( SYNOPSYS_UNCONNECTED_98 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( optlc_net_97 ) , + .HI ( SYNOPSYS_UNCONNECTED_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( optlc_net_98 ) , + .HI ( SYNOPSYS_UNCONNECTED_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( optlc_net_99 ) , + .HI ( SYNOPSYS_UNCONNECTED_101 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( optlc_net_100 ) , + .HI ( SYNOPSYS_UNCONNECTED_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( optlc_net_101 ) , + .HI ( SYNOPSYS_UNCONNECTED_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( optlc_net_102 ) , + .HI ( SYNOPSYS_UNCONNECTED_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( optlc_net_103 ) , + .HI ( SYNOPSYS_UNCONNECTED_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( optlc_net_104 ) , + .HI ( SYNOPSYS_UNCONNECTED_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( optlc_net_105 ) , + .HI ( SYNOPSYS_UNCONNECTED_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( optlc_net_106 ) , + .HI ( SYNOPSYS_UNCONNECTED_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( optlc_net_107 ) , + .HI ( SYNOPSYS_UNCONNECTED_109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( optlc_net_108 ) , + .HI ( SYNOPSYS_UNCONNECTED_110 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( optlc_net_109 ) , + .HI ( SYNOPSYS_UNCONNECTED_111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( optlc_net_110 ) , + .HI ( SYNOPSYS_UNCONNECTED_112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( optlc_net_111 ) , + .HI ( SYNOPSYS_UNCONNECTED_113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( optlc_net_112 ) , + .HI ( SYNOPSYS_UNCONNECTED_114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( optlc_net_113 ) , + .HI ( SYNOPSYS_UNCONNECTED_115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( optlc_net_114 ) , + .HI ( SYNOPSYS_UNCONNECTED_116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( optlc_net_115 ) , + .HI ( SYNOPSYS_UNCONNECTED_117 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( optlc_net_116 ) , + .HI ( SYNOPSYS_UNCONNECTED_118 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( optlc_net_117 ) , + .HI ( SYNOPSYS_UNCONNECTED_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( optlc_net_118 ) , + .HI ( SYNOPSYS_UNCONNECTED_120 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( optlc_net_119 ) , + .HI ( SYNOPSYS_UNCONNECTED_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( optlc_net_120 ) , + .HI ( SYNOPSYS_UNCONNECTED_122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( optlc_net_121 ) , + .HI ( SYNOPSYS_UNCONNECTED_123 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( optlc_net_122 ) , + .HI ( SYNOPSYS_UNCONNECTED_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( optlc_net_123 ) , + .HI ( SYNOPSYS_UNCONNECTED_125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( optlc_net_124 ) , + .HI ( SYNOPSYS_UNCONNECTED_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( optlc_net_125 ) , + .HI ( SYNOPSYS_UNCONNECTED_127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( optlc_net_126 ) , + .HI ( SYNOPSYS_UNCONNECTED_128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( optlc_net_127 ) , + .HI ( SYNOPSYS_UNCONNECTED_129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( optlc_net_128 ) , + .HI ( SYNOPSYS_UNCONNECTED_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( optlc_net_129 ) , + .HI ( SYNOPSYS_UNCONNECTED_131 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( optlc_net_130 ) , + .HI ( SYNOPSYS_UNCONNECTED_132 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( optlc_net_131 ) , + .HI ( SYNOPSYS_UNCONNECTED_133 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( optlc_net_132 ) , + .HI ( SYNOPSYS_UNCONNECTED_134 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( optlc_net_133 ) , + .HI ( SYNOPSYS_UNCONNECTED_135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( optlc_net_134 ) , + .HI ( SYNOPSYS_UNCONNECTED_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( optlc_net_135 ) , + .HI ( SYNOPSYS_UNCONNECTED_137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( optlc_net_136 ) , + .HI ( SYNOPSYS_UNCONNECTED_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( optlc_net_137 ) , + .HI ( SYNOPSYS_UNCONNECTED_139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( optlc_net_138 ) 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, + .HI ( SYNOPSYS_UNCONNECTED_270 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_270 ( .LO ( optlc_net_269 ) , + .HI ( SYNOPSYS_UNCONNECTED_271 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_271 ( .LO ( optlc_net_270 ) , + .HI ( SYNOPSYS_UNCONNECTED_272 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_272 ( .LO ( optlc_net_271 ) , + .HI ( SYNOPSYS_UNCONNECTED_273 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_273 ( .LO ( optlc_net_272 ) , + .HI ( SYNOPSYS_UNCONNECTED_274 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_274 ( .LO ( optlc_net_273 ) , + .HI ( SYNOPSYS_UNCONNECTED_275 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_275 ( .LO ( optlc_net_274 ) , + .HI ( SYNOPSYS_UNCONNECTED_276 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_276 ( .LO ( optlc_net_275 ) , + .HI ( SYNOPSYS_UNCONNECTED_277 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_277 ( .LO ( optlc_net_276 ) , + .HI ( SYNOPSYS_UNCONNECTED_278 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_278 ( .LO ( optlc_net_277 ) , + .HI ( SYNOPSYS_UNCONNECTED_279 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_279 ( .LO ( optlc_net_278 ) , + .HI ( SYNOPSYS_UNCONNECTED_280 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_280 ( .LO ( optlc_net_279 ) , + .HI ( SYNOPSYS_UNCONNECTED_281 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_281 ( .LO ( optlc_net_280 ) , + .HI ( SYNOPSYS_UNCONNECTED_282 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_282 ( .LO ( optlc_net_281 ) , + .HI ( SYNOPSYS_UNCONNECTED_283 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_283 ( .LO ( optlc_net_282 ) , + .HI ( SYNOPSYS_UNCONNECTED_284 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_284 ( .LO ( optlc_net_283 ) , + .HI ( SYNOPSYS_UNCONNECTED_285 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_285 ( .LO ( optlc_net_284 ) , + .HI ( SYNOPSYS_UNCONNECTED_286 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_286 ( .LO ( optlc_net_285 ) , + .HI ( SYNOPSYS_UNCONNECTED_287 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_287 ( .LO ( optlc_net_286 ) , + .HI ( SYNOPSYS_UNCONNECTED_288 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_288 ( .LO ( optlc_net_287 ) , + .HI ( SYNOPSYS_UNCONNECTED_289 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_289 ( .LO ( optlc_net_288 ) , + .HI ( SYNOPSYS_UNCONNECTED_290 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_290 ( .LO ( optlc_net_289 ) , + .HI ( SYNOPSYS_UNCONNECTED_291 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_291 ( .LO ( optlc_net_290 ) , + .HI ( SYNOPSYS_UNCONNECTED_292 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_292 ( .LO ( optlc_net_291 ) , + .HI ( SYNOPSYS_UNCONNECTED_293 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_293 ( .LO ( optlc_net_292 ) , + .HI ( SYNOPSYS_UNCONNECTED_294 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_294 ( .LO ( optlc_net_293 ) , + .HI ( SYNOPSYS_UNCONNECTED_295 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_295 ( .LO ( optlc_net_294 ) , + .HI ( SYNOPSYS_UNCONNECTED_296 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_296 ( .LO ( optlc_net_295 ) , + .HI ( SYNOPSYS_UNCONNECTED_297 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_297 ( .LO ( optlc_net_296 ) , + .HI ( SYNOPSYS_UNCONNECTED_298 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_298 ( .LO ( optlc_net_297 ) , + .HI ( SYNOPSYS_UNCONNECTED_299 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_299 ( .LO ( optlc_net_298 ) , + .HI ( SYNOPSYS_UNCONNECTED_300 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_300 ( .LO ( optlc_net_299 ) , + .HI ( SYNOPSYS_UNCONNECTED_301 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_301 ( .LO ( optlc_net_300 ) , + .HI ( SYNOPSYS_UNCONNECTED_302 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_302 ( .LO ( optlc_net_301 ) , + .HI ( SYNOPSYS_UNCONNECTED_303 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_303 ( .LO ( optlc_net_302 ) , + .HI ( SYNOPSYS_UNCONNECTED_304 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_304 ( .LO ( optlc_net_303 ) , + .HI ( SYNOPSYS_UNCONNECTED_305 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_305 ( .LO ( optlc_net_304 ) , + .HI ( SYNOPSYS_UNCONNECTED_306 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_306 ( .LO ( optlc_net_305 ) , + .HI ( SYNOPSYS_UNCONNECTED_307 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_307 ( .LO ( optlc_net_306 ) , + .HI ( SYNOPSYS_UNCONNECTED_308 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_308 ( .LO ( optlc_net_307 ) , + .HI ( SYNOPSYS_UNCONNECTED_309 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_309 ( .LO ( optlc_net_308 ) , + .HI ( SYNOPSYS_UNCONNECTED_310 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_310 ( .LO ( optlc_net_309 ) , + .HI ( SYNOPSYS_UNCONNECTED_311 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_311 ( .LO ( optlc_net_310 ) , + .HI ( SYNOPSYS_UNCONNECTED_312 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_312 ( .LO ( optlc_net_311 ) , + .HI ( SYNOPSYS_UNCONNECTED_313 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_313 ( .LO ( optlc_net_312 ) , + .HI ( SYNOPSYS_UNCONNECTED_314 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_314 ( .LO ( optlc_net_313 ) , + .HI ( SYNOPSYS_UNCONNECTED_315 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_315 ( .LO ( optlc_net_314 ) , + .HI ( SYNOPSYS_UNCONNECTED_316 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_316 ( .LO ( optlc_net_315 ) , + .HI ( SYNOPSYS_UNCONNECTED_317 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_317 ( .LO ( optlc_net_316 ) , + .HI ( SYNOPSYS_UNCONNECTED_318 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_318 ( .LO ( optlc_net_317 ) , + .HI ( SYNOPSYS_UNCONNECTED_319 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_319 ( .LO ( optlc_net_318 ) , + .HI ( SYNOPSYS_UNCONNECTED_320 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_320 ( .LO ( optlc_net_319 ) , + .HI ( SYNOPSYS_UNCONNECTED_321 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_321 ( .LO ( optlc_net_320 ) , + .HI ( SYNOPSYS_UNCONNECTED_322 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_322 ( .LO ( optlc_net_321 ) , + .HI ( SYNOPSYS_UNCONNECTED_323 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_323 ( .LO ( optlc_net_322 ) , + .HI ( SYNOPSYS_UNCONNECTED_324 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_324 ( .LO ( optlc_net_323 ) , + .HI ( SYNOPSYS_UNCONNECTED_325 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_325 ( .LO ( optlc_net_324 ) , + .HI ( SYNOPSYS_UNCONNECTED_326 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_326 ( .LO ( optlc_net_325 ) , + .HI ( SYNOPSYS_UNCONNECTED_327 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_327 ( .LO ( optlc_net_326 ) , + .HI ( SYNOPSYS_UNCONNECTED_328 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_328 ( .LO ( optlc_net_327 ) , + .HI ( SYNOPSYS_UNCONNECTED_329 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_329 ( .LO ( optlc_net_328 ) , + .HI ( SYNOPSYS_UNCONNECTED_330 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_330 ( .LO ( optlc_net_329 ) , + .HI ( SYNOPSYS_UNCONNECTED_331 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_331 ( .LO ( optlc_net_330 ) , + .HI ( SYNOPSYS_UNCONNECTED_332 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_332 ( .LO ( optlc_net_331 ) , + .HI ( SYNOPSYS_UNCONNECTED_333 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_333 ( .LO ( optlc_net_332 ) , + .HI ( SYNOPSYS_UNCONNECTED_334 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_334 ( .LO ( optlc_net_333 ) , + .HI ( SYNOPSYS_UNCONNECTED_335 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_335 ( .LO ( optlc_net_334 ) , + .HI ( SYNOPSYS_UNCONNECTED_336 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_336 ( .LO ( optlc_net_335 ) , + .HI ( SYNOPSYS_UNCONNECTED_337 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_337 ( .LO ( optlc_net_336 ) , + .HI ( SYNOPSYS_UNCONNECTED_338 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_338 ( .LO ( optlc_net_337 ) , + .HI ( SYNOPSYS_UNCONNECTED_339 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_339 ( .LO ( optlc_net_338 ) , + .HI ( SYNOPSYS_UNCONNECTED_340 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_340 ( .LO ( optlc_net_339 ) , + .HI ( SYNOPSYS_UNCONNECTED_341 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_341 ( .LO ( optlc_net_340 ) , + .HI ( SYNOPSYS_UNCONNECTED_342 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_342 ( .LO ( optlc_net_341 ) , + .HI ( SYNOPSYS_UNCONNECTED_343 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_343 ( .LO ( optlc_net_342 ) , + .HI ( SYNOPSYS_UNCONNECTED_344 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_344 ( .LO ( optlc_net_343 ) , + .HI ( SYNOPSYS_UNCONNECTED_345 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_345 ( .LO ( optlc_net_344 ) , + .HI ( SYNOPSYS_UNCONNECTED_346 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_346 ( .LO ( optlc_net_345 ) , + .HI ( SYNOPSYS_UNCONNECTED_347 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_347 ( .LO ( optlc_net_346 ) , + .HI ( SYNOPSYS_UNCONNECTED_348 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_348 ( .LO ( optlc_net_347 ) , + .HI ( SYNOPSYS_UNCONNECTED_349 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_349 ( .LO ( optlc_net_348 ) , + .HI ( SYNOPSYS_UNCONNECTED_350 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_350 ( .LO ( optlc_net_349 ) , + .HI ( SYNOPSYS_UNCONNECTED_351 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_351 ( .LO ( optlc_net_350 ) , + .HI ( SYNOPSYS_UNCONNECTED_352 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_352 ( .LO ( optlc_net_351 ) , + .HI ( SYNOPSYS_UNCONNECTED_353 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_353 ( .LO ( optlc_net_352 ) , + .HI ( SYNOPSYS_UNCONNECTED_354 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_354 ( .LO ( optlc_net_353 ) , + .HI ( SYNOPSYS_UNCONNECTED_355 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_355 ( .LO ( optlc_net_354 ) , + .HI ( SYNOPSYS_UNCONNECTED_356 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_356 ( .LO ( optlc_net_355 ) , + .HI ( SYNOPSYS_UNCONNECTED_357 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_357 ( .LO ( optlc_net_356 ) , + .HI ( SYNOPSYS_UNCONNECTED_358 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_358 ( .LO ( optlc_net_357 ) , + .HI ( SYNOPSYS_UNCONNECTED_359 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_359 ( .LO ( optlc_net_358 ) , + .HI ( SYNOPSYS_UNCONNECTED_360 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_360 ( .LO ( optlc_net_359 ) , + .HI ( SYNOPSYS_UNCONNECTED_361 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_361 ( .LO ( optlc_net_360 ) , + .HI ( SYNOPSYS_UNCONNECTED_362 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_362 ( .LO ( optlc_net_361 ) , + .HI ( SYNOPSYS_UNCONNECTED_363 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_363 ( .LO ( optlc_net_362 ) , + .HI ( SYNOPSYS_UNCONNECTED_364 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_364 ( .LO ( optlc_net_363 ) , + .HI ( SYNOPSYS_UNCONNECTED_365 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_365 ( .LO ( optlc_net_364 ) , + .HI ( SYNOPSYS_UNCONNECTED_366 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_366 ( .LO ( optlc_net_365 ) , + .HI ( SYNOPSYS_UNCONNECTED_367 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_367 ( .LO ( optlc_net_366 ) , + .HI ( SYNOPSYS_UNCONNECTED_368 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_368 ( .LO ( optlc_net_367 ) , + .HI ( SYNOPSYS_UNCONNECTED_369 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_369 ( .LO ( optlc_net_368 ) , + .HI ( SYNOPSYS_UNCONNECTED_370 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_370 ( .LO ( optlc_net_369 ) , + .HI ( SYNOPSYS_UNCONNECTED_371 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_371 ( .LO ( optlc_net_370 ) , + .HI ( SYNOPSYS_UNCONNECTED_372 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_372 ( .LO ( optlc_net_371 ) , + .HI ( SYNOPSYS_UNCONNECTED_373 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_373 ( .LO ( optlc_net_372 ) , + .HI ( SYNOPSYS_UNCONNECTED_374 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_374 ( .LO ( optlc_net_373 ) , + .HI ( SYNOPSYS_UNCONNECTED_375 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_375 ( .LO ( optlc_net_374 ) , + .HI ( SYNOPSYS_UNCONNECTED_376 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_376 ( .LO ( optlc_net_375 ) , + .HI ( SYNOPSYS_UNCONNECTED_377 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_377 ( .LO ( optlc_net_376 ) , + .HI ( SYNOPSYS_UNCONNECTED_378 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_378 ( .LO ( optlc_net_377 ) , + .HI ( SYNOPSYS_UNCONNECTED_379 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_379 ( .LO ( optlc_net_378 ) , + .HI ( SYNOPSYS_UNCONNECTED_380 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_380 ( .LO ( optlc_net_379 ) , + .HI ( SYNOPSYS_UNCONNECTED_381 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_381 ( .LO ( optlc_net_380 ) , + .HI ( SYNOPSYS_UNCONNECTED_382 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_382 ( .LO ( optlc_net_381 ) , + .HI ( SYNOPSYS_UNCONNECTED_383 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_383 ( .LO ( optlc_net_382 ) , + .HI ( SYNOPSYS_UNCONNECTED_384 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_384 ( .LO ( optlc_net_383 ) , + .HI ( SYNOPSYS_UNCONNECTED_385 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_385 ( .LO ( optlc_net_384 ) , + .HI ( SYNOPSYS_UNCONNECTED_386 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_386 ( .LO ( optlc_net_385 ) , + .HI ( SYNOPSYS_UNCONNECTED_387 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_387 ( .LO ( optlc_net_386 ) , + .HI ( SYNOPSYS_UNCONNECTED_388 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_388 ( .LO ( optlc_net_387 ) , + .HI ( SYNOPSYS_UNCONNECTED_389 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_389 ( .LO ( optlc_net_388 ) , + .HI ( SYNOPSYS_UNCONNECTED_390 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_390 ( .LO ( optlc_net_389 ) , + .HI ( SYNOPSYS_UNCONNECTED_391 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_391 ( .LO ( optlc_net_390 ) , + .HI ( SYNOPSYS_UNCONNECTED_392 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_392 ( .LO ( optlc_net_391 ) , + .HI ( SYNOPSYS_UNCONNECTED_393 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_393 ( .LO ( optlc_net_392 ) , + .HI ( SYNOPSYS_UNCONNECTED_394 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_394 ( .LO ( optlc_net_393 ) , + .HI ( SYNOPSYS_UNCONNECTED_395 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_395 ( .LO ( optlc_net_394 ) , + .HI ( SYNOPSYS_UNCONNECTED_396 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_396 ( .LO ( optlc_net_395 ) , + .HI ( SYNOPSYS_UNCONNECTED_397 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_397 ( .LO ( optlc_net_396 ) , + .HI ( SYNOPSYS_UNCONNECTED_398 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_398 ( .LO ( optlc_net_397 ) , + .HI ( SYNOPSYS_UNCONNECTED_399 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_399 ( .LO ( optlc_net_398 ) , + .HI ( SYNOPSYS_UNCONNECTED_400 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_400 ( .LO ( optlc_net_399 ) , + .HI ( SYNOPSYS_UNCONNECTED_401 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_401 ( .LO ( optlc_net_400 ) , + .HI ( SYNOPSYS_UNCONNECTED_402 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_402 ( .LO ( optlc_net_401 ) , + .HI ( SYNOPSYS_UNCONNECTED_403 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_403 ( .LO ( optlc_net_402 ) , + .HI ( SYNOPSYS_UNCONNECTED_404 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_404 ( .LO ( optlc_net_403 ) , + .HI ( SYNOPSYS_UNCONNECTED_405 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_405 ( .LO ( optlc_net_404 ) , + .HI ( SYNOPSYS_UNCONNECTED_406 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_405 ) , + .HI ( SYNOPSYS_UNCONNECTED_407 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_406 ) , + .HI ( SYNOPSYS_UNCONNECTED_408 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_407 ) , + .HI ( SYNOPSYS_UNCONNECTED_409 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_408 ) , + .HI ( SYNOPSYS_UNCONNECTED_410 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_410 ( .LO ( optlc_net_409 ) , + .HI ( SYNOPSYS_UNCONNECTED_411 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_410 ) , + .HI ( SYNOPSYS_UNCONNECTED_412 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_412 ( .LO ( optlc_net_411 ) , + .HI ( SYNOPSYS_UNCONNECTED_413 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_413 ( .LO ( optlc_net_412 ) , + .HI ( SYNOPSYS_UNCONNECTED_414 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_414 ( .LO ( optlc_net_413 ) , + .HI ( SYNOPSYS_UNCONNECTED_415 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_415 ( .LO ( optlc_net_414 ) , + .HI ( SYNOPSYS_UNCONNECTED_416 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_415 ) , + .HI ( SYNOPSYS_UNCONNECTED_417 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_416 ) , + .HI ( SYNOPSYS_UNCONNECTED_418 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_417 ) , + .HI ( SYNOPSYS_UNCONNECTED_419 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_418 ) , + .HI ( SYNOPSYS_UNCONNECTED_420 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_419 ) , + .HI ( SYNOPSYS_UNCONNECTED_421 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_420 ) , + .HI ( SYNOPSYS_UNCONNECTED_422 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_421 ) , + .HI ( SYNOPSYS_UNCONNECTED_423 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_422 ) , + .HI ( SYNOPSYS_UNCONNECTED_424 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_423 ) , + .HI ( SYNOPSYS_UNCONNECTED_425 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_424 ) , + .HI ( SYNOPSYS_UNCONNECTED_426 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_425 ) , + .HI ( SYNOPSYS_UNCONNECTED_427 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_426 ) , + .HI ( SYNOPSYS_UNCONNECTED_428 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_427 ) , + .HI ( SYNOPSYS_UNCONNECTED_429 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_428 ) , + .HI ( SYNOPSYS_UNCONNECTED_430 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_429 ) , + .HI ( SYNOPSYS_UNCONNECTED_431 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_430 ) , + .HI ( SYNOPSYS_UNCONNECTED_432 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_431 ) , + .HI ( SYNOPSYS_UNCONNECTED_433 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_432 ) , + .HI ( SYNOPSYS_UNCONNECTED_434 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_433 ) , + .HI ( SYNOPSYS_UNCONNECTED_435 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_434 ) , + .HI ( SYNOPSYS_UNCONNECTED_436 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_435 ) , + .HI ( SYNOPSYS_UNCONNECTED_437 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_436 ) , + .HI ( SYNOPSYS_UNCONNECTED_438 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_437 ) , + .HI ( SYNOPSYS_UNCONNECTED_439 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_438 ) , + .HI ( SYNOPSYS_UNCONNECTED_440 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_439 ) , + .HI ( SYNOPSYS_UNCONNECTED_441 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_440 ) , + .HI ( SYNOPSYS_UNCONNECTED_442 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_441 ) , + .HI ( SYNOPSYS_UNCONNECTED_443 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_442 ) , + .HI ( SYNOPSYS_UNCONNECTED_444 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_443 ) , + .HI ( SYNOPSYS_UNCONNECTED_445 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_444 ) , + .HI ( SYNOPSYS_UNCONNECTED_446 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_445 ) , + .HI ( SYNOPSYS_UNCONNECTED_447 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_446 ) , + .HI ( SYNOPSYS_UNCONNECTED_448 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_447 ) , + .HI ( SYNOPSYS_UNCONNECTED_449 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_448 ) , + .HI ( SYNOPSYS_UNCONNECTED_450 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_449 ) , + .HI ( SYNOPSYS_UNCONNECTED_451 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_450 ) , + .HI ( SYNOPSYS_UNCONNECTED_452 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_451 ) , + .HI ( SYNOPSYS_UNCONNECTED_453 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_452 ) , + .HI ( SYNOPSYS_UNCONNECTED_454 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_453 ) , + .HI ( SYNOPSYS_UNCONNECTED_455 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_454 ) , + .HI ( SYNOPSYS_UNCONNECTED_456 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_455 ) , + .HI ( SYNOPSYS_UNCONNECTED_457 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_456 ) , + .HI ( SYNOPSYS_UNCONNECTED_458 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_457 ) , + .HI ( SYNOPSYS_UNCONNECTED_459 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_458 ) , + .HI ( SYNOPSYS_UNCONNECTED_460 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_459 ) , + .HI ( SYNOPSYS_UNCONNECTED_461 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_460 ) , + .HI ( SYNOPSYS_UNCONNECTED_462 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_461 ) , + .HI ( SYNOPSYS_UNCONNECTED_463 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_462 ) , + .HI ( SYNOPSYS_UNCONNECTED_464 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_463 ) , + .HI ( SYNOPSYS_UNCONNECTED_465 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_464 ) , + .HI ( SYNOPSYS_UNCONNECTED_466 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_465 ) , + .HI ( SYNOPSYS_UNCONNECTED_467 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_466 ) , + .HI ( SYNOPSYS_UNCONNECTED_468 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_467 ) , + .HI ( SYNOPSYS_UNCONNECTED_469 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_468 ) , + .HI ( SYNOPSYS_UNCONNECTED_470 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_469 ) , + .HI ( SYNOPSYS_UNCONNECTED_471 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_470 ) , + .HI ( SYNOPSYS_UNCONNECTED_472 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_471 ) , + .HI ( SYNOPSYS_UNCONNECTED_473 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_472 ) , + .HI ( SYNOPSYS_UNCONNECTED_474 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_473 ) , + .HI ( SYNOPSYS_UNCONNECTED_475 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_474 ) , + .HI ( SYNOPSYS_UNCONNECTED_476 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_475 ) , + .HI ( SYNOPSYS_UNCONNECTED_477 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_476 ) , + .HI ( SYNOPSYS_UNCONNECTED_478 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_477 ) , + .HI ( SYNOPSYS_UNCONNECTED_479 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_478 ) , + .HI ( SYNOPSYS_UNCONNECTED_480 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_479 ) , + .HI ( SYNOPSYS_UNCONNECTED_481 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_480 ) , + .HI ( SYNOPSYS_UNCONNECTED_482 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_481 ) , + .HI ( SYNOPSYS_UNCONNECTED_483 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_482 ) , + .HI ( SYNOPSYS_UNCONNECTED_484 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_483 ) , + .HI ( SYNOPSYS_UNCONNECTED_485 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_484 ) , + .HI ( SYNOPSYS_UNCONNECTED_486 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_485 ) , + .HI ( SYNOPSYS_UNCONNECTED_487 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_486 ) , + .HI ( SYNOPSYS_UNCONNECTED_488 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_487 ) , + .HI ( SYNOPSYS_UNCONNECTED_489 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_488 ) , + .HI ( SYNOPSYS_UNCONNECTED_490 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_489 ) , + .HI ( SYNOPSYS_UNCONNECTED_491 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_490 ) , + .HI ( SYNOPSYS_UNCONNECTED_492 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_491 ) , + .HI ( SYNOPSYS_UNCONNECTED_493 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_492 ) , + .HI ( SYNOPSYS_UNCONNECTED_494 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_493 ) , + .HI ( SYNOPSYS_UNCONNECTED_495 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_494 ) , + .HI ( SYNOPSYS_UNCONNECTED_496 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_495 ) , + .HI ( SYNOPSYS_UNCONNECTED_497 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_496 ) , + .HI ( SYNOPSYS_UNCONNECTED_498 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_497 ) , + .HI ( SYNOPSYS_UNCONNECTED_499 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_498 ) , + .HI ( SYNOPSYS_UNCONNECTED_500 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_499 ) , + .HI ( SYNOPSYS_UNCONNECTED_501 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_500 ) , + .HI ( SYNOPSYS_UNCONNECTED_502 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_501 ) , + .HI ( SYNOPSYS_UNCONNECTED_503 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_502 ) , + .HI ( SYNOPSYS_UNCONNECTED_504 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_503 ) , + .HI ( SYNOPSYS_UNCONNECTED_505 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_504 ) , + .HI ( SYNOPSYS_UNCONNECTED_506 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_505 ) , + .HI ( SYNOPSYS_UNCONNECTED_507 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_506 ) , + .HI ( SYNOPSYS_UNCONNECTED_508 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_507 ) , + .HI ( SYNOPSYS_UNCONNECTED_509 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_508 ) , + .HI ( SYNOPSYS_UNCONNECTED_510 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_509 ) , + .HI ( SYNOPSYS_UNCONNECTED_511 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_510 ) , + .HI ( SYNOPSYS_UNCONNECTED_512 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_511 ) , + .HI ( SYNOPSYS_UNCONNECTED_513 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_512 ) , + .HI ( SYNOPSYS_UNCONNECTED_514 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_513 ) , + .HI ( SYNOPSYS_UNCONNECTED_515 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_514 ) , + .HI ( SYNOPSYS_UNCONNECTED_516 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_515 ) , + .HI ( SYNOPSYS_UNCONNECTED_517 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_516 ) , + .HI ( SYNOPSYS_UNCONNECTED_518 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_517 ) , + .HI ( SYNOPSYS_UNCONNECTED_519 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_518 ) , + .HI ( SYNOPSYS_UNCONNECTED_520 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_519 ) , + .HI ( SYNOPSYS_UNCONNECTED_521 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_520 ) , + .HI ( SYNOPSYS_UNCONNECTED_522 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_521 ) , + .HI ( SYNOPSYS_UNCONNECTED_523 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_522 ) , + .HI ( SYNOPSYS_UNCONNECTED_524 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_523 ) , + .HI ( SYNOPSYS_UNCONNECTED_525 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_524 ) , + .HI ( SYNOPSYS_UNCONNECTED_526 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_525 ) , + .HI ( SYNOPSYS_UNCONNECTED_527 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_526 ) , + .HI ( SYNOPSYS_UNCONNECTED_528 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_527 ) , + .HI ( SYNOPSYS_UNCONNECTED_529 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_528 ) , + .HI ( SYNOPSYS_UNCONNECTED_530 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_529 ) , + .HI ( SYNOPSYS_UNCONNECTED_531 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_530 ) , + .HI ( SYNOPSYS_UNCONNECTED_532 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_531 ) , + .HI ( SYNOPSYS_UNCONNECTED_533 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_532 ) , + .HI ( SYNOPSYS_UNCONNECTED_534 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_533 ) , + .HI ( SYNOPSYS_UNCONNECTED_535 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_534 ) , + .HI ( SYNOPSYS_UNCONNECTED_536 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_535 ) , + .HI ( SYNOPSYS_UNCONNECTED_537 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_536 ) , + .HI ( SYNOPSYS_UNCONNECTED_538 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_537 ) , + .HI ( SYNOPSYS_UNCONNECTED_539 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_538 ) , + .HI ( SYNOPSYS_UNCONNECTED_540 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_539 ) , + .HI ( SYNOPSYS_UNCONNECTED_541 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_540 ) , + .HI ( SYNOPSYS_UNCONNECTED_542 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_541 ) , + .HI ( SYNOPSYS_UNCONNECTED_543 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_542 ) , + .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_543 ) , + .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_544 ) , + .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_545 ) , + .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_546 ) , + .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_547 ) , + .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_548 ) , + .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_549 ) , + .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_550 ) , + .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_551 ) , + .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_552 ) , + .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_553 ) , + .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_554 ) , + .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_555 ) , + .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_556 ) , + .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_557 ) , + .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_558 ) , + .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_559 ) , + .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_560 ) , + .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_561 ) , + .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_562 ) , + .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_563 ) , + .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_564 ) , + .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_565 ) , + .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_566 ) , + .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_567 ) , + .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_568 ) , + .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_569 ) , + .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_570 ) , + .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_571 ) , + .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_572 ) , + .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_573 ) , + .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_574 ) , + .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_575 ) , + .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_576 ) , + .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_577 ) , + .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_578 ) , + .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_579 ) , + .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_580 ) , + .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_581 ) , + .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_582 ) , + .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_583 ) , + .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_584 ) , + .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_585 ) , + .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_586 ) , + .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_587 ) , + .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_588 ) , + .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_589 ) , + .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_590 ) , + .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_591 ) , + .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_592 ) , + .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_593 ) , + .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_594 ) , + .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_595 ) , + .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_596 ) , + .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_597 ) , + .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_598 ) , + .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_599 ) , + .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_600 ) , + .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_601 ) , + .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_602 ) , + .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_603 ) , + .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_604 ) , + .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_605 ) , + .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_606 ) , + .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_607 ) , + .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_608 ) , + .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_609 ) , + .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_610 ) , + .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_611 ) , + .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_612 ) , + .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_613 ) , + .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_614 ) , + .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_615 ) , + .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_616 ) , + .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_617 ) , + .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_618 ) , + .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_619 ) , + .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_620 ) , + .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_621 ) , + .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_622 ) , + .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_623 ) , + .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_624 ) , + .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_625 ) , + .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_626 ) , + .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_627 ) , + .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_628 ) , + .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_629 ) , + .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_630 ) , + .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_631 ) , + .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_632 ) , + .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_633 ) , + .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_634 ) , + .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_635 ) , + .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_636 ) , + .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_637 ) , + .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_638 ) , + .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_639 ) , + .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_640 ) , + .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_642 ( .LO ( optlc_net_641 ) , + .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_642 ) , + .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_643 ) , + .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_644 ) , + .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_645 ) , + .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_646 ) , + .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_647 ) , + .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_648 ) , + .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_649 ) , + .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_650 ) , + .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_651 ) , + .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_652 ) , + .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_653 ) , + .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_654 ) , + .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_655 ) , + .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_656 ) , + .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_657 ) , + .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_658 ) , + .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_659 ) , + .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_660 ) , + .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_661 ) , + .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_662 ) , + .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_663 ) , + .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_664 ) , + .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_665 ) , + .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_667 ( .LO ( optlc_net_666 ) , + .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_667 ) , + .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_668 ) , + .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_669 ) , + .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_670 ) , + .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_671 ) , + .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_672 ) , + .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_673 ) , + .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_674 ) , + .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_675 ) , + .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_676 ) , + .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_677 ) , + .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_678 ) , + .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_679 ) , + .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_681 ( .LO ( optlc_net_680 ) , + .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_681 ) , + .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_682 ) , + .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_683 ) , + .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_684 ) , + .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_685 ) , + .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_686 ) , + .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_687 ) , + .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_688 ) , + .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_689 ) , + .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_690 ) , + .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_691 ) , + .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_692 ) , + .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_693 ) , + .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_694 ) , + .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_695 ) , + .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_696 ) , + .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_697 ) , + .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_698 ) , + .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_699 ) , + .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_700 ) , + .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_701 ) , + .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_702 ) , + .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_703 ) , + .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_704 ) , + .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_705 ) , + .HI ( SYNOPSYS_UNCONNECTED_707 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_706 ) , + .HI ( SYNOPSYS_UNCONNECTED_708 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_707 ) , + .HI ( SYNOPSYS_UNCONNECTED_709 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_708 ) , + .HI ( SYNOPSYS_UNCONNECTED_710 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_709 ) , + .HI ( SYNOPSYS_UNCONNECTED_711 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_710 ) , + .HI ( SYNOPSYS_UNCONNECTED_712 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_711 ) , + .HI ( SYNOPSYS_UNCONNECTED_713 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_712 ) , + .HI ( SYNOPSYS_UNCONNECTED_714 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_713 ) , + .HI ( SYNOPSYS_UNCONNECTED_715 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_714 ) , + .HI ( SYNOPSYS_UNCONNECTED_716 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_715 ) , + .HI ( SYNOPSYS_UNCONNECTED_717 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_716 ) , + .HI ( SYNOPSYS_UNCONNECTED_718 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_717 ) , + .HI ( SYNOPSYS_UNCONNECTED_719 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_718 ) , + .HI ( SYNOPSYS_UNCONNECTED_720 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_719 ) , + .HI ( SYNOPSYS_UNCONNECTED_721 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_720 ) , + .HI ( SYNOPSYS_UNCONNECTED_722 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_721 ) , + .HI ( SYNOPSYS_UNCONNECTED_723 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_722 ) , + .HI ( SYNOPSYS_UNCONNECTED_724 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_723 ) , + .HI ( SYNOPSYS_UNCONNECTED_725 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_724 ) , + .HI ( SYNOPSYS_UNCONNECTED_726 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_725 ) , + .HI ( SYNOPSYS_UNCONNECTED_727 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_726 ) , + .HI ( SYNOPSYS_UNCONNECTED_728 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_727 ) , + .HI ( SYNOPSYS_UNCONNECTED_729 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_728 ) , + .HI ( SYNOPSYS_UNCONNECTED_730 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_729 ) , + .HI ( SYNOPSYS_UNCONNECTED_731 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_730 ) , + .HI ( SYNOPSYS_UNCONNECTED_732 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_731 ) , + .HI ( SYNOPSYS_UNCONNECTED_733 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_732 ) , + .HI ( SYNOPSYS_UNCONNECTED_734 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_733 ) , + .HI ( SYNOPSYS_UNCONNECTED_735 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_734 ) , + .HI ( SYNOPSYS_UNCONNECTED_736 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_735 ) , + .HI ( SYNOPSYS_UNCONNECTED_737 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_736 ) , + .HI ( SYNOPSYS_UNCONNECTED_738 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_737 ) , + .HI ( SYNOPSYS_UNCONNECTED_739 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_740 ( .LO ( optlc_net_738 ) , + .HI ( SYNOPSYS_UNCONNECTED_740 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_739 ) , + .HI ( SYNOPSYS_UNCONNECTED_741 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_740 ) , + .HI ( SYNOPSYS_UNCONNECTED_742 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_741 ) , + .HI ( SYNOPSYS_UNCONNECTED_743 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_742 ) , + .HI ( SYNOPSYS_UNCONNECTED_744 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_743 ) , + .HI ( SYNOPSYS_UNCONNECTED_745 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_744 ) , + .HI ( SYNOPSYS_UNCONNECTED_746 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_745 ) , + .HI ( SYNOPSYS_UNCONNECTED_747 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_746 ) , + .HI ( SYNOPSYS_UNCONNECTED_748 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_747 ) , + .HI ( SYNOPSYS_UNCONNECTED_749 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_748 ) , + .HI ( SYNOPSYS_UNCONNECTED_750 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_751 ( .LO ( optlc_net_749 ) , + .HI ( SYNOPSYS_UNCONNECTED_751 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_750 ) , + .HI ( SYNOPSYS_UNCONNECTED_752 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_751 ) , + .HI ( SYNOPSYS_UNCONNECTED_753 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_752 ) , + .HI ( SYNOPSYS_UNCONNECTED_754 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_753 ) , + .HI ( SYNOPSYS_UNCONNECTED_755 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_754 ) , + .HI ( SYNOPSYS_UNCONNECTED_756 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_755 ) , + .HI ( SYNOPSYS_UNCONNECTED_757 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_756 ) , + .HI ( SYNOPSYS_UNCONNECTED_758 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_757 ) , + .HI ( SYNOPSYS_UNCONNECTED_759 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_758 ) , + .HI ( SYNOPSYS_UNCONNECTED_760 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_759 ) , + .HI ( SYNOPSYS_UNCONNECTED_761 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_760 ) , + .HI ( SYNOPSYS_UNCONNECTED_762 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_761 ) , + .HI ( SYNOPSYS_UNCONNECTED_763 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_762 ) , + .HI ( SYNOPSYS_UNCONNECTED_764 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_763 ) , + .HI ( SYNOPSYS_UNCONNECTED_765 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_764 ) , + .HI ( SYNOPSYS_UNCONNECTED_766 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_765 ) , + .HI ( SYNOPSYS_UNCONNECTED_767 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_766 ) , + .HI ( SYNOPSYS_UNCONNECTED_768 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_767 ) , + .HI ( SYNOPSYS_UNCONNECTED_769 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_768 ) , + .HI ( SYNOPSYS_UNCONNECTED_770 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_769 ) , + .HI ( SYNOPSYS_UNCONNECTED_771 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_770 ) , + .HI ( SYNOPSYS_UNCONNECTED_772 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_771 ) , + .HI ( SYNOPSYS_UNCONNECTED_773 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_772 ) , + .HI ( SYNOPSYS_UNCONNECTED_774 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_773 ) , + .HI ( SYNOPSYS_UNCONNECTED_775 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_774 ) , + .HI ( SYNOPSYS_UNCONNECTED_776 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_775 ) , + .HI ( SYNOPSYS_UNCONNECTED_777 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_776 ) , + .HI ( SYNOPSYS_UNCONNECTED_778 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_777 ) , + .HI ( SYNOPSYS_UNCONNECTED_779 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_778 ) , + .HI ( SYNOPSYS_UNCONNECTED_780 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_779 ) , + .HI ( SYNOPSYS_UNCONNECTED_781 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_780 ) , + .HI ( SYNOPSYS_UNCONNECTED_782 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_781 ) , + .HI ( SYNOPSYS_UNCONNECTED_783 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_782 ) , + .HI ( SYNOPSYS_UNCONNECTED_784 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_783 ) , + .HI ( SYNOPSYS_UNCONNECTED_785 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_784 ) , + .HI ( SYNOPSYS_UNCONNECTED_786 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_785 ) , + .HI ( SYNOPSYS_UNCONNECTED_787 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_786 ) , + .HI ( SYNOPSYS_UNCONNECTED_788 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_787 ) , + .HI ( SYNOPSYS_UNCONNECTED_789 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_788 ) , + .HI ( SYNOPSYS_UNCONNECTED_790 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_789 ) , + .HI ( SYNOPSYS_UNCONNECTED_791 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_790 ) , + .HI ( SYNOPSYS_UNCONNECTED_792 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_791 ) , + .HI ( SYNOPSYS_UNCONNECTED_793 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_792 ) , + .HI ( SYNOPSYS_UNCONNECTED_794 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_793 ) , + .HI ( SYNOPSYS_UNCONNECTED_795 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_794 ) , + .HI ( SYNOPSYS_UNCONNECTED_796 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_795 ) , + .HI ( SYNOPSYS_UNCONNECTED_797 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_796 ) , + .HI ( SYNOPSYS_UNCONNECTED_798 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_797 ) , + .HI ( SYNOPSYS_UNCONNECTED_799 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_798 ) , + .HI ( SYNOPSYS_UNCONNECTED_800 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_799 ) , + .HI ( SYNOPSYS_UNCONNECTED_801 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_800 ) , + .HI ( SYNOPSYS_UNCONNECTED_802 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_801 ) , + .HI ( SYNOPSYS_UNCONNECTED_803 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_802 ) , + .HI ( SYNOPSYS_UNCONNECTED_804 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_803 ) , + .HI ( SYNOPSYS_UNCONNECTED_805 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_804 ) , + .HI ( SYNOPSYS_UNCONNECTED_806 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_805 ) , + .HI ( SYNOPSYS_UNCONNECTED_807 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_806 ) , + .HI ( SYNOPSYS_UNCONNECTED_808 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_807 ) , + .HI ( SYNOPSYS_UNCONNECTED_809 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_808 ) , + .HI ( SYNOPSYS_UNCONNECTED_810 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_809 ) , + .HI ( SYNOPSYS_UNCONNECTED_811 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_810 ) , + .HI ( SYNOPSYS_UNCONNECTED_812 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_811 ) , + .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_812 ) , + .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_813 ) , + .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_814 ) , + .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_815 ) , + .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_816 ) , + .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_817 ) , + .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_818 ) , + .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_819 ) , + .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_820 ) , + .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_825 ( .LO ( optlc_net_821 ) , + .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_822 ) , + .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_823 ) , + .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_824 ) , + .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_825 ) , + .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_826 ) , + .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_827 ) , + .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_828 ) , + .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_829 ) , + .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_834 ( .LO ( optlc_net_830 ) , + .HI ( SYNOPSYS_UNCONNECTED_832 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_831 ) , + .HI ( SYNOPSYS_UNCONNECTED_833 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_832 ) , + .HI ( SYNOPSYS_UNCONNECTED_834 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_833 ) , + .HI ( SYNOPSYS_UNCONNECTED_835 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_834 ) , + .HI ( SYNOPSYS_UNCONNECTED_836 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_835 ) , + .HI ( SYNOPSYS_UNCONNECTED_837 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_836 ) , + .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_837 ) , + .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_838 ) , + .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_839 ) , + .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_840 ) , + .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_841 ) , + .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_842 ) , + .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_843 ) , + .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_844 ) , + .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_845 ) , + .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_850 ( .LO ( optlc_net_846 ) , + .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_847 ) , + .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_848 ) , + .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_849 ) , + .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_850 ) , + .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_851 ) , + .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_852 ) , + .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_857 ( .LO ( optlc_net_853 ) , + .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_854 ) , + .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_855 ) , + .HI ( SYNOPSYS_UNCONNECTED_857 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_856 ) , + .HI ( SYNOPSYS_UNCONNECTED_858 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_857 ) , + .HI ( SYNOPSYS_UNCONNECTED_859 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_858 ) , + .HI ( SYNOPSYS_UNCONNECTED_860 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_859 ) , + .HI ( SYNOPSYS_UNCONNECTED_861 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_860 ) , + .HI ( SYNOPSYS_UNCONNECTED_862 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_861 ) , + .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_862 ) , + .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_863 ) , + .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_864 ) , + .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_865 ) , + .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_866 ) , + .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_867 ) , + .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_868 ) , + .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_869 ) , + .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_870 ) , + .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_871 ) , + .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_872 ) , + .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_873 ) , + .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_874 ) , + .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_875 ) , + .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_876 ) , + .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_877 ) , + .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_878 ) , + .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_879 ) , + .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_880 ) , + .HI ( SYNOPSYS_UNCONNECTED_882 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_881 ) , + .HI ( SYNOPSYS_UNCONNECTED_883 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_882 ) , + .HI ( SYNOPSYS_UNCONNECTED_884 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_883 ) , + .HI ( SYNOPSYS_UNCONNECTED_885 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_884 ) , + .HI ( SYNOPSYS_UNCONNECTED_886 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_889 ( .LO ( optlc_net_885 ) , + .HI ( SYNOPSYS_UNCONNECTED_887 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_886 ) , + .HI ( SYNOPSYS_UNCONNECTED_888 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_887 ) , + .HI ( SYNOPSYS_UNCONNECTED_889 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_888 ) , + .HI ( SYNOPSYS_UNCONNECTED_890 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_889 ) , + .HI ( SYNOPSYS_UNCONNECTED_891 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_890 ) , + .HI ( SYNOPSYS_UNCONNECTED_892 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_891 ) , + .HI ( SYNOPSYS_UNCONNECTED_893 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_892 ) , + .HI ( SYNOPSYS_UNCONNECTED_894 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_893 ) , + .HI ( SYNOPSYS_UNCONNECTED_895 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_894 ) , + .HI ( SYNOPSYS_UNCONNECTED_896 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_895 ) , + .HI ( SYNOPSYS_UNCONNECTED_897 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_900 ( .LO ( optlc_net_896 ) , + .HI ( SYNOPSYS_UNCONNECTED_898 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_897 ) , + .HI ( SYNOPSYS_UNCONNECTED_899 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_898 ) , + .HI ( SYNOPSYS_UNCONNECTED_900 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_899 ) , + .HI ( SYNOPSYS_UNCONNECTED_901 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_900 ) , + .HI ( SYNOPSYS_UNCONNECTED_902 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_901 ) , + .HI ( SYNOPSYS_UNCONNECTED_903 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_902 ) , + .HI ( SYNOPSYS_UNCONNECTED_904 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_903 ) , + .HI ( SYNOPSYS_UNCONNECTED_905 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_904 ) , + .HI ( SYNOPSYS_UNCONNECTED_906 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_905 ) , + .HI ( SYNOPSYS_UNCONNECTED_907 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_906 ) , + .HI ( SYNOPSYS_UNCONNECTED_908 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_907 ) , + .HI ( SYNOPSYS_UNCONNECTED_909 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_908 ) , + .HI ( SYNOPSYS_UNCONNECTED_910 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_909 ) , + .HI ( SYNOPSYS_UNCONNECTED_911 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_910 ) , + .HI ( SYNOPSYS_UNCONNECTED_912 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_911 ) , + .HI ( SYNOPSYS_UNCONNECTED_913 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_912 ) , + .HI ( SYNOPSYS_UNCONNECTED_914 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_913 ) , + .HI ( SYNOPSYS_UNCONNECTED_915 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_914 ) , + .HI ( SYNOPSYS_UNCONNECTED_916 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_915 ) , + .HI ( SYNOPSYS_UNCONNECTED_917 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_920 ( .LO ( optlc_net_916 ) , + .HI ( SYNOPSYS_UNCONNECTED_918 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_917 ) , + .HI ( SYNOPSYS_UNCONNECTED_919 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_918 ) , + .HI ( SYNOPSYS_UNCONNECTED_920 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_919 ) , + .HI ( SYNOPSYS_UNCONNECTED_921 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_920 ) , + .HI ( SYNOPSYS_UNCONNECTED_922 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_921 ) , + .HI ( SYNOPSYS_UNCONNECTED_923 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_922 ) , + .HI ( SYNOPSYS_UNCONNECTED_924 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_923 ) , + .HI ( SYNOPSYS_UNCONNECTED_925 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_924 ) , + .HI ( SYNOPSYS_UNCONNECTED_926 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_925 ) , + .HI ( SYNOPSYS_UNCONNECTED_927 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_926 ) , + .HI ( SYNOPSYS_UNCONNECTED_928 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_927 ) , + .HI ( SYNOPSYS_UNCONNECTED_929 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_928 ) , + .HI ( SYNOPSYS_UNCONNECTED_930 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_933 ( .LO ( optlc_net_929 ) , + .HI ( SYNOPSYS_UNCONNECTED_931 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_934 ( .LO ( optlc_net_930 ) , + .HI ( SYNOPSYS_UNCONNECTED_932 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_935 ( .LO ( optlc_net_931 ) , + .HI ( SYNOPSYS_UNCONNECTED_933 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_936 ( .LO ( optlc_net_932 ) , + .HI ( SYNOPSYS_UNCONNECTED_934 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_937 ( .LO ( optlc_net_933 ) , + .HI ( SYNOPSYS_UNCONNECTED_935 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_938 ( .LO ( optlc_net_934 ) , + .HI ( SYNOPSYS_UNCONNECTED_936 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_939 ( .LO ( optlc_net_935 ) , + .HI ( SYNOPSYS_UNCONNECTED_937 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_940 ( .LO ( optlc_net_936 ) , + .HI ( SYNOPSYS_UNCONNECTED_938 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_941 ( .LO ( optlc_net_937 ) , + .HI ( SYNOPSYS_UNCONNECTED_939 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_942 ( .LO ( optlc_net_938 ) , + .HI ( SYNOPSYS_UNCONNECTED_940 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_943 ( .LO ( optlc_net_939 ) , + .HI ( SYNOPSYS_UNCONNECTED_941 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_944 ( .LO ( optlc_net_940 ) , + .HI ( SYNOPSYS_UNCONNECTED_942 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_945 ( .LO ( optlc_net_941 ) , + .HI ( SYNOPSYS_UNCONNECTED_943 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_946 ( .LO ( optlc_net_942 ) , + .HI ( SYNOPSYS_UNCONNECTED_944 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_947 ( .LO ( optlc_net_943 ) , + .HI ( SYNOPSYS_UNCONNECTED_945 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_948 ( .LO ( optlc_net_944 ) , + .HI ( SYNOPSYS_UNCONNECTED_946 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_949 ( .LO ( optlc_net_945 ) , + .HI ( SYNOPSYS_UNCONNECTED_947 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_950 ( .LO ( optlc_net_946 ) , + .HI ( SYNOPSYS_UNCONNECTED_948 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_951 ( .LO ( optlc_net_947 ) , + .HI ( SYNOPSYS_UNCONNECTED_949 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_952 ( .LO ( optlc_net_948 ) , + .HI ( SYNOPSYS_UNCONNECTED_950 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_953 ( .LO ( optlc_net_949 ) , + .HI ( SYNOPSYS_UNCONNECTED_951 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_954 ( .LO ( optlc_net_950 ) , + .HI ( SYNOPSYS_UNCONNECTED_952 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_955 ( .LO ( optlc_net_951 ) , + .HI ( SYNOPSYS_UNCONNECTED_953 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_956 ( .LO ( optlc_net_952 ) , + .HI ( SYNOPSYS_UNCONNECTED_954 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_957 ( .LO ( optlc_net_953 ) , + .HI ( SYNOPSYS_UNCONNECTED_955 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_958 ( .LO ( optlc_net_954 ) , + .HI ( SYNOPSYS_UNCONNECTED_956 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_959 ( .LO ( optlc_net_955 ) , + .HI ( SYNOPSYS_UNCONNECTED_957 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_961 ( .LO ( optlc_net_956 ) , + .HI ( SYNOPSYS_UNCONNECTED_958 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_962 ( .LO ( optlc_net_957 ) , + .HI ( SYNOPSYS_UNCONNECTED_959 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_963 ( .LO ( optlc_net_958 ) , + .HI ( SYNOPSYS_UNCONNECTED_960 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_964 ( .LO ( optlc_net_959 ) , + .HI ( SYNOPSYS_UNCONNECTED_961 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_965 ( .LO ( optlc_net_960 ) , + .HI ( SYNOPSYS_UNCONNECTED_962 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_966 ( .LO ( optlc_net_961 ) , + .HI ( SYNOPSYS_UNCONNECTED_963 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_968 ( .LO ( optlc_net_962 ) , + .HI ( SYNOPSYS_UNCONNECTED_964 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_969 ( .LO ( optlc_net_963 ) , + .HI ( SYNOPSYS_UNCONNECTED_965 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_970 ( .LO ( optlc_net_964 ) , + .HI ( SYNOPSYS_UNCONNECTED_966 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_971 ( .LO ( optlc_net_965 ) , + .HI ( SYNOPSYS_UNCONNECTED_967 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_972 ( .LO ( optlc_net_966 ) , + .HI ( SYNOPSYS_UNCONNECTED_968 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_973 ( .LO ( optlc_net_967 ) , + .HI ( SYNOPSYS_UNCONNECTED_969 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_974 ( .LO ( optlc_net_968 ) , + .HI ( SYNOPSYS_UNCONNECTED_970 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_975 ( .LO ( optlc_net_969 ) , + .HI ( SYNOPSYS_UNCONNECTED_971 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_976 ( .LO ( optlc_net_970 ) , + .HI ( SYNOPSYS_UNCONNECTED_972 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_977 ( .LO ( optlc_net_971 ) , + .HI ( SYNOPSYS_UNCONNECTED_973 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_978 ( .LO ( optlc_net_972 ) , + .HI ( SYNOPSYS_UNCONNECTED_974 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_979 ( .LO ( optlc_net_973 ) , + .HI ( SYNOPSYS_UNCONNECTED_975 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_980 ( .LO ( optlc_net_974 ) , + .HI ( SYNOPSYS_UNCONNECTED_976 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_981 ( .LO ( optlc_net_975 ) , + .HI ( SYNOPSYS_UNCONNECTED_977 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_982 ( .LO ( optlc_net_976 ) , + .HI ( SYNOPSYS_UNCONNECTED_978 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_983 ( .LO ( optlc_net_977 ) , + .HI ( SYNOPSYS_UNCONNECTED_979 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_984 ( .LO ( optlc_net_978 ) , + .HI ( SYNOPSYS_UNCONNECTED_980 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_985 ( .LO ( optlc_net_979 ) , + .HI ( SYNOPSYS_UNCONNECTED_981 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_986 ( .LO ( optlc_net_980 ) , + .HI ( SYNOPSYS_UNCONNECTED_982 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_987 ( .LO ( optlc_net_981 ) , + .HI ( SYNOPSYS_UNCONNECTED_983 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_988 ( .LO ( optlc_net_982 ) , + .HI ( SYNOPSYS_UNCONNECTED_984 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_989 ( .LO ( optlc_net_983 ) , + .HI ( SYNOPSYS_UNCONNECTED_985 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_990 ( .LO ( optlc_net_984 ) , + .HI ( SYNOPSYS_UNCONNECTED_986 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_991 ( .LO ( optlc_net_985 ) , + .HI ( SYNOPSYS_UNCONNECTED_987 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_992 ( .LO ( optlc_net_986 ) , + .HI ( SYNOPSYS_UNCONNECTED_988 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_993 ( .LO ( optlc_net_987 ) , + .HI ( SYNOPSYS_UNCONNECTED_989 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_994 ( .LO ( optlc_net_988 ) , + .HI ( SYNOPSYS_UNCONNECTED_990 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_995 ( .LO ( optlc_net_989 ) , + .HI ( SYNOPSYS_UNCONNECTED_991 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_996 ( .LO ( optlc_net_990 ) , + .HI ( SYNOPSYS_UNCONNECTED_992 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_997 ( .LO ( optlc_net_991 ) , + .HI ( SYNOPSYS_UNCONNECTED_993 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_998 ( .LO ( optlc_net_992 ) , + .HI ( SYNOPSYS_UNCONNECTED_994 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_999 ( .LO ( optlc_net_993 ) , + .HI ( SYNOPSYS_UNCONNECTED_995 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1000 ( .LO ( optlc_net_994 ) , + .HI ( SYNOPSYS_UNCONNECTED_996 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1001 ( .LO ( optlc_net_995 ) , + .HI ( SYNOPSYS_UNCONNECTED_997 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1002 ( .LO ( optlc_net_996 ) , + .HI ( SYNOPSYS_UNCONNECTED_998 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1003 ( .LO ( optlc_net_997 ) , + .HI ( SYNOPSYS_UNCONNECTED_999 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1004 ( .LO ( optlc_net_998 ) , + .HI ( SYNOPSYS_UNCONNECTED_1000 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1005 ( .LO ( optlc_net_999 ) , + .HI ( SYNOPSYS_UNCONNECTED_1001 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1006 ( .LO ( optlc_net_1000 ) , + .HI ( SYNOPSYS_UNCONNECTED_1002 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1007 ( .LO ( optlc_net_1001 ) , + .HI ( SYNOPSYS_UNCONNECTED_1003 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1008 ( .LO ( optlc_net_1002 ) , + .HI ( SYNOPSYS_UNCONNECTED_1004 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1009 ( .LO ( optlc_net_1003 ) , + .HI ( SYNOPSYS_UNCONNECTED_1005 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1010 ( .LO ( optlc_net_1004 ) , + .HI ( SYNOPSYS_UNCONNECTED_1006 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1011 ( .LO ( optlc_net_1005 ) , + .HI ( SYNOPSYS_UNCONNECTED_1007 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1012 ( .LO ( optlc_net_1006 ) , + .HI ( SYNOPSYS_UNCONNECTED_1008 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1013 ( .LO ( optlc_net_1007 ) , + .HI ( SYNOPSYS_UNCONNECTED_1009 ) ) ; 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SYNOPSYS_UNCONNECTED_1019 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1024 ( .LO ( optlc_net_1018 ) , + .HI ( SYNOPSYS_UNCONNECTED_1020 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1025 ( .LO ( optlc_net_1019 ) , + .HI ( SYNOPSYS_UNCONNECTED_1021 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1026 ( .LO ( optlc_net_1020 ) , + .HI ( SYNOPSYS_UNCONNECTED_1022 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1027 ( .LO ( optlc_net_1021 ) , + .HI ( SYNOPSYS_UNCONNECTED_1023 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1028 ( .LO ( optlc_net_1022 ) , + .HI ( SYNOPSYS_UNCONNECTED_1024 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1029 ( .LO ( optlc_net_1023 ) , + .HI ( SYNOPSYS_UNCONNECTED_1025 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1030 ( .LO ( optlc_net_1024 ) , + .HI ( SYNOPSYS_UNCONNECTED_1026 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1031 ( .LO ( optlc_net_1025 ) , + .HI ( SYNOPSYS_UNCONNECTED_1027 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1032 ( .LO ( optlc_net_1026 ) , + .HI ( SYNOPSYS_UNCONNECTED_1028 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1033 ( .LO ( optlc_net_1027 ) , + .HI ( SYNOPSYS_UNCONNECTED_1029 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1034 ( .LO ( optlc_net_1028 ) , + .HI ( SYNOPSYS_UNCONNECTED_1030 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1035 ( .LO ( optlc_net_1029 ) , + .HI ( SYNOPSYS_UNCONNECTED_1031 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1036 ( .LO ( optlc_net_1030 ) , + .HI ( SYNOPSYS_UNCONNECTED_1032 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1037 ( .LO ( optlc_net_1031 ) , + .HI ( SYNOPSYS_UNCONNECTED_1033 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1038 ( .LO ( optlc_net_1032 ) , + .HI ( SYNOPSYS_UNCONNECTED_1034 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1039 ( .LO ( optlc_net_1033 ) , + .HI ( SYNOPSYS_UNCONNECTED_1035 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1040 ( .LO ( optlc_net_1034 ) , + .HI ( SYNOPSYS_UNCONNECTED_1036 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1041 ( .LO ( optlc_net_1035 ) , + .HI ( SYNOPSYS_UNCONNECTED_1037 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1042 ( .LO ( optlc_net_1036 ) , + .HI ( SYNOPSYS_UNCONNECTED_1038 ) ) ; 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SYNOPSYS_UNCONNECTED_1048 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1054 ( .LO ( optlc_net_1047 ) , + .HI ( SYNOPSYS_UNCONNECTED_1049 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1055 ( .LO ( optlc_net_1048 ) , + .HI ( SYNOPSYS_UNCONNECTED_1050 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1056 ( .LO ( optlc_net_1049 ) , + .HI ( SYNOPSYS_UNCONNECTED_1051 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1057 ( .LO ( optlc_net_1050 ) , + .HI ( SYNOPSYS_UNCONNECTED_1052 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1058 ( .LO ( optlc_net_1051 ) , + .HI ( SYNOPSYS_UNCONNECTED_1053 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1059 ( .LO ( optlc_net_1052 ) , + .HI ( SYNOPSYS_UNCONNECTED_1054 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1060 ( .LO ( optlc_net_1053 ) , + .HI ( SYNOPSYS_UNCONNECTED_1055 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1061 ( .LO ( optlc_net_1054 ) , + .HI ( SYNOPSYS_UNCONNECTED_1056 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1062 ( .LO ( optlc_net_1055 ) , + .HI ( SYNOPSYS_UNCONNECTED_1057 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1063 ( .LO ( optlc_net_1056 ) , + .HI ( SYNOPSYS_UNCONNECTED_1058 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1064 ( .LO ( optlc_net_1057 ) , + .HI ( SYNOPSYS_UNCONNECTED_1059 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1065 ( .LO ( optlc_net_1058 ) , + .HI ( SYNOPSYS_UNCONNECTED_1060 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1066 ( .LO ( optlc_net_1059 ) , + .HI ( SYNOPSYS_UNCONNECTED_1061 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1067 ( .LO ( optlc_net_1060 ) , + .HI ( SYNOPSYS_UNCONNECTED_1062 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1068 ( .LO ( optlc_net_1061 ) , + .HI ( SYNOPSYS_UNCONNECTED_1063 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1069 ( .LO ( optlc_net_1062 ) , + .HI ( SYNOPSYS_UNCONNECTED_1064 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1070 ( .LO ( optlc_net_1063 ) , + .HI ( SYNOPSYS_UNCONNECTED_1065 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1072 ( .LO ( optlc_net_1064 ) , + .HI ( SYNOPSYS_UNCONNECTED_1066 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1073 ( .LO ( optlc_net_1065 ) , + .HI ( SYNOPSYS_UNCONNECTED_1067 ) ) ; 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SYNOPSYS_UNCONNECTED_1077 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1085 ( .LO ( optlc_net_1076 ) , + .HI ( SYNOPSYS_UNCONNECTED_1078 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1086 ( .LO ( optlc_net_1077 ) , + .HI ( SYNOPSYS_UNCONNECTED_1079 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1087 ( .LO ( optlc_net_1078 ) , + .HI ( SYNOPSYS_UNCONNECTED_1080 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1088 ( .LO ( optlc_net_1079 ) , + .HI ( SYNOPSYS_UNCONNECTED_1081 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1089 ( .LO ( optlc_net_1080 ) , + .HI ( SYNOPSYS_UNCONNECTED_1082 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1090 ( .LO ( optlc_net_1081 ) , + .HI ( SYNOPSYS_UNCONNECTED_1083 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1091 ( .LO ( optlc_net_1082 ) , + .HI ( SYNOPSYS_UNCONNECTED_1084 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1092 ( .LO ( optlc_net_1083 ) , + .HI ( SYNOPSYS_UNCONNECTED_1085 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1093 ( .LO ( optlc_net_1084 ) , + .HI ( SYNOPSYS_UNCONNECTED_1086 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1094 ( .LO ( optlc_net_1085 ) , + .HI ( SYNOPSYS_UNCONNECTED_1087 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1095 ( .LO ( optlc_net_1086 ) , + .HI ( SYNOPSYS_UNCONNECTED_1088 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1096 ( .LO ( optlc_net_1087 ) , + .HI ( SYNOPSYS_UNCONNECTED_1089 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1097 ( .LO ( optlc_net_1088 ) , + .HI ( SYNOPSYS_UNCONNECTED_1090 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1098 ( .LO ( optlc_net_1089 ) , + .HI ( SYNOPSYS_UNCONNECTED_1091 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1099 ( .LO ( optlc_net_1090 ) , + .HI ( SYNOPSYS_UNCONNECTED_1092 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1100 ( .LO ( optlc_net_1091 ) , + .HI ( SYNOPSYS_UNCONNECTED_1093 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1101 ( .LO ( optlc_net_1092 ) , + .HI ( SYNOPSYS_UNCONNECTED_1094 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1102 ( .LO ( optlc_net_1093 ) , + .HI ( SYNOPSYS_UNCONNECTED_1095 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1103 ( .LO ( optlc_net_1094 ) , + .HI ( SYNOPSYS_UNCONNECTED_1096 ) ) ; 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SYNOPSYS_UNCONNECTED_1106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1114 ( .LO ( optlc_net_1105 ) , + .HI ( SYNOPSYS_UNCONNECTED_1107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1115 ( .LO ( optlc_net_1106 ) , + .HI ( SYNOPSYS_UNCONNECTED_1108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1116 ( .LO ( optlc_net_1107 ) , + .HI ( SYNOPSYS_UNCONNECTED_1109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1117 ( .LO ( optlc_net_1108 ) , + .HI ( SYNOPSYS_UNCONNECTED_1110 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1118 ( .LO ( optlc_net_1109 ) , + .HI ( SYNOPSYS_UNCONNECTED_1111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1119 ( .LO ( optlc_net_1110 ) , + .HI ( SYNOPSYS_UNCONNECTED_1112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1120 ( .LO ( optlc_net_1111 ) , + .HI ( SYNOPSYS_UNCONNECTED_1113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1121 ( .LO ( optlc_net_1112 ) , + .HI ( SYNOPSYS_UNCONNECTED_1114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1122 ( .LO ( optlc_net_1113 ) , + .HI ( SYNOPSYS_UNCONNECTED_1115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1123 ( .LO ( optlc_net_1114 ) , + .HI ( SYNOPSYS_UNCONNECTED_1116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1124 ( .LO ( optlc_net_1115 ) , + .HI ( SYNOPSYS_UNCONNECTED_1117 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1125 ( .LO ( optlc_net_1116 ) , + .HI ( SYNOPSYS_UNCONNECTED_1118 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1126 ( .LO ( optlc_net_1117 ) , + .HI ( SYNOPSYS_UNCONNECTED_1119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1127 ( .LO ( optlc_net_1118 ) , + .HI ( SYNOPSYS_UNCONNECTED_1120 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1128 ( .LO ( optlc_net_1119 ) , + .HI ( SYNOPSYS_UNCONNECTED_1121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1129 ( .LO ( optlc_net_1120 ) , + .HI ( SYNOPSYS_UNCONNECTED_1122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1130 ( .LO ( optlc_net_1121 ) , + .HI ( SYNOPSYS_UNCONNECTED_1123 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1131 ( .LO ( optlc_net_1122 ) , + .HI ( SYNOPSYS_UNCONNECTED_1124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1132 ( .LO ( optlc_net_1123 ) , + .HI ( SYNOPSYS_UNCONNECTED_1125 ) ) ; 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SYNOPSYS_UNCONNECTED_1135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1143 ( .LO ( optlc_net_1134 ) , + .HI ( SYNOPSYS_UNCONNECTED_1136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1144 ( .LO ( optlc_net_1135 ) , + .HI ( SYNOPSYS_UNCONNECTED_1137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1145 ( .LO ( optlc_net_1136 ) , + .HI ( SYNOPSYS_UNCONNECTED_1138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1146 ( .LO ( optlc_net_1137 ) , + .HI ( SYNOPSYS_UNCONNECTED_1139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1147 ( .LO ( optlc_net_1138 ) , + .HI ( SYNOPSYS_UNCONNECTED_1140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1148 ( .LO ( optlc_net_1139 ) , + .HI ( SYNOPSYS_UNCONNECTED_1141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1149 ( .LO ( optlc_net_1140 ) , + .HI ( SYNOPSYS_UNCONNECTED_1142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1150 ( .LO ( optlc_net_1141 ) , + .HI ( SYNOPSYS_UNCONNECTED_1143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1151 ( .LO ( optlc_net_1142 ) , + .HI ( SYNOPSYS_UNCONNECTED_1144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1152 ( .LO ( optlc_net_1143 ) , + .HI ( SYNOPSYS_UNCONNECTED_1145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1154 ( .LO ( optlc_net_1144 ) , + .HI ( SYNOPSYS_UNCONNECTED_1146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1155 ( .LO ( optlc_net_1145 ) , + .HI ( SYNOPSYS_UNCONNECTED_1147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1156 ( .LO ( optlc_net_1146 ) , + .HI ( SYNOPSYS_UNCONNECTED_1148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1157 ( .LO ( optlc_net_1147 ) , + .HI ( SYNOPSYS_UNCONNECTED_1149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1158 ( .LO ( optlc_net_1148 ) , + .HI ( SYNOPSYS_UNCONNECTED_1150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1159 ( .LO ( optlc_net_1149 ) , + .HI ( SYNOPSYS_UNCONNECTED_1151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1160 ( .LO ( optlc_net_1150 ) , + .HI ( SYNOPSYS_UNCONNECTED_1152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1161 ( .LO ( optlc_net_1151 ) , + .HI ( SYNOPSYS_UNCONNECTED_1153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1162 ( .LO ( optlc_net_1152 ) , + .HI ( SYNOPSYS_UNCONNECTED_1154 ) ) ; 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SYNOPSYS_UNCONNECTED_1164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1173 ( .LO ( optlc_net_1163 ) , + .HI ( SYNOPSYS_UNCONNECTED_1165 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1174 ( .LO ( optlc_net_1164 ) , + .HI ( SYNOPSYS_UNCONNECTED_1166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1175 ( .LO ( optlc_net_1165 ) , + .HI ( SYNOPSYS_UNCONNECTED_1167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1176 ( .LO ( optlc_net_1166 ) , + .HI ( SYNOPSYS_UNCONNECTED_1168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1177 ( .LO ( optlc_net_1167 ) , + .HI ( SYNOPSYS_UNCONNECTED_1169 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1178 ( .LO ( optlc_net_1168 ) , + .HI ( SYNOPSYS_UNCONNECTED_1170 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1179 ( .LO ( optlc_net_1169 ) , + .HI ( SYNOPSYS_UNCONNECTED_1171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1180 ( .LO ( optlc_net_1170 ) , + .HI ( SYNOPSYS_UNCONNECTED_1172 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1181 ( .LO ( optlc_net_1171 ) , + .HI ( SYNOPSYS_UNCONNECTED_1173 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1182 ( .LO ( optlc_net_1172 ) , + .HI ( SYNOPSYS_UNCONNECTED_1174 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1183 ( .LO ( optlc_net_1173 ) , + .HI ( SYNOPSYS_UNCONNECTED_1175 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1184 ( .LO ( optlc_net_1174 ) , + .HI ( SYNOPSYS_UNCONNECTED_1176 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1185 ( .LO ( optlc_net_1175 ) , + .HI ( SYNOPSYS_UNCONNECTED_1177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1186 ( .LO ( optlc_net_1176 ) , + .HI ( SYNOPSYS_UNCONNECTED_1178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1187 ( .LO ( optlc_net_1177 ) , + .HI ( SYNOPSYS_UNCONNECTED_1179 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1188 ( .LO ( optlc_net_1178 ) , + .HI ( SYNOPSYS_UNCONNECTED_1180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1189 ( .LO ( optlc_net_1179 ) , + .HI ( SYNOPSYS_UNCONNECTED_1181 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1190 ( .LO ( optlc_net_1180 ) , + .HI ( SYNOPSYS_UNCONNECTED_1182 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1191 ( .LO ( optlc_net_1181 ) , + .HI ( SYNOPSYS_UNCONNECTED_1183 ) ) ; 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SYNOPSYS_UNCONNECTED_1193 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1202 ( .LO ( optlc_net_1192 ) , + .HI ( SYNOPSYS_UNCONNECTED_1194 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1203 ( .LO ( optlc_net_1193 ) , + .HI ( SYNOPSYS_UNCONNECTED_1195 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1204 ( .LO ( optlc_net_1194 ) , + .HI ( SYNOPSYS_UNCONNECTED_1196 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1205 ( .LO ( optlc_net_1195 ) , + .HI ( SYNOPSYS_UNCONNECTED_1197 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1207 ( .LO ( optlc_net_1196 ) , + .HI ( SYNOPSYS_UNCONNECTED_1198 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1208 ( .LO ( optlc_net_1197 ) , + .HI ( SYNOPSYS_UNCONNECTED_1199 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1209 ( .LO ( optlc_net_1198 ) , + .HI ( SYNOPSYS_UNCONNECTED_1200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1210 ( .LO ( optlc_net_1199 ) , + .HI ( SYNOPSYS_UNCONNECTED_1201 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1211 ( .LO ( optlc_net_1200 ) , + .HI ( SYNOPSYS_UNCONNECTED_1202 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1212 ( .LO ( optlc_net_1201 ) , + .HI ( SYNOPSYS_UNCONNECTED_1203 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1213 ( .LO ( optlc_net_1202 ) , + .HI ( SYNOPSYS_UNCONNECTED_1204 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1214 ( .LO ( optlc_net_1203 ) , + .HI ( SYNOPSYS_UNCONNECTED_1205 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1215 ( .LO ( optlc_net_1204 ) , + .HI ( SYNOPSYS_UNCONNECTED_1206 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1216 ( .LO ( optlc_net_1205 ) , + .HI ( SYNOPSYS_UNCONNECTED_1207 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1217 ( .LO ( optlc_net_1206 ) , + .HI ( SYNOPSYS_UNCONNECTED_1208 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1218 ( .LO ( optlc_net_1207 ) , + .HI ( SYNOPSYS_UNCONNECTED_1209 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1219 ( .LO ( optlc_net_1208 ) , + .HI ( SYNOPSYS_UNCONNECTED_1210 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1220 ( .LO ( optlc_net_1209 ) , + .HI ( SYNOPSYS_UNCONNECTED_1211 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1221 ( .LO ( optlc_net_1210 ) , + .HI ( SYNOPSYS_UNCONNECTED_1212 ) ) ; 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SYNOPSYS_UNCONNECTED_1222 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1232 ( .LO ( optlc_net_1221 ) , + .HI ( SYNOPSYS_UNCONNECTED_1223 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1233 ( .LO ( optlc_net_1222 ) , + .HI ( SYNOPSYS_UNCONNECTED_1224 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1234 ( .LO ( optlc_net_1223 ) , + .HI ( SYNOPSYS_UNCONNECTED_1225 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1235 ( .LO ( optlc_net_1224 ) , + .HI ( SYNOPSYS_UNCONNECTED_1226 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1236 ( .LO ( optlc_net_1225 ) , + .HI ( SYNOPSYS_UNCONNECTED_1227 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1237 ( .LO ( optlc_net_1226 ) , + .HI ( SYNOPSYS_UNCONNECTED_1228 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1238 ( .LO ( optlc_net_1227 ) , + .HI ( SYNOPSYS_UNCONNECTED_1229 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1239 ( .LO ( optlc_net_1228 ) , + .HI ( SYNOPSYS_UNCONNECTED_1230 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1241 ( .LO ( optlc_net_1229 ) , + .HI ( SYNOPSYS_UNCONNECTED_1231 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1243 ( .LO ( optlc_net_1230 ) , + .HI ( SYNOPSYS_UNCONNECTED_1232 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1244 ( .LO ( optlc_net_1231 ) , + .HI ( SYNOPSYS_UNCONNECTED_1233 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1245 ( .LO ( optlc_net_1232 ) , + .HI ( SYNOPSYS_UNCONNECTED_1234 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1246 ( .LO ( optlc_net_1233 ) , + .HI ( SYNOPSYS_UNCONNECTED_1235 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1247 ( .LO ( optlc_net_1234 ) , + .HI ( SYNOPSYS_UNCONNECTED_1236 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1248 ( .LO ( optlc_net_1235 ) , + .HI ( SYNOPSYS_UNCONNECTED_1237 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1250 ( .LO ( optlc_net_1236 ) , + .HI ( SYNOPSYS_UNCONNECTED_1238 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1252 ( .LO ( optlc_net_1237 ) , + .HI ( SYNOPSYS_UNCONNECTED_1239 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1253 ( .LO ( optlc_net_1238 ) , + .HI ( SYNOPSYS_UNCONNECTED_1240 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1254 ( .LO ( optlc_net_1239 ) , + .HI ( SYNOPSYS_UNCONNECTED_1241 ) ) ; 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SYNOPSYS_UNCONNECTED_1251 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1267 ( .LO ( optlc_net_1250 ) , + .HI ( SYNOPSYS_UNCONNECTED_1252 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1268 ( .LO ( optlc_net_1251 ) , + .HI ( SYNOPSYS_UNCONNECTED_1253 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1269 ( .LO ( optlc_net_1252 ) , + .HI ( SYNOPSYS_UNCONNECTED_1254 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1270 ( .LO ( optlc_net_1253 ) , + .HI ( SYNOPSYS_UNCONNECTED_1255 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1271 ( .LO ( optlc_net_1254 ) , + .HI ( SYNOPSYS_UNCONNECTED_1256 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1272 ( .LO ( optlc_net_1255 ) , + .HI ( SYNOPSYS_UNCONNECTED_1257 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1273 ( .LO ( optlc_net_1256 ) , + .HI ( SYNOPSYS_UNCONNECTED_1258 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1274 ( .LO ( optlc_net_1257 ) , + .HI ( SYNOPSYS_UNCONNECTED_1259 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1276 ( .LO ( optlc_net_1258 ) , + .HI ( SYNOPSYS_UNCONNECTED_1260 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1277 ( .LO ( optlc_net_1259 ) , + .HI ( SYNOPSYS_UNCONNECTED_1261 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1278 ( .LO ( optlc_net_1260 ) , + .HI ( SYNOPSYS_UNCONNECTED_1262 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1280 ( .LO ( optlc_net_1261 ) , + .HI ( SYNOPSYS_UNCONNECTED_1263 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1281 ( .LO ( optlc_net_1262 ) , + .HI ( SYNOPSYS_UNCONNECTED_1264 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1282 ( .LO ( optlc_net_1263 ) , + .HI ( SYNOPSYS_UNCONNECTED_1265 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1283 ( .LO ( optlc_net_1264 ) , + .HI ( SYNOPSYS_UNCONNECTED_1266 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1284 ( .LO ( optlc_net_1265 ) , + .HI ( SYNOPSYS_UNCONNECTED_1267 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1285 ( .LO ( optlc_net_1266 ) , + .HI ( SYNOPSYS_UNCONNECTED_1268 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1286 ( .LO ( optlc_net_1267 ) , + .HI ( SYNOPSYS_UNCONNECTED_1269 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1287 ( .LO ( optlc_net_1268 ) , + .HI ( SYNOPSYS_UNCONNECTED_1270 ) ) ; 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SYNOPSYS_UNCONNECTED_1280 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1298 ( .LO ( optlc_net_1279 ) , + .HI ( SYNOPSYS_UNCONNECTED_1281 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1299 ( .LO ( optlc_net_1280 ) , + .HI ( SYNOPSYS_UNCONNECTED_1282 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1300 ( .LO ( optlc_net_1281 ) , + .HI ( SYNOPSYS_UNCONNECTED_1283 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1301 ( .LO ( optlc_net_1282 ) , + .HI ( SYNOPSYS_UNCONNECTED_1284 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1302 ( .LO ( optlc_net_1283 ) , + .HI ( SYNOPSYS_UNCONNECTED_1285 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1303 ( .LO ( optlc_net_1284 ) , + .HI ( SYNOPSYS_UNCONNECTED_1286 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1304 ( .LO ( optlc_net_1285 ) , + .HI ( SYNOPSYS_UNCONNECTED_1287 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1305 ( .LO ( optlc_net_1286 ) , + .HI ( SYNOPSYS_UNCONNECTED_1288 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1306 ( .LO ( optlc_net_1287 ) , + .HI ( SYNOPSYS_UNCONNECTED_1289 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1307 ( .LO ( optlc_net_1288 ) , + .HI ( SYNOPSYS_UNCONNECTED_1290 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1308 ( .LO ( optlc_net_1289 ) , + .HI ( SYNOPSYS_UNCONNECTED_1291 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1309 ( .LO ( optlc_net_1290 ) , + .HI ( SYNOPSYS_UNCONNECTED_1292 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1310 ( .LO ( optlc_net_1291 ) , + .HI ( SYNOPSYS_UNCONNECTED_1293 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1311 ( .LO ( optlc_net_1292 ) , + .HI ( SYNOPSYS_UNCONNECTED_1294 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1312 ( .LO ( optlc_net_1293 ) , + .HI ( SYNOPSYS_UNCONNECTED_1295 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1313 ( .LO ( optlc_net_1294 ) , + .HI ( SYNOPSYS_UNCONNECTED_1296 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1314 ( .LO ( optlc_net_1295 ) , + .HI ( SYNOPSYS_UNCONNECTED_1297 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1315 ( .LO ( optlc_net_1296 ) , + .HI ( SYNOPSYS_UNCONNECTED_1298 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1316 ( .LO ( optlc_net_1297 ) , + .HI ( SYNOPSYS_UNCONNECTED_1299 ) ) ; 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SYNOPSYS_UNCONNECTED_1309 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1328 ( .LO ( optlc_net_1308 ) , + .HI ( SYNOPSYS_UNCONNECTED_1310 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1329 ( .LO ( optlc_net_1309 ) , + .HI ( SYNOPSYS_UNCONNECTED_1311 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1330 ( .LO ( optlc_net_1310 ) , + .HI ( SYNOPSYS_UNCONNECTED_1312 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1331 ( .LO ( optlc_net_1311 ) , + .HI ( SYNOPSYS_UNCONNECTED_1313 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1332 ( .LO ( optlc_net_1312 ) , + .HI ( SYNOPSYS_UNCONNECTED_1314 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1333 ( .LO ( optlc_net_1313 ) , + .HI ( SYNOPSYS_UNCONNECTED_1315 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1334 ( .LO ( optlc_net_1314 ) , + .HI ( SYNOPSYS_UNCONNECTED_1316 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1335 ( .LO ( optlc_net_1315 ) , + .HI ( SYNOPSYS_UNCONNECTED_1317 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1336 ( .LO ( optlc_net_1316 ) , + .HI ( SYNOPSYS_UNCONNECTED_1318 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1337 ( .LO ( optlc_net_1317 ) , + .HI ( SYNOPSYS_UNCONNECTED_1319 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1338 ( .LO ( optlc_net_1318 ) , + .HI ( SYNOPSYS_UNCONNECTED_1320 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1339 ( .LO ( optlc_net_1319 ) , + .HI ( SYNOPSYS_UNCONNECTED_1321 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1340 ( .LO ( optlc_net_1320 ) , + .HI ( SYNOPSYS_UNCONNECTED_1322 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1342 ( .LO ( optlc_net_1321 ) , + .HI ( SYNOPSYS_UNCONNECTED_1323 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1343 ( .LO ( optlc_net_1322 ) , + .HI ( SYNOPSYS_UNCONNECTED_1324 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1344 ( .LO ( optlc_net_1323 ) , + .HI ( SYNOPSYS_UNCONNECTED_1325 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1345 ( .LO ( optlc_net_1324 ) , + .HI ( SYNOPSYS_UNCONNECTED_1326 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1346 ( .LO ( optlc_net_1325 ) , + .HI ( SYNOPSYS_UNCONNECTED_1327 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1347 ( .LO ( optlc_net_1326 ) , + .HI ( SYNOPSYS_UNCONNECTED_1328 ) ) ; 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SYNOPSYS_UNCONNECTED_1338 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1359 ( .LO ( optlc_net_1337 ) , + .HI ( SYNOPSYS_UNCONNECTED_1339 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1360 ( .LO ( optlc_net_1338 ) , + .HI ( SYNOPSYS_UNCONNECTED_1340 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1361 ( .LO ( optlc_net_1339 ) , + .HI ( SYNOPSYS_UNCONNECTED_1341 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1362 ( .LO ( optlc_net_1340 ) , + .HI ( SYNOPSYS_UNCONNECTED_1342 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1363 ( .LO ( optlc_net_1341 ) , + .HI ( SYNOPSYS_UNCONNECTED_1343 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1364 ( .LO ( optlc_net_1342 ) , + .HI ( SYNOPSYS_UNCONNECTED_1344 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1365 ( .LO ( optlc_net_1343 ) , + .HI ( SYNOPSYS_UNCONNECTED_1345 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1366 ( .LO ( optlc_net_1344 ) , + .HI ( SYNOPSYS_UNCONNECTED_1346 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1367 ( .LO ( optlc_net_1345 ) , + .HI ( SYNOPSYS_UNCONNECTED_1347 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1368 ( .LO ( optlc_net_1346 ) , + .HI ( SYNOPSYS_UNCONNECTED_1348 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1369 ( .LO ( optlc_net_1347 ) , + .HI ( SYNOPSYS_UNCONNECTED_1349 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1370 ( .LO ( optlc_net_1348 ) , + .HI ( SYNOPSYS_UNCONNECTED_1350 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1371 ( .LO ( optlc_net_1349 ) , + .HI ( SYNOPSYS_UNCONNECTED_1351 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1372 ( .LO ( optlc_net_1350 ) , + .HI ( SYNOPSYS_UNCONNECTED_1352 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1373 ( .LO ( optlc_net_1351 ) , + .HI ( SYNOPSYS_UNCONNECTED_1353 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1374 ( .LO ( optlc_net_1352 ) , + .HI ( SYNOPSYS_UNCONNECTED_1354 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1375 ( .LO ( optlc_net_1353 ) , + .HI ( SYNOPSYS_UNCONNECTED_1355 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1376 ( .LO ( optlc_net_1354 ) , + .HI ( SYNOPSYS_UNCONNECTED_1356 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1377 ( .LO ( optlc_net_1355 ) , + .HI ( SYNOPSYS_UNCONNECTED_1357 ) ) ; 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SYNOPSYS_UNCONNECTED_1367 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1389 ( .LO ( optlc_net_1366 ) , + .HI ( SYNOPSYS_UNCONNECTED_1368 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1391 ( .LO ( optlc_net_1367 ) , + .HI ( SYNOPSYS_UNCONNECTED_1369 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1393 ( .LO ( optlc_net_1368 ) , + .HI ( SYNOPSYS_UNCONNECTED_1370 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1394 ( .LO ( optlc_net_1369 ) , + .HI ( SYNOPSYS_UNCONNECTED_1371 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1395 ( .LO ( optlc_net_1370 ) , + .HI ( SYNOPSYS_UNCONNECTED_1372 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1396 ( .LO ( optlc_net_1371 ) , + .HI ( SYNOPSYS_UNCONNECTED_1373 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1397 ( .LO ( optlc_net_1372 ) , + .HI ( SYNOPSYS_UNCONNECTED_1374 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1398 ( .LO ( optlc_net_1373 ) , + .HI ( SYNOPSYS_UNCONNECTED_1375 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1399 ( .LO ( optlc_net_1374 ) , + .HI ( SYNOPSYS_UNCONNECTED_1376 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1400 ( .LO ( optlc_net_1375 ) , + .HI ( SYNOPSYS_UNCONNECTED_1377 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1401 ( .LO ( optlc_net_1376 ) , + .HI ( SYNOPSYS_UNCONNECTED_1378 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1402 ( .LO ( optlc_net_1377 ) , + .HI ( SYNOPSYS_UNCONNECTED_1379 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1404 ( .LO ( optlc_net_1378 ) , + .HI ( SYNOPSYS_UNCONNECTED_1380 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1405 ( .LO ( optlc_net_1379 ) , + .HI ( SYNOPSYS_UNCONNECTED_1381 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1406 ( .LO ( optlc_net_1380 ) , + .HI ( SYNOPSYS_UNCONNECTED_1382 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1407 ( .LO ( optlc_net_1381 ) , + .HI ( SYNOPSYS_UNCONNECTED_1383 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1408 ( .LO ( optlc_net_1382 ) , + .HI ( SYNOPSYS_UNCONNECTED_1384 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1409 ( .LO ( optlc_net_1383 ) , + .HI ( SYNOPSYS_UNCONNECTED_1385 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1411 ( .LO ( optlc_net_1384 ) , + .HI ( SYNOPSYS_UNCONNECTED_1386 ) ) ; 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SYNOPSYS_UNCONNECTED_1396 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1425 ( .LO ( optlc_net_1395 ) , + .HI ( SYNOPSYS_UNCONNECTED_1397 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1426 ( .LO ( optlc_net_1396 ) , + .HI ( SYNOPSYS_UNCONNECTED_1398 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1427 ( .LO ( optlc_net_1397 ) , + .HI ( SYNOPSYS_UNCONNECTED_1399 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1428 ( .LO ( optlc_net_1398 ) , + .HI ( SYNOPSYS_UNCONNECTED_1400 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1429 ( .LO ( optlc_net_1399 ) , + .HI ( SYNOPSYS_UNCONNECTED_1401 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1430 ( .LO ( optlc_net_1400 ) , + .HI ( SYNOPSYS_UNCONNECTED_1402 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1431 ( .LO ( optlc_net_1401 ) , + .HI ( SYNOPSYS_UNCONNECTED_1403 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1433 ( .LO ( optlc_net_1402 ) , + .HI ( SYNOPSYS_UNCONNECTED_1404 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1434 ( .LO ( optlc_net_1403 ) , + .HI ( SYNOPSYS_UNCONNECTED_1405 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1436 ( .LO ( optlc_net_1404 ) , + .HI ( SYNOPSYS_UNCONNECTED_1406 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1437 ( .LO ( optlc_net_1405 ) , + .HI ( SYNOPSYS_UNCONNECTED_1407 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1438 ( .LO ( optlc_net_1406 ) , + .HI ( SYNOPSYS_UNCONNECTED_1408 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1439 ( .LO ( optlc_net_1407 ) , + .HI ( SYNOPSYS_UNCONNECTED_1409 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1440 ( .LO ( optlc_net_1408 ) , + .HI ( SYNOPSYS_UNCONNECTED_1410 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1442 ( .LO ( optlc_net_1409 ) , + .HI ( SYNOPSYS_UNCONNECTED_1411 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1443 ( .LO ( optlc_net_1410 ) , + .HI ( SYNOPSYS_UNCONNECTED_1412 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1444 ( .LO ( optlc_net_1411 ) , + .HI ( SYNOPSYS_UNCONNECTED_1413 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1446 ( .LO ( optlc_net_1412 ) , + .HI ( SYNOPSYS_UNCONNECTED_1414 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1447 ( .LO ( optlc_net_1413 ) , + .HI ( SYNOPSYS_UNCONNECTED_1415 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1448 ( .LO ( optlc_net_1414 ) , + .HI ( SYNOPSYS_UNCONNECTED_1416 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1450 ( .LO ( optlc_net_1415 ) , + .HI ( SYNOPSYS_UNCONNECTED_1417 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1452 ( .LO ( optlc_net_1416 ) , + .HI ( SYNOPSYS_UNCONNECTED_1418 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1453 ( .LO ( optlc_net_1417 ) , + .HI ( SYNOPSYS_UNCONNECTED_1419 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1454 ( .LO ( optlc_net_1418 ) , + .HI ( SYNOPSYS_UNCONNECTED_1420 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1455 ( .LO ( optlc_net_1419 ) , + .HI ( SYNOPSYS_UNCONNECTED_1421 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1457 ( .LO ( optlc_net_1420 ) , + .HI ( SYNOPSYS_UNCONNECTED_1422 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1459 ( .LO ( optlc_net_1421 ) , + .HI ( SYNOPSYS_UNCONNECTED_1423 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1460 ( .LO ( optlc_net_1422 ) , + .HI ( SYNOPSYS_UNCONNECTED_1424 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1462 ( .LO ( optlc_net_1423 ) , + .HI ( SYNOPSYS_UNCONNECTED_1425 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1463 ( .LO ( optlc_net_1424 ) , + .HI ( SYNOPSYS_UNCONNECTED_1426 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1464 ( .LO ( optlc_net_1425 ) , + .HI ( SYNOPSYS_UNCONNECTED_1427 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1465 ( .LO ( optlc_net_1426 ) , + .HI ( SYNOPSYS_UNCONNECTED_1428 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1467 ( .LO ( optlc_net_1427 ) , + .HI ( SYNOPSYS_UNCONNECTED_1429 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1468 ( .LO ( optlc_net_1428 ) , + .HI ( SYNOPSYS_UNCONNECTED_1430 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1469 ( .LO ( optlc_net_1429 ) , + .HI ( SYNOPSYS_UNCONNECTED_1431 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1471 ( .LO ( optlc_net_1430 ) , + .HI ( SYNOPSYS_UNCONNECTED_1432 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1472 ( .LO ( optlc_net_1431 ) , + .HI ( SYNOPSYS_UNCONNECTED_1433 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1474 ( .LO ( optlc_net_1432 ) , + .HI ( SYNOPSYS_UNCONNECTED_1434 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1475 ( .LO ( optlc_net_1433 ) , + .HI ( SYNOPSYS_UNCONNECTED_1435 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1477 ( .LO ( optlc_net_1434 ) , + .HI ( SYNOPSYS_UNCONNECTED_1436 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1478 ( .LO ( optlc_net_1435 ) , + .HI ( SYNOPSYS_UNCONNECTED_1437 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1479 ( .LO ( optlc_net_1436 ) , + .HI ( SYNOPSYS_UNCONNECTED_1438 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1480 ( .LO ( optlc_net_1437 ) , + .HI ( SYNOPSYS_UNCONNECTED_1439 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1482 ( .LO ( optlc_net_1438 ) , + .HI ( SYNOPSYS_UNCONNECTED_1440 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1483 ( .LO ( optlc_net_1439 ) , + .HI ( SYNOPSYS_UNCONNECTED_1441 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1440 ) , + .HI ( SYNOPSYS_UNCONNECTED_1442 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1486 ( .LO ( optlc_net_1441 ) , + .HI ( SYNOPSYS_UNCONNECTED_1443 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1488 ( .LO ( optlc_net_1442 ) , + .HI ( SYNOPSYS_UNCONNECTED_1444 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1489 ( .LO ( optlc_net_1443 ) , + .HI ( SYNOPSYS_UNCONNECTED_1445 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1490 ( .LO ( optlc_net_1444 ) , + .HI ( SYNOPSYS_UNCONNECTED_1446 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1491 ( .LO ( optlc_net_1445 ) , + .HI ( SYNOPSYS_UNCONNECTED_1447 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1492 ( .LO ( optlc_net_1446 ) , + .HI ( SYNOPSYS_UNCONNECTED_1448 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1493 ( .LO ( optlc_net_1447 ) , + .HI ( SYNOPSYS_UNCONNECTED_1449 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1494 ( .LO ( optlc_net_1448 ) , + .HI ( SYNOPSYS_UNCONNECTED_1450 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1496 ( .LO ( optlc_net_1449 ) , + .HI ( SYNOPSYS_UNCONNECTED_1451 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1497 ( .LO ( optlc_net_1450 ) , + .HI ( SYNOPSYS_UNCONNECTED_1452 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1499 ( .LO ( optlc_net_1451 ) , + .HI ( SYNOPSYS_UNCONNECTED_1453 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1501 ( .LO ( optlc_net_1452 ) , + .HI ( SYNOPSYS_UNCONNECTED_1454 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1502 ( .LO ( optlc_net_1453 ) , + .HI ( SYNOPSYS_UNCONNECTED_1455 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1503 ( .LO ( optlc_net_1454 ) , + .HI ( SYNOPSYS_UNCONNECTED_1456 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1505 ( .LO ( optlc_net_1455 ) , + .HI ( SYNOPSYS_UNCONNECTED_1457 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1506 ( .LO ( optlc_net_1456 ) , + .HI ( SYNOPSYS_UNCONNECTED_1458 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1507 ( .LO ( optlc_net_1457 ) , + .HI ( SYNOPSYS_UNCONNECTED_1459 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1508 ( .LO ( optlc_net_1458 ) , + .HI ( SYNOPSYS_UNCONNECTED_1460 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1509 ( .LO ( optlc_net_1459 ) , + .HI ( SYNOPSYS_UNCONNECTED_1461 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1510 ( .LO ( optlc_net_1460 ) , + .HI ( SYNOPSYS_UNCONNECTED_1462 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1512 ( .LO ( optlc_net_1461 ) , + .HI ( SYNOPSYS_UNCONNECTED_1463 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1513 ( .LO ( optlc_net_1462 ) , + .HI ( SYNOPSYS_UNCONNECTED_1464 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1514 ( .LO ( optlc_net_1463 ) , + .HI ( SYNOPSYS_UNCONNECTED_1465 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1515 ( .LO ( optlc_net_1464 ) , + .HI ( SYNOPSYS_UNCONNECTED_1466 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1516 ( .LO ( optlc_net_1465 ) , + .HI ( SYNOPSYS_UNCONNECTED_1467 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1517 ( .LO ( optlc_net_1466 ) , + .HI ( SYNOPSYS_UNCONNECTED_1468 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1518 ( .LO ( optlc_net_1467 ) , + .HI ( SYNOPSYS_UNCONNECTED_1469 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1519 ( .LO ( optlc_net_1468 ) , + .HI ( SYNOPSYS_UNCONNECTED_1470 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1521 ( .LO ( optlc_net_1469 ) , + .HI ( SYNOPSYS_UNCONNECTED_1471 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1523 ( .LO ( optlc_net_1470 ) , + .HI ( SYNOPSYS_UNCONNECTED_1472 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1524 ( .LO ( optlc_net_1471 ) , + .HI ( SYNOPSYS_UNCONNECTED_1473 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1525 ( .LO ( optlc_net_1472 ) , + .HI ( SYNOPSYS_UNCONNECTED_1474 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1527 ( .LO ( optlc_net_1473 ) , + .HI ( SYNOPSYS_UNCONNECTED_1475 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1528 ( .LO ( optlc_net_1474 ) , + .HI ( SYNOPSYS_UNCONNECTED_1476 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1529 ( .LO ( optlc_net_1475 ) , + .HI ( SYNOPSYS_UNCONNECTED_1477 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1530 ( .LO ( optlc_net_1476 ) , + .HI ( SYNOPSYS_UNCONNECTED_1478 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1531 ( .LO ( optlc_net_1477 ) , + .HI ( SYNOPSYS_UNCONNECTED_1479 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1532 ( .LO ( optlc_net_1478 ) , + .HI ( SYNOPSYS_UNCONNECTED_1480 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1533 ( .LO ( optlc_net_1479 ) , + .HI ( SYNOPSYS_UNCONNECTED_1481 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1534 ( .LO ( optlc_net_1480 ) , + .HI ( SYNOPSYS_UNCONNECTED_1482 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1536 ( .LO ( optlc_net_1481 ) , + .HI ( SYNOPSYS_UNCONNECTED_1483 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1538 ( .LO ( optlc_net_1482 ) , + .HI ( SYNOPSYS_UNCONNECTED_1484 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1539 ( .LO ( optlc_net_1483 ) , + .HI ( SYNOPSYS_UNCONNECTED_1485 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1540 ( .LO ( optlc_net_1484 ) , + .HI ( SYNOPSYS_UNCONNECTED_1486 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1542 ( .LO ( optlc_net_1485 ) , + .HI ( SYNOPSYS_UNCONNECTED_1487 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1543 ( .LO ( optlc_net_1486 ) , + .HI ( SYNOPSYS_UNCONNECTED_1488 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1544 ( .LO ( optlc_net_1487 ) , + .HI ( SYNOPSYS_UNCONNECTED_1489 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1545 ( .LO ( optlc_net_1488 ) , + .HI ( SYNOPSYS_UNCONNECTED_1490 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1547 ( .LO ( optlc_net_1489 ) , + .HI ( SYNOPSYS_UNCONNECTED_1491 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1549 ( .LO ( optlc_net_1490 ) , + .HI ( SYNOPSYS_UNCONNECTED_1492 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1551 ( .LO ( optlc_net_1491 ) , + .HI ( SYNOPSYS_UNCONNECTED_1493 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1552 ( .LO ( optlc_net_1492 ) , + .HI ( SYNOPSYS_UNCONNECTED_1494 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1553 ( .LO ( optlc_net_1493 ) , + .HI ( SYNOPSYS_UNCONNECTED_1495 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1555 ( .LO ( optlc_net_1494 ) , + .HI ( SYNOPSYS_UNCONNECTED_1496 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1557 ( .LO ( optlc_net_1495 ) , + .HI ( SYNOPSYS_UNCONNECTED_1497 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1559 ( .LO ( optlc_net_1496 ) , + .HI ( SYNOPSYS_UNCONNECTED_1498 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1560 ( .LO ( optlc_net_1497 ) , + .HI ( SYNOPSYS_UNCONNECTED_1499 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1561 ( .LO ( optlc_net_1498 ) , + .HI ( SYNOPSYS_UNCONNECTED_1500 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1562 ( .LO ( optlc_net_1499 ) , + .HI ( SYNOPSYS_UNCONNECTED_1501 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1563 ( .LO ( optlc_net_1500 ) , + .HI ( SYNOPSYS_UNCONNECTED_1502 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1564 ( .LO ( optlc_net_1501 ) , + .HI ( SYNOPSYS_UNCONNECTED_1503 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1566 ( .LO ( optlc_net_1502 ) , + .HI ( SYNOPSYS_UNCONNECTED_1504 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1567 ( .LO ( optlc_net_1503 ) , + .HI ( SYNOPSYS_UNCONNECTED_1505 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1568 ( .LO ( optlc_net_1504 ) , + .HI ( SYNOPSYS_UNCONNECTED_1506 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1570 ( .LO ( optlc_net_1505 ) , + .HI ( SYNOPSYS_UNCONNECTED_1507 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1571 ( .LO ( optlc_net_1506 ) , + .HI ( SYNOPSYS_UNCONNECTED_1508 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1572 ( .LO ( optlc_net_1507 ) , + .HI ( SYNOPSYS_UNCONNECTED_1509 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1573 ( .LO ( optlc_net_1508 ) , + .HI ( SYNOPSYS_UNCONNECTED_1510 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1575 ( .LO ( optlc_net_1509 ) , + .HI ( SYNOPSYS_UNCONNECTED_1511 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1577 ( .LO ( optlc_net_1510 ) , + .HI ( SYNOPSYS_UNCONNECTED_1512 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1578 ( .LO ( optlc_net_1511 ) , + .HI ( SYNOPSYS_UNCONNECTED_1513 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1580 ( .LO ( optlc_net_1512 ) , + .HI ( SYNOPSYS_UNCONNECTED_1514 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1582 ( .LO ( optlc_net_1513 ) , + .HI ( SYNOPSYS_UNCONNECTED_1515 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1583 ( .LO ( optlc_net_1514 ) , + .HI ( SYNOPSYS_UNCONNECTED_1516 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1585 ( .LO ( optlc_net_1515 ) , + .HI ( SYNOPSYS_UNCONNECTED_1517 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1586 ( .LO ( optlc_net_1516 ) , + .HI ( SYNOPSYS_UNCONNECTED_1518 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1588 ( .LO ( optlc_net_1517 ) , + .HI ( SYNOPSYS_UNCONNECTED_1519 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1590 ( .LO ( optlc_net_1518 ) , + .HI ( SYNOPSYS_UNCONNECTED_1520 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1591 ( .LO ( optlc_net_1519 ) , + .HI ( SYNOPSYS_UNCONNECTED_1521 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1592 ( .LO ( optlc_net_1520 ) , + .HI ( SYNOPSYS_UNCONNECTED_1522 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1594 ( .LO ( optlc_net_1521 ) , + .HI ( SYNOPSYS_UNCONNECTED_1523 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1595 ( .LO ( optlc_net_1522 ) , + .HI ( SYNOPSYS_UNCONNECTED_1524 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1597 ( .LO ( optlc_net_1523 ) , + .HI ( SYNOPSYS_UNCONNECTED_1525 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1598 ( .LO ( optlc_net_1524 ) , + .HI ( SYNOPSYS_UNCONNECTED_1526 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1599 ( .LO ( optlc_net_1525 ) , + .HI ( SYNOPSYS_UNCONNECTED_1527 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1600 ( .LO ( optlc_net_1526 ) , + .HI ( SYNOPSYS_UNCONNECTED_1528 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1602 ( .LO ( optlc_net_1527 ) , + .HI ( SYNOPSYS_UNCONNECTED_1529 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1603 ( .LO ( optlc_net_1528 ) , + .HI ( SYNOPSYS_UNCONNECTED_1530 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1605 ( .LO ( optlc_net_1529 ) , + .HI ( SYNOPSYS_UNCONNECTED_1531 ) ) ; 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SYNOPSYS_UNCONNECTED_1541 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1621 ( .LO ( optlc_net_1540 ) , + .HI ( SYNOPSYS_UNCONNECTED_1542 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1623 ( .LO ( optlc_net_1541 ) , + .HI ( SYNOPSYS_UNCONNECTED_1543 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1625 ( .LO ( optlc_net_1542 ) , + .HI ( SYNOPSYS_UNCONNECTED_1544 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1626 ( .LO ( optlc_net_1543 ) , + .HI ( SYNOPSYS_UNCONNECTED_1545 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1627 ( .LO ( optlc_net_1544 ) , + .HI ( SYNOPSYS_UNCONNECTED_1546 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1628 ( .LO ( optlc_net_1545 ) , + .HI ( SYNOPSYS_UNCONNECTED_1547 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1629 ( .LO ( optlc_net_1546 ) , + .HI ( SYNOPSYS_UNCONNECTED_1548 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1630 ( .LO ( optlc_net_1547 ) , + .HI ( SYNOPSYS_UNCONNECTED_1549 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1631 ( .LO ( optlc_net_1548 ) , + .HI ( SYNOPSYS_UNCONNECTED_1550 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1633 ( .LO ( optlc_net_1549 ) , + .HI ( SYNOPSYS_UNCONNECTED_1551 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1634 ( .LO ( optlc_net_1550 ) , + .HI ( SYNOPSYS_UNCONNECTED_1552 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1636 ( .LO ( optlc_net_1551 ) , + .HI ( SYNOPSYS_UNCONNECTED_1553 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1637 ( .LO ( optlc_net_1552 ) , + .HI ( SYNOPSYS_UNCONNECTED_1554 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1639 ( .LO ( optlc_net_1553 ) , + .HI ( SYNOPSYS_UNCONNECTED_1555 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1641 ( .LO ( optlc_net_1554 ) , + .HI ( SYNOPSYS_UNCONNECTED_1556 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1642 ( .LO ( optlc_net_1555 ) , + .HI ( SYNOPSYS_UNCONNECTED_1557 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1643 ( .LO ( optlc_net_1556 ) , + .HI ( SYNOPSYS_UNCONNECTED_1558 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1645 ( .LO ( optlc_net_1557 ) , + .HI ( SYNOPSYS_UNCONNECTED_1559 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1646 ( .LO ( optlc_net_1558 ) , + .HI ( SYNOPSYS_UNCONNECTED_1560 ) ) ; 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SYNOPSYS_UNCONNECTED_1570 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1659 ( .LO ( optlc_net_1569 ) , + .HI ( SYNOPSYS_UNCONNECTED_1571 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1661 ( .LO ( optlc_net_1570 ) , + .HI ( SYNOPSYS_UNCONNECTED_1572 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1662 ( .LO ( optlc_net_1571 ) , + .HI ( SYNOPSYS_UNCONNECTED_1573 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1663 ( .LO ( optlc_net_1572 ) , + .HI ( SYNOPSYS_UNCONNECTED_1574 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1665 ( .LO ( optlc_net_1573 ) , + .HI ( SYNOPSYS_UNCONNECTED_1575 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1667 ( .LO ( optlc_net_1574 ) , + .HI ( SYNOPSYS_UNCONNECTED_1576 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1669 ( .LO ( optlc_net_1575 ) , + .HI ( SYNOPSYS_UNCONNECTED_1577 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1671 ( .LO ( optlc_net_1576 ) , + .HI ( SYNOPSYS_UNCONNECTED_1578 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1672 ( .LO ( optlc_net_1577 ) , + .HI ( SYNOPSYS_UNCONNECTED_1579 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1674 ( .LO ( optlc_net_1578 ) , + .HI ( SYNOPSYS_UNCONNECTED_1580 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1675 ( .LO ( optlc_net_1579 ) , + .HI ( SYNOPSYS_UNCONNECTED_1581 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1676 ( .LO ( optlc_net_1580 ) , + .HI ( SYNOPSYS_UNCONNECTED_1582 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1677 ( .LO ( optlc_net_1581 ) , + .HI ( SYNOPSYS_UNCONNECTED_1583 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1679 ( .LO ( optlc_net_1582 ) , + .HI ( SYNOPSYS_UNCONNECTED_1584 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1681 ( .LO ( optlc_net_1583 ) , + .HI ( SYNOPSYS_UNCONNECTED_1585 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1683 ( .LO ( optlc_net_1584 ) , + .HI ( SYNOPSYS_UNCONNECTED_1586 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1685 ( .LO ( optlc_net_1585 ) , + .HI ( SYNOPSYS_UNCONNECTED_1587 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1687 ( .LO ( optlc_net_1586 ) , + .HI ( SYNOPSYS_UNCONNECTED_1588 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1689 ( .LO ( optlc_net_1587 ) , + .HI ( SYNOPSYS_UNCONNECTED_1589 ) ) ; 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SYNOPSYS_UNCONNECTED_1599 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1706 ( .LO ( optlc_net_1598 ) , + .HI ( SYNOPSYS_UNCONNECTED_1600 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1707 ( .LO ( optlc_net_1599 ) , + .HI ( SYNOPSYS_UNCONNECTED_1601 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1708 ( .LO ( optlc_net_1600 ) , + .HI ( SYNOPSYS_UNCONNECTED_1602 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1710 ( .LO ( optlc_net_1601 ) , + .HI ( SYNOPSYS_UNCONNECTED_1603 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1712 ( .LO ( optlc_net_1602 ) , + .HI ( SYNOPSYS_UNCONNECTED_1604 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1713 ( .LO ( optlc_net_1603 ) , + .HI ( SYNOPSYS_UNCONNECTED_1605 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1714 ( .LO ( optlc_net_1604 ) , + .HI ( SYNOPSYS_UNCONNECTED_1606 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1715 ( .LO ( optlc_net_1605 ) , + .HI ( SYNOPSYS_UNCONNECTED_1607 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1716 ( .LO ( optlc_net_1606 ) , + .HI ( SYNOPSYS_UNCONNECTED_1608 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1717 ( .LO ( optlc_net_1607 ) , + .HI ( SYNOPSYS_UNCONNECTED_1609 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1718 ( .LO ( optlc_net_1608 ) , + .HI ( SYNOPSYS_UNCONNECTED_1610 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1719 ( .LO ( optlc_net_1609 ) , + .HI ( SYNOPSYS_UNCONNECTED_1611 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1721 ( .LO ( optlc_net_1610 ) , + .HI ( SYNOPSYS_UNCONNECTED_1612 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1722 ( .LO ( optlc_net_1611 ) , + .HI ( SYNOPSYS_UNCONNECTED_1613 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1723 ( .LO ( optlc_net_1612 ) , + .HI ( SYNOPSYS_UNCONNECTED_1614 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1725 ( .LO ( optlc_net_1613 ) , + .HI ( SYNOPSYS_UNCONNECTED_1615 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1726 ( .LO ( optlc_net_1614 ) , + .HI ( SYNOPSYS_UNCONNECTED_1616 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1728 ( .LO ( optlc_net_1615 ) , + .HI ( SYNOPSYS_UNCONNECTED_1617 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1730 ( .LO ( optlc_net_1616 ) , + .HI ( SYNOPSYS_UNCONNECTED_1618 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1731 ( .LO ( optlc_net_1617 ) , + .HI ( SYNOPSYS_UNCONNECTED_1619 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1732 ( .LO ( optlc_net_1618 ) , + .HI ( SYNOPSYS_UNCONNECTED_1620 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1733 ( .LO ( optlc_net_1619 ) , + .HI ( SYNOPSYS_UNCONNECTED_1621 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1734 ( .LO ( optlc_net_1620 ) , + .HI ( SYNOPSYS_UNCONNECTED_1622 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1735 ( .LO ( optlc_net_1621 ) , + .HI ( SYNOPSYS_UNCONNECTED_1623 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1737 ( .LO ( optlc_net_1622 ) , + .HI ( SYNOPSYS_UNCONNECTED_1624 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1739 ( .LO ( optlc_net_1623 ) , + .HI ( SYNOPSYS_UNCONNECTED_1625 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1741 ( .LO ( optlc_net_1624 ) , + .HI ( SYNOPSYS_UNCONNECTED_1626 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1743 ( .LO ( optlc_net_1625 ) , + .HI ( SYNOPSYS_UNCONNECTED_1627 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1745 ( .LO ( optlc_net_1626 ) , + .HI ( SYNOPSYS_UNCONNECTED_1628 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1746 ( .LO ( optlc_net_1627 ) , + .HI ( SYNOPSYS_UNCONNECTED_1629 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1748 ( .LO ( optlc_net_1628 ) , + .HI ( SYNOPSYS_UNCONNECTED_1630 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1750 ( .LO ( optlc_net_1629 ) , + .HI ( SYNOPSYS_UNCONNECTED_1631 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1751 ( .LO ( optlc_net_1630 ) , + .HI ( SYNOPSYS_UNCONNECTED_1632 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1752 ( .LO ( optlc_net_1631 ) , + .HI ( SYNOPSYS_UNCONNECTED_1633 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1753 ( .LO ( optlc_net_1632 ) , + .HI ( SYNOPSYS_UNCONNECTED_1634 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1755 ( .LO ( optlc_net_1633 ) , + .HI ( SYNOPSYS_UNCONNECTED_1635 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1757 ( .LO ( optlc_net_1634 ) , + .HI ( SYNOPSYS_UNCONNECTED_1636 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1759 ( .LO ( optlc_net_1635 ) , + .HI ( SYNOPSYS_UNCONNECTED_1637 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1760 ( .LO ( optlc_net_1636 ) , + .HI ( SYNOPSYS_UNCONNECTED_1638 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1761 ( .LO ( optlc_net_1637 ) , + .HI ( SYNOPSYS_UNCONNECTED_1639 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1762 ( .LO ( optlc_net_1638 ) , + .HI ( SYNOPSYS_UNCONNECTED_1640 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1763 ( .LO ( optlc_net_1639 ) , + .HI ( SYNOPSYS_UNCONNECTED_1641 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1764 ( .LO ( optlc_net_1640 ) , + .HI ( SYNOPSYS_UNCONNECTED_1642 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1765 ( .LO ( optlc_net_1641 ) , + .HI ( SYNOPSYS_UNCONNECTED_1643 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1766 ( .LO ( optlc_net_1642 ) , + .HI ( SYNOPSYS_UNCONNECTED_1644 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1768 ( .LO ( optlc_net_1643 ) , + .HI ( SYNOPSYS_UNCONNECTED_1645 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1769 ( .LO ( optlc_net_1644 ) , + .HI ( SYNOPSYS_UNCONNECTED_1646 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1771 ( .LO ( optlc_net_1645 ) , + .HI ( SYNOPSYS_UNCONNECTED_1647 ) ) ; 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SYNOPSYS_UNCONNECTED_1657 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1785 ( .LO ( optlc_net_1656 ) , + .HI ( SYNOPSYS_UNCONNECTED_1658 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1787 ( .LO ( optlc_net_1657 ) , + .HI ( SYNOPSYS_UNCONNECTED_1659 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1788 ( .LO ( optlc_net_1658 ) , + .HI ( SYNOPSYS_UNCONNECTED_1660 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1790 ( .LO ( optlc_net_1659 ) , + .HI ( SYNOPSYS_UNCONNECTED_1661 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1791 ( .LO ( optlc_net_1660 ) , + .HI ( SYNOPSYS_UNCONNECTED_1662 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1793 ( .LO ( optlc_net_1661 ) , + .HI ( SYNOPSYS_UNCONNECTED_1663 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1794 ( .LO ( optlc_net_1662 ) , + .HI ( SYNOPSYS_UNCONNECTED_1664 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1796 ( .LO ( optlc_net_1663 ) , + .HI ( SYNOPSYS_UNCONNECTED_1665 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1797 ( .LO ( optlc_net_1664 ) , + .HI ( SYNOPSYS_UNCONNECTED_1666 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1799 ( .LO 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SYNOPSYS_UNCONNECTED_1918 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2131 ( .LO ( optlc_net_1917 ) , + .HI ( SYNOPSYS_UNCONNECTED_1919 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2132 ( .LO ( optlc_net_1918 ) , + .HI ( SYNOPSYS_UNCONNECTED_1920 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2133 ( .LO ( optlc_net_1919 ) , + .HI ( SYNOPSYS_UNCONNECTED_1921 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2134 ( .LO ( optlc_net_1920 ) , + .HI ( SYNOPSYS_UNCONNECTED_1922 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2135 ( .LO ( optlc_net_1921 ) , + .HI ( SYNOPSYS_UNCONNECTED_1923 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2136 ( .LO ( optlc_net_1922 ) , + .HI ( SYNOPSYS_UNCONNECTED_1924 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2137 ( .LO ( optlc_net_1923 ) , + .HI ( SYNOPSYS_UNCONNECTED_1925 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2138 ( .LO ( optlc_net_1924 ) , + .HI ( SYNOPSYS_UNCONNECTED_1926 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2139 ( .LO ( optlc_net_1925 ) , + .HI ( SYNOPSYS_UNCONNECTED_1927 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2140 ( .LO ( optlc_net_1926 ) , + .HI ( SYNOPSYS_UNCONNECTED_1928 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2141 ( .LO ( optlc_net_1927 ) , + .HI ( SYNOPSYS_UNCONNECTED_1929 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2142 ( .LO ( optlc_net_1928 ) , + .HI ( SYNOPSYS_UNCONNECTED_1930 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2143 ( .LO ( optlc_net_1929 ) , + .HI ( SYNOPSYS_UNCONNECTED_1931 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2144 ( .LO ( optlc_net_1930 ) , + .HI ( SYNOPSYS_UNCONNECTED_1932 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2145 ( .LO ( optlc_net_1931 ) , + .HI ( SYNOPSYS_UNCONNECTED_1933 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2146 ( .LO ( optlc_net_1932 ) , + .HI ( SYNOPSYS_UNCONNECTED_1934 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2147 ( .LO ( optlc_net_1933 ) , + .HI ( SYNOPSYS_UNCONNECTED_1935 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2148 ( .LO ( optlc_net_1934 ) , + .HI ( SYNOPSYS_UNCONNECTED_1936 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2149 ( .LO ( optlc_net_1935 ) , + .HI ( SYNOPSYS_UNCONNECTED_1937 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2150 ( .LO ( optlc_net_1936 ) , + .HI ( SYNOPSYS_UNCONNECTED_1938 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2151 ( .LO ( optlc_net_1937 ) , + .HI ( SYNOPSYS_UNCONNECTED_1939 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2152 ( .LO ( optlc_net_1938 ) , + .HI ( SYNOPSYS_UNCONNECTED_1940 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2153 ( .LO ( optlc_net_1939 ) , + .HI ( SYNOPSYS_UNCONNECTED_1941 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2154 ( .LO ( optlc_net_1940 ) , + .HI ( SYNOPSYS_UNCONNECTED_1942 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2155 ( .LO ( optlc_net_1941 ) , + .HI ( SYNOPSYS_UNCONNECTED_1943 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2156 ( .LO ( optlc_net_1942 ) , + .HI ( SYNOPSYS_UNCONNECTED_1944 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2157 ( .LO ( optlc_net_1943 ) , + .HI ( SYNOPSYS_UNCONNECTED_1945 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2158 ( .LO ( optlc_net_1944 ) , + .HI ( SYNOPSYS_UNCONNECTED_1946 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2159 ( .LO ( optlc_net_1945 ) , + .HI ( SYNOPSYS_UNCONNECTED_1947 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2160 ( .LO ( optlc_net_1946 ) , + .HI ( SYNOPSYS_UNCONNECTED_1948 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1947 ) , + .HI ( SYNOPSYS_UNCONNECTED_1949 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1948 ) , + .HI ( SYNOPSYS_UNCONNECTED_1950 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2163 ( .LO ( optlc_net_1949 ) , + .HI ( SYNOPSYS_UNCONNECTED_1951 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2164 ( .LO ( optlc_net_1950 ) , + .HI ( SYNOPSYS_UNCONNECTED_1952 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2165 ( .LO ( optlc_net_1951 ) , + .HI ( SYNOPSYS_UNCONNECTED_1953 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2166 ( .LO ( optlc_net_1952 ) , + .HI ( SYNOPSYS_UNCONNECTED_1954 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1953 ) , + .HI ( SYNOPSYS_UNCONNECTED_1955 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2168 ( .LO ( optlc_net_1954 ) , + .HI ( SYNOPSYS_UNCONNECTED_1956 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1955 ) , + .HI ( SYNOPSYS_UNCONNECTED_1957 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2170 ( .LO ( optlc_net_1956 ) , + .HI ( SYNOPSYS_UNCONNECTED_1958 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1957 ) , + .HI ( SYNOPSYS_UNCONNECTED_1959 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2172 ( .LO ( optlc_net_1958 ) , + .HI ( SYNOPSYS_UNCONNECTED_1960 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1959 ) , + .HI ( SYNOPSYS_UNCONNECTED_1961 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2174 ( .LO ( optlc_net_1960 ) , + .HI ( SYNOPSYS_UNCONNECTED_1962 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1961 ) , + .HI ( SYNOPSYS_UNCONNECTED_1963 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2176 ( .LO ( optlc_net_1962 ) , + .HI ( SYNOPSYS_UNCONNECTED_1964 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1963 ) , + .HI ( SYNOPSYS_UNCONNECTED_1965 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2178 ( .LO ( optlc_net_1964 ) , + .HI ( SYNOPSYS_UNCONNECTED_1966 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2179 ( .LO ( optlc_net_1965 ) , + .HI ( SYNOPSYS_UNCONNECTED_1967 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1966 ) , + .HI ( SYNOPSYS_UNCONNECTED_1968 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2181 ( .LO ( optlc_net_1967 ) , + .HI ( SYNOPSYS_UNCONNECTED_1969 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2182 ( .LO ( optlc_net_1968 ) , + .HI ( SYNOPSYS_UNCONNECTED_1970 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2183 ( .LO ( optlc_net_1969 ) , + .HI ( SYNOPSYS_UNCONNECTED_1971 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2184 ( .LO ( optlc_net_1970 ) , + .HI ( SYNOPSYS_UNCONNECTED_1972 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2185 ( .LO ( optlc_net_1971 ) , + .HI ( SYNOPSYS_UNCONNECTED_1973 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2186 ( .LO ( optlc_net_1972 ) , + .HI ( SYNOPSYS_UNCONNECTED_1974 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2187 ( .LO ( optlc_net_1973 ) , + .HI ( SYNOPSYS_UNCONNECTED_1975 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1974 ) , + .HI ( SYNOPSYS_UNCONNECTED_1976 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2189 ( .LO ( optlc_net_1975 ) , + .HI ( SYNOPSYS_UNCONNECTED_1977 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1976 ) , + .HI ( SYNOPSYS_UNCONNECTED_1978 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2191 ( .LO ( optlc_net_1977 ) , + .HI ( SYNOPSYS_UNCONNECTED_1979 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2192 ( .LO ( optlc_net_1978 ) , + .HI ( SYNOPSYS_UNCONNECTED_1980 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2193 ( .LO ( optlc_net_1979 ) , + .HI ( SYNOPSYS_UNCONNECTED_1981 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1980 ) , + .HI ( SYNOPSYS_UNCONNECTED_1982 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2195 ( .LO ( optlc_net_1981 ) , + .HI ( SYNOPSYS_UNCONNECTED_1983 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2196 ( .LO ( optlc_net_1982 ) , + .HI ( SYNOPSYS_UNCONNECTED_1984 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2197 ( .LO ( optlc_net_1983 ) , + .HI ( SYNOPSYS_UNCONNECTED_1985 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2198 ( .LO ( optlc_net_1984 ) , + .HI ( SYNOPSYS_UNCONNECTED_1986 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2199 ( .LO ( optlc_net_1985 ) , + .HI ( SYNOPSYS_UNCONNECTED_1987 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1986 ) , + .HI ( SYNOPSYS_UNCONNECTED_1988 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2201 ( .LO ( optlc_net_1987 ) , + .HI ( SYNOPSYS_UNCONNECTED_1989 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1988 ) , + .HI ( SYNOPSYS_UNCONNECTED_1990 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1989 ) , + .HI ( SYNOPSYS_UNCONNECTED_1991 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2205 ( .LO ( optlc_net_1990 ) , + .HI ( SYNOPSYS_UNCONNECTED_1992 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2206 ( .LO ( optlc_net_1991 ) , + .HI ( SYNOPSYS_UNCONNECTED_1993 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1992 ) , + .HI ( SYNOPSYS_UNCONNECTED_1994 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2208 ( .LO ( optlc_net_1993 ) , + .HI ( SYNOPSYS_UNCONNECTED_1995 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1994 ) , + .HI ( SYNOPSYS_UNCONNECTED_1996 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2210 ( .LO ( optlc_net_1995 ) , + .HI ( SYNOPSYS_UNCONNECTED_1997 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2211 ( .LO ( optlc_net_1996 ) , + .HI ( SYNOPSYS_UNCONNECTED_1998 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1997 ) , + .HI ( SYNOPSYS_UNCONNECTED_1999 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2213 ( .LO ( optlc_net_1998 ) , + .HI ( SYNOPSYS_UNCONNECTED_2000 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1999 ) , + .HI ( SYNOPSYS_UNCONNECTED_2001 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2215 ( .LO ( optlc_net_2000 ) , + .HI ( SYNOPSYS_UNCONNECTED_2002 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2216 ( .LO ( optlc_net_2001 ) , + .HI ( SYNOPSYS_UNCONNECTED_2003 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2217 ( .LO ( optlc_net_2002 ) , + .HI ( SYNOPSYS_UNCONNECTED_2004 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_2003 ) , + .HI ( SYNOPSYS_UNCONNECTED_2005 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2219 ( .LO ( optlc_net_2004 ) , + .HI ( SYNOPSYS_UNCONNECTED_2006 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2220 ( .LO ( optlc_net_2005 ) , + .HI ( SYNOPSYS_UNCONNECTED_2007 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2222 ( .LO ( optlc_net_2006 ) , + .HI ( SYNOPSYS_UNCONNECTED_2008 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2223 ( .LO ( optlc_net_2007 ) , + .HI ( SYNOPSYS_UNCONNECTED_2009 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2224 ( .LO ( optlc_net_2008 ) , + .HI ( SYNOPSYS_UNCONNECTED_2010 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2225 ( .LO ( optlc_net_2009 ) , + .HI ( SYNOPSYS_UNCONNECTED_2011 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2226 ( .LO ( optlc_net_2010 ) , + .HI ( SYNOPSYS_UNCONNECTED_2012 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2228 ( .LO ( optlc_net_2011 ) , + .HI ( SYNOPSYS_UNCONNECTED_2013 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2229 ( .LO ( optlc_net_2012 ) , + .HI ( SYNOPSYS_UNCONNECTED_2014 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2230 ( .LO ( optlc_net_2013 ) , + .HI ( SYNOPSYS_UNCONNECTED_2015 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2232 ( .LO ( optlc_net_2014 ) , + .HI ( SYNOPSYS_UNCONNECTED_2016 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2233 ( .LO ( optlc_net_2015 ) , + .HI ( SYNOPSYS_UNCONNECTED_2017 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2234 ( .LO ( optlc_net_2016 ) , + .HI ( SYNOPSYS_UNCONNECTED_2018 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2235 ( .LO ( optlc_net_2017 ) , + .HI ( SYNOPSYS_UNCONNECTED_2019 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2236 ( .LO ( optlc_net_2018 ) , + .HI ( SYNOPSYS_UNCONNECTED_2020 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2237 ( .LO ( optlc_net_2019 ) , + .HI ( SYNOPSYS_UNCONNECTED_2021 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2238 ( .LO ( optlc_net_2020 ) , + .HI ( SYNOPSYS_UNCONNECTED_2022 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2239 ( .LO ( optlc_net_2021 ) , + .HI ( SYNOPSYS_UNCONNECTED_2023 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2240 ( .LO ( optlc_net_2022 ) , + .HI ( SYNOPSYS_UNCONNECTED_2024 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2241 ( .LO ( optlc_net_2023 ) , + .HI ( SYNOPSYS_UNCONNECTED_2025 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2242 ( .LO ( optlc_net_2024 ) , + .HI ( SYNOPSYS_UNCONNECTED_2026 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2243 ( .LO ( optlc_net_2025 ) , + .HI ( SYNOPSYS_UNCONNECTED_2027 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2244 ( .LO ( optlc_net_2026 ) , + .HI ( SYNOPSYS_UNCONNECTED_2028 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2246 ( .LO ( optlc_net_2027 ) , + .HI ( SYNOPSYS_UNCONNECTED_2029 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2247 ( .LO ( optlc_net_2028 ) , + .HI ( SYNOPSYS_UNCONNECTED_2030 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2248 ( .LO ( optlc_net_2029 ) , + .HI ( SYNOPSYS_UNCONNECTED_2031 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2249 ( .LO ( optlc_net_2030 ) , + .HI ( SYNOPSYS_UNCONNECTED_2032 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2250 ( .LO ( optlc_net_2031 ) , + .HI ( SYNOPSYS_UNCONNECTED_2033 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2251 ( .LO ( optlc_net_2032 ) , + .HI ( SYNOPSYS_UNCONNECTED_2034 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2252 ( .LO ( optlc_net_2033 ) , + .HI ( SYNOPSYS_UNCONNECTED_2035 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2253 ( .LO ( optlc_net_2034 ) , + .HI ( SYNOPSYS_UNCONNECTED_2036 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2254 ( .LO ( optlc_net_2035 ) , + .HI ( SYNOPSYS_UNCONNECTED_2037 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2255 ( .LO ( optlc_net_2036 ) , + .HI ( SYNOPSYS_UNCONNECTED_2038 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2256 ( .LO ( optlc_net_2037 ) , + .HI ( SYNOPSYS_UNCONNECTED_2039 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2257 ( .LO ( optlc_net_2038 ) , + .HI ( SYNOPSYS_UNCONNECTED_2040 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2258 ( .LO ( optlc_net_2039 ) , + .HI ( SYNOPSYS_UNCONNECTED_2041 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2260 ( .LO ( optlc_net_2040 ) , + .HI ( SYNOPSYS_UNCONNECTED_2042 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2261 ( .LO ( optlc_net_2041 ) , + .HI ( SYNOPSYS_UNCONNECTED_2043 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2262 ( .LO ( optlc_net_2042 ) , + .HI ( SYNOPSYS_UNCONNECTED_2044 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2263 ( .LO ( optlc_net_2043 ) , + .HI ( SYNOPSYS_UNCONNECTED_2045 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2264 ( .LO ( optlc_net_2044 ) , + .HI ( SYNOPSYS_UNCONNECTED_2046 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2265 ( .LO ( optlc_net_2045 ) , + .HI ( SYNOPSYS_UNCONNECTED_2047 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2266 ( .LO ( optlc_net_2046 ) , + .HI ( SYNOPSYS_UNCONNECTED_2048 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2267 ( .LO ( optlc_net_2047 ) , + .HI ( SYNOPSYS_UNCONNECTED_2049 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2268 ( .LO ( optlc_net_2048 ) , + .HI ( SYNOPSYS_UNCONNECTED_2050 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2269 ( .LO ( optlc_net_2049 ) , + .HI ( SYNOPSYS_UNCONNECTED_2051 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2271 ( .LO ( optlc_net_2050 ) , + .HI ( SYNOPSYS_UNCONNECTED_2052 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2272 ( .LO ( optlc_net_2051 ) , + .HI ( SYNOPSYS_UNCONNECTED_2053 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2273 ( .LO ( optlc_net_2052 ) , + .HI ( SYNOPSYS_UNCONNECTED_2054 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2274 ( .LO ( optlc_net_2053 ) , + .HI ( SYNOPSYS_UNCONNECTED_2055 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2275 ( .LO ( optlc_net_2054 ) , + .HI ( SYNOPSYS_UNCONNECTED_2056 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2277 ( .LO ( optlc_net_2055 ) , + .HI ( SYNOPSYS_UNCONNECTED_2057 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2278 ( .LO ( optlc_net_2056 ) , + .HI ( SYNOPSYS_UNCONNECTED_2058 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2279 ( .LO ( optlc_net_2057 ) , + .HI ( SYNOPSYS_UNCONNECTED_2059 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2280 ( .LO ( optlc_net_2058 ) , + .HI ( SYNOPSYS_UNCONNECTED_2060 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2281 ( .LO ( optlc_net_2059 ) , + .HI ( SYNOPSYS_UNCONNECTED_2061 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2283 ( .LO ( optlc_net_2060 ) , + .HI ( SYNOPSYS_UNCONNECTED_2062 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2284 ( .LO ( optlc_net_2061 ) , + .HI ( SYNOPSYS_UNCONNECTED_2063 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2285 ( .LO ( optlc_net_2062 ) , + .HI ( SYNOPSYS_UNCONNECTED_2064 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2286 ( .LO ( optlc_net_2063 ) , + .HI ( SYNOPSYS_UNCONNECTED_2065 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2287 ( .LO ( optlc_net_2064 ) , + .HI ( SYNOPSYS_UNCONNECTED_2066 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2289 ( .LO ( optlc_net_2065 ) , + .HI ( SYNOPSYS_UNCONNECTED_2067 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2290 ( .LO ( optlc_net_2066 ) , + .HI ( SYNOPSYS_UNCONNECTED_2068 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2291 ( .LO ( optlc_net_2067 ) , + .HI ( SYNOPSYS_UNCONNECTED_2069 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2293 ( .LO ( optlc_net_2068 ) , + .HI ( SYNOPSYS_UNCONNECTED_2070 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2294 ( .LO ( optlc_net_2069 ) , + .HI ( SYNOPSYS_UNCONNECTED_2071 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2295 ( .LO ( optlc_net_2070 ) , + .HI ( SYNOPSYS_UNCONNECTED_2072 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2296 ( .LO ( optlc_net_2071 ) , + .HI ( SYNOPSYS_UNCONNECTED_2073 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2297 ( .LO ( optlc_net_2072 ) , + .HI ( SYNOPSYS_UNCONNECTED_2074 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2299 ( .LO ( optlc_net_2073 ) , + .HI ( SYNOPSYS_UNCONNECTED_2075 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2300 ( .LO ( optlc_net_2074 ) , + .HI ( SYNOPSYS_UNCONNECTED_2076 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2301 ( .LO ( optlc_net_2075 ) , + .HI ( SYNOPSYS_UNCONNECTED_2077 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2302 ( .LO ( optlc_net_2076 ) , + .HI ( SYNOPSYS_UNCONNECTED_2078 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2303 ( .LO ( optlc_net_2077 ) , + .HI ( SYNOPSYS_UNCONNECTED_2079 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2305 ( .LO ( optlc_net_2078 ) , + .HI ( SYNOPSYS_UNCONNECTED_2080 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2306 ( .LO ( optlc_net_2079 ) , + .HI ( SYNOPSYS_UNCONNECTED_2081 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2308 ( .LO ( optlc_net_2080 ) , + .HI ( SYNOPSYS_UNCONNECTED_2082 ) ) ; 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SYNOPSYS_UNCONNECTED_2092 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2319 ( .LO ( optlc_net_2091 ) , + .HI ( SYNOPSYS_UNCONNECTED_2093 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2320 ( .LO ( optlc_net_2092 ) , + .HI ( SYNOPSYS_UNCONNECTED_2094 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2321 ( .LO ( optlc_net_2093 ) , + .HI ( SYNOPSYS_UNCONNECTED_2095 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2322 ( .LO ( optlc_net_2094 ) , + .HI ( SYNOPSYS_UNCONNECTED_2096 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2323 ( .LO ( optlc_net_2095 ) , + .HI ( SYNOPSYS_UNCONNECTED_2097 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2324 ( .LO ( optlc_net_2096 ) , + .HI ( SYNOPSYS_UNCONNECTED_2098 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2326 ( .LO ( optlc_net_2097 ) , + .HI ( SYNOPSYS_UNCONNECTED_2099 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2328 ( .LO ( optlc_net_2098 ) , + .HI ( SYNOPSYS_UNCONNECTED_2100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2329 ( .LO ( optlc_net_2099 ) , + .HI ( SYNOPSYS_UNCONNECTED_2101 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2330 ( .LO ( optlc_net_2100 ) , + .HI ( SYNOPSYS_UNCONNECTED_2102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2332 ( .LO ( optlc_net_2101 ) , + .HI ( SYNOPSYS_UNCONNECTED_2103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2334 ( .LO ( optlc_net_2102 ) , + .HI ( SYNOPSYS_UNCONNECTED_2104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2335 ( .LO ( optlc_net_2103 ) , + .HI ( SYNOPSYS_UNCONNECTED_2105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2336 ( .LO ( optlc_net_2104 ) , + .HI ( SYNOPSYS_UNCONNECTED_2106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2337 ( .LO ( optlc_net_2105 ) , + .HI ( SYNOPSYS_UNCONNECTED_2107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2338 ( .LO ( optlc_net_2106 ) , + .HI ( SYNOPSYS_UNCONNECTED_2108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2340 ( .LO ( optlc_net_2107 ) , + .HI ( SYNOPSYS_UNCONNECTED_2109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2341 ( .LO ( optlc_net_2108 ) , + .HI ( SYNOPSYS_UNCONNECTED_2110 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2343 ( .LO ( optlc_net_2109 ) , + .HI ( SYNOPSYS_UNCONNECTED_2111 ) ) ; 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SYNOPSYS_UNCONNECTED_2121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2359 ( .LO ( optlc_net_2120 ) , + .HI ( SYNOPSYS_UNCONNECTED_2122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2360 ( .LO ( optlc_net_2121 ) , + .HI ( SYNOPSYS_UNCONNECTED_2123 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2361 ( .LO ( optlc_net_2122 ) , + .HI ( SYNOPSYS_UNCONNECTED_2124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2362 ( .LO ( optlc_net_2123 ) , + .HI ( SYNOPSYS_UNCONNECTED_2125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2364 ( .LO ( optlc_net_2124 ) , + .HI ( SYNOPSYS_UNCONNECTED_2126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2365 ( .LO ( optlc_net_2125 ) , + .HI ( SYNOPSYS_UNCONNECTED_2127 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2367 ( .LO ( optlc_net_2126 ) , + .HI ( SYNOPSYS_UNCONNECTED_2128 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2368 ( .LO ( optlc_net_2127 ) , + .HI ( SYNOPSYS_UNCONNECTED_2129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2370 ( .LO ( optlc_net_2128 ) , + .HI ( SYNOPSYS_UNCONNECTED_2130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2371 ( .LO ( optlc_net_2129 ) , + .HI ( SYNOPSYS_UNCONNECTED_2131 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2373 ( .LO ( optlc_net_2130 ) , + .HI ( SYNOPSYS_UNCONNECTED_2132 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2374 ( .LO ( optlc_net_2131 ) , + .HI ( SYNOPSYS_UNCONNECTED_2133 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2375 ( .LO ( optlc_net_2132 ) , + .HI ( SYNOPSYS_UNCONNECTED_2134 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2376 ( .LO ( optlc_net_2133 ) , + .HI ( SYNOPSYS_UNCONNECTED_2135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2377 ( .LO ( optlc_net_2134 ) , + .HI ( SYNOPSYS_UNCONNECTED_2136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2378 ( .LO ( optlc_net_2135 ) , + .HI ( SYNOPSYS_UNCONNECTED_2137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2379 ( .LO ( optlc_net_2136 ) , + .HI ( SYNOPSYS_UNCONNECTED_2138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2380 ( .LO ( optlc_net_2137 ) , + .HI ( SYNOPSYS_UNCONNECTED_2139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2381 ( .LO ( optlc_net_2138 ) , + .HI ( SYNOPSYS_UNCONNECTED_2140 ) ) ; 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SYNOPSYS_UNCONNECTED_2150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2395 ( .LO ( optlc_net_2149 ) , + .HI ( SYNOPSYS_UNCONNECTED_2151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2397 ( .LO ( optlc_net_2150 ) , + .HI ( SYNOPSYS_UNCONNECTED_2152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2398 ( .LO ( optlc_net_2151 ) , + .HI ( SYNOPSYS_UNCONNECTED_2153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2400 ( .LO ( optlc_net_2152 ) , + .HI ( SYNOPSYS_UNCONNECTED_2154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2401 ( .LO ( optlc_net_2153 ) , + .HI ( SYNOPSYS_UNCONNECTED_2155 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2402 ( .LO ( optlc_net_2154 ) , + .HI ( SYNOPSYS_UNCONNECTED_2156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2403 ( .LO ( optlc_net_2155 ) , + .HI ( SYNOPSYS_UNCONNECTED_2157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2404 ( .LO ( optlc_net_2156 ) , + .HI ( SYNOPSYS_UNCONNECTED_2158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2405 ( .LO ( optlc_net_2157 ) , + .HI ( SYNOPSYS_UNCONNECTED_2159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2406 ( .LO ( optlc_net_2158 ) , + .HI ( SYNOPSYS_UNCONNECTED_2160 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2407 ( .LO ( optlc_net_2159 ) , + .HI ( SYNOPSYS_UNCONNECTED_2161 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2408 ( .LO ( optlc_net_2160 ) , + .HI ( SYNOPSYS_UNCONNECTED_2162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2409 ( .LO ( optlc_net_2161 ) , + .HI ( SYNOPSYS_UNCONNECTED_2163 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2410 ( .LO ( optlc_net_2162 ) , + .HI ( SYNOPSYS_UNCONNECTED_2164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2411 ( .LO ( optlc_net_2163 ) , + .HI ( SYNOPSYS_UNCONNECTED_2165 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2412 ( .LO ( optlc_net_2164 ) , + .HI ( SYNOPSYS_UNCONNECTED_2166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2413 ( .LO ( optlc_net_2165 ) , + .HI ( SYNOPSYS_UNCONNECTED_2167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2415 ( .LO ( optlc_net_2166 ) , + .HI ( SYNOPSYS_UNCONNECTED_2168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2416 ( .LO ( optlc_net_2167 ) , + .HI ( SYNOPSYS_UNCONNECTED_2169 ) ) ; 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SYNOPSYS_UNCONNECTED_2179 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2428 ( .LO ( optlc_net_2178 ) , + .HI ( SYNOPSYS_UNCONNECTED_2180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2430 ( .LO ( optlc_net_2179 ) , + .HI ( SYNOPSYS_UNCONNECTED_2181 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2431 ( .LO ( optlc_net_2180 ) , + .HI ( SYNOPSYS_UNCONNECTED_2182 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2432 ( .LO ( optlc_net_2181 ) , + .HI ( SYNOPSYS_UNCONNECTED_2183 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2433 ( .LO ( optlc_net_2182 ) , + .HI ( SYNOPSYS_UNCONNECTED_2184 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2434 ( .LO ( optlc_net_2183 ) , + .HI ( SYNOPSYS_UNCONNECTED_2185 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2435 ( .LO ( optlc_net_2184 ) , + .HI ( SYNOPSYS_UNCONNECTED_2186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2436 ( .LO ( optlc_net_2185 ) , + .HI ( SYNOPSYS_UNCONNECTED_2187 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2438 ( .LO ( optlc_net_2186 ) , + .HI ( SYNOPSYS_UNCONNECTED_2188 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2439 ( .LO ( optlc_net_2187 ) , + .HI ( SYNOPSYS_UNCONNECTED_2189 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2440 ( .LO ( optlc_net_2188 ) , + .HI ( SYNOPSYS_UNCONNECTED_2190 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2441 ( .LO ( optlc_net_2189 ) , + .HI ( SYNOPSYS_UNCONNECTED_2191 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2442 ( .LO ( optlc_net_2190 ) , + .HI ( SYNOPSYS_UNCONNECTED_2192 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2443 ( .LO ( optlc_net_2191 ) , + .HI ( SYNOPSYS_UNCONNECTED_2193 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2444 ( .LO ( optlc_net_2192 ) , + .HI ( SYNOPSYS_UNCONNECTED_2194 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2445 ( .LO ( optlc_net_2193 ) , + .HI ( SYNOPSYS_UNCONNECTED_2195 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2446 ( .LO ( optlc_net_2194 ) , + .HI ( SYNOPSYS_UNCONNECTED_2196 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2447 ( .LO ( optlc_net_2195 ) , + .HI ( SYNOPSYS_UNCONNECTED_2197 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2448 ( .LO ( optlc_net_2196 ) , + .HI ( SYNOPSYS_UNCONNECTED_2198 ) ) ; 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SYNOPSYS_UNCONNECTED_2208 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2459 ( .LO ( optlc_net_2207 ) , + .HI ( SYNOPSYS_UNCONNECTED_2209 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2460 ( .LO ( optlc_net_2208 ) , + .HI ( SYNOPSYS_UNCONNECTED_2210 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2461 ( .LO ( optlc_net_2209 ) , + .HI ( SYNOPSYS_UNCONNECTED_2211 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2462 ( .LO ( optlc_net_2210 ) , + .HI ( SYNOPSYS_UNCONNECTED_2212 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2463 ( .LO ( optlc_net_2211 ) , + .HI ( SYNOPSYS_UNCONNECTED_2213 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2464 ( .LO ( optlc_net_2212 ) , + .HI ( SYNOPSYS_UNCONNECTED_2214 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2465 ( .LO ( optlc_net_2213 ) , + .HI ( SYNOPSYS_UNCONNECTED_2215 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2466 ( .LO ( optlc_net_2214 ) , + .HI ( SYNOPSYS_UNCONNECTED_2216 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2467 ( .LO ( optlc_net_2215 ) , + .HI ( SYNOPSYS_UNCONNECTED_2217 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2468 ( .LO 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SYNOPSYS_UNCONNECTED_2266 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2517 ( .LO ( optlc_net_2265 ) , + .HI ( SYNOPSYS_UNCONNECTED_2267 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2518 ( .LO ( optlc_net_2266 ) , + .HI ( SYNOPSYS_UNCONNECTED_2268 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2519 ( .LO ( optlc_net_2267 ) , + .HI ( SYNOPSYS_UNCONNECTED_2269 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2520 ( .LO ( optlc_net_2268 ) , + .HI ( SYNOPSYS_UNCONNECTED_2270 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2521 ( .LO ( optlc_net_2269 ) , + .HI ( SYNOPSYS_UNCONNECTED_2271 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2522 ( .LO ( optlc_net_2270 ) , + .HI ( SYNOPSYS_UNCONNECTED_2272 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2523 ( .LO ( optlc_net_2271 ) , + .HI ( SYNOPSYS_UNCONNECTED_2273 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2524 ( .LO ( optlc_net_2272 ) , + .HI ( SYNOPSYS_UNCONNECTED_2274 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2525 ( .LO ( optlc_net_2273 ) , + .HI ( SYNOPSYS_UNCONNECTED_2275 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2526 ( .LO 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SYNOPSYS_UNCONNECTED_2353 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2614 ( .LO ( optlc_net_2352 ) , + .HI ( SYNOPSYS_UNCONNECTED_2354 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2615 ( .LO ( optlc_net_2353 ) , + .HI ( SYNOPSYS_UNCONNECTED_2355 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2616 ( .LO ( optlc_net_2354 ) , + .HI ( SYNOPSYS_UNCONNECTED_2356 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2617 ( .LO ( optlc_net_2355 ) , + .HI ( SYNOPSYS_UNCONNECTED_2357 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2619 ( .LO ( optlc_net_2356 ) , + .HI ( SYNOPSYS_UNCONNECTED_2358 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2620 ( .LO ( optlc_net_2357 ) , + .HI ( SYNOPSYS_UNCONNECTED_2359 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2621 ( .LO ( optlc_net_2358 ) , + .HI ( SYNOPSYS_UNCONNECTED_2360 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2622 ( .LO ( optlc_net_2359 ) , + .HI ( SYNOPSYS_UNCONNECTED_2361 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2623 ( .LO ( optlc_net_2360 ) , + .HI ( SYNOPSYS_UNCONNECTED_2362 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2624 ( .LO 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SYNOPSYS_UNCONNECTED_2382 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2649 ( .LO ( optlc_net_2381 ) , + .HI ( SYNOPSYS_UNCONNECTED_2383 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2650 ( .LO ( optlc_net_2382 ) , + .HI ( SYNOPSYS_UNCONNECTED_2384 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2651 ( .LO ( optlc_net_2383 ) , + .HI ( SYNOPSYS_UNCONNECTED_2385 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2652 ( .LO ( optlc_net_2384 ) , + .HI ( SYNOPSYS_UNCONNECTED_2386 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2653 ( .LO ( optlc_net_2385 ) , + .HI ( SYNOPSYS_UNCONNECTED_2387 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2654 ( .LO ( optlc_net_2386 ) , + .HI ( SYNOPSYS_UNCONNECTED_2388 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2655 ( .LO ( optlc_net_2387 ) , + .HI ( SYNOPSYS_UNCONNECTED_2389 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2656 ( .LO ( optlc_net_2388 ) , + .HI ( SYNOPSYS_UNCONNECTED_2390 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2657 ( .LO ( optlc_net_2389 ) , + .HI ( SYNOPSYS_UNCONNECTED_2391 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2658 ( .LO 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SYNOPSYS_UNCONNECTED_2411 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2684 ( .LO ( optlc_net_2410 ) , + .HI ( SYNOPSYS_UNCONNECTED_2412 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2685 ( .LO ( optlc_net_2411 ) , + .HI ( SYNOPSYS_UNCONNECTED_2413 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2686 ( .LO ( optlc_net_2412 ) , + .HI ( SYNOPSYS_UNCONNECTED_2414 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2687 ( .LO ( optlc_net_2413 ) , + .HI ( SYNOPSYS_UNCONNECTED_2415 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2688 ( .LO ( optlc_net_2414 ) , + .HI ( SYNOPSYS_UNCONNECTED_2416 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2689 ( .LO ( optlc_net_2415 ) , + .HI ( SYNOPSYS_UNCONNECTED_2417 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2690 ( .LO ( optlc_net_2416 ) , + .HI ( SYNOPSYS_UNCONNECTED_2418 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2691 ( .LO ( optlc_net_2417 ) , + .HI ( SYNOPSYS_UNCONNECTED_2419 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2692 ( .LO ( optlc_net_2418 ) , + .HI ( SYNOPSYS_UNCONNECTED_2420 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2693 ( .LO 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SYNOPSYS_UNCONNECTED_2440 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2718 ( .LO ( optlc_net_2439 ) , + .HI ( SYNOPSYS_UNCONNECTED_2441 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2719 ( .LO ( optlc_net_2440 ) , + .HI ( SYNOPSYS_UNCONNECTED_2442 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2720 ( .LO ( optlc_net_2441 ) , + .HI ( SYNOPSYS_UNCONNECTED_2443 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2721 ( .LO ( optlc_net_2442 ) , + .HI ( SYNOPSYS_UNCONNECTED_2444 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2722 ( .LO ( optlc_net_2443 ) , + .HI ( SYNOPSYS_UNCONNECTED_2445 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2723 ( .LO ( optlc_net_2444 ) , + .HI ( SYNOPSYS_UNCONNECTED_2446 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2724 ( .LO ( optlc_net_2445 ) , + .HI ( SYNOPSYS_UNCONNECTED_2447 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2725 ( .LO ( optlc_net_2446 ) , + .HI ( SYNOPSYS_UNCONNECTED_2448 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2726 ( .LO ( optlc_net_2447 ) , + .HI ( SYNOPSYS_UNCONNECTED_2449 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2727 ( .LO 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SYNOPSYS_UNCONNECTED_2469 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2747 ( .LO ( optlc_net_2468 ) , + .HI ( SYNOPSYS_UNCONNECTED_2470 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2748 ( .LO ( optlc_net_2469 ) , + .HI ( SYNOPSYS_UNCONNECTED_2471 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2749 ( .LO ( optlc_net_2470 ) , + .HI ( SYNOPSYS_UNCONNECTED_2472 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2750 ( .LO ( optlc_net_2471 ) , + .HI ( SYNOPSYS_UNCONNECTED_2473 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2751 ( .LO ( optlc_net_2472 ) , + .HI ( SYNOPSYS_UNCONNECTED_2474 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2752 ( .LO ( optlc_net_2473 ) , + .HI ( SYNOPSYS_UNCONNECTED_2475 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2753 ( .LO ( optlc_net_2474 ) , + .HI ( SYNOPSYS_UNCONNECTED_2476 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2754 ( .LO ( optlc_net_2475 ) , + .HI ( SYNOPSYS_UNCONNECTED_2477 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2755 ( .LO ( optlc_net_2476 ) , + .HI ( SYNOPSYS_UNCONNECTED_2478 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2756 ( .LO ( optlc_net_2477 ) , + .HI ( SYNOPSYS_UNCONNECTED_2479 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2757 ( .LO ( optlc_net_2478 ) , + .HI ( SYNOPSYS_UNCONNECTED_2480 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2758 ( .LO ( optlc_net_2479 ) , + .HI ( SYNOPSYS_UNCONNECTED_2481 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2759 ( .LO ( optlc_net_2480 ) , + .HI ( SYNOPSYS_UNCONNECTED_2482 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2760 ( .LO ( optlc_net_2481 ) , + .HI ( SYNOPSYS_UNCONNECTED_2483 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2761 ( .LO ( optlc_net_2482 ) , + .HI ( SYNOPSYS_UNCONNECTED_2484 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2762 ( .LO ( optlc_net_2483 ) , + .HI ( SYNOPSYS_UNCONNECTED_2485 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2763 ( .LO ( optlc_net_2484 ) , + .HI ( SYNOPSYS_UNCONNECTED_2486 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2764 ( .LO ( optlc_net_2485 ) , + .HI ( SYNOPSYS_UNCONNECTED_2487 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2765 ( .LO ( optlc_net_2486 ) , + .HI ( SYNOPSYS_UNCONNECTED_2488 ) ) ; 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SYNOPSYS_UNCONNECTED_2498 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2776 ( .LO ( optlc_net_2497 ) , + .HI ( SYNOPSYS_UNCONNECTED_2499 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2777 ( .LO ( optlc_net_2498 ) , + .HI ( SYNOPSYS_UNCONNECTED_2500 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2778 ( .LO ( optlc_net_2499 ) , + .HI ( SYNOPSYS_UNCONNECTED_2501 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2779 ( .LO ( optlc_net_2500 ) , + .HI ( SYNOPSYS_UNCONNECTED_2502 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2780 ( .LO ( optlc_net_2501 ) , + .HI ( SYNOPSYS_UNCONNECTED_2503 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2781 ( .LO ( optlc_net_2502 ) , + .HI ( SYNOPSYS_UNCONNECTED_2504 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2782 ( .LO ( optlc_net_2503 ) , + .HI ( SYNOPSYS_UNCONNECTED_2505 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2783 ( .LO ( optlc_net_2504 ) , + .HI ( SYNOPSYS_UNCONNECTED_2506 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2784 ( .LO ( optlc_net_2505 ) , + .HI ( SYNOPSYS_UNCONNECTED_2507 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2785 ( .LO ( optlc_net_2506 ) , + .HI ( SYNOPSYS_UNCONNECTED_2508 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2786 ( .LO ( optlc_net_2507 ) , + .HI ( SYNOPSYS_UNCONNECTED_2509 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2787 ( .LO ( optlc_net_2508 ) , + .HI ( SYNOPSYS_UNCONNECTED_2510 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2788 ( .LO ( optlc_net_2509 ) , + .HI ( SYNOPSYS_UNCONNECTED_2511 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2789 ( .LO ( optlc_net_2510 ) , + .HI ( SYNOPSYS_UNCONNECTED_2512 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2790 ( .LO ( optlc_net_2511 ) , + .HI ( SYNOPSYS_UNCONNECTED_2513 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2791 ( .LO ( optlc_net_2512 ) , + .HI ( SYNOPSYS_UNCONNECTED_2514 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2792 ( .LO ( optlc_net_2513 ) , + .HI ( SYNOPSYS_UNCONNECTED_2515 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2793 ( .LO ( optlc_net_2514 ) , + .HI ( SYNOPSYS_UNCONNECTED_2516 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2794 ( .LO ( optlc_net_2515 ) , + .HI ( SYNOPSYS_UNCONNECTED_2517 ) ) ; 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SYNOPSYS_UNCONNECTED_2527 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2805 ( .LO ( optlc_net_2526 ) , + .HI ( SYNOPSYS_UNCONNECTED_2528 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2806 ( .LO ( optlc_net_2527 ) , + .HI ( SYNOPSYS_UNCONNECTED_2529 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2808 ( .LO ( optlc_net_2528 ) , + .HI ( SYNOPSYS_UNCONNECTED_2530 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2809 ( .LO ( optlc_net_2529 ) , + .HI ( SYNOPSYS_UNCONNECTED_2531 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2811 ( .LO ( optlc_net_2530 ) , + .HI ( SYNOPSYS_UNCONNECTED_2532 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2812 ( .LO ( optlc_net_2531 ) , + .HI ( SYNOPSYS_UNCONNECTED_2533 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2813 ( .LO ( optlc_net_2532 ) , + .HI ( SYNOPSYS_UNCONNECTED_2534 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2814 ( .LO ( optlc_net_2533 ) , + .HI ( SYNOPSYS_UNCONNECTED_2535 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2815 ( .LO ( optlc_net_2534 ) , + .HI ( SYNOPSYS_UNCONNECTED_2536 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2816 ( .LO ( optlc_net_2535 ) , + .HI ( SYNOPSYS_UNCONNECTED_2537 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2817 ( .LO ( optlc_net_2536 ) , + .HI ( SYNOPSYS_UNCONNECTED_2538 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2818 ( .LO ( optlc_net_2537 ) , + .HI ( SYNOPSYS_UNCONNECTED_2539 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2820 ( .LO ( optlc_net_2538 ) , + .HI ( SYNOPSYS_UNCONNECTED_2540 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2821 ( .LO ( optlc_net_2539 ) , + .HI ( SYNOPSYS_UNCONNECTED_2541 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2822 ( .LO ( optlc_net_2540 ) , + .HI ( SYNOPSYS_UNCONNECTED_2542 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2823 ( .LO ( optlc_net_2541 ) , + .HI ( SYNOPSYS_UNCONNECTED_2543 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2824 ( .LO ( optlc_net_2542 ) , + .HI ( SYNOPSYS_UNCONNECTED_2544 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2825 ( .LO ( optlc_net_2543 ) , + .HI ( SYNOPSYS_UNCONNECTED_2545 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2826 ( .LO ( optlc_net_2544 ) , + .HI ( SYNOPSYS_UNCONNECTED_2546 ) ) ; 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SYNOPSYS_UNCONNECTED_2556 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2838 ( .LO ( optlc_net_2555 ) , + .HI ( SYNOPSYS_UNCONNECTED_2557 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2839 ( .LO ( optlc_net_2556 ) , + .HI ( SYNOPSYS_UNCONNECTED_2558 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2840 ( .LO ( optlc_net_2557 ) , + .HI ( SYNOPSYS_UNCONNECTED_2559 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2841 ( .LO ( optlc_net_2558 ) , + .HI ( SYNOPSYS_UNCONNECTED_2560 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2843 ( .LO ( optlc_net_2559 ) , + .HI ( SYNOPSYS_UNCONNECTED_2561 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2844 ( .LO ( optlc_net_2560 ) , + .HI ( SYNOPSYS_UNCONNECTED_2562 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2845 ( .LO ( optlc_net_2561 ) , + .HI ( SYNOPSYS_UNCONNECTED_2563 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2846 ( .LO ( optlc_net_2562 ) , + .HI ( SYNOPSYS_UNCONNECTED_2564 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2847 ( .LO ( optlc_net_2563 ) , + .HI ( SYNOPSYS_UNCONNECTED_2565 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2848 ( .LO ( optlc_net_2564 ) , + .HI ( SYNOPSYS_UNCONNECTED_2566 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2849 ( .LO ( optlc_net_2565 ) , + .HI ( SYNOPSYS_UNCONNECTED_2567 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2850 ( .LO ( optlc_net_2566 ) , + .HI ( SYNOPSYS_UNCONNECTED_2568 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2851 ( .LO ( optlc_net_2567 ) , + .HI ( SYNOPSYS_UNCONNECTED_2569 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2852 ( .LO ( optlc_net_2568 ) , + .HI ( SYNOPSYS_UNCONNECTED_2570 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2853 ( .LO ( optlc_net_2569 ) , + .HI ( SYNOPSYS_UNCONNECTED_2571 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2855 ( .LO ( optlc_net_2570 ) , + .HI ( SYNOPSYS_UNCONNECTED_2572 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2856 ( .LO ( optlc_net_2571 ) , + .HI ( SYNOPSYS_UNCONNECTED_2573 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2857 ( .LO ( optlc_net_2572 ) , + .HI ( SYNOPSYS_UNCONNECTED_2574 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2859 ( .LO ( optlc_net_2573 ) , + .HI ( SYNOPSYS_UNCONNECTED_2575 ) ) ; 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SYNOPSYS_UNCONNECTED_2585 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2872 ( .LO ( optlc_net_2584 ) , + .HI ( SYNOPSYS_UNCONNECTED_2586 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2873 ( .LO ( optlc_net_2585 ) , + .HI ( SYNOPSYS_UNCONNECTED_2587 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2874 ( .LO ( optlc_net_2586 ) , + .HI ( SYNOPSYS_UNCONNECTED_2588 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2875 ( .LO ( optlc_net_2587 ) , + .HI ( SYNOPSYS_UNCONNECTED_2589 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2876 ( .LO ( optlc_net_2588 ) , + .HI ( SYNOPSYS_UNCONNECTED_2590 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2877 ( .LO ( optlc_net_2589 ) , + .HI ( SYNOPSYS_UNCONNECTED_2591 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2878 ( .LO ( optlc_net_2590 ) , + .HI ( SYNOPSYS_UNCONNECTED_2592 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2879 ( .LO ( optlc_net_2591 ) , + .HI ( SYNOPSYS_UNCONNECTED_2593 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2880 ( .LO ( optlc_net_2592 ) , + .HI ( SYNOPSYS_UNCONNECTED_2594 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2882 ( .LO ( optlc_net_2593 ) , + .HI ( SYNOPSYS_UNCONNECTED_2595 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2884 ( .LO ( optlc_net_2594 ) , + .HI ( SYNOPSYS_UNCONNECTED_2596 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2885 ( .LO ( optlc_net_2595 ) , + .HI ( SYNOPSYS_UNCONNECTED_2597 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2886 ( .LO ( optlc_net_2596 ) , + .HI ( SYNOPSYS_UNCONNECTED_2598 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2887 ( .LO ( optlc_net_2597 ) , + .HI ( SYNOPSYS_UNCONNECTED_2599 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2888 ( .LO ( optlc_net_2598 ) , + .HI ( SYNOPSYS_UNCONNECTED_2600 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2889 ( .LO ( optlc_net_2599 ) , + .HI ( SYNOPSYS_UNCONNECTED_2601 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2890 ( .LO ( optlc_net_2600 ) , + .HI ( SYNOPSYS_UNCONNECTED_2602 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2891 ( .LO ( optlc_net_2601 ) , + .HI ( SYNOPSYS_UNCONNECTED_2603 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2892 ( .LO ( optlc_net_2602 ) , + .HI ( SYNOPSYS_UNCONNECTED_2604 ) ) ; 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SYNOPSYS_UNCONNECTED_2759 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3056 ( .LO ( optlc_net_2758 ) , + .HI ( SYNOPSYS_UNCONNECTED_2760 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3057 ( .LO ( optlc_net_2759 ) , + .HI ( SYNOPSYS_UNCONNECTED_2761 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3058 ( .LO ( optlc_net_2760 ) , + .HI ( SYNOPSYS_UNCONNECTED_2762 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3059 ( .LO ( optlc_net_2761 ) , + .HI ( SYNOPSYS_UNCONNECTED_2763 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3060 ( .LO ( optlc_net_2762 ) , + .HI ( SYNOPSYS_UNCONNECTED_2764 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3061 ( .LO ( optlc_net_2763 ) , + .HI ( SYNOPSYS_UNCONNECTED_2765 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3062 ( .LO ( optlc_net_2764 ) , + .HI ( SYNOPSYS_UNCONNECTED_2766 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3063 ( .LO ( optlc_net_2765 ) , + .HI ( SYNOPSYS_UNCONNECTED_2767 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3064 ( .LO ( optlc_net_2766 ) , + .HI ( SYNOPSYS_UNCONNECTED_2768 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3065 ( .LO ( optlc_net_2767 ) , + .HI ( SYNOPSYS_UNCONNECTED_2769 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3066 ( .LO ( optlc_net_2768 ) , + .HI ( SYNOPSYS_UNCONNECTED_2770 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3067 ( .LO ( optlc_net_2769 ) , + .HI ( SYNOPSYS_UNCONNECTED_2771 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3068 ( .LO ( optlc_net_2770 ) , + .HI ( SYNOPSYS_UNCONNECTED_2772 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3069 ( .LO ( optlc_net_2771 ) , + .HI ( SYNOPSYS_UNCONNECTED_2773 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3070 ( .LO ( optlc_net_2772 ) , + .HI ( SYNOPSYS_UNCONNECTED_2774 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3071 ( .LO ( optlc_net_2773 ) , + .HI ( SYNOPSYS_UNCONNECTED_2775 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3072 ( .LO ( optlc_net_2774 ) , + .HI ( SYNOPSYS_UNCONNECTED_2776 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3073 ( .LO ( optlc_net_2775 ) , + .HI ( SYNOPSYS_UNCONNECTED_2777 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3074 ( .LO ( optlc_net_2776 ) , + .HI ( SYNOPSYS_UNCONNECTED_2778 ) ) ; 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SYNOPSYS_UNCONNECTED_2788 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3086 ( .LO ( optlc_net_2787 ) , + .HI ( SYNOPSYS_UNCONNECTED_2789 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3087 ( .LO ( optlc_net_2788 ) , + .HI ( SYNOPSYS_UNCONNECTED_2790 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3088 ( .LO ( optlc_net_2789 ) , + .HI ( SYNOPSYS_UNCONNECTED_2791 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3089 ( .LO ( optlc_net_2790 ) , + .HI ( SYNOPSYS_UNCONNECTED_2792 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3090 ( .LO ( optlc_net_2791 ) , + .HI ( SYNOPSYS_UNCONNECTED_2793 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3091 ( .LO ( optlc_net_2792 ) , + .HI ( SYNOPSYS_UNCONNECTED_2794 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3092 ( .LO ( optlc_net_2793 ) , + .HI ( SYNOPSYS_UNCONNECTED_2795 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3093 ( .LO ( optlc_net_2794 ) , + .HI ( SYNOPSYS_UNCONNECTED_2796 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3094 ( .LO ( optlc_net_2795 ) , + .HI ( SYNOPSYS_UNCONNECTED_2797 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3095 ( .LO ( optlc_net_2796 ) , + .HI ( SYNOPSYS_UNCONNECTED_2798 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3096 ( .LO ( optlc_net_2797 ) , + .HI ( SYNOPSYS_UNCONNECTED_2799 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3097 ( .LO ( optlc_net_2798 ) , + .HI ( SYNOPSYS_UNCONNECTED_2800 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3098 ( .LO ( optlc_net_2799 ) , + .HI ( SYNOPSYS_UNCONNECTED_2801 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3099 ( .LO ( optlc_net_2800 ) , + .HI ( SYNOPSYS_UNCONNECTED_2802 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3100 ( .LO ( optlc_net_2801 ) , + .HI ( SYNOPSYS_UNCONNECTED_2803 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3101 ( .LO ( optlc_net_2802 ) , + .HI ( SYNOPSYS_UNCONNECTED_2804 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3103 ( .LO ( optlc_net_2803 ) , + .HI ( SYNOPSYS_UNCONNECTED_2805 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3104 ( .LO ( optlc_net_2804 ) , + .HI ( SYNOPSYS_UNCONNECTED_2806 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3105 ( .LO ( optlc_net_2805 ) , + .HI ( SYNOPSYS_UNCONNECTED_2807 ) ) ; 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SYNOPSYS_UNCONNECTED_2817 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3116 ( .LO ( optlc_net_2816 ) , + .HI ( SYNOPSYS_UNCONNECTED_2818 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3117 ( .LO ( optlc_net_2817 ) , + .HI ( SYNOPSYS_UNCONNECTED_2819 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3118 ( .LO ( optlc_net_2818 ) , + .HI ( SYNOPSYS_UNCONNECTED_2820 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3119 ( .LO ( optlc_net_2819 ) , + .HI ( SYNOPSYS_UNCONNECTED_2821 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3120 ( .LO ( optlc_net_2820 ) , + .HI ( SYNOPSYS_UNCONNECTED_2822 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3121 ( .LO ( optlc_net_2821 ) , + .HI ( SYNOPSYS_UNCONNECTED_2823 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3122 ( .LO ( optlc_net_2822 ) , + .HI ( SYNOPSYS_UNCONNECTED_2824 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3123 ( .LO ( optlc_net_2823 ) , + .HI ( SYNOPSYS_UNCONNECTED_2825 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3124 ( .LO ( optlc_net_2824 ) , + .HI ( SYNOPSYS_UNCONNECTED_2826 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3125 ( .LO ( optlc_net_2825 ) , + .HI ( SYNOPSYS_UNCONNECTED_2827 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3126 ( .LO ( optlc_net_2826 ) , + .HI ( SYNOPSYS_UNCONNECTED_2828 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3127 ( .LO ( optlc_net_2827 ) , + .HI ( SYNOPSYS_UNCONNECTED_2829 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3128 ( .LO ( optlc_net_2828 ) , + .HI ( SYNOPSYS_UNCONNECTED_2830 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3129 ( .LO ( optlc_net_2829 ) , + .HI ( SYNOPSYS_UNCONNECTED_2831 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3130 ( .LO ( optlc_net_2830 ) , + .HI ( SYNOPSYS_UNCONNECTED_2832 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3131 ( .LO ( optlc_net_2831 ) , + .HI ( SYNOPSYS_UNCONNECTED_2833 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3132 ( .LO ( optlc_net_2832 ) , + .HI ( SYNOPSYS_UNCONNECTED_2834 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3133 ( .LO ( optlc_net_2833 ) , + .HI ( SYNOPSYS_UNCONNECTED_2835 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3134 ( .LO ( optlc_net_2834 ) , + .HI ( SYNOPSYS_UNCONNECTED_2836 ) ) ; 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SYNOPSYS_UNCONNECTED_2846 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3145 ( .LO ( optlc_net_2845 ) , + .HI ( SYNOPSYS_UNCONNECTED_2847 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3146 ( .LO ( optlc_net_2846 ) , + .HI ( SYNOPSYS_UNCONNECTED_2848 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3147 ( .LO ( optlc_net_2847 ) , + .HI ( SYNOPSYS_UNCONNECTED_2849 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3148 ( .LO ( optlc_net_2848 ) , + .HI ( SYNOPSYS_UNCONNECTED_2850 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3149 ( .LO ( optlc_net_2849 ) , + .HI ( SYNOPSYS_UNCONNECTED_2851 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3150 ( .LO ( optlc_net_2850 ) , + .HI ( SYNOPSYS_UNCONNECTED_2852 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3151 ( .LO ( optlc_net_2851 ) , + .HI ( SYNOPSYS_UNCONNECTED_2853 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3152 ( .LO ( optlc_net_2852 ) , + .HI ( SYNOPSYS_UNCONNECTED_2854 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3153 ( .LO ( optlc_net_2853 ) , + .HI ( SYNOPSYS_UNCONNECTED_2855 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3154 ( .LO ( optlc_net_2854 ) , + .HI ( SYNOPSYS_UNCONNECTED_2856 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3155 ( .LO ( optlc_net_2855 ) , + .HI ( SYNOPSYS_UNCONNECTED_2857 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3156 ( .LO ( optlc_net_2856 ) , + .HI ( SYNOPSYS_UNCONNECTED_2858 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3157 ( .LO ( optlc_net_2857 ) , + .HI ( SYNOPSYS_UNCONNECTED_2859 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3158 ( .LO ( optlc_net_2858 ) , + .HI ( SYNOPSYS_UNCONNECTED_2860 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3159 ( .LO ( optlc_net_2859 ) , + .HI ( SYNOPSYS_UNCONNECTED_2861 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3160 ( .LO ( optlc_net_2860 ) , + .HI ( SYNOPSYS_UNCONNECTED_2862 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3161 ( .LO ( optlc_net_2861 ) , + .HI ( SYNOPSYS_UNCONNECTED_2863 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3162 ( .LO ( optlc_net_2862 ) , + .HI ( SYNOPSYS_UNCONNECTED_2864 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3163 ( .LO ( optlc_net_2863 ) , + .HI ( SYNOPSYS_UNCONNECTED_2865 ) ) ; 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SYNOPSYS_UNCONNECTED_2875 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3174 ( .LO ( optlc_net_2874 ) , + .HI ( SYNOPSYS_UNCONNECTED_2876 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3175 ( .LO ( optlc_net_2875 ) , + .HI ( SYNOPSYS_UNCONNECTED_2877 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3176 ( .LO ( optlc_net_2876 ) , + .HI ( SYNOPSYS_UNCONNECTED_2878 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3177 ( .LO ( optlc_net_2877 ) , + .HI ( SYNOPSYS_UNCONNECTED_2879 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3178 ( .LO ( optlc_net_2878 ) , + .HI ( SYNOPSYS_UNCONNECTED_2880 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3179 ( .LO ( optlc_net_2879 ) , + .HI ( SYNOPSYS_UNCONNECTED_2881 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3180 ( .LO ( optlc_net_2880 ) , + .HI ( SYNOPSYS_UNCONNECTED_2882 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3181 ( .LO ( optlc_net_2881 ) , + .HI ( SYNOPSYS_UNCONNECTED_2883 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3182 ( .LO ( optlc_net_2882 ) , + .HI ( SYNOPSYS_UNCONNECTED_2884 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3183 ( .LO ( optlc_net_2883 ) , + .HI ( SYNOPSYS_UNCONNECTED_2885 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3184 ( .LO ( optlc_net_2884 ) , + .HI ( SYNOPSYS_UNCONNECTED_2886 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3185 ( .LO ( optlc_net_2885 ) , + .HI ( SYNOPSYS_UNCONNECTED_2887 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3186 ( .LO ( optlc_net_2886 ) , + .HI ( SYNOPSYS_UNCONNECTED_2888 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3187 ( .LO ( optlc_net_2887 ) , + .HI ( SYNOPSYS_UNCONNECTED_2889 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3188 ( .LO ( optlc_net_2888 ) , + .HI ( SYNOPSYS_UNCONNECTED_2890 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3189 ( .LO ( optlc_net_2889 ) , + .HI ( SYNOPSYS_UNCONNECTED_2891 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3190 ( .LO ( optlc_net_2890 ) , + .HI ( SYNOPSYS_UNCONNECTED_2892 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3191 ( .LO ( optlc_net_2891 ) , + .HI ( SYNOPSYS_UNCONNECTED_2893 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3192 ( .LO ( optlc_net_2892 ) , + .HI ( SYNOPSYS_UNCONNECTED_2894 ) ) ; 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SYNOPSYS_UNCONNECTED_2904 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3203 ( .LO ( optlc_net_2903 ) , + .HI ( SYNOPSYS_UNCONNECTED_2905 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3204 ( .LO ( optlc_net_2904 ) , + .HI ( SYNOPSYS_UNCONNECTED_2906 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3205 ( .LO ( optlc_net_2905 ) , + .HI ( SYNOPSYS_UNCONNECTED_2907 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3206 ( .LO ( optlc_net_2906 ) , + .HI ( SYNOPSYS_UNCONNECTED_2908 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3207 ( .LO ( optlc_net_2907 ) , + .HI ( SYNOPSYS_UNCONNECTED_2909 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3208 ( .LO ( optlc_net_2908 ) , + .HI ( SYNOPSYS_UNCONNECTED_2910 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3209 ( .LO ( optlc_net_2909 ) , + .HI ( SYNOPSYS_UNCONNECTED_2911 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3210 ( .LO ( optlc_net_2910 ) , + .HI ( SYNOPSYS_UNCONNECTED_2912 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3211 ( .LO ( optlc_net_2911 ) , + .HI ( SYNOPSYS_UNCONNECTED_2913 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3212 ( .LO ( optlc_net_2912 ) , + .HI ( SYNOPSYS_UNCONNECTED_2914 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3213 ( .LO ( optlc_net_2913 ) , + .HI ( SYNOPSYS_UNCONNECTED_2915 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3214 ( .LO ( optlc_net_2914 ) , + .HI ( SYNOPSYS_UNCONNECTED_2916 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3215 ( .LO ( optlc_net_2915 ) , + .HI ( SYNOPSYS_UNCONNECTED_2917 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3216 ( .LO ( optlc_net_2916 ) , + .HI ( SYNOPSYS_UNCONNECTED_2918 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3217 ( .LO ( optlc_net_2917 ) , + .HI ( SYNOPSYS_UNCONNECTED_2919 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3218 ( .LO ( optlc_net_2918 ) , + .HI ( SYNOPSYS_UNCONNECTED_2920 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3219 ( .LO ( optlc_net_2919 ) , + .HI ( SYNOPSYS_UNCONNECTED_2921 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3220 ( .LO ( optlc_net_2920 ) , + .HI ( SYNOPSYS_UNCONNECTED_2922 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3221 ( .LO ( optlc_net_2921 ) , + .HI ( SYNOPSYS_UNCONNECTED_2923 ) ) ; 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SYNOPSYS_UNCONNECTED_2933 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3232 ( .LO ( optlc_net_2932 ) , + .HI ( SYNOPSYS_UNCONNECTED_2934 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3233 ( .LO ( optlc_net_2933 ) , + .HI ( SYNOPSYS_UNCONNECTED_2935 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3234 ( .LO ( optlc_net_2934 ) , + .HI ( SYNOPSYS_UNCONNECTED_2936 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3235 ( .LO ( optlc_net_2935 ) , + .HI ( SYNOPSYS_UNCONNECTED_2937 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3236 ( .LO ( optlc_net_2936 ) , + .HI ( SYNOPSYS_UNCONNECTED_2938 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3237 ( .LO ( optlc_net_2937 ) , + .HI ( SYNOPSYS_UNCONNECTED_2939 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3238 ( .LO ( optlc_net_2938 ) , + .HI ( SYNOPSYS_UNCONNECTED_2940 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3239 ( .LO ( optlc_net_2939 ) , + .HI ( SYNOPSYS_UNCONNECTED_2941 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3240 ( .LO ( optlc_net_2940 ) , + .HI ( SYNOPSYS_UNCONNECTED_2942 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3241 ( .LO ( optlc_net_2941 ) , + .HI ( SYNOPSYS_UNCONNECTED_2943 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3242 ( .LO ( optlc_net_2942 ) , + .HI ( SYNOPSYS_UNCONNECTED_2944 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3243 ( .LO ( optlc_net_2943 ) , + .HI ( SYNOPSYS_UNCONNECTED_2945 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3244 ( .LO ( optlc_net_2944 ) , + .HI ( SYNOPSYS_UNCONNECTED_2946 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3245 ( .LO ( optlc_net_2945 ) , + .HI ( SYNOPSYS_UNCONNECTED_2947 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3246 ( .LO ( optlc_net_2946 ) , + .HI ( SYNOPSYS_UNCONNECTED_2948 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3247 ( .LO ( optlc_net_2947 ) , + .HI ( SYNOPSYS_UNCONNECTED_2949 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3248 ( .LO ( optlc_net_2948 ) , + .HI ( SYNOPSYS_UNCONNECTED_2950 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3249 ( .LO ( optlc_net_2949 ) , + .HI ( SYNOPSYS_UNCONNECTED_2951 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3250 ( .LO ( optlc_net_2950 ) , + .HI ( SYNOPSYS_UNCONNECTED_2952 ) ) ; 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SYNOPSYS_UNCONNECTED_2962 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3261 ( .LO ( optlc_net_2961 ) , + .HI ( SYNOPSYS_UNCONNECTED_2963 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3262 ( .LO ( optlc_net_2962 ) , + .HI ( SYNOPSYS_UNCONNECTED_2964 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3263 ( .LO ( optlc_net_2963 ) , + .HI ( SYNOPSYS_UNCONNECTED_2965 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3264 ( .LO ( optlc_net_2964 ) , + .HI ( SYNOPSYS_UNCONNECTED_2966 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3265 ( .LO ( optlc_net_2965 ) , + .HI ( SYNOPSYS_UNCONNECTED_2967 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3266 ( .LO ( optlc_net_2966 ) , + .HI ( SYNOPSYS_UNCONNECTED_2968 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3267 ( .LO ( optlc_net_2967 ) , + .HI ( SYNOPSYS_UNCONNECTED_2969 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3268 ( .LO ( optlc_net_2968 ) , + .HI ( SYNOPSYS_UNCONNECTED_2970 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3269 ( .LO ( optlc_net_2969 ) , + .HI ( SYNOPSYS_UNCONNECTED_2971 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3270 ( .LO ( optlc_net_2970 ) , + .HI ( SYNOPSYS_UNCONNECTED_2972 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3271 ( .LO ( optlc_net_2971 ) , + .HI ( SYNOPSYS_UNCONNECTED_2973 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3272 ( .LO ( optlc_net_2972 ) , + .HI ( SYNOPSYS_UNCONNECTED_2974 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3273 ( .LO ( optlc_net_2973 ) , + .HI ( SYNOPSYS_UNCONNECTED_2975 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3274 ( .LO ( optlc_net_2974 ) , + .HI ( SYNOPSYS_UNCONNECTED_2976 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3275 ( .LO ( optlc_net_2975 ) , + .HI ( SYNOPSYS_UNCONNECTED_2977 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3276 ( .LO ( optlc_net_2976 ) , + .HI ( SYNOPSYS_UNCONNECTED_2978 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3277 ( .LO ( optlc_net_2977 ) , + .HI ( SYNOPSYS_UNCONNECTED_2979 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3278 ( .LO ( optlc_net_2978 ) , + .HI ( SYNOPSYS_UNCONNECTED_2980 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3279 ( .LO ( optlc_net_2979 ) , + .HI ( SYNOPSYS_UNCONNECTED_2981 ) ) ; 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SYNOPSYS_UNCONNECTED_2991 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3290 ( .LO ( optlc_net_2990 ) , + .HI ( SYNOPSYS_UNCONNECTED_2992 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3291 ( .LO ( optlc_net_2991 ) , + .HI ( SYNOPSYS_UNCONNECTED_2993 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3292 ( .LO ( optlc_net_2992 ) , + .HI ( SYNOPSYS_UNCONNECTED_2994 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3293 ( .LO ( optlc_net_2993 ) , + .HI ( SYNOPSYS_UNCONNECTED_2995 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3294 ( .LO ( optlc_net_2994 ) , + .HI ( SYNOPSYS_UNCONNECTED_2996 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3295 ( .LO ( optlc_net_2995 ) , + .HI ( SYNOPSYS_UNCONNECTED_2997 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3296 ( .LO ( optlc_net_2996 ) , + .HI ( SYNOPSYS_UNCONNECTED_2998 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3297 ( .LO ( optlc_net_2997 ) , + .HI ( SYNOPSYS_UNCONNECTED_2999 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3298 ( .LO ( optlc_net_2998 ) , + .HI ( SYNOPSYS_UNCONNECTED_3000 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3299 ( .LO ( optlc_net_2999 ) , + .HI ( SYNOPSYS_UNCONNECTED_3001 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3300 ( .LO ( optlc_net_3000 ) , + .HI ( SYNOPSYS_UNCONNECTED_3002 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3301 ( .LO ( optlc_net_3001 ) , + .HI ( SYNOPSYS_UNCONNECTED_3003 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3302 ( .LO ( optlc_net_3002 ) , + .HI ( SYNOPSYS_UNCONNECTED_3004 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3303 ( .LO ( optlc_net_3003 ) , + .HI ( SYNOPSYS_UNCONNECTED_3005 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3304 ( .LO ( optlc_net_3004 ) , + .HI ( SYNOPSYS_UNCONNECTED_3006 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3305 ( .LO ( optlc_net_3005 ) , + .HI ( SYNOPSYS_UNCONNECTED_3007 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3306 ( .LO ( optlc_net_3006 ) , + .HI ( SYNOPSYS_UNCONNECTED_3008 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3307 ( .LO ( optlc_net_3007 ) , + .HI ( SYNOPSYS_UNCONNECTED_3009 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3308 ( .LO ( optlc_net_3008 ) , + .HI ( SYNOPSYS_UNCONNECTED_3010 ) ) ; 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SYNOPSYS_UNCONNECTED_3020 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3319 ( .LO ( optlc_net_3019 ) , + .HI ( SYNOPSYS_UNCONNECTED_3021 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3320 ( .LO ( optlc_net_3020 ) , + .HI ( SYNOPSYS_UNCONNECTED_3022 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3321 ( .LO ( optlc_net_3021 ) , + .HI ( SYNOPSYS_UNCONNECTED_3023 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3322 ( .LO ( optlc_net_3022 ) , + .HI ( SYNOPSYS_UNCONNECTED_3024 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3323 ( .LO ( optlc_net_3023 ) , + .HI ( SYNOPSYS_UNCONNECTED_3025 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3324 ( .LO ( optlc_net_3024 ) , + .HI ( SYNOPSYS_UNCONNECTED_3026 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3325 ( .LO ( optlc_net_3025 ) , + .HI ( SYNOPSYS_UNCONNECTED_3027 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3327 ( .LO ( optlc_net_3026 ) , + .HI ( SYNOPSYS_UNCONNECTED_3028 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3328 ( .LO ( optlc_net_3027 ) , + .HI ( SYNOPSYS_UNCONNECTED_3029 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3329 ( .LO ( optlc_net_3028 ) , + .HI ( SYNOPSYS_UNCONNECTED_3030 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3330 ( .LO ( optlc_net_3029 ) , + .HI ( SYNOPSYS_UNCONNECTED_3031 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3331 ( .LO ( optlc_net_3030 ) , + .HI ( SYNOPSYS_UNCONNECTED_3032 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3332 ( .LO ( optlc_net_3031 ) , + .HI ( SYNOPSYS_UNCONNECTED_3033 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3333 ( .LO ( optlc_net_3032 ) , + .HI ( SYNOPSYS_UNCONNECTED_3034 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3334 ( .LO ( optlc_net_3033 ) , + .HI ( SYNOPSYS_UNCONNECTED_3035 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3335 ( .LO ( optlc_net_3034 ) , + .HI ( SYNOPSYS_UNCONNECTED_3036 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3336 ( .LO ( optlc_net_3035 ) , + .HI ( SYNOPSYS_UNCONNECTED_3037 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3337 ( .LO ( optlc_net_3036 ) , + .HI ( SYNOPSYS_UNCONNECTED_3038 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3338 ( .LO ( optlc_net_3037 ) , + .HI ( SYNOPSYS_UNCONNECTED_3039 ) ) ; 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SYNOPSYS_UNCONNECTED_3049 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3349 ( .LO ( optlc_net_3048 ) , + .HI ( SYNOPSYS_UNCONNECTED_3050 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3350 ( .LO ( optlc_net_3049 ) , + .HI ( SYNOPSYS_UNCONNECTED_3051 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3351 ( .LO ( optlc_net_3050 ) , + .HI ( SYNOPSYS_UNCONNECTED_3052 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3352 ( .LO ( optlc_net_3051 ) , + .HI ( SYNOPSYS_UNCONNECTED_3053 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3353 ( .LO ( optlc_net_3052 ) , + .HI ( SYNOPSYS_UNCONNECTED_3054 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3354 ( .LO ( optlc_net_3053 ) , + .HI ( SYNOPSYS_UNCONNECTED_3055 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3355 ( .LO ( optlc_net_3054 ) , + .HI ( SYNOPSYS_UNCONNECTED_3056 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3356 ( .LO ( optlc_net_3055 ) , + .HI ( SYNOPSYS_UNCONNECTED_3057 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3357 ( .LO ( optlc_net_3056 ) , + .HI ( SYNOPSYS_UNCONNECTED_3058 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3358 ( .LO ( optlc_net_3057 ) , + .HI ( SYNOPSYS_UNCONNECTED_3059 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3359 ( .LO ( optlc_net_3058 ) , + .HI ( SYNOPSYS_UNCONNECTED_3060 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3360 ( .LO ( optlc_net_3059 ) , + .HI ( SYNOPSYS_UNCONNECTED_3061 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3361 ( .LO ( optlc_net_3060 ) , + .HI ( SYNOPSYS_UNCONNECTED_3062 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3362 ( .LO ( optlc_net_3061 ) , + .HI ( SYNOPSYS_UNCONNECTED_3063 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3363 ( .LO ( optlc_net_3062 ) , + .HI ( SYNOPSYS_UNCONNECTED_3064 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3364 ( .LO ( optlc_net_3063 ) , + .HI ( SYNOPSYS_UNCONNECTED_3065 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3365 ( .LO ( optlc_net_3064 ) , + .HI ( SYNOPSYS_UNCONNECTED_3066 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3366 ( .LO ( optlc_net_3065 ) , + .HI ( SYNOPSYS_UNCONNECTED_3067 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3367 ( .LO ( optlc_net_3066 ) , + .HI ( SYNOPSYS_UNCONNECTED_3068 ) ) ; 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SYNOPSYS_UNCONNECTED_3078 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3378 ( .LO ( optlc_net_3077 ) , + .HI ( SYNOPSYS_UNCONNECTED_3079 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3379 ( .LO ( optlc_net_3078 ) , + .HI ( SYNOPSYS_UNCONNECTED_3080 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3380 ( .LO ( optlc_net_3079 ) , + .HI ( SYNOPSYS_UNCONNECTED_3081 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3381 ( .LO ( optlc_net_3080 ) , + .HI ( SYNOPSYS_UNCONNECTED_3082 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3382 ( .LO ( optlc_net_3081 ) , + .HI ( SYNOPSYS_UNCONNECTED_3083 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3383 ( .LO ( optlc_net_3082 ) , + .HI ( SYNOPSYS_UNCONNECTED_3084 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3384 ( .LO ( optlc_net_3083 ) , + .HI ( SYNOPSYS_UNCONNECTED_3085 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3385 ( .LO ( optlc_net_3084 ) , + .HI ( SYNOPSYS_UNCONNECTED_3086 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3386 ( .LO ( optlc_net_3085 ) , + .HI ( SYNOPSYS_UNCONNECTED_3087 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3387 ( .LO ( optlc_net_3086 ) , + .HI ( SYNOPSYS_UNCONNECTED_3088 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3388 ( .LO ( optlc_net_3087 ) , + .HI ( SYNOPSYS_UNCONNECTED_3089 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3389 ( .LO ( optlc_net_3088 ) , + .HI ( SYNOPSYS_UNCONNECTED_3090 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3390 ( .LO ( optlc_net_3089 ) , + .HI ( SYNOPSYS_UNCONNECTED_3091 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3391 ( .LO ( optlc_net_3090 ) , + .HI ( SYNOPSYS_UNCONNECTED_3092 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3392 ( .LO ( optlc_net_3091 ) , + .HI ( SYNOPSYS_UNCONNECTED_3093 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3393 ( .LO ( optlc_net_3092 ) , + .HI ( SYNOPSYS_UNCONNECTED_3094 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3394 ( .LO ( optlc_net_3093 ) , + .HI ( SYNOPSYS_UNCONNECTED_3095 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3395 ( .LO ( optlc_net_3094 ) , + .HI ( SYNOPSYS_UNCONNECTED_3096 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3396 ( .LO ( optlc_net_3095 ) , + .HI ( SYNOPSYS_UNCONNECTED_3097 ) ) ; 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SYNOPSYS_UNCONNECTED_3107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3407 ( .LO ( optlc_net_3106 ) , + .HI ( SYNOPSYS_UNCONNECTED_3108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3408 ( .LO ( optlc_net_3107 ) , + .HI ( SYNOPSYS_UNCONNECTED_3109 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3409 ( .LO ( optlc_net_3108 ) , + .HI ( SYNOPSYS_UNCONNECTED_3110 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3410 ( .LO ( optlc_net_3109 ) , + .HI ( SYNOPSYS_UNCONNECTED_3111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3411 ( .LO ( optlc_net_3110 ) , + .HI ( SYNOPSYS_UNCONNECTED_3112 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3412 ( .LO ( optlc_net_3111 ) , + .HI ( SYNOPSYS_UNCONNECTED_3113 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3413 ( .LO ( optlc_net_3112 ) , + .HI ( SYNOPSYS_UNCONNECTED_3114 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3414 ( .LO ( optlc_net_3113 ) , + .HI ( SYNOPSYS_UNCONNECTED_3115 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3415 ( .LO ( optlc_net_3114 ) , + .HI ( SYNOPSYS_UNCONNECTED_3116 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3416 ( .LO ( optlc_net_3115 ) , + .HI ( SYNOPSYS_UNCONNECTED_3117 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3417 ( .LO ( optlc_net_3116 ) , + .HI ( SYNOPSYS_UNCONNECTED_3118 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3418 ( .LO ( optlc_net_3117 ) , + .HI ( SYNOPSYS_UNCONNECTED_3119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3419 ( .LO ( optlc_net_3118 ) , + .HI ( SYNOPSYS_UNCONNECTED_3120 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3420 ( .LO ( optlc_net_3119 ) , + .HI ( SYNOPSYS_UNCONNECTED_3121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3421 ( .LO ( optlc_net_3120 ) , + .HI ( SYNOPSYS_UNCONNECTED_3122 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3422 ( .LO ( optlc_net_3121 ) , + .HI ( SYNOPSYS_UNCONNECTED_3123 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3423 ( .LO ( optlc_net_3122 ) , + .HI ( SYNOPSYS_UNCONNECTED_3124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3424 ( .LO ( optlc_net_3123 ) , + .HI ( SYNOPSYS_UNCONNECTED_3125 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3425 ( .LO ( optlc_net_3124 ) , + .HI ( SYNOPSYS_UNCONNECTED_3126 ) ) ; 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SYNOPSYS_UNCONNECTED_3136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3436 ( .LO ( optlc_net_3135 ) , + .HI ( SYNOPSYS_UNCONNECTED_3137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3437 ( .LO ( optlc_net_3136 ) , + .HI ( SYNOPSYS_UNCONNECTED_3138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3438 ( .LO ( optlc_net_3137 ) , + .HI ( SYNOPSYS_UNCONNECTED_3139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3439 ( .LO ( optlc_net_3138 ) , + .HI ( SYNOPSYS_UNCONNECTED_3140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3440 ( .LO ( optlc_net_3139 ) , + .HI ( SYNOPSYS_UNCONNECTED_3141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3441 ( .LO ( optlc_net_3140 ) , + .HI ( SYNOPSYS_UNCONNECTED_3142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3442 ( .LO ( optlc_net_3141 ) , + .HI ( SYNOPSYS_UNCONNECTED_3143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3443 ( .LO ( optlc_net_3142 ) , + .HI ( SYNOPSYS_UNCONNECTED_3144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3444 ( .LO ( optlc_net_3143 ) , + .HI ( SYNOPSYS_UNCONNECTED_3145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3445 ( .LO ( optlc_net_3144 ) , + .HI ( SYNOPSYS_UNCONNECTED_3146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3446 ( .LO ( optlc_net_3145 ) , + .HI ( SYNOPSYS_UNCONNECTED_3147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3447 ( .LO ( optlc_net_3146 ) , + .HI ( SYNOPSYS_UNCONNECTED_3148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3448 ( .LO ( optlc_net_3147 ) , + .HI ( SYNOPSYS_UNCONNECTED_3149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3449 ( .LO ( optlc_net_3148 ) , + .HI ( SYNOPSYS_UNCONNECTED_3150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3450 ( .LO ( optlc_net_3149 ) , + .HI ( SYNOPSYS_UNCONNECTED_3151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3451 ( .LO ( optlc_net_3150 ) , + .HI ( SYNOPSYS_UNCONNECTED_3152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3452 ( .LO ( optlc_net_3151 ) , + .HI ( SYNOPSYS_UNCONNECTED_3153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3453 ( .LO ( optlc_net_3152 ) , + .HI ( SYNOPSYS_UNCONNECTED_3154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3454 ( .LO ( optlc_net_3153 ) , + .HI ( SYNOPSYS_UNCONNECTED_3155 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3455 ( .LO ( optlc_net_3154 ) , + .HI ( SYNOPSYS_UNCONNECTED_3156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3456 ( .LO ( optlc_net_3155 ) , + .HI ( SYNOPSYS_UNCONNECTED_3157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3457 ( .LO ( optlc_net_3156 ) , + .HI ( SYNOPSYS_UNCONNECTED_3158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3458 ( .LO ( optlc_net_3157 ) , + .HI ( SYNOPSYS_UNCONNECTED_3159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3459 ( .LO ( optlc_net_3158 ) , + .HI ( SYNOPSYS_UNCONNECTED_3160 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3460 ( .LO ( optlc_net_3159 ) , + .HI ( SYNOPSYS_UNCONNECTED_3161 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3461 ( .LO ( optlc_net_3160 ) , + .HI ( SYNOPSYS_UNCONNECTED_3162 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3462 ( .LO ( optlc_net_3161 ) , + .HI ( SYNOPSYS_UNCONNECTED_3163 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3463 ( .LO ( optlc_net_3162 ) , + .HI ( SYNOPSYS_UNCONNECTED_3164 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3464 ( .LO ( optlc_net_3163 ) , + .HI ( SYNOPSYS_UNCONNECTED_3165 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3465 ( .LO ( optlc_net_3164 ) , + .HI ( SYNOPSYS_UNCONNECTED_3166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3466 ( .LO ( optlc_net_3165 ) , + .HI ( SYNOPSYS_UNCONNECTED_3167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3467 ( .LO ( optlc_net_3166 ) , + .HI ( SYNOPSYS_UNCONNECTED_3168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3468 ( .LO ( optlc_net_3167 ) , + .HI ( SYNOPSYS_UNCONNECTED_3169 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3469 ( .LO ( optlc_net_3168 ) , + .HI ( SYNOPSYS_UNCONNECTED_3170 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3470 ( .LO ( optlc_net_3169 ) , + .HI ( SYNOPSYS_UNCONNECTED_3171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3471 ( .LO ( optlc_net_3170 ) , + .HI ( SYNOPSYS_UNCONNECTED_3172 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3472 ( .LO ( optlc_net_3171 ) , + .HI ( SYNOPSYS_UNCONNECTED_3173 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3473 ( .LO ( optlc_net_3172 ) , + .HI ( SYNOPSYS_UNCONNECTED_3174 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3474 ( .LO ( optlc_net_3173 ) , + .HI ( SYNOPSYS_UNCONNECTED_3175 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3475 ( .LO ( optlc_net_3174 ) , + .HI ( SYNOPSYS_UNCONNECTED_3176 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3476 ( .LO ( optlc_net_3175 ) , + .HI ( SYNOPSYS_UNCONNECTED_3177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3477 ( .LO ( optlc_net_3176 ) , + .HI ( SYNOPSYS_UNCONNECTED_3178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3478 ( .LO ( optlc_net_3177 ) , + .HI ( SYNOPSYS_UNCONNECTED_3179 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3479 ( .LO ( optlc_net_3178 ) , + .HI ( SYNOPSYS_UNCONNECTED_3180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3480 ( .LO ( optlc_net_3179 ) , + .HI ( SYNOPSYS_UNCONNECTED_3181 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3481 ( .LO ( optlc_net_3180 ) , + .HI ( SYNOPSYS_UNCONNECTED_3182 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3482 ( .LO ( optlc_net_3181 ) , + .HI ( SYNOPSYS_UNCONNECTED_3183 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3483 ( .LO ( optlc_net_3182 ) , + .HI ( SYNOPSYS_UNCONNECTED_3184 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3484 ( .LO ( optlc_net_3183 ) , + .HI ( SYNOPSYS_UNCONNECTED_3185 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3485 ( .LO ( optlc_net_3184 ) , + .HI ( SYNOPSYS_UNCONNECTED_3186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3486 ( .LO ( optlc_net_3185 ) , + .HI ( SYNOPSYS_UNCONNECTED_3187 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3487 ( .LO ( optlc_net_3186 ) , + .HI ( SYNOPSYS_UNCONNECTED_3188 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3488 ( .LO ( optlc_net_3187 ) , + .HI ( SYNOPSYS_UNCONNECTED_3189 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3489 ( .LO ( optlc_net_3188 ) , + .HI ( SYNOPSYS_UNCONNECTED_3190 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3490 ( .LO ( optlc_net_3189 ) , + .HI ( SYNOPSYS_UNCONNECTED_3191 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3491 ( .LO ( optlc_net_3190 ) , + .HI ( SYNOPSYS_UNCONNECTED_3192 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3492 ( .LO ( optlc_net_3191 ) , + .HI ( SYNOPSYS_UNCONNECTED_3193 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3493 ( .LO ( optlc_net_3192 ) , + .HI ( SYNOPSYS_UNCONNECTED_3194 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3494 ( .LO ( optlc_net_3193 ) , + .HI ( SYNOPSYS_UNCONNECTED_3195 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3495 ( .LO ( optlc_net_3194 ) , + .HI ( SYNOPSYS_UNCONNECTED_3196 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3496 ( .LO ( optlc_net_3195 ) , + .HI ( SYNOPSYS_UNCONNECTED_3197 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3497 ( .LO ( optlc_net_3196 ) , + .HI ( SYNOPSYS_UNCONNECTED_3198 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3498 ( .LO ( optlc_net_3197 ) , + .HI ( SYNOPSYS_UNCONNECTED_3199 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3499 ( .LO ( optlc_net_3198 ) , + .HI ( SYNOPSYS_UNCONNECTED_3200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3500 ( .LO ( optlc_net_3199 ) , + .HI ( SYNOPSYS_UNCONNECTED_3201 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3501 ( .LO ( optlc_net_3200 ) , + .HI ( SYNOPSYS_UNCONNECTED_3202 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3502 ( .LO ( optlc_net_3201 ) , + .HI ( SYNOPSYS_UNCONNECTED_3203 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3503 ( .LO ( optlc_net_3202 ) , + .HI ( SYNOPSYS_UNCONNECTED_3204 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3504 ( .LO ( optlc_net_3203 ) , + .HI ( SYNOPSYS_UNCONNECTED_3205 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3505 ( .LO ( optlc_net_3204 ) , + .HI ( SYNOPSYS_UNCONNECTED_3206 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3506 ( .LO ( optlc_net_3205 ) , + .HI ( SYNOPSYS_UNCONNECTED_3207 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3507 ( .LO ( optlc_net_3206 ) , + .HI ( SYNOPSYS_UNCONNECTED_3208 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3508 ( .LO ( optlc_net_3207 ) , + .HI ( SYNOPSYS_UNCONNECTED_3209 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3509 ( .LO ( optlc_net_3208 ) , + .HI ( SYNOPSYS_UNCONNECTED_3210 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3510 ( .LO ( optlc_net_3209 ) , + .HI ( SYNOPSYS_UNCONNECTED_3211 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3511 ( .LO ( optlc_net_3210 ) , + .HI ( SYNOPSYS_UNCONNECTED_3212 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3512 ( .LO ( optlc_net_3211 ) , + .HI ( SYNOPSYS_UNCONNECTED_3213 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3513 ( .LO ( optlc_net_3212 ) , + .HI ( SYNOPSYS_UNCONNECTED_3214 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3514 ( .LO ( optlc_net_3213 ) , + .HI ( SYNOPSYS_UNCONNECTED_3215 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3515 ( .LO ( optlc_net_3214 ) , + .HI ( SYNOPSYS_UNCONNECTED_3216 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3516 ( .LO ( optlc_net_3215 ) , + .HI ( SYNOPSYS_UNCONNECTED_3217 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3517 ( .LO ( optlc_net_3216 ) , + .HI ( SYNOPSYS_UNCONNECTED_3218 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3518 ( .LO ( optlc_net_3217 ) , + .HI ( SYNOPSYS_UNCONNECTED_3219 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3519 ( .LO ( optlc_net_3218 ) , + .HI ( SYNOPSYS_UNCONNECTED_3220 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3520 ( .LO ( optlc_net_3219 ) , + .HI ( SYNOPSYS_UNCONNECTED_3221 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3521 ( .LO ( optlc_net_3220 ) , + .HI ( SYNOPSYS_UNCONNECTED_3222 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3522 ( .LO ( optlc_net_3221 ) , + .HI ( SYNOPSYS_UNCONNECTED_3223 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3523 ( .LO ( optlc_net_3222 ) , + .HI ( SYNOPSYS_UNCONNECTED_3224 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3524 ( .LO ( optlc_net_3223 ) , + .HI ( SYNOPSYS_UNCONNECTED_3225 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3525 ( .LO ( optlc_net_3224 ) , + .HI ( SYNOPSYS_UNCONNECTED_3226 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3526 ( .LO ( optlc_net_3225 ) , + .HI ( SYNOPSYS_UNCONNECTED_3227 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3527 ( .LO ( optlc_net_3226 ) , + .HI ( SYNOPSYS_UNCONNECTED_3228 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3528 ( .LO ( optlc_net_3227 ) , + .HI ( SYNOPSYS_UNCONNECTED_3229 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3529 ( .LO ( optlc_net_3228 ) , + .HI ( SYNOPSYS_UNCONNECTED_3230 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3530 ( .LO ( optlc_net_3229 ) , + .HI ( SYNOPSYS_UNCONNECTED_3231 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3531 ( .LO ( optlc_net_3230 ) , + .HI ( SYNOPSYS_UNCONNECTED_3232 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3532 ( .LO ( optlc_net_3231 ) , + .HI ( SYNOPSYS_UNCONNECTED_3233 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3533 ( .LO ( optlc_net_3232 ) , + .HI ( SYNOPSYS_UNCONNECTED_3234 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3534 ( .LO ( optlc_net_3233 ) , + .HI ( SYNOPSYS_UNCONNECTED_3235 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3535 ( .LO ( optlc_net_3234 ) , + .HI ( SYNOPSYS_UNCONNECTED_3236 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3536 ( .LO ( optlc_net_3235 ) , + .HI ( SYNOPSYS_UNCONNECTED_3237 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3537 ( .LO ( optlc_net_3236 ) , + .HI ( SYNOPSYS_UNCONNECTED_3238 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3538 ( .LO ( optlc_net_3237 ) , + .HI ( SYNOPSYS_UNCONNECTED_3239 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3539 ( .LO ( optlc_net_3238 ) , + .HI ( SYNOPSYS_UNCONNECTED_3240 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3540 ( .LO ( optlc_net_3239 ) , + .HI ( SYNOPSYS_UNCONNECTED_3241 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3541 ( .LO ( optlc_net_3240 ) , + .HI ( SYNOPSYS_UNCONNECTED_3242 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3542 ( .LO ( optlc_net_3241 ) , + .HI ( SYNOPSYS_UNCONNECTED_3243 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3543 ( .LO ( optlc_net_3242 ) , + .HI ( SYNOPSYS_UNCONNECTED_3244 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3544 ( .LO ( optlc_net_3243 ) , + .HI ( SYNOPSYS_UNCONNECTED_3245 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3545 ( .LO ( optlc_net_3244 ) , + .HI ( SYNOPSYS_UNCONNECTED_3246 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3546 ( .LO ( optlc_net_3245 ) , + .HI ( SYNOPSYS_UNCONNECTED_3247 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3547 ( .LO ( optlc_net_3246 ) , + .HI ( SYNOPSYS_UNCONNECTED_3248 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3548 ( .LO ( optlc_net_3247 ) , + .HI ( SYNOPSYS_UNCONNECTED_3249 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3549 ( .LO ( optlc_net_3248 ) , + .HI ( SYNOPSYS_UNCONNECTED_3250 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3550 ( .LO ( optlc_net_3249 ) , + .HI ( SYNOPSYS_UNCONNECTED_3251 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3551 ( .LO ( optlc_net_3250 ) , + .HI ( SYNOPSYS_UNCONNECTED_3252 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3552 ( .LO ( optlc_net_3251 ) , + .HI ( SYNOPSYS_UNCONNECTED_3253 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3553 ( .LO ( optlc_net_3252 ) , + .HI ( SYNOPSYS_UNCONNECTED_3254 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3554 ( .LO ( optlc_net_3253 ) , + .HI ( SYNOPSYS_UNCONNECTED_3255 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3555 ( .LO ( optlc_net_3254 ) , + .HI ( SYNOPSYS_UNCONNECTED_3256 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3556 ( .LO ( optlc_net_3255 ) , + .HI ( SYNOPSYS_UNCONNECTED_3257 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3557 ( .LO ( optlc_net_3256 ) , + .HI ( SYNOPSYS_UNCONNECTED_3258 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3558 ( .LO ( optlc_net_3257 ) , + .HI ( SYNOPSYS_UNCONNECTED_3259 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3559 ( .LO ( optlc_net_3258 ) , + .HI ( SYNOPSYS_UNCONNECTED_3260 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3560 ( .LO ( optlc_net_3259 ) , + .HI ( SYNOPSYS_UNCONNECTED_3261 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3561 ( .LO ( optlc_net_3260 ) , + .HI ( SYNOPSYS_UNCONNECTED_3262 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3562 ( .LO ( optlc_net_3261 ) , + .HI ( SYNOPSYS_UNCONNECTED_3263 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3563 ( .LO ( optlc_net_3262 ) , + .HI ( SYNOPSYS_UNCONNECTED_3264 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3564 ( .LO ( optlc_net_3263 ) , + .HI ( SYNOPSYS_UNCONNECTED_3265 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3565 ( .LO ( optlc_net_3264 ) , + .HI ( SYNOPSYS_UNCONNECTED_3266 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3566 ( .LO ( optlc_net_3265 ) , + .HI ( SYNOPSYS_UNCONNECTED_3267 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3567 ( .LO ( optlc_net_3266 ) , + .HI ( SYNOPSYS_UNCONNECTED_3268 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3568 ( .LO ( optlc_net_3267 ) , + .HI ( SYNOPSYS_UNCONNECTED_3269 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3569 ( .LO ( optlc_net_3268 ) , + .HI ( SYNOPSYS_UNCONNECTED_3270 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3570 ( .LO ( optlc_net_3269 ) , + .HI ( SYNOPSYS_UNCONNECTED_3271 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3571 ( .LO ( optlc_net_3270 ) , + .HI ( SYNOPSYS_UNCONNECTED_3272 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3572 ( .LO ( optlc_net_3271 ) , + .HI ( SYNOPSYS_UNCONNECTED_3273 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3573 ( .LO ( optlc_net_3272 ) , + .HI ( SYNOPSYS_UNCONNECTED_3274 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3574 ( .LO ( optlc_net_3273 ) , + .HI ( SYNOPSYS_UNCONNECTED_3275 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3575 ( .LO ( optlc_net_3274 ) , + .HI ( SYNOPSYS_UNCONNECTED_3276 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3576 ( .LO ( optlc_net_3275 ) , + .HI ( SYNOPSYS_UNCONNECTED_3277 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3577 ( .LO ( optlc_net_3276 ) , + .HI ( SYNOPSYS_UNCONNECTED_3278 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3578 ( .LO ( optlc_net_3277 ) , + .HI ( SYNOPSYS_UNCONNECTED_3279 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3579 ( .LO ( optlc_net_3278 ) , + .HI ( SYNOPSYS_UNCONNECTED_3280 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3580 ( .LO ( optlc_net_3279 ) , + .HI ( SYNOPSYS_UNCONNECTED_3281 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3581 ( .LO ( optlc_net_3280 ) , + .HI ( SYNOPSYS_UNCONNECTED_3282 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3582 ( .LO ( optlc_net_3281 ) , + .HI ( SYNOPSYS_UNCONNECTED_3283 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3583 ( .LO ( optlc_net_3282 ) , + .HI ( SYNOPSYS_UNCONNECTED_3284 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3584 ( .LO ( optlc_net_3283 ) , + .HI ( SYNOPSYS_UNCONNECTED_3285 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3585 ( .LO ( optlc_net_3284 ) , + .HI ( SYNOPSYS_UNCONNECTED_3286 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3586 ( .LO ( optlc_net_3285 ) , + .HI ( SYNOPSYS_UNCONNECTED_3287 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3587 ( .LO ( optlc_net_3286 ) , + .HI ( SYNOPSYS_UNCONNECTED_3288 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3588 ( .LO ( optlc_net_3287 ) , + .HI ( SYNOPSYS_UNCONNECTED_3289 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3589 ( .LO ( optlc_net_3288 ) , + .HI ( SYNOPSYS_UNCONNECTED_3290 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3590 ( .LO ( optlc_net_3289 ) , + .HI ( SYNOPSYS_UNCONNECTED_3291 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3591 ( .LO ( optlc_net_3290 ) , + .HI ( SYNOPSYS_UNCONNECTED_3292 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3592 ( .LO ( optlc_net_3291 ) , + .HI ( SYNOPSYS_UNCONNECTED_3293 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3593 ( .LO ( optlc_net_3292 ) , + .HI ( SYNOPSYS_UNCONNECTED_3294 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3594 ( .LO ( optlc_net_3293 ) , + .HI ( SYNOPSYS_UNCONNECTED_3295 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3595 ( .LO ( optlc_net_3294 ) , + .HI ( SYNOPSYS_UNCONNECTED_3296 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3596 ( .LO ( optlc_net_3295 ) , + .HI ( SYNOPSYS_UNCONNECTED_3297 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3597 ( .LO ( optlc_net_3296 ) , + .HI ( SYNOPSYS_UNCONNECTED_3298 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3598 ( .LO ( optlc_net_3297 ) , + .HI ( SYNOPSYS_UNCONNECTED_3299 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3599 ( .LO ( optlc_net_3298 ) , + .HI ( SYNOPSYS_UNCONNECTED_3300 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3600 ( .LO ( optlc_net_3299 ) , + .HI ( SYNOPSYS_UNCONNECTED_3301 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3601 ( .LO ( optlc_net_3300 ) , + .HI ( SYNOPSYS_UNCONNECTED_3302 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3602 ( .LO ( optlc_net_3301 ) , + .HI ( SYNOPSYS_UNCONNECTED_3303 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3603 ( .LO ( optlc_net_3302 ) , + .HI ( SYNOPSYS_UNCONNECTED_3304 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3604 ( .LO ( optlc_net_3303 ) , + .HI ( SYNOPSYS_UNCONNECTED_3305 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3605 ( .LO ( optlc_net_3304 ) , + .HI ( SYNOPSYS_UNCONNECTED_3306 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3606 ( .LO ( optlc_net_3305 ) , + .HI ( SYNOPSYS_UNCONNECTED_3307 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3607 ( .LO ( optlc_net_3306 ) , + .HI ( SYNOPSYS_UNCONNECTED_3308 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3608 ( .LO ( optlc_net_3307 ) , + .HI ( SYNOPSYS_UNCONNECTED_3309 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3609 ( .LO ( optlc_net_3308 ) , + .HI ( SYNOPSYS_UNCONNECTED_3310 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3610 ( .LO ( optlc_net_3309 ) , + .HI ( SYNOPSYS_UNCONNECTED_3311 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3611 ( .LO ( optlc_net_3310 ) , + .HI ( SYNOPSYS_UNCONNECTED_3312 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3612 ( .LO ( optlc_net_3311 ) , + .HI ( SYNOPSYS_UNCONNECTED_3313 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3613 ( .LO ( optlc_net_3312 ) , + .HI ( SYNOPSYS_UNCONNECTED_3314 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3614 ( .LO ( optlc_net_3313 ) , + .HI ( SYNOPSYS_UNCONNECTED_3315 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3615 ( .LO ( optlc_net_3314 ) , + .HI ( SYNOPSYS_UNCONNECTED_3316 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3616 ( .LO ( optlc_net_3315 ) , + .HI ( SYNOPSYS_UNCONNECTED_3317 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3617 ( .LO ( optlc_net_3316 ) , + .HI ( SYNOPSYS_UNCONNECTED_3318 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3618 ( .LO ( optlc_net_3317 ) , + .HI ( SYNOPSYS_UNCONNECTED_3319 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3619 ( .LO ( optlc_net_3318 ) , + .HI ( SYNOPSYS_UNCONNECTED_3320 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3620 ( .LO ( optlc_net_3319 ) , + .HI ( SYNOPSYS_UNCONNECTED_3321 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3621 ( .LO ( optlc_net_3320 ) , + .HI ( SYNOPSYS_UNCONNECTED_3322 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3622 ( .LO ( optlc_net_3321 ) , + .HI ( SYNOPSYS_UNCONNECTED_3323 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3623 ( .LO ( optlc_net_3322 ) , + .HI ( SYNOPSYS_UNCONNECTED_3324 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3624 ( .LO ( optlc_net_3323 ) , + .HI ( SYNOPSYS_UNCONNECTED_3325 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3625 ( .LO ( optlc_net_3324 ) , + .HI ( SYNOPSYS_UNCONNECTED_3326 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3626 ( .LO ( optlc_net_3325 ) , + .HI ( SYNOPSYS_UNCONNECTED_3327 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3627 ( .LO ( optlc_net_3326 ) , + .HI ( SYNOPSYS_UNCONNECTED_3328 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3628 ( .LO ( optlc_net_3327 ) , + .HI ( SYNOPSYS_UNCONNECTED_3329 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3629 ( .LO ( optlc_net_3328 ) , + .HI ( SYNOPSYS_UNCONNECTED_3330 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3630 ( .LO ( optlc_net_3329 ) , + .HI ( SYNOPSYS_UNCONNECTED_3331 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3631 ( .LO ( optlc_net_3330 ) , + .HI ( SYNOPSYS_UNCONNECTED_3332 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3632 ( .LO ( optlc_net_3331 ) , + .HI ( SYNOPSYS_UNCONNECTED_3333 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3633 ( .LO ( optlc_net_3332 ) , + .HI ( SYNOPSYS_UNCONNECTED_3334 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3634 ( .LO ( optlc_net_3333 ) , + .HI ( SYNOPSYS_UNCONNECTED_3335 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3635 ( .LO ( optlc_net_3334 ) , + .HI ( SYNOPSYS_UNCONNECTED_3336 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3636 ( .LO ( optlc_net_3335 ) , + .HI ( SYNOPSYS_UNCONNECTED_3337 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3637 ( .LO ( optlc_net_3336 ) , + .HI ( SYNOPSYS_UNCONNECTED_3338 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3638 ( .LO ( optlc_net_3337 ) , + .HI ( SYNOPSYS_UNCONNECTED_3339 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3639 ( .LO ( optlc_net_3338 ) , + .HI ( SYNOPSYS_UNCONNECTED_3340 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3640 ( .LO ( optlc_net_3339 ) , + .HI ( SYNOPSYS_UNCONNECTED_3341 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3641 ( .LO ( optlc_net_3340 ) , + .HI ( SYNOPSYS_UNCONNECTED_3342 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3642 ( .LO ( optlc_net_3341 ) , + .HI ( SYNOPSYS_UNCONNECTED_3343 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3643 ( .LO ( optlc_net_3342 ) , + .HI ( SYNOPSYS_UNCONNECTED_3344 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3644 ( .LO ( optlc_net_3343 ) , + .HI ( SYNOPSYS_UNCONNECTED_3345 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3645 ( .LO ( optlc_net_3344 ) , + .HI ( SYNOPSYS_UNCONNECTED_3346 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3646 ( .LO ( optlc_net_3345 ) , + .HI ( SYNOPSYS_UNCONNECTED_3347 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3647 ( .LO ( optlc_net_3346 ) , + .HI ( SYNOPSYS_UNCONNECTED_3348 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3648 ( .LO ( optlc_net_3347 ) , + .HI ( SYNOPSYS_UNCONNECTED_3349 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3649 ( .LO ( optlc_net_3348 ) , + .HI ( SYNOPSYS_UNCONNECTED_3350 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3650 ( .LO ( optlc_net_3349 ) , + .HI ( SYNOPSYS_UNCONNECTED_3351 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3651 ( .LO ( optlc_net_3350 ) , + .HI ( SYNOPSYS_UNCONNECTED_3352 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3652 ( .LO ( optlc_net_3351 ) , + .HI ( SYNOPSYS_UNCONNECTED_3353 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3653 ( .LO ( optlc_net_3352 ) , + .HI ( SYNOPSYS_UNCONNECTED_3354 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3654 ( .LO ( optlc_net_3353 ) , + .HI ( SYNOPSYS_UNCONNECTED_3355 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3655 ( .LO ( optlc_net_3354 ) , + .HI ( SYNOPSYS_UNCONNECTED_3356 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3656 ( .LO ( optlc_net_3355 ) , + .HI ( SYNOPSYS_UNCONNECTED_3357 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3657 ( .LO ( optlc_net_3356 ) , + .HI ( SYNOPSYS_UNCONNECTED_3358 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3658 ( .LO ( optlc_net_3357 ) , + .HI ( SYNOPSYS_UNCONNECTED_3359 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3659 ( .LO ( optlc_net_3358 ) , + .HI ( SYNOPSYS_UNCONNECTED_3360 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3660 ( .LO ( optlc_net_3359 ) , + .HI ( SYNOPSYS_UNCONNECTED_3361 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3661 ( .LO ( optlc_net_3360 ) , + .HI ( SYNOPSYS_UNCONNECTED_3362 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3662 ( .LO ( optlc_net_3361 ) , + .HI ( SYNOPSYS_UNCONNECTED_3363 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3663 ( .LO ( optlc_net_3362 ) , + .HI ( SYNOPSYS_UNCONNECTED_3364 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3664 ( .LO ( optlc_net_3363 ) , + .HI ( SYNOPSYS_UNCONNECTED_3365 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3665 ( .LO ( optlc_net_3364 ) , + .HI ( SYNOPSYS_UNCONNECTED_3366 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3666 ( .LO ( optlc_net_3365 ) , + .HI ( SYNOPSYS_UNCONNECTED_3367 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3667 ( .LO ( optlc_net_3366 ) , + .HI ( SYNOPSYS_UNCONNECTED_3368 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3668 ( .LO ( optlc_net_3367 ) , + .HI ( SYNOPSYS_UNCONNECTED_3369 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3669 ( .LO ( optlc_net_3368 ) , + .HI ( SYNOPSYS_UNCONNECTED_3370 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3670 ( .LO ( optlc_net_3369 ) , + .HI ( SYNOPSYS_UNCONNECTED_3371 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3671 ( .LO ( optlc_net_3370 ) , + .HI ( SYNOPSYS_UNCONNECTED_3372 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3672 ( .LO ( optlc_net_3371 ) , + .HI ( SYNOPSYS_UNCONNECTED_3373 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3673 ( .LO ( optlc_net_3372 ) , + .HI ( SYNOPSYS_UNCONNECTED_3374 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3674 ( .LO ( optlc_net_3373 ) , + .HI ( SYNOPSYS_UNCONNECTED_3375 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3675 ( .LO ( optlc_net_3374 ) , + .HI ( SYNOPSYS_UNCONNECTED_3376 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3676 ( .LO ( optlc_net_3375 ) , + .HI ( SYNOPSYS_UNCONNECTED_3377 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3677 ( .LO ( optlc_net_3376 ) , + .HI ( SYNOPSYS_UNCONNECTED_3378 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3678 ( .LO ( optlc_net_3377 ) , + .HI ( SYNOPSYS_UNCONNECTED_3379 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3679 ( .LO ( optlc_net_3378 ) , + .HI ( SYNOPSYS_UNCONNECTED_3380 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3680 ( .LO ( optlc_net_3379 ) , + .HI ( SYNOPSYS_UNCONNECTED_3381 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3681 ( .LO ( optlc_net_3380 ) , + .HI ( SYNOPSYS_UNCONNECTED_3382 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3682 ( .LO ( optlc_net_3381 ) , + .HI ( SYNOPSYS_UNCONNECTED_3383 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3683 ( .LO ( optlc_net_3382 ) , + .HI ( SYNOPSYS_UNCONNECTED_3384 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3684 ( .LO ( optlc_net_3383 ) , + .HI ( SYNOPSYS_UNCONNECTED_3385 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3685 ( .LO ( optlc_net_3384 ) , + .HI ( SYNOPSYS_UNCONNECTED_3386 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3686 ( .LO ( optlc_net_3385 ) , + .HI ( SYNOPSYS_UNCONNECTED_3387 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3687 ( .LO ( optlc_net_3386 ) , + .HI ( SYNOPSYS_UNCONNECTED_3388 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3688 ( .LO ( optlc_net_3387 ) , + .HI ( SYNOPSYS_UNCONNECTED_3389 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3689 ( .LO ( optlc_net_3388 ) , + .HI ( SYNOPSYS_UNCONNECTED_3390 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3690 ( .LO ( optlc_net_3389 ) , + .HI ( SYNOPSYS_UNCONNECTED_3391 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3691 ( .LO ( optlc_net_3390 ) , + .HI ( SYNOPSYS_UNCONNECTED_3392 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3692 ( .LO ( optlc_net_3391 ) , + .HI ( SYNOPSYS_UNCONNECTED_3393 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3693 ( .LO ( optlc_net_3392 ) , + .HI ( SYNOPSYS_UNCONNECTED_3394 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3694 ( .LO ( optlc_net_3393 ) , + .HI ( SYNOPSYS_UNCONNECTED_3395 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3695 ( .LO ( optlc_net_3394 ) , + .HI ( SYNOPSYS_UNCONNECTED_3396 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3696 ( .LO ( optlc_net_3395 ) , + .HI ( SYNOPSYS_UNCONNECTED_3397 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3697 ( .LO ( optlc_net_3396 ) , + .HI ( SYNOPSYS_UNCONNECTED_3398 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3698 ( .LO ( optlc_net_3397 ) , + .HI ( SYNOPSYS_UNCONNECTED_3399 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3699 ( .LO ( optlc_net_3398 ) , + .HI ( SYNOPSYS_UNCONNECTED_3400 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3700 ( .LO ( optlc_net_3399 ) , + .HI ( SYNOPSYS_UNCONNECTED_3401 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3701 ( .LO ( optlc_net_3400 ) , + .HI ( SYNOPSYS_UNCONNECTED_3402 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3702 ( .LO ( optlc_net_3401 ) , + .HI ( SYNOPSYS_UNCONNECTED_3403 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3703 ( .LO ( optlc_net_3402 ) , + .HI ( SYNOPSYS_UNCONNECTED_3404 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3704 ( .LO ( optlc_net_3403 ) , + .HI ( SYNOPSYS_UNCONNECTED_3405 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3705 ( .LO ( optlc_net_3404 ) , + .HI ( SYNOPSYS_UNCONNECTED_3406 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3706 ( .LO ( optlc_net_3405 ) , + .HI ( SYNOPSYS_UNCONNECTED_3407 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3707 ( .LO ( optlc_net_3406 ) , + .HI ( SYNOPSYS_UNCONNECTED_3408 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3708 ( .LO ( optlc_net_3407 ) , + .HI ( SYNOPSYS_UNCONNECTED_3409 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3709 ( .LO ( optlc_net_3408 ) , + .HI ( SYNOPSYS_UNCONNECTED_3410 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3710 ( .LO ( optlc_net_3409 ) , + .HI ( SYNOPSYS_UNCONNECTED_3411 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3711 ( .LO ( optlc_net_3410 ) , + .HI ( SYNOPSYS_UNCONNECTED_3412 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3712 ( .LO ( optlc_net_3411 ) , + .HI ( SYNOPSYS_UNCONNECTED_3413 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3713 ( .LO ( optlc_net_3412 ) , + .HI ( SYNOPSYS_UNCONNECTED_3414 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3714 ( .LO ( optlc_net_3413 ) , + .HI ( SYNOPSYS_UNCONNECTED_3415 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3715 ( .LO ( optlc_net_3414 ) , + .HI ( SYNOPSYS_UNCONNECTED_3416 ) ) ; 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SYNOPSYS_UNCONNECTED_3426 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3726 ( .LO ( optlc_net_3425 ) , + .HI ( SYNOPSYS_UNCONNECTED_3427 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3727 ( .LO ( optlc_net_3426 ) , + .HI ( SYNOPSYS_UNCONNECTED_3428 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3728 ( .LO ( optlc_net_3427 ) , + .HI ( SYNOPSYS_UNCONNECTED_3429 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3729 ( .LO ( optlc_net_3428 ) , + .HI ( SYNOPSYS_UNCONNECTED_3430 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3730 ( .LO ( optlc_net_3429 ) , + .HI ( SYNOPSYS_UNCONNECTED_3431 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3731 ( .LO ( optlc_net_3430 ) , + .HI ( SYNOPSYS_UNCONNECTED_3432 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3732 ( .LO ( optlc_net_3431 ) , + .HI ( SYNOPSYS_UNCONNECTED_3433 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3733 ( .LO ( optlc_net_3432 ) , + .HI ( SYNOPSYS_UNCONNECTED_3434 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3734 ( .LO ( optlc_net_3433 ) , + .HI ( SYNOPSYS_UNCONNECTED_3435 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3735 ( .LO ( optlc_net_3434 ) , + .HI ( SYNOPSYS_UNCONNECTED_3436 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3736 ( .LO ( optlc_net_3435 ) , + .HI ( SYNOPSYS_UNCONNECTED_3437 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3737 ( .LO ( optlc_net_3436 ) , + .HI ( SYNOPSYS_UNCONNECTED_3438 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3738 ( .LO ( optlc_net_3437 ) , + .HI ( SYNOPSYS_UNCONNECTED_3439 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3739 ( .LO ( optlc_net_3438 ) , + .HI ( SYNOPSYS_UNCONNECTED_3440 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3740 ( .LO ( optlc_net_3439 ) , + .HI ( SYNOPSYS_UNCONNECTED_3441 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3741 ( .LO ( optlc_net_3440 ) , + .HI ( SYNOPSYS_UNCONNECTED_3442 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3742 ( .LO ( optlc_net_3441 ) , + .HI ( SYNOPSYS_UNCONNECTED_3443 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3743 ( .LO ( optlc_net_3442 ) , + .HI ( SYNOPSYS_UNCONNECTED_3444 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3744 ( .LO ( optlc_net_3443 ) , + .HI ( SYNOPSYS_UNCONNECTED_3445 ) ) ; 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SYNOPSYS_UNCONNECTED_3455 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3755 ( .LO ( optlc_net_3454 ) , + .HI ( SYNOPSYS_UNCONNECTED_3456 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3756 ( .LO ( optlc_net_3455 ) , + .HI ( SYNOPSYS_UNCONNECTED_3457 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3757 ( .LO ( optlc_net_3456 ) , + .HI ( SYNOPSYS_UNCONNECTED_3458 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3758 ( .LO ( optlc_net_3457 ) , + .HI ( SYNOPSYS_UNCONNECTED_3459 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3759 ( .LO ( optlc_net_3458 ) , + .HI ( SYNOPSYS_UNCONNECTED_3460 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3760 ( .LO ( optlc_net_3459 ) , + .HI ( SYNOPSYS_UNCONNECTED_3461 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3761 ( .LO ( optlc_net_3460 ) , + .HI ( SYNOPSYS_UNCONNECTED_3462 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3762 ( .LO ( optlc_net_3461 ) , + .HI ( SYNOPSYS_UNCONNECTED_3463 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3763 ( .LO ( optlc_net_3462 ) , + .HI ( SYNOPSYS_UNCONNECTED_3464 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3764 ( .LO ( optlc_net_3463 ) , + .HI ( SYNOPSYS_UNCONNECTED_3465 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3765 ( .LO ( optlc_net_3464 ) , + .HI ( SYNOPSYS_UNCONNECTED_3466 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3766 ( .LO ( optlc_net_3465 ) , + .HI ( SYNOPSYS_UNCONNECTED_3467 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3767 ( .LO ( optlc_net_3466 ) , + .HI ( SYNOPSYS_UNCONNECTED_3468 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3768 ( .LO ( optlc_net_3467 ) , + .HI ( SYNOPSYS_UNCONNECTED_3469 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3769 ( .LO ( optlc_net_3468 ) , + .HI ( SYNOPSYS_UNCONNECTED_3470 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3770 ( .LO ( optlc_net_3469 ) , + .HI ( SYNOPSYS_UNCONNECTED_3471 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3771 ( .LO ( optlc_net_3470 ) , + .HI ( SYNOPSYS_UNCONNECTED_3472 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3772 ( .LO ( optlc_net_3471 ) , + .HI ( SYNOPSYS_UNCONNECTED_3473 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3773 ( .LO ( optlc_net_3472 ) , + .HI ( SYNOPSYS_UNCONNECTED_3474 ) ) ; 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SYNOPSYS_UNCONNECTED_3484 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3784 ( .LO ( optlc_net_3483 ) , + .HI ( SYNOPSYS_UNCONNECTED_3485 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3785 ( .LO ( optlc_net_3484 ) , + .HI ( SYNOPSYS_UNCONNECTED_3486 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3786 ( .LO ( optlc_net_3485 ) , + .HI ( SYNOPSYS_UNCONNECTED_3487 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3787 ( .LO ( optlc_net_3486 ) , + .HI ( SYNOPSYS_UNCONNECTED_3488 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3788 ( .LO ( optlc_net_3487 ) , + .HI ( SYNOPSYS_UNCONNECTED_3489 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3789 ( .LO ( optlc_net_3488 ) , + .HI ( SYNOPSYS_UNCONNECTED_3490 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3790 ( .LO ( optlc_net_3489 ) , + .HI ( SYNOPSYS_UNCONNECTED_3491 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3791 ( .LO ( optlc_net_3490 ) , + .HI ( SYNOPSYS_UNCONNECTED_3492 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3792 ( .LO ( optlc_net_3491 ) , + .HI ( SYNOPSYS_UNCONNECTED_3493 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3793 ( .LO ( optlc_net_3492 ) , + .HI ( SYNOPSYS_UNCONNECTED_3494 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3794 ( .LO ( optlc_net_3493 ) , + .HI ( SYNOPSYS_UNCONNECTED_3495 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3795 ( .LO ( optlc_net_3494 ) , + .HI ( SYNOPSYS_UNCONNECTED_3496 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3796 ( .LO ( optlc_net_3495 ) , + .HI ( SYNOPSYS_UNCONNECTED_3497 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3797 ( .LO ( optlc_net_3496 ) , + .HI ( SYNOPSYS_UNCONNECTED_3498 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3798 ( .LO ( optlc_net_3497 ) , + .HI ( SYNOPSYS_UNCONNECTED_3499 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3799 ( .LO ( optlc_net_3498 ) , + .HI ( SYNOPSYS_UNCONNECTED_3500 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3800 ( .LO ( optlc_net_3499 ) , + .HI ( SYNOPSYS_UNCONNECTED_3501 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3801 ( .LO ( optlc_net_3500 ) , + .HI ( SYNOPSYS_UNCONNECTED_3502 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3802 ( .LO ( optlc_net_3501 ) , + .HI ( SYNOPSYS_UNCONNECTED_3503 ) ) ; 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SYNOPSYS_UNCONNECTED_3513 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3813 ( .LO ( optlc_net_3512 ) , + .HI ( SYNOPSYS_UNCONNECTED_3514 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3814 ( .LO ( optlc_net_3513 ) , + .HI ( SYNOPSYS_UNCONNECTED_3515 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3815 ( .LO ( optlc_net_3514 ) , + .HI ( SYNOPSYS_UNCONNECTED_3516 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3816 ( .LO ( optlc_net_3515 ) , + .HI ( SYNOPSYS_UNCONNECTED_3517 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3817 ( .LO ( optlc_net_3516 ) , + .HI ( SYNOPSYS_UNCONNECTED_3518 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3818 ( .LO ( optlc_net_3517 ) , + .HI ( SYNOPSYS_UNCONNECTED_3519 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3819 ( .LO ( optlc_net_3518 ) , + .HI ( SYNOPSYS_UNCONNECTED_3520 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3820 ( .LO ( optlc_net_3519 ) , + .HI ( SYNOPSYS_UNCONNECTED_3521 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3821 ( .LO ( optlc_net_3520 ) , + .HI ( SYNOPSYS_UNCONNECTED_3522 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3822 ( .LO ( optlc_net_3521 ) , + .HI ( SYNOPSYS_UNCONNECTED_3523 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3823 ( .LO ( optlc_net_3522 ) , + .HI ( SYNOPSYS_UNCONNECTED_3524 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3824 ( .LO ( optlc_net_3523 ) , + .HI ( SYNOPSYS_UNCONNECTED_3525 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3825 ( .LO ( optlc_net_3524 ) , + .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3826 ( .LO ( optlc_net_3525 ) , + .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3827 ( .LO ( optlc_net_3526 ) , + .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3828 ( .LO ( optlc_net_3527 ) , + .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3829 ( .LO ( optlc_net_3528 ) , + .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3830 ( .LO ( optlc_net_3529 ) , + .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3831 ( .LO ( optlc_net_3530 ) , + .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3832 ( .LO ( optlc_net_3531 ) , + .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3833 ( .LO ( optlc_net_3532 ) , + .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3834 ( .LO ( optlc_net_3533 ) , + .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3835 ( .LO ( optlc_net_3534 ) , + .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3836 ( .LO ( optlc_net_3535 ) , + .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3837 ( .LO ( optlc_net_3536 ) , + .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3838 ( .LO ( optlc_net_3537 ) , + .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3839 ( .LO ( optlc_net_3538 ) , + .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ; endmodule diff --git a/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.gds.gz b/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.gds.gz index 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