mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #42 from LNIS-Projects/xt_dev
Push-button Modelsim Verification for Specific FPGA fabric
This commit is contained in:
Laboratory for Nano Integrated Systems (LNIS)
GitHub
commit
90f4e3fa70
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@ -0,0 +1,12 @@
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# Skywater PDK
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This directory is the workspace for running Mentor Modelsim simulations for FPGA fabrics
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Please keep this directory clean and organize as follows:
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- Each task-run should be placed in a separated directory
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- **common**: include commonly used scripts for post-PnR verification
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- READMD is the only file allowed in the directory, others should be sub-directories.
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* Quick Example to run simulations for task-run
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```
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python3 run_post_pnr_msim_task.py --testbench_dir_name ../../TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --task_name k4_N8_caravel_io_FPGA_12x12_fdhd_cc
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```
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@ -9,14 +9,14 @@ proc create_project_with_close {projectname modelsim_path} {
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#Get the current project name
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set project_env [project env]
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if {$project_env eq ""} {
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#If string empty (no project)
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create_project $projectname $modelsim_path
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} else {
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#If string not empty (a project is loaded so clsoe it first)
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project close
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create_project $projectname $modelsim_path
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}
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#If string empty (no project)
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create_project $projectname $modelsim_path
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} else {
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#If string not empty (a project is loaded so clsoe it first)
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project close
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create_project $projectname $modelsim_path
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}
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}
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proc add_files_project {verilog_files} {
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#Get the length of the list
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@ -30,11 +30,9 @@ proc add_files_project {verilog_files} {
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proc add_waves {top_tb} {
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add wave -position insertpoint sim:/$top_tb/*
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}
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proc runsim {simtime unit} {
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run $simtime $unit
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}
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#Top procedure to create enw project
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proc top_create_new_project {projectname verilog_files modelsim_path simtime unit top_tb} {
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proc top_create_new_project {projectname verilog_files modelsim_path top_tb} {
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#Create the project
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create_project_with_close $projectname $modelsim_path
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#Add the verilog files
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@ -42,30 +40,12 @@ proc top_create_new_project {projectname verilog_files modelsim_path simtime uni
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#Compile all the files
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set myFiles [project filenames]
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foreach x $myFiles {
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vlog +define+ENABLE_TIMING +define+ENABLE_SIGNAL_INITIALIZATION $x
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vlog +define+ENABLE_SIGNAL_INITIALIZATION $x
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}
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#Start the simulation
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vsim $projectname.$top_tb -voptargs=+acc
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#Add the waves
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add_waves $top_tb
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#run the simulation
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runsim $simtime $unit
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#Fit the window view
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wave zoom full
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}
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#Top proc to recompile files and re run the simulation
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proc top_rerun_sim {simtime unit top_tb} {
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#Save actual format
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set myLoc [pwd]
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write format wave -window .main_pane.wave.interior.cs.body.pw.wf $myLoc/relaunch.do
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quit -sim
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#Compile updated verilog files
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set myFiles [project filenames]
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foreach x $myFiles {
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vlog +define+ENABLE_TIMING +define+ENABLE_SIGNAL_INITIALIZATION $x
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}
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set projectname K4n4_test_fpga_msim
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vsim $projectname.$top_tb -voptargs=+acc -do relaunch.do
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#run the simulation
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run $simtime $unit
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run -all
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}
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@ -0,0 +1,76 @@
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#####################################################################
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# Python script to run ModelSim simulations for all the post-pnr testbenches
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# in a project directory
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# This script will
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# - Collect all the testbenches in a given directory
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# For instance:
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# ../k4_arch/pre_pnr/verilog_testbenches/and2_post_pnr_include_netlist.v
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# - Use run_post_pnr_msim_test.py to run Modelsim simulations and check results
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#####################################################################
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import os
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from os.path import dirname, abspath
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import shutil
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import re
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import argparse
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import logging
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import subprocess
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import glob
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#####################################################################
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# Initialize logger
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO)
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#####################################################################
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# Parse the options
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#####################################################################
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parser = argparse.ArgumentParser(description='Run a ModelSim verification task for a tape-out FPGA')
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parser.add_argument('--testbench_dir_name', required=True,
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help='Specify the directory path for the Verilog testbenches')
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parser.add_argument('--task_name', required=True,
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help='Specify the directory path for the Verilog testbenches')
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args = parser.parse_args()
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#####################################################################
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# Walk through the parent directory and find all the pre-PnR testbenches
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#####################################################################
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logging.info("Finding testbenches...");
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testbench_dir_abspath = abspath(args.testbench_dir_name) + "/postpnr/verilog_testbench";
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testbench_files = []
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for globbed_file in glob.glob(testbench_dir_abspath + "/*_include_netlists.v"):
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testbench_files.append(globbed_file)
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logging.info("Found " + str(len(testbench_files)) + " testbenches")
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#####################################################################
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# Try to create the directory of Modelsim projects
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#####################################################################
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parent_dir_abspath = dirname(dirname(abspath(__file__)))
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msim_task_dir_abspath = abspath(parent_dir_abspath + args.task_name) + "/postpnr/verilog_testbench";
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os.makedirs(msim_task_dir_abspath, exist_ok=True)
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#####################################################################
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# Run ModelSim simulations for each testbench
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#####################################################################
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logging.info("Running Modelsim simulations...");
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num_sim_finished = 0
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msim_testrun_script_abspath = os.path.abspath(__file__)
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msim_testrun_script_abspath = re.sub(os.path.basename(msim_testrun_script_abspath), "run_post_pnr_msim_test.py", msim_testrun_script_abspath)
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for testbench_file in testbench_files:
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# Find testbench name
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testbench_name = re.findall("(\w+)_include_netlists.v", os.path.basename(testbench_file))[0]
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cmd = "python3 " + msim_testrun_script_abspath \
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+ " --verilog_testbench " + testbench_file \
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+ " --project_path " + msim_task_dir_abspath + "/" + testbench_name \
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+ " --testbench_name " + testbench_name + "_autocheck_top_tb"
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subprocess.run(cmd, shell=True, check=True)
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num_sim_finished += 1
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logging.info("Done")
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logging.info("Finish " + str(num_sim_finished) + " ModelSim simulations")
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@ -0,0 +1,147 @@
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#####################################################################
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# Python script to execute modelsim simulation for a given testbench netlist
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# This script will
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# - Create the tcl script to enable modelsim simulation
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# - Run modelsim simulation
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# - Analyze output log files and return succeed or failure
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#####################################################################
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import os
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from os.path import dirname, abspath, isfile
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import shutil
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import re
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import argparse
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import logging
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import subprocess
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#####################################################################
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# Initialize logger
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.INFO)
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#####################################################################
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# Parse the options
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#####################################################################
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parser = argparse.ArgumentParser(description='Run ModelSim verification for a testbench')
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parser.add_argument('--verilog_testbench', required=True,
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help='Specify the file path for the Verilog testbench as input')
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parser.add_argument('--project_path', required=True,
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help='Specify the file path to create the ModelSim project')
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parser.add_argument('--testbench_name', required=True,
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help='Specify the top-level module of the testbench')
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args = parser.parse_args()
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#####################################################################
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# Check options:
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# - Input testbench file must be valid
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# Otherwise, error out
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# - If the modelsim project path does not exist, create it
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#####################################################################
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if not isfile(args.verilog_testbench):
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logging.error("Invalid Verilog testbench: " + args.verilog_testbench + "\nFile does not exist!\n")
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exit(1)
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project_abs_path = os.path.abspath(args.project_path)
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if not os.path.isdir(project_abs_path):
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logging.debug("Creating ModelSim project directory : " + project_abs_path + " ...\n")
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os.makedirs(project_abs_path, exist_ok=True)
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logging.debug("Done\n")
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#####################################################################
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# Create the Tcl script for Modelsim
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#####################################################################
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# Get modelsim process tcl file path
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msim_proc_tcl_path = os.path.abspath(__file__)
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msim_proc_tcl_path = re.sub(os.path.basename(msim_proc_tcl_path), "modelsim_proc.tcl", msim_proc_tcl_path)
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if not isfile(msim_proc_tcl_path):
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logging.error("Invalid process script for ModelSim: " + msim_proc_tcl_path + "\nFile does not exist!\n")
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exit(1)
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# Create output file handler
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tcl_file_path = project_abs_path + "/" + os.path.basename(args.testbench_name) + ".tcl"
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logging.debug("Generating Tcl script for ModelSim: " + tcl_file_path)
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tcl_file = open(tcl_file_path, "w")
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# A string buffer to write tcl content
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tcl_lines = []
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tcl_lines.append("echo \"==============================\"")
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tcl_lines.append("pwd")
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tcl_lines.append("echo \"==============================\"")
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tcl_lines.append("\n")
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tcl_lines.append("set project_name " + args.testbench_name)
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tcl_lines.append("set top_tb " + args.testbench_name)
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tcl_lines.append("\n")
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tcl_lines.append("set project_path \"" + project_abs_path + "\"")
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tcl_lines.append("set verilog_files \"" + os.path.abspath(args.verilog_testbench) + "\"")
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tcl_lines.append("\n")
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tcl_lines.append("source " + msim_proc_tcl_path)
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tcl_lines.append("\n")
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tcl_lines.append("try {")
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tcl_lines.append("\ttop_create_new_project $project_name $verilog_files $project_path $top_tb")
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tcl_lines.append("} finally {")
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tcl_lines.append("\tquit")
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tcl_lines.append("}")
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for line in tcl_lines:
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tcl_file.write(line + "\n")
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tcl_file.close()
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logging.debug("Done")
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#####################################################################
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# Run ModelSim simulation
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#####################################################################
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curr_dir = os.getcwd()
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# Change to the project directory
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os.chdir(project_abs_path)
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logging.debug("Changed to directory: " + project_abs_path)
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# Run ModelSim
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vsim_log_file_path = project_abs_path + "/vsim_run_log"
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vsim_bin = "/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/bin/vsim"
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vsim_cmd = vsim_bin + " -c -do " + os.path.abspath(tcl_file_path) + " > " + vsim_log_file_path
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logging.debug("Running modelsim by : " + vsim_cmd)
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subprocess.run(vsim_cmd, shell=True, check=True)
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# Go back to current directory
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os.chdir(curr_dir)
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#####################################################################
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# Parse log files and report any errors
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#####################################################################
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vsim_log_file = open(vsim_log_file_path, "r")
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# Error counter
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num_err = 0
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num_err_lines_found = 0
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verification_passed = False
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for line in vsim_log_file:
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# Check errors from self-testing testbench output
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if line.startswith("# Simulation finish with") :
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num_sim_err = int(re.findall("# Simulation finish with(\s+)(\d+) errors", line)[0][1])
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num_err_lines_found = num_err_lines_found + 1
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if (0 < num_sim_err) :
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logging.error("Simulation failed with " + str(num_sim_err) + " errors!\n")
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# Add to total errors
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num_err = num_err + num_sim_err
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# Check total errors by Modelsim
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if line.startswith("# Errors:") :
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num_msim_err = int(re.findall("# Errors:(\s)(\d+),", line)[0][1])
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num_err_lines_found = num_err_lines_found + 1
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num_err = num_err + num_msim_err
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vsim_log_file.close()
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if (0 == num_err_lines_found) :
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logging.error("No error lines found!Something wrong in setting up modelsim simulation\n")
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elif (0 < num_err) :
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logging.error("ModelSim failed with " + str(num_err) + " errors!\n")
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else :
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verification_passed = True
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if (verification_passed) :
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logging.info(args.testbench_name + "...[Passed]\n")
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else :
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logging.error(args.testbench_name + "...[Failed]\n")
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Binary file not shown.
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@ -25,49 +25,46 @@ import glob
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#####################################################################
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logging.basicConfig(format='%(levelname)s: %(message)s', level=logging.DEBUG)
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#####################################################################
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# Parse the options
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#####################################################################
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parser = argparse.ArgumentParser(description='Generate post-PnR testbenches for a given directory')
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parser.add_argument('--pre_pnr_testbench_dir_name', required=True,
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help='Specify the directory path for the pre-PnR Verilog testbenches')
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args = parser.parse_args()
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#####################################################################
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# Walk through the parent directory and find all the pre-PnR testbenches
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#####################################################################
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logging.info("Finding pre-PnR testbenches...");
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parent_dirpath = dirname(dirname(abspath(__file__)))
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pre_pnr_testbench_dir_abspath = abspath(args.pre_pnr_testbench_dir_name) + "/prepnr/verilog_testbench";
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# Count how many testbenches have been converted
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num_converted_testbenches = 0
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# Collect the pre-PnR testbenches to be converted
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pre_pnr_testbench_files = []
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post_pnr_testbench_dirs = []
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for root, dirs, files in os.walk(parent_dirpath):
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for dir_name in dirs:
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# Skip 'common' directory as the testbenches inside are already converted
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# Also skip any hidden directories
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if ((dir_name == "common") or (dir_name.startswith("."))):
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continue;
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# Find the testbenches in the fixed location of the tree
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curr_pre_pnr_testbench_dir_path = os.path.join(root, dir_name + "/prepnr/verilog_testbench")
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# Add to list
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logging.info("Checking directory: " + str(curr_pre_pnr_testbench_dir_path))
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for globbed_file in glob.glob(curr_pre_pnr_testbench_dir_path + "/*_autocheck_top_tb.v"):
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pre_pnr_testbench_files.append(globbed_file)
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# If we have testbenches to convert, try to create the directory of post-pnr testbenches
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curr_post_pnr_testbench_dir_path = os.path.join(root, dir_name + "/postpnr/verilog_testbench")
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post_pnr_testbench_dirs.append(curr_post_pnr_testbench_dir_path)
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# Add to list
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for globbed_file in glob.glob(pre_pnr_testbench_dir_abspath + "/*_autocheck_top_tb.v"):
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pre_pnr_testbench_files.append(globbed_file)
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# If we have testbenches to convert, try to create the directory of post-pnr testbenches
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post_pnr_testbench_dir_abspath = abspath(args.pre_pnr_testbench_dir_name) + "/postpnr/verilog_testbench";
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logging.info("Found " + str(len(pre_pnr_testbench_files)) + " pre-PnR testbenches")
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#####################################################################
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# Try to create the directory of post-pnr testbenches
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#####################################################################
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for post_pnr_testbench_dir in post_pnr_testbench_dirs:
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os.makedirs(curr_post_pnr_testbench_dir_path, exist_ok=True)
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os.makedirs(post_pnr_testbench_dir_abspath, exist_ok=True)
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#####################################################################
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# Convert pre-PnR testbenches to post-PnR testbenches
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#####################################################################
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logging.info("Converting pre-PnR testbench to post-PnR testbench...");
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for curr_pre_pnr_testbench_file in pre_pnr_testbench_files:
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logging.info("\nProcessing " + curr_pre_pnr_testbench_file + " testbench:\n")
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logging.info("Processing " + curr_pre_pnr_testbench_file + " testbench:")
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curr_post_pnr_testbench_file = re.sub("_autocheck_top_tb.v$", "_post_pnr_autocheck_top_tb.v", curr_pre_pnr_testbench_file)
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curr_post_pnr_testbench_file = re.sub("\/prepnr\/", "\/postpnr\/", curr_post_pnr_testbench_file)
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cmd = "python3 ./post_pnr_testbench_converter.py " \
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@ -75,6 +72,6 @@ for curr_pre_pnr_testbench_file in pre_pnr_testbench_files:
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+ " --post_pnr_testbench " + curr_post_pnr_testbench_file
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subprocess.run(cmd, shell=True, check=True)
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num_converted_testbenches += 1
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logging.info("Done")
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||||
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||||
logging.info("Done")
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||||
logging.info("\nConverted " + str(num_converted_testbenches) + " testbenches.")
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||||
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|||
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@ -1,197 +0,0 @@
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//-------------------------------------------
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||||
// Verilog Testbench for Verifying
|
||||
// Configuration Chain of a FPGA
|
||||
// Description: This test is applicable to FPGAs which have 1 configuration
|
||||
// chain. It will feed a pulse to the head of the configuration chain and
|
||||
// check if the pulse is outputted by the tail of the configuration chain
|
||||
// in a given time period
|
||||
//
|
||||
// Note: This test bench is tuned for the post PnR netlists
|
||||
// Author: Xifan TANG
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||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// Design parameter for FPGA I/O sizes
|
||||
//`define FPGA_IO_SIZE 144
|
||||
//
|
||||
// Design parameter for FPGA bitstream sizes
|
||||
//`define FPGA_BITSTREAM_SIZE 65656
|
||||
|
||||
module post_pnr_ccff_test;
|
||||
// ----- Local wires for global ports of FPGA fabric -----
|
||||
wire [0:0] prog_clk;
|
||||
wire [0:0] Test_en;
|
||||
wire [0:0] clk;
|
||||
|
||||
// ----- Local wires for I/Os of FPGA fabric -----
|
||||
|
||||
wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_SOC_IN;
|
||||
wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_SOC_OUT;
|
||||
wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_SOC_DIR;
|
||||
|
||||
wire [0:0] prog_clock;
|
||||
reg [0:0] prog_clock_reg;
|
||||
wire [0:0] op_clock;
|
||||
reg [0:0] op_clock_reg;
|
||||
reg [0:0] prog_reset;
|
||||
reg [0:0] prog_set;
|
||||
reg [0:0] greset;
|
||||
reg [0:0] gset;
|
||||
// ---- Configuration-chain head -----
|
||||
reg [0:0] ccff_head;
|
||||
// ---- Configuration-chain tail -----
|
||||
wire [0:0] ccff_tail;
|
||||
|
||||
// ---- Scan-chain head -----
|
||||
wire [0:0] sc_head;
|
||||
// ---- Scan-chain tail -----
|
||||
wire [0:0] sc_tail;
|
||||
|
||||
wire [0:0] IO_ISOL_N;
|
||||
|
||||
// ----- Counters for error checking -----
|
||||
integer num_prog_cycles = 0;
|
||||
integer num_errors = 0;
|
||||
integer num_checked_points = 0;
|
||||
|
||||
// Indicate when configuration should be finished
|
||||
reg config_done = 0;
|
||||
|
||||
initial
|
||||
begin
|
||||
config_done = 1'b0;
|
||||
end
|
||||
|
||||
// ----- Begin raw programming clock signal generation -----
|
||||
initial
|
||||
begin
|
||||
prog_clock_reg[0] = 1'b0;
|
||||
end
|
||||
always
|
||||
begin
|
||||
#5 prog_clock_reg[0] = ~prog_clock_reg[0];
|
||||
end
|
||||
|
||||
// ----- End raw programming clock signal generation -----
|
||||
|
||||
// ----- Actual programming clock is triggered only when config_done and prog_reset are disabled -----
|
||||
assign prog_clock[0] = prog_clock_reg[0] & (~prog_reset[0]);
|
||||
|
||||
// ----- Begin raw operating clock signal generation -----
|
||||
initial
|
||||
begin
|
||||
op_clock_reg[0] = 1'b0;
|
||||
end
|
||||
|
||||
// ----- End raw operating clock signal generation -----
|
||||
// ----- Actual operating clock is triggered only when config_done is enabled -----
|
||||
assign op_clock[0] = op_clock_reg[0];
|
||||
|
||||
// ----- Begin programming reset signal generation -----
|
||||
initial
|
||||
begin
|
||||
prog_reset[0] = 1'b1;
|
||||
#10 prog_reset[0] = 1'b0;
|
||||
end
|
||||
|
||||
// ----- End programming reset signal generation -----
|
||||
|
||||
// ----- Begin programming set signal generation -----
|
||||
initial
|
||||
begin
|
||||
prog_set[0] = 1'b1;
|
||||
#10 prog_set[0] = 1'b0;
|
||||
end
|
||||
|
||||
// ----- End programming set signal generation -----
|
||||
|
||||
// ----- Begin operating reset signal generation -----
|
||||
// ----- Reset signal is disabled always -----
|
||||
initial
|
||||
begin
|
||||
greset[0] = 1'b1;
|
||||
end
|
||||
|
||||
// ----- End operating reset signal generation -----
|
||||
// ----- Begin operating set signal generation: always disabled -----
|
||||
initial
|
||||
begin
|
||||
gset[0] = 1'b0;
|
||||
end
|
||||
|
||||
// ----- End operating set signal generation: always disabled -----
|
||||
|
||||
// ----- Begin connecting global ports of FPGA fabric to stimuli -----
|
||||
assign clk[0] = op_clock[0];
|
||||
assign prog_clk[0] = prog_clock[0];
|
||||
assign Test_en[0] = 1'b0;
|
||||
assign sc_head[0] = 1'b0;
|
||||
assign IO_ISOL_N[0] = 1'b0;
|
||||
// ----- End connecting global ports of FPGA fabric to stimuli -----
|
||||
// ----- FPGA top-level module to be capsulated -----
|
||||
fpga_core FPGA_DUT (
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.clk(clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.sc_head(sc_head[0]),
|
||||
.sc_tail(sc_tail[0]),
|
||||
.IO_ISOL_N(IO_ISOL_N)
|
||||
);
|
||||
|
||||
// ----- Force constant '0' to FPGA I/O as this testbench only check
|
||||
// programming phase -----
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_IN[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
|
||||
assign gfpga_pad_EMBEDDED_IO_SOC_OUT[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
|
||||
|
||||
// Generate a pulse after programming reset is disabled (in the 2nd clock
|
||||
// cycle). Then the head of configuration chain should be always zero
|
||||
always @(negedge prog_clock[0]) begin
|
||||
ccff_head = 1'b1;
|
||||
if (0 != num_prog_cycles) begin
|
||||
ccff_head = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// ----- Count the number of programming cycles -------
|
||||
always @(posedge prog_clock[0]) begin
|
||||
num_prog_cycles = num_prog_cycles + 1;
|
||||
// Indicate when configuration is suppose to end
|
||||
if (`FPGA_BITSTREAM_SIZE + 1 == num_prog_cycles) begin
|
||||
config_done = 1'b1;
|
||||
end
|
||||
|
||||
// Check the ccff_tail when configuration is done
|
||||
if (1'b1 == config_done) begin
|
||||
// The tail should spit a pulse after configuration is done
|
||||
// So it should be at logic '1' and then pulled down to logic '0'
|
||||
if (0 == num_checked_points) begin
|
||||
if (ccff_tail !== 1'b1) begin
|
||||
$display("Error: ccff_tail = %b", sc_tail);
|
||||
num_errors = num_errors + 1;
|
||||
end
|
||||
end
|
||||
if (1 <= num_checked_points) begin
|
||||
if (ccff_tail !== 1'b0) begin
|
||||
$display("Error: ccff_tail = %b", sc_tail);
|
||||
num_errors = num_errors + 1;
|
||||
end
|
||||
end
|
||||
num_checked_points = num_checked_points + 1;
|
||||
end
|
||||
|
||||
if (2 < num_checked_points) begin
|
||||
$display("Simulation finish with %d errors", num_errors);
|
||||
|
||||
// End simulation
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
BIN
TESTBENCH/common/post_pnr_fpga_cells.v (Stored with Git LFS)
BIN
TESTBENCH/common/post_pnr_fpga_cells.v (Stored with Git LFS)
Binary file not shown.
|
|
@ -1,193 +0,0 @@
|
|||
//-------------------------------------------
|
||||
// Verilog Testbench for Verifying
|
||||
// Scan Chain of a FPGA
|
||||
// Description: This test is applicable to FPGAs which have a built-in scan
|
||||
// chain. It will feed a pulse to the head of the scan chain and
|
||||
// check if the pulse is outputted by the tail of the can chain
|
||||
// in a given time period
|
||||
//
|
||||
// Note: This test bench is tuned for the pre PnR netlists
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// Design parameter for FPGA I/O sizes
|
||||
//`define FPGA_IO_SIZE 144
|
||||
//
|
||||
// Design parameter for FPGA scan-chain sizes
|
||||
//`define FPGA_SCANCHAIN_SIZE 2304
|
||||
|
||||
module post_pnr_scff_test;
|
||||
// ----- Local wires for global ports of FPGA fabric -----
|
||||
wire [0:0] prog_clk;
|
||||
wire [0:0] Test_en;
|
||||
wire [0:0] clk;
|
||||
|
||||
// ----- Local wires for I/Os of FPGA fabric -----
|
||||
|
||||
wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_IN;
|
||||
wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT;
|
||||
wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR;
|
||||
|
||||
reg [0:0] prog_clock_reg;
|
||||
wire [0:0] prog_clock;
|
||||
wire [0:0] op_clock;
|
||||
reg [0:0] op_clock_reg;
|
||||
reg [0:0] prog_reset;
|
||||
reg [0:0] prog_set;
|
||||
reg [0:0] greset;
|
||||
reg [0:0] gset;
|
||||
// ---- Configuration-chain head -----
|
||||
wire [0:0] ccff_head;
|
||||
// ---- Configuration-chain tail -----
|
||||
wire [0:0] ccff_tail;
|
||||
|
||||
// ---- Scan-chain head -----
|
||||
reg [0:0] sc_head;
|
||||
// ---- Scan-chain tail -----
|
||||
wire [0:0] sc_tail;
|
||||
|
||||
wire [0:0] IO_ISOL_N;
|
||||
|
||||
// ----- Counters for error checking -----
|
||||
integer num_clock_cycles = 0;
|
||||
integer num_errors = 0;
|
||||
integer num_checked_points = 0;
|
||||
|
||||
// Indicate when configuration should be finished
|
||||
reg scan_done = 0;
|
||||
|
||||
initial
|
||||
begin
|
||||
scan_done = 1'b0;
|
||||
end
|
||||
|
||||
// ----- Begin raw programming clock signal generation -----
|
||||
initial
|
||||
begin
|
||||
prog_clock_reg[0] = 1'b0;
|
||||
end
|
||||
// ----- End raw programming clock signal generation -----
|
||||
|
||||
// ----- Begin raw operating clock signal generation -----
|
||||
initial
|
||||
begin
|
||||
op_clock_reg[0] = 1'b0;
|
||||
end
|
||||
always
|
||||
begin
|
||||
#5 op_clock_reg[0] = ~op_clock_reg[0];
|
||||
end
|
||||
|
||||
// ----- End raw operating clock signal generation -----
|
||||
// ----- Actual operating clock is triggered only when scan_done is enabled -----
|
||||
assign prog_clock[0] = prog_clock_reg[0] & ~greset;
|
||||
assign op_clock[0] = op_clock_reg[0] & ~greset;
|
||||
|
||||
// ----- Begin programming reset signal generation -----
|
||||
initial
|
||||
begin
|
||||
prog_reset[0] = 1'b0;
|
||||
end
|
||||
|
||||
// ----- End programming reset signal generation -----
|
||||
|
||||
// ----- Begin programming set signal generation -----
|
||||
initial
|
||||
begin
|
||||
prog_set[0] = 1'b0;
|
||||
end
|
||||
|
||||
// ----- End programming set signal generation -----
|
||||
|
||||
// ----- Begin operating reset signal generation -----
|
||||
// ----- Reset signal is disabled always -----
|
||||
initial
|
||||
begin
|
||||
greset[0] = 1'b1;
|
||||
#10 greset[0] = 1'b0;
|
||||
end
|
||||
|
||||
// ----- End operating reset signal generation -----
|
||||
// ----- Begin operating set signal generation: always disabled -----
|
||||
initial
|
||||
begin
|
||||
gset[0] = 1'b0;
|
||||
end
|
||||
|
||||
// ----- End operating set signal generation: always disabled -----
|
||||
|
||||
// ----- Begin connecting global ports of FPGA fabric to stimuli -----
|
||||
assign clk[0] = op_clock[0];
|
||||
assign prog_clk[0] = prog_clock[0];
|
||||
assign Test_en[0] = ~greset;
|
||||
assign ccff_head[0] = 1'b0;
|
||||
assign IO_ISOL_N[0] = 1'b0;
|
||||
// ----- End connecting global ports of FPGA fabric to stimuli -----
|
||||
// ----- FPGA top-level module to be capsulated -----
|
||||
fpga_core FPGA_DUT (
|
||||
.prog_clk(prog_clk[0]),
|
||||
.Test_en(Test_en[0]),
|
||||
.clk(clk[0]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]),
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]),
|
||||
.ccff_head(ccff_head[0]),
|
||||
.ccff_tail(ccff_tail[0]),
|
||||
.sc_head(sc_head[0]),
|
||||
.sc_tail(sc_tail[0]),
|
||||
.IO_ISOL_N(IO_ISOL_N)
|
||||
);
|
||||
|
||||
// ----- Force constant '0' to FPGA I/O as this testbench only check
|
||||
// programming phase -----
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
|
||||
assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}};
|
||||
|
||||
// Generate a pulse after operating reset is disabled (in the 2nd clock
|
||||
// cycle). Then the head of scan chain should be always zero
|
||||
always @(negedge op_clock[0]) begin
|
||||
sc_head = 1'b1;
|
||||
if (0 != num_clock_cycles) begin
|
||||
sc_head = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// ----- Count the number of programming cycles -------
|
||||
always @(posedge op_clock[0]) begin
|
||||
num_clock_cycles = num_clock_cycles + 1;
|
||||
// Indicate when scan chain loading is suppose to end
|
||||
if (`FPGA_SCANCHAIN_SIZE + 1 == num_clock_cycles) begin
|
||||
scan_done = 1'b1;
|
||||
end
|
||||
|
||||
// Check the tail of scan-chain when configuration is done
|
||||
if (1'b1 == scan_done) begin
|
||||
// The tail should spit a pulse after configuration is done
|
||||
// So it should be at logic '1' and then pulled down to logic '0'
|
||||
if (0 == num_checked_points) begin
|
||||
if (sc_tail !== 1'b1) begin
|
||||
$display("Error: sc_tail = %b", sc_tail);
|
||||
num_errors = num_errors + 1;
|
||||
end
|
||||
end
|
||||
if (1 <= num_checked_points) begin
|
||||
if (sc_tail !== 1'b0) begin
|
||||
$display("Error: sc_tail = %b", sc_tail);
|
||||
num_errors = num_errors + 1;
|
||||
end
|
||||
end
|
||||
num_checked_points = num_checked_points + 1;
|
||||
end
|
||||
|
||||
if (2 < num_checked_points) begin
|
||||
$display("Simulation finish with %d errors", num_errors);
|
||||
|
||||
// End simulation
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -61,6 +61,11 @@ with open(args.pre_pnr_testbench, "r") as wp:
|
|||
# Other lines can be directly copied to post-PnR Verilog testbenches
|
||||
line2output = curr_line \
|
||||
# Condition A:
|
||||
# Add post_pnr to top-level module name
|
||||
if (curr_line.startswith("module")):
|
||||
line2output = re.sub("autocheck_top_tb;$", "post_pnr_autocheck_top_tb;", curr_line)
|
||||
# Add sc_head and sc_tail wire definition after ccff tail definition
|
||||
# Condition B:
|
||||
# Add sc_head and sc_tail wire definition after ccff tail definition
|
||||
if (curr_line == "wire [0:0] ccff_tail;\n"):
|
||||
line2output = line2output \
|
||||
|
|
@ -68,16 +73,16 @@ with open(args.pre_pnr_testbench, "r") as wp:
|
|||
+ "wire [0:0] sc_head;\n" \
|
||||
+ "// ---- Scan-chain tail ----\n" \
|
||||
+ "wire [0:0] sc_tail;\n"
|
||||
# Condition B:
|
||||
# Condition C:
|
||||
# Assign an initial value to sc_head after other ports
|
||||
elif (curr_line == "\tassign IO_ISOL_N[0] = 1'b1;\n"):
|
||||
line2output = line2output \
|
||||
+ "\tassign sc_head[0] = 1'b0;\n"
|
||||
# Condition C:
|
||||
# Condition D:
|
||||
# Replace fpga_top with fpga_core in DUT instanciation
|
||||
elif (curr_line == "\tfpga_top FPGA_DUT (\n"):
|
||||
line2output = "\tfpga_core FPGA_DUT (\n"
|
||||
# Condition D:
|
||||
# Condition E:
|
||||
# Add sc_head and sc_tail to the port mapping of FPGA core instance
|
||||
elif (curr_line == "\t\t.ccff_tail(ccff_tail[0]));\n"):
|
||||
line2output = "\t\t.ccff_tail(ccff_tail[0]),\n" \
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v (Stored with Git LFS)
BIN
TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v (Stored with Git LFS)
Binary file not shown.
Binary file not shown.
|
|
@ -1,30 +0,0 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Netlist Summary
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
// Date: Fri Nov 20 15:48:46 2020
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ------ Include simulation defines -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
|
||||
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
|
||||
// ------ Include Skywater cell netlists -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "bin2bcd_output_verilog.v"
|
||||
`endif
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_autocheck_top_tb.v"
|
||||
`endif
|
||||
|
||||
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|
|
@ -1,29 +0,0 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Netlist Summary
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
// Date: Fri Nov 20 15:48:45 2020
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ------ Include simulation defines -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
|
||||
// ------ Include Skywater cell netlists -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "counter_output_verilog.v"
|
||||
`endif
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/counter_post_pnr_autocheck_top_tb.v"
|
||||
`endif
|
||||
|
||||
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|
|
@ -1,30 +0,0 @@
|
|||
//-------------------------------------------
|
||||
// FPGA Synthesizable Verilog Netlist
|
||||
// Description: Netlist Summary
|
||||
// Author: Xifan TANG
|
||||
// Organization: University of Utah
|
||||
// Date: Fri Nov 20 15:49:05 2020
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// ------ Include simulation defines -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
|
||||
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
|
||||
// ------ Include Skywater cell netlists -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
//`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_FC_HD_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v"
|
||||
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/Nov2020_Skywater/FPGA1212_FLAT_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "top_module_output_verilog.v"
|
||||
`endif
|
||||
|
||||
`ifdef AUTOCHECKED_SIMULATION
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/top_module_post_pnr_autocheck_top_tb.v"
|
||||
`endif
|
||||
|
||||
Loading…
Reference in New Issue