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SOFA
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631 Commits 16 Branches 1 Tag 1.8 GiB
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75 Commits

Author SHA1 Message Date
Lalit Sharma 0cdd94139f using default yosys script instead of custom script for multi_enc_decx2x4 design as custom script generated blif file is causing an assertion in openfpga. This is done temporarily to enable developers to checkin in SOFA, also requested Xifan to review this crash in openfpga. 2021-02-03 01:08:27 -08:00
Lalit Sharma c34c777409 Using custom yosys script for benchmarks run in generate_testbench task 2021-01-20 21:18:38 -08:00
Lalit Sharma 4128f4cd1b Enabling custom yosys script only for and gate design, will enable later for other designs when yosys submodule is updated 2021-01-07 01:15:41 -08:00
Lalit Sharma 847d0ec8f6 Adding io_reg related simple design 2021-01-06 23:24:34 -08:00
Lalit Sharma 9b3cd1f5ff Updating task template file by calling synth_quicklogic inside yosys 2021-01-06 23:19:20 -08:00
Tarachand Pagarani 1a4b1bc6b4 Disable generation of formal verification testbench due to disk space 
limitation on github actions.
Disable testcase not fitting on 32x32 device
 2021-01-05 19:44:08 -08:00
Tarachand Pagarani cbe50535ca further changes in architecture to make io interfaces routable 2020-12-28 08:35:17 -08:00
Tarachand Pagarani 474ed9b2ff Merge remote-tracking branch 'origin/master' into ql_ap3_arch_eval 2020-12-26 23:57:23 -08:00
Tarachand Pagarani 353207693a 1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture 2020-12-26 23:29:13 -08:00
Tarachand Pagarani 1aa0ef68e4 incoporated changes based on feedback from xifan 2020-12-24 23:05:47 -08:00
Tarachand Pagarani 01fabc65cc added a new architecture with LUT4, Soft adder and cross local routing with 24 clb inputs and feedback 2020-12-21 07:13:38 -08:00
Ganesh Gore f494c31ca0 [Action] More cleanup while precheck 2020-12-20 17:04:56 -07:00
Ganesh Gore 37bca4684b [BugFix] After Integration with mpw-one-b 2020-12-17 09:29:54 -07:00
Tarachand Pagarani 8d5036f108 commented/corrected failing benchmarks 2020-12-17 05:46:30 -08:00
Tarachand Pagarani c264ee0ddd add more benchmark tests 2020-12-17 02:17:20 -08:00
Tarachand Pagarani cfdaedcdd0 added script with random key generation example 2020-12-17 01:42:19 -08:00
Tarachand Pagarani b556cf452c add tasks for 32x32 configuration 2020-12-17 01:40:19 -08:00
Ganesh Gore 3c174619b0 [Action] Updated action script for local run 2020-12-14 12:08:16 -07:00
Ganesh Gore def270a94b [Actions] Launched checker in correct directory 2020-12-08 21:50:18 -07:00
Ganesh Gore 3ecd96596f [Actions] Merged Caravel with Klayout 2020-12-08 13:33:17 -07:00
Ganesh Gore b0098ed4b9 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-12-06 21:29:06 -07:00
Ganesh Gore 10cab93799 [Action] Integrated MPW prechecker 2020-12-06 01:41:58 -07:00
tangxifan c015d65a03 [Script] Add task run for custom cell FPGA architectures 2020-12-06 01:40:21 -07:00
tangxifan 696529b43d [Script] Increase routing chan width from 40 to 60 for version 1.2 2020-12-06 01:39:16 -07:00
tangxifan 2db2b468fe [Script] Try auto number of simulation clock cycles 2020-12-02 19:33:28 -07:00
tangxifan 930f7ec486 [Script] Remove task run for redundant architectures 2020-12-02 17:56:58 -07:00
tangxifan b966829566 [Script] Force a fixed number of clock cycles in simulation to avoid false-positive 2020-12-02 17:50:23 -07:00
tangxifan 147dd8d606 [Script] Add task run for custom cell FPGA architectures 2020-12-01 20:22:16 -07:00
tangxifan 0eb1b68bee [Script] Increase routing chan width from 40 to 60 for version 1.2 2020-12-01 10:17:47 -07:00
tangxifan 6a12cdbad1 [Script] Add task run for the architecture with both reset and soft adders 2020-11-27 18:15:05 -07:00
tangxifan e5a66dd47f [Script] Add task run for softadder architecture 2020-11-27 16:14:14 -07:00
tangxifan 28c8dba87b [Script] Bug fix in task configuration files 2020-11-27 15:05:35 -07:00
tangxifan 91edfb8e02 [Script] Add task run for the architecture with reset 2020-11-27 14:45:00 -07:00
tangxifan 2d30c10403 [Script] Now batch task run will error out in the first failed task 2020-11-26 18:30:01 -07:00
tangxifan c237500588 [Script] Remove signal initialization from testbench generator 2020-11-26 18:23:26 -07:00
tangxifan 973fe1acc8 [Script] Add signal initialization to openfpga-run scripts 2020-11-23 15:13:06 -07:00
tangxifan e8abcc64bb [Script] Add and2_or2 benchmark to the testbench generation script for 12x12 HD FPGA 2020-11-22 13:34:53 -07:00
tangxifan a5a92d719a [Script] Remove benchmarks which cannot fit from task-run 2020-11-20 15:44:30 -07:00
tangxifan ce188bbe2c [Script] Add benchmarks to openfpga testbench generator task-run 2020-11-20 15:35:57 -07:00
tangxifan b07a156432 [Script] Deploy more testing benchmarks to the OpenFPGA testbench generation task 2020-11-20 15:10:29 -07:00
tangxifan 86bb530709 [Script] Update openfpga task-run script to use the adhoc simulation settings tuned for Caravel SoC 2020-11-17 15:03:10 -07:00
tangxifan cbd9239e41 [Script] Add custom simulation settings for the Skywater 130nm eFPGA fabric 2020-11-17 14:57:23 -07:00
tangxifan a97598cef9 [Script] Patch example openfpga shell script to manage clock routing in VPR 2020-11-17 14:27:14 -07:00
tangxifan 0e2ee8a0cc [Script] Add benchmarks to OpenFPGA task run 2020-11-17 14:01:48 -07:00
tangxifan 39aa11c42c [Script] Update OpenFPGA task run configuration for pre-pnr files 2020-11-17 13:46:25 -07:00
tangxifan efda8e0f73 [Script] Update task run configuration in output directory 2020-11-17 13:21:26 -07:00
tangxifan 46171472a7 [Script] Rename output directory for netlsit generation 2020-11-13 17:47:38 -07:00
tangxifan be33082faf [Arch] Remove out-of-data architectures 2020-11-13 09:50:45 -07:00
tangxifan 6344bb420d [Script] Remove out-of-data task run 2020-11-13 09:47:32 -07:00
tangxifan d3ae847f43 [Script] Add openfpga task for 12x12 fabric fit caravel SoC 2020-11-11 15:20:01 -07:00