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[Script] Add signal initialization to openfpga-run scripts

This commit is contained in:
tangxifan 2020-11-23 15:13:06 -07:00
parent 1c40ab68a1
commit 973fe1acc8
1 changed files with 1 additions and 0 deletions
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SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
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@ -59,6 +59,7 @@ write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench
--print_top_testbench \
--print_preconfig_top_testbench \
--print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
--include_signal_init \
--explicit_port_mapping
# Write the SDC to run timing analysis for a mapped FPGA fabric