diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
index 38e4631..b2cf0f9 100644
--- a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
+++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
@@ -59,6 +59,7 @@ write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench
   --print_top_testbench \
   --print_preconfig_top_testbench \
   --print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
+  --include_signal_init \
   --explicit_port_mapping
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric