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614 Commits 16 Branches 1 Tag 1.8 GiB
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614 Commits

Author SHA1 Message Date
Kevin Liao f1eb4c4f88 rename module name to IO from EMBEDDED_IO_HD 2021-01-21 20:52:16 -08:00
Kevin Liao f7af0b40cf rename prefix for circuit_model iopad 2021-01-21 20:50:00 -08:00
Tarachand Pagarani 9c1b2ca4d4 update the name of IO cell and ports to be consistent with QL names 2021-01-21 04:18:25 -08:00
Tarachand Pagarani 3085cf7c2c remove io clk from output mux till prepack in VPR is updated to ignore physical mode 2021-01-20 01:16:59 -08:00
Tarachand Pagarani 36739d9c7c Merge branch 'k4_N8_interface' of https://github.com/lnis-uofu/SOFA into k4_N8_interface 2021-01-17 23:55:54 -08:00
Tarachand Pagarani 72d8d20356 1. Add 4 clocks to IO interfaces 
2. Mux the clock with the output for sending the clock out of the FPGA
 2021-01-17 23:54:39 -08:00
Kevin Liao 69ed6b5e27 forgot to add new port, IO_ISOL_N, for EMBEDDED_IO_HD 2021-01-15 12:48:32 -08:00
Kevin Liao f428234df8 correct EMBEDDED_IO_HD verilog pointer 2021-01-15 11:08:43 -08:00
Tarachand Pagarani ac355c370d merge latest changes from master 2021-01-15 00:26:25 -08:00
tpagarani 6f0dc05ffa
Merge pull request #87 from lnis-uofu/multiple_global_clocks 
add 4 global clocks
 2021-01-15 02:34:21 -05:00
Kevin Liao 806303af11 remove soft_adder, and fix Test_en from ccff 2021-01-14 20:14:04 -08:00
Kevin Liao 742d16ec39 new revised isolation io logic 2021-01-14 20:11:21 -08:00
Tarachand Pagarani 3f5409eee2 add 4 global clocks 2021-01-14 02:28:07 -08:00
Lalit Sharma ba34ebb4e5 Removing commented sections/attributes. Also corrected indentation 2021-01-13 00:48:03 -08:00
Lalit Sharma 6702de4516 Merging latest changes from master related to tile_port deprecation 2021-01-12 22:33:04 -08:00
tpagarani 40ddcdff67
Merge pull request #85 from lnis-uofu/update_tile_port 
Replacing deprecated tile_port syntax
 2021-01-13 01:22:45 -05:00
Lalit Sharma 51f11ee630 Replacing deprecated tile_port syntax 2021-01-12 21:33:53 -08:00
Kevin Liao e06fdd0a48 add annotation to support soft_adder mode 2021-01-12 21:21:53 -08:00
Kevin Liao e330b19408 Merge branch 'k4_N8_interface' of https://github.com/lnis-uofu/SOFA into k4_N8_interface 2021-01-12 21:15:15 -08:00
Kevin Liao be47862b87 created for quicklogic special io logic 2021-01-12 21:14:09 -08:00
Lalit Sharma ef4e064838 Updating openfpga with Kevin's changes done related to IO interface with an option of registered and non-registered IOs 2021-01-12 11:06:29 +05:30
Kevin Liao 489e370390 init 2021-01-11 21:11:12 -08:00
Lalit Sharma 8f1bdc2e87 Updating interface definition for QL k4_N8 device 2021-01-11 23:20:49 +05:30
tpagarani e82d2bf0d1
Merge pull request #84 from lnis-uofu/update_task_conf 
Update task conf
 2021-01-07 07:59:54 -05:00
Lalit Sharma 4128f4cd1b Enabling custom yosys script only for and gate design, will enable later for other designs when yosys submodule is updated 2021-01-07 01:15:41 -08:00
Lalit Sharma 847d0ec8f6 Adding io_reg related simple design 2021-01-06 23:24:34 -08:00
Lalit Sharma 9b3cd1f5ff Updating task template file by calling synth_quicklogic inside yosys 2021-01-06 23:19:20 -08:00
tangxifan b3f001c3fa
Merge pull request #81 from lnis-uofu/ql_ap3_arch_eval 
QL specific architecture compatible with AP3
 2021-01-06 11:08:10 -07:00
Tarachand Pagarani 1a4b1bc6b4 Disable generation of formal verification testbench due to disk space 
limitation on github actions.
Disable testcase not fitting on 32x32 device
 2021-01-05 19:44:08 -08:00
Tarachand Pagarani f04e72b5b3 create a copy of cout to connect to regular routing 2020-12-30 06:02:51 -08:00
Tarachand Pagarani 473e1d68a6 fix the carry in dangling 2020-12-29 19:04:56 -08:00
Tarachand Pagarani 61facff870 fix the carry in dangling and carry out accessible to regular routing 2020-12-29 18:54:48 -08:00
Tarachand Pagarani cbe50535ca further changes in architecture to make io interfaces routable 2020-12-28 08:35:17 -08:00
Tarachand Pagarani 474ed9b2ff Merge remote-tracking branch 'origin/master' into ql_ap3_arch_eval 2020-12-26 23:57:23 -08:00
Tarachand Pagarani 353207693a 1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture 2020-12-26 23:29:13 -08:00
Tarachand Pagarani 1aa0ef68e4 incoporated changes based on feedback from xifan 2020-12-24 23:05:47 -08:00
tangxifan 6428539dcb
Merge pull request #80 from lnis-uofu/ganesh_dev 
Physical design - Critical patch on dangling nets in logic elements
 2020-12-22 08:15:29 -07:00
tangxifan d4b4676ec8
Merge pull request #79 from lnis-uofu/xt_dev 
Critical patch on dangling nets in logic elements
 2020-12-22 08:15:14 -07:00
Ganesh Gore e1a25d61dc [QLSOFA] Bugfix to fix floating cin net 2020-12-22 00:23:37 -07:00
Ganesh Gore 562641ed4d [SOFA-CHD] Bugfix to fix floating cin net 2020-12-22 00:23:12 -07:00
tangxifan 6a6b89e7b8 [Arch] Critical patch on dangling nets in logic elements 2020-12-21 22:23:41 -07:00
tangxifan eba3827b77
Merge pull request #78 from lnis-uofu/xt_dev 
Update documentation with latest GDS view
 2020-12-21 13:16:33 -07:00
tangxifan 81a31ea022 [Doc] Update documentation with latest GDS view 2020-12-21 12:37:19 -07:00
Tarachand Pagarani 01fabc65cc added a new architecture with LUT4, Soft adder and cross local routing with 24 clb inputs and feedback 2020-12-21 07:13:38 -08:00
Ganesh Gore f494c31ca0 [Action] More cleanup while precheck 2020-12-20 17:04:56 -07:00
tangxifan e2c33f1ab3
Merge pull request #77 from lnis-uofu/ganesh_dev 
Updated GDS with chip art  + Cleanup
 2020-12-20 12:11:58 -07:00
Ganesh Gore 6ef27d5399 [Cleanup] Removed old task and verilog directories 2020-12-20 10:50:13 -07:00
Ganesh Gore c36e8d797a Updated all the results 2020-12-20 03:44:00 -07:00
Ganesh Gore 55acf06335 Updated design with new GDS nad updated verilog netlist 2020-12-20 03:31:26 -07:00
Ganesh Gore 5bb8adb448 [Cleanup] Converted .gds to .gds.gz 2020-12-20 02:12:31 -07:00