| .. |
|
verilog_api.c
|
add top module generation and refactored verilog generation for top module
|
2019-10-23 12:16:58 -06:00 |
|
verilog_api.h
|
move mux_lib to fpga_x2p_setup
|
2019-10-19 19:13:52 -06:00 |
|
verilog_autocheck_top_testbench.c
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
verilog_autocheck_top_testbench.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_compact_netlist.c
|
move the refactored function for physical block Verilog generation to a new source file
|
2019-10-07 16:03:15 -06:00 |
|
verilog_compact_netlist.h
|
move the refactored function for physical block Verilog generation to a new source file
|
2019-10-07 16:03:15 -06:00 |
|
verilog_decoder.c
|
fix
|
2019-10-01 16:54:16 -06:00 |
|
verilog_decoder.h
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_decoders.cpp
|
plug in module graph to feed verilog writers
|
2019-10-18 21:59:22 -06:00 |
|
verilog_decoders.h
|
start refactoring memory decoders
|
2019-09-13 20:58:55 -06:00 |
|
verilog_essential_gates.cpp
|
add const 0 and 1 module Verilog generation
|
2019-10-21 14:17:09 -06:00 |
|
verilog_essential_gates.h
|
plug in module manager
|
2019-08-23 20:23:41 -06:00 |
|
verilog_formal_random_top_testbench.c
|
Update Testbenches to increase accuracy + commented compact routing option until debug
|
2019-06-26 10:01:12 -06:00 |
|
verilog_formal_random_top_testbench.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_formality_autodeck.c
|
Separated Modelsim tcl script generation
|
2019-09-07 12:36:22 -04:00 |
|
verilog_formality_autodeck.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_global.c
|
Finish renaming SCFF to CCFF
|
2019-09-26 14:04:40 -06:00 |
|
verilog_global.h
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
|
verilog_grid.cpp
|
add grid module generation
|
2019-10-22 16:14:11 -06:00 |
|
verilog_grid.h
|
add grid module generation
|
2019-10-22 16:14:11 -06:00 |
|
verilog_include_netlists.c
|
rework on the order of top-level functions
|
2019-09-13 21:59:52 -06:00 |
|
verilog_include_netlists.h
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
|
verilog_lut.cpp
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
verilog_lut.h
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
verilog_memory.cpp
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
verilog_memory.h
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
verilog_modelsim_autodeck.c
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_modelsim_autodeck.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
verilog_module_writer.cpp
|
bug fixed for local encoders and module nets creation
|
2019-10-21 12:23:00 -06:00 |
|
verilog_module_writer.h
|
developing verilog writer for generic module graph
|
2019-10-10 20:09:55 -06:00 |
|
verilog_mux.cpp
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
verilog_mux.h
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
verilog_pbtypes.c
|
refactored port addition for pb_types in Verilog generation
|
2019-10-08 14:03:17 -06:00 |
|
verilog_pbtypes.h
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |
|
verilog_primitives.c
|
Fully functional
|
2019-09-13 16:02:06 -06:00 |
|
verilog_primitives.h
|
Include new files in the parameter spreading
|
2019-07-01 11:27:48 -06:00 |
|
verilog_report_timing.c
|
Explicit verilog final push
|
2019-07-16 13:13:30 -06:00 |
|
verilog_report_timing.h
|
updated bitstream to use new RRSwitchBlock as well as the report timing engine
|
2019-05-24 12:54:10 -06:00 |
|
verilog_routing.c
|
refactored routing module generation and verilog writing
|
2019-10-23 11:46:55 -06:00 |
|
verilog_routing.h
|
refactored routing module generation and verilog writing
|
2019-10-23 11:46:55 -06:00 |
|
verilog_sdc.c
|
Correction to the explicit Verilog for FPGAs above 2x2
|
2019-09-13 16:02:06 -06:00 |
|
verilog_sdc.h
|
Division between horizontal and vertical analysis
|
2019-06-25 13:44:41 -06:00 |
|
verilog_sdc_pb_types.c
|
Break memories even in the clb sdc
|
2019-06-16 14:27:29 -06:00 |
|
verilog_sdc_pb_types.h
|
clean up warnings in SDC pb_type generator
|
2019-05-24 15:23:38 -06:00 |
|
verilog_submodule_utils.cpp
|
minor tuning on the delay assignment
|
2019-08-21 23:11:54 -06:00 |
|
verilog_submodule_utils.h
|
complete refacotriing the inv and buf part in submodules
|
2019-08-21 14:54:05 -06:00 |
|
verilog_submodules.c
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
verilog_submodules.h
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-25 15:33:37 -06:00 |
|
verilog_tcl_utils.c
|
Correction to the explicit Verilog for FPGAs above 2x2
|
2019-09-13 16:02:06 -06:00 |
|
verilog_tcl_utils.h
|
Snapshot of progress
|
2019-07-02 10:10:48 -06:00 |
|
verilog_top_module.cpp
|
add top module generation and refactored verilog generation for top module
|
2019-10-23 12:16:58 -06:00 |
|
verilog_top_module.h
|
add top module generation and refactored verilog generation for top module
|
2019-10-23 12:16:58 -06:00 |
|
verilog_top_netlist_utils.c
|
Explicit verilog passing all tests
|
2019-10-02 10:22:28 -06:00 |
|
verilog_top_netlist_utils.h
|
Latest version explicit
|
2019-07-11 14:33:56 -06:00 |
|
verilog_top_testbench.c
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
verilog_top_testbench.h
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
verilog_utils.c
|
move the refactored function for physical block Verilog generation to a new source file
|
2019-10-07 16:03:15 -06:00 |
|
verilog_utils.h
|
move the refactored function for physical block Verilog generation to a new source file
|
2019-10-07 16:03:15 -06:00 |
|
verilog_verification_top_netlist.c
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
|
verilog_verification_top_netlist.h
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
verilog_wire.cpp
|
add wire module generation and simplify Verilog generation for wires
|
2019-10-21 20:20:34 -06:00 |
|
verilog_wire.h
|
refactored wire Verilog generation
|
2019-09-12 20:49:02 -06:00 |
|
verilog_writer_utils.cpp
|
add memory ports and nets to intermediate pb_types
|
2019-10-13 17:45:32 -06:00 |
|
verilog_writer_utils.h
|
developing verilog writer for generic module graph
|
2019-10-10 20:09:55 -06:00 |
fb2f003d5b