| .. |
|
basic_command.cpp
|
add read_openfpga_arch to OpenFPGA shell
|
2020-01-23 19:10:53 -07:00 |
|
basic_command.h
|
add read_openfpga_arch to OpenFPGA shell
|
2020-01-23 19:10:53 -07:00 |
|
io_location_map.cpp
|
build io location map
|
2020-02-26 19:58:18 -07:00 |
|
io_location_map.h
|
add io location map data structure and start porting verilog testbench generator
|
2020-02-26 17:10:57 -07:00 |
|
openfpga_bitstream.cpp
|
bring pnr sdc generator online and fixed minor bugs in bitstream writing
|
2020-02-28 11:14:50 -07:00 |
|
openfpga_bitstream.h
|
make write bitstream online
|
2020-02-26 11:09:23 -07:00 |
|
openfpga_bitstream_command.cpp
|
clean-up command addition and add fabric bitstream building to sample script
|
2020-03-02 10:39:19 -07:00 |
|
openfpga_bitstream_command.h
|
start working on repack
|
2020-02-17 17:57:43 -07:00 |
|
openfpga_build_fabric.cpp
|
build io location map
|
2020-02-26 19:58:18 -07:00 |
|
openfpga_build_fabric.h
|
build io location map
|
2020-02-26 19:58:18 -07:00 |
|
openfpga_context.h
|
adapt top-level function for analysis SDC writer
|
2020-03-02 17:58:44 -07:00 |
|
openfpga_flow_manager.cpp
|
bring fpga verilog create directory online
|
2020-02-15 20:38:45 -07:00 |
|
openfpga_flow_manager.h
|
bring fpga verilog create directory online
|
2020-02-15 20:38:45 -07:00 |
|
openfpga_interconnect_types.h
|
make grid module builder online; basic support on physical tiles
|
2020-02-13 15:27:16 -07:00 |
|
openfpga_link_arch.cpp
|
move simulation setting annotation to a separated source file
|
2020-02-29 15:19:02 -07:00 |
|
openfpga_link_arch.h
|
add verbose output option for openfpga linking architecture
|
2020-01-31 11:36:58 -07:00 |
|
openfpga_lut_truth_table_fixup.cpp
|
bug fixed for lut truth table fixup. Results look good
|
2020-02-06 17:47:25 -07:00 |
|
openfpga_lut_truth_table_fixup.h
|
add functionality of LUT truth table fix-up
|
2020-02-06 17:14:29 -07:00 |
|
openfpga_naming.cpp
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
|
openfpga_naming.h
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
|
openfpga_pb_pin_fixup.cpp
|
bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
|
2020-02-20 20:50:59 -07:00 |
|
openfpga_pb_pin_fixup.h
|
done an initial version of clustering net fix-up based on routing results. Debugging on the way
|
2020-02-05 21:50:52 -07:00 |
|
openfpga_read_arch.cpp
|
add write_openfpga_arch command to openfpga shell
|
2020-01-23 20:58:15 -07:00 |
|
openfpga_read_arch.h
|
add write_openfpga_arch command to openfpga shell
|
2020-01-23 20:58:15 -07:00 |
|
openfpga_repack.cpp
|
add truth table build up for physical LUTs
|
2020-02-25 22:39:42 -07:00 |
|
openfpga_repack.h
|
start working on repack
|
2020-02-17 17:57:43 -07:00 |
|
openfpga_reserved_words.h
|
make grid module builder online; basic support on physical tiles
|
2020-02-13 15:27:16 -07:00 |
|
openfpga_sdc.cpp
|
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
|
openfpga_sdc.h
|
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
|
openfpga_sdc_command.cpp
|
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
|
openfpga_sdc_command.h
|
bring pnr sdc generator online and fixed minor bugs in bitstream writing
|
2020-02-28 11:14:50 -07:00 |
|
openfpga_setup_command.cpp
|
clean-up command addition and add fabric bitstream building to sample script
|
2020-03-02 10:39:19 -07:00 |
|
openfpga_setup_command.h
|
add read_openfpga_arch to OpenFPGA shell
|
2020-01-23 19:10:53 -07:00 |
|
openfpga_title.cpp
|
update title page
|
2020-01-24 17:00:53 -07:00 |
|
openfpga_title.h
|
start split workload from the main.cpp in openfpga
|
2020-01-23 13:24:35 -07:00 |
|
openfpga_verilog.cpp
|
bug fix for using renamed i/o names
|
2020-02-27 16:37:20 -07:00 |
|
openfpga_verilog.h
|
ported verilog testbench generator online. Split from fabric generator. Testing to be done
|
2020-02-27 12:33:09 -07:00 |
|
openfpga_verilog_command.cpp
|
clean-up command addition and add fabric bitstream building to sample script
|
2020-03-02 10:39:19 -07:00 |
|
openfpga_verilog_command.h
|
bring fpga verilog create directory online
|
2020-02-15 20:38:45 -07:00 |
7fcd27e000