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OpenFPGA/openfpga/src/fpga_verilog
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tangxifan 8ab090651a [FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports 2022-03-16 20:51:37 +08:00
..
fabric_verilog_options.cpp [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
fabric_verilog_options.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_api.cpp [FPGA-Verilog] Adding bus group support to all Verilog testbench generators 2022-02-17 23:48:44 -08:00
verilog_api.h [FPGA-Verilog] Adding bus group support to all Verilog testbench generators 2022-02-17 23:48:44 -08:00
verilog_auxiliary_netlists.cpp [FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path`` 2022-02-01 13:25:09 -08:00
verilog_auxiliary_netlists.h [FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path`` 2022-02-01 13:25:09 -08:00
verilog_constants.h [FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists 2021-09-29 20:56:02 -07:00
verilog_decoders.cpp [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
verilog_decoders.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_essential_gates.cpp [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
verilog_essential_gates.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_formal_random_top_testbench.cpp [FPGA-Verilog] Now output atom block name removal has a dedicated function 2022-02-18 14:30:46 -08:00
verilog_formal_random_top_testbench.h [FPGA-Verilog] Adding bus group support to all Verilog testbench generators 2022-02-17 23:48:44 -08:00
verilog_grid.cpp [FPGA-Verilog] Fix bugs 2022-01-31 14:23:04 -08:00
verilog_grid.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_lut.cpp [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
verilog_lut.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_memory.cpp [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
verilog_memory.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_module_writer.cpp [Tool] Bug fix for printing single-bit ports in Verilog netlists 2021-02-28 16:12:57 -07:00
verilog_module_writer.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_mux.cpp [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
verilog_mux.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_port_types.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_preconfig_top_module.cpp [FPGA-Verilog] Fixed a bug on config-enable signals 2022-02-23 22:35:23 -08:00
verilog_preconfig_top_module.h [FPGA-Verilog] Adding bus group support in Verilog testbenches 2022-02-17 23:14:28 -08:00
verilog_routing.cpp [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
verilog_routing.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_shift_register_banks.cpp [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
verilog_shift_register_banks.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_simulation_info_writer.cpp [Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes 2021-06-29 15:26:40 -06:00
verilog_simulation_info_writer.h [Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches 2021-06-25 10:10:16 -06:00
verilog_submodule.cpp [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_submodule.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_submodule_utils.cpp [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_submodule_utils.h [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
verilog_testbench_options.cpp [FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path`` 2022-02-01 12:17:02 -08:00
verilog_testbench_options.h [FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path`` 2022-02-01 12:17:02 -08:00
verilog_testbench_utils.cpp [FPGA-Verilog] Add big/little endian support to output ports 2022-02-19 09:23:48 -08:00
verilog_testbench_utils.h [FPGA-Verilog] Streamline codes by using APIs 2022-02-18 14:47:36 -08:00
verilog_top_module.cpp [FPGA-Verilog] Fix bugs 2022-01-31 14:23:04 -08:00
verilog_top_module.h [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
verilog_top_testbench.cpp [FPGA-Verilog] Fixing bugs when using bus group in full testbench generator 2022-02-18 15:41:35 -08:00
verilog_top_testbench.h [FPGA-Verilog] Adding bus group support in Verilog testbenches 2022-02-17 23:14:28 -08:00
verilog_top_testbench_constants.h [FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports 2022-03-16 20:51:37 +08:00
verilog_top_testbench_memory_bank.cpp [FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks 2021-10-10 23:19:39 -07:00
verilog_top_testbench_memory_bank.h [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
verilog_wire.cpp [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
verilog_wire.h [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
verilog_writer_utils.cpp [FPGA-Verilog] Now support big/little-endian in bus group 2022-02-18 23:05:03 -08:00
verilog_writer_utils.h [FPGA-Verilog] Now support big/little-endian in bus group 2022-02-18 23:05:03 -08:00