104 lines
4.2 KiB
C++
104 lines
4.2 KiB
C++
#ifndef VERILOG_TESTBENCH_OPTIONS_H
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#define VERILOG_TESTBENCH_OPTIONS_H
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/********************************************************************
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* Include header files required by the data structure definition
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*******************************************************************/
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#include <string>
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#include "verilog_port_types.h"
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/* Begin namespace openfpga */
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namespace openfpga {
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/* Embedded bitstream code style */
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enum e_embedded_bitstream_hdl_type {
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EMBEDDED_BITSTREAM_HDL_IVERILOG,
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EMBEDDED_BITSTREAM_HDL_MODELSIM,
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NUM_EMBEDDED_BITSTREAM_HDL_TYPES
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};
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constexpr std::array<const char*, NUM_EMBEDDED_BITSTREAM_HDL_TYPES + 1> EMBEDDED_BITSTREAM_HDL_TYPE_STRING = {{"iverilog", "modelsim", "none"}}; //String versions of default net types
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/********************************************************************
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* Options for Verilog Testbench generator
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* Typicall usage:
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* VerilogTestbench verilog_tb_opt();
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* // Set options
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* ...
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*
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*******************************************************************/
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class VerilogTestbenchOption {
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public: /* Public constructor */
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/* Set default options */
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VerilogTestbenchOption();
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public: /* Public accessors */
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std::string output_directory() const;
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std::string fabric_netlist_file_path() const;
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std::string reference_benchmark_file_path() const;
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bool fast_configuration() const;
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bool print_formal_verification_top_netlist() const;
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bool print_preconfig_top_testbench() const;
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bool print_top_testbench() const;
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bool print_simulation_ini() const;
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std::string simulation_ini_path() const;
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bool explicit_port_mapping() const;
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bool include_signal_init() const;
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bool no_self_checking() const;
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e_verilog_default_net_type default_net_type() const;
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e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const;
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float time_unit() const;
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bool time_stamp() const;
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bool use_relative_path() const;
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bool verbose_output() const;
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public: /* Public validator */
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bool validate() const;
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public: /* Public mutators */
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void set_output_directory(const std::string& output_dir);
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/* The reference verilog file path is the key parameters that will have an impact on other options:
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* - print_preconfig_top_testbench
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* - print_top_testbench
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* If the file path is empty, the above testbench generation will not be enabled
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*/
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void set_reference_benchmark_file_path(const std::string& reference_benchmark_file_path);
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/* The fabric netlist file path is an optional parameter
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* to allow users to specify a fabric netlist at another location
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*/
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void set_fabric_netlist_file_path(const std::string& fabric_netlist_file_path);
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void set_print_formal_verification_top_netlist(const bool& enabled);
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/* The preconfig top testbench generation can be enabled only when formal verification top netlist is enabled */
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void set_print_preconfig_top_testbench(const bool& enabled);
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void set_fast_configuration(const bool& enabled);
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void set_print_top_testbench(const bool& enabled);
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void set_print_simulation_ini(const std::string& simulation_ini_path);
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void set_explicit_port_mapping(const bool& enabled);
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void set_include_signal_init(const bool& enabled);
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void set_default_net_type(const std::string& default_net_type);
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void set_time_unit(const float& time_unit);
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void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
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void set_time_stamp(const bool& enabled);
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void set_use_relative_path(const bool& enabled);
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void set_verbose_output(const bool& enabled);
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private: /* Internal Data */
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std::string output_directory_;
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std::string fabric_netlist_file_path_;
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std::string reference_benchmark_file_path_;
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bool fast_configuration_;
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bool print_formal_verification_top_netlist_;
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bool print_preconfig_top_testbench_;
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bool print_top_testbench_;
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/* Print simulation ini is enabled only when the path is not empty */
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std::string simulation_ini_path_;
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bool explicit_port_mapping_;
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bool include_signal_init_;
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e_verilog_default_net_type default_net_type_;
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e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
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float time_unit_;
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bool time_stamp_;
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bool use_relative_path_;
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bool verbose_output_;
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};
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} /* End namespace openfpga*/
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#endif
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