tangxifan
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fc6abc13fd
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add physical tile utils to identify pins that have Fc=0
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2020-03-21 21:02:47 -06:00 |
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tangxifan
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7b9384f3b2
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add write_gsb command to shell interface
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2020-03-21 19:40:26 -06:00 |
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tangxifan
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637be076dc
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adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
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2020-03-21 18:49:20 -06:00 |
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tangxifan
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9a518e8bb6
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bug fixed for tileable rr_graph builder for more 4x4 fabrics
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2020-03-21 18:07:00 -06:00 |
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tangxifan
|
63c4669dbb
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fixed bug in the fast look-up for tileable rr_graph
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2020-03-21 17:36:08 -06:00 |
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tangxifan
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c0e8d98c6f
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bug fixed in tile direct builder
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2020-03-21 12:43:56 -06:00 |
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tangxifan
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8f35f191eb
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use the formalized function in FPGA-SDC to identify direct connection
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2020-03-21 11:42:00 -06:00 |
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tangxifan
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28123b8052
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remove the direct connected IPIN/OPIN from RR GSB builder
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2020-03-21 11:38:39 -06:00 |
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tangxifan
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2ff2d65e58
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start debugging tileable routing using larger array size. Bug spotted in finding chan nodes
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2020-03-20 22:12:23 -06:00 |
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tangxifan
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682b667a3c
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minor bug fix for direct connection in FPGA-SDC
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2020-03-20 21:44:01 -06:00 |
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tangxifan
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05ec86430a
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temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT!
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2020-03-20 17:56:03 -06:00 |
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tangxifan
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3c37b33f17
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critical bug fixed in edge sorting for rr_gsb
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2020-03-20 17:45:50 -06:00 |
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tangxifan
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2c0c5a061b
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spot a bug in assigning rr_switch in tileable routing
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2020-03-20 16:53:43 -06:00 |
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tangxifan
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708fda9606
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fixed a bug in using tileable routing when directlist is enabled
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2020-03-20 16:38:58 -06:00 |
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tangxifan
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c5049a1ec8
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keep debugging tile direct connections
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2020-03-20 15:10:00 -06:00 |
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tangxifan
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a46fc9f028
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add debugging information for tile direct builder
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2020-03-20 14:59:46 -06:00 |
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tangxifan
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9837be618d
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start debugging tile direct with micro architecture
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2020-03-20 14:52:52 -06:00 |
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tangxifan
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a0b150f12e
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adding micro architecture using adder chain
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2020-03-20 14:18:59 -06:00 |
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tangxifan
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8d57808d07
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add missing files for micro benchmarks
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2020-03-20 11:08:55 -06:00 |
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tangxifan
|
808853db0b
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critical bug fixed for find proper pb_route traceback
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2020-03-13 12:26:37 -06:00 |
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tangxifan
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81e5af464e
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improve lb_route to avoid routing combinational loops
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2020-03-12 23:58:56 -06:00 |
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tangxifan
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773e6da308
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Spot a bug in lb router where path finder fail to use low-occupancy node when expanding the tree
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2020-03-12 22:53:17 -06:00 |
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tangxifan
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f90dc5c296
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remove redundant XML codes
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2020-03-12 20:44:07 -06:00 |
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tangxifan
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29450f3472
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debugging multi-source lb router
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2020-03-12 20:42:41 -06:00 |
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tangxifan
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8921905bec
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annotate multiple-source and multiple-sink nets from pb to lb router
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2020-03-12 19:21:13 -06:00 |
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tangxifan
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f0b22aaa11
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Make lb router support multiple sources to be routed
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2020-03-12 13:44:14 -06:00 |
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tangxifan
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c40675ca9d
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minor code formatting
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2020-03-12 11:55:25 -06:00 |
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tangxifan
|
f1e8e78410
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minor code formatting
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2020-03-12 11:47:42 -06:00 |
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tangxifan
|
689c50dff1
|
label the routing status for each sink in lb_router
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2020-03-12 11:36:31 -06:00 |
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tangxifan
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a1f19e776e
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Add comments to lb router and extract a private function for routing a single net
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2020-03-12 11:05:38 -06:00 |
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tangxifan
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cd50155e29
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rename variables in lb router
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2020-03-12 10:24:38 -06:00 |
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tangxifan
|
17a1c61b9d
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minor change in variable names in lb_router
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2020-03-11 21:10:16 -06:00 |
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tangxifan
|
8e796f152f
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add comments to lb_router about how-to-use
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2020-03-11 21:05:06 -06:00 |
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tangxifan
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2a260a05aa
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add a microbenchmark `and_latch` to test LUTs in wired mode
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2020-03-11 10:40:59 -06:00 |
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tangxifan
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aff73bdd74
|
deployed edge sorting and make it as an option to link_arch command
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2020-03-08 15:59:53 -06:00 |
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tangxifan
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b80e26e711
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update bitstream generator to use sorted edges
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2020-03-08 15:36:47 -06:00 |
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tangxifan
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5558932762
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use sorted edges in building routing modules
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2020-03-08 15:31:41 -06:00 |
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tangxifan
|
f9499afe04
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remove unused variable
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2020-03-08 15:00:01 -06:00 |
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tangxifan
|
0c7aa2581d
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update vpr8 version with hotfix on undriven pins in GSB
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2020-03-08 14:58:56 -06:00 |
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tangxifan
|
ca92c2717f
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bug fix for tile directs
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2020-03-07 16:00:32 -07:00 |
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tangxifan
|
37423729ec
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bug fixing for naming the duplicated pins
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2020-03-07 15:44:57 -07:00 |
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tangxifan
|
5be118d695
|
tileable rr_graph builder ready to debug
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2020-03-06 16:18:45 -07:00 |
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tangxifan
|
6e83154703
|
move rr_gsb and rr_chan to tileable rr_graph builder
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2020-03-04 14:14:28 -07:00 |
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tangxifan
|
4b7d2221d1
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adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr
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2020-03-04 13:55:53 -07:00 |
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tangxifan
|
7fcd27e000
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now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
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tangxifan
|
3241d8bd37
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put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
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tangxifan
|
037c7e5c43
|
adapt top-level function for analysis SDC writer
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2020-03-02 17:58:44 -07:00 |
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tangxifan
|
24f7416c71
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adapt analysis SDC writer for grids
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2020-03-02 17:15:01 -07:00 |
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tangxifan
|
6474183539
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adapt analysis SDC writer for routing modules
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2020-03-02 14:29:58 -07:00 |
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tangxifan
|
543cff58b9
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start porting analysis SDC writer
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2020-03-02 13:44:08 -07:00 |