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OpenFPGA
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3066 Commits

Author SHA1 Message Date
Ganesh Gore fba6996d59 Trying to merge artifact_regression_tests and docker_distribution 2021-01-24 00:24:09 -07:00
Ganesh Gore a4206e6cfc Corrected OPENFPGA_PATH in dockerfile 2021-01-24 00:05:24 -07:00
Ganesh Gore 3cb50dbf26 Updated docker_regression_tests 2021-01-23 23:33:52 -07:00
Ganesh Gore 72b02507ad Reverted CMAKE parallel build 2021-01-23 23:08:13 -07:00
Ganesh Gore 29dae79066 Added parallel build option to cmake 2021-01-23 22:37:55 -07:00
Ganesh Gore 0dc01f2a93 Optimized docekrfile.env 2021-01-23 21:59:58 -07:00
Ganesh Gore 5b93909082 Test on docker optimization pull request 2021-01-23 19:27:36 -07:00
Ganesh Gore 022eb673d4 Merge remote-tracking branch 'lnis_origin/github-action-optimizations' into ganesh_dev 2021-01-23 19:19:28 -07:00
Ganesh Gore fec1d8eeb2 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2021-01-23 19:06:35 -07:00
ganeshgore d502410b40
Merge pull request #179 from lnis-uofu/unused_gpout_patch 
Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
 2021-01-23 18:27:54 -07:00
ganeshgore 2ca47e8557
Merge pull request #182 from lnis-uofu/buid_version_addition 
Add OpenFPGA version display
 2021-01-23 18:21:30 -07:00
tangxifan 4cc8b08a6c [Tool] Add openfpga version display 2021-01-23 16:38:00 -07:00
Ganesh Gore 47cee0988c [Shellrun] Added nested tasks to shortcuts 2021-01-22 23:33:02 -07:00
Ashton Snelgrove 2e947efc64 Add openfpga.sh and force a master build. 2021-01-22 19:50:23 -07:00
tangxifan d2defebee9 [Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches 2021-01-22 16:42:13 -07:00
Ashton Snelgrove 25f8ea6e73 Fix chmod and env variables for test. 2021-01-22 16:36:19 -07:00
Ashton Snelgrove 40276ceaa4 Move openfpga binary to matching location. 2021-01-22 16:27:55 -07:00
Ashton Snelgrove bd57662a9e Copy openfpga_flow into master image. 2021-01-22 15:37:45 -07:00
Ashton Snelgrove a45b9cb801 Add OPENFPGA_PATH env variable to master dockerfile. 2021-01-22 15:30:01 -07:00
Ashton Snelgrove 22144924fc Restore conditionals. 2021-01-22 10:52:21 -07:00
Ashton Snelgrove a6b97db314 Trigger master image build. 2021-01-22 10:16:44 -07:00
Ashton Snelgrove cb80a9bbd4 Merge remote-tracking branch 'origin/master' into github-action-optimizations 2021-01-22 10:12:12 -07:00
Ashton Snelgrove 8cca1c63c3 Fix dockerfile for master build to include yosys/share, and fix conditionals. 2021-01-21 16:40:09 -07:00
Lalit Narain Sharma 1823eb857d
Merge pull request #177 from lnis-uofu/bump_yosys_submodule 
Bumping the latest changes in yosys sub-module related to yosys synth…
 2021-01-21 09:40:29 +05:30
Ashton Snelgrove f956f28792 Update docker images, remove runtime/test split 2021-01-20 14:20:12 -07:00
Ashton Snelgrove 5f613c46f7 Switch code change check to a script 2021-01-20 12:40:18 -07:00
Lalit Sharma df073c327e Bumping the latest changes in yosys sub-module related to yosys synthesis for openfpga quicklogic device 2021-01-20 07:23:51 -08:00
tangxifan 3a69ece199
Merge pull request #175 from lnis-uofu/dev 
Pin Constraint Support in Testbench Generation
 2021-01-19 19:24:10 -07:00
tangxifan 3f80a26172 [Tool] Bug fix for combinational benchmarks in pre-config testbench generation 2021-01-19 18:22:50 -07:00
tangxifan ac8c63553a [Doc] Add file format index file 2021-01-19 18:07:53 -07:00
tangxifan fbb5c0cf8f [Doc] Add pin constraints to documentation 2021-01-19 18:04:45 -07:00
tangxifan af0646260c [Test] Bug fix in pin constraints 2021-01-19 17:44:05 -07:00
tangxifan 186f2f1968 [Test] Use pin constraint in multi-clock test case 2021-01-19 17:42:40 -07:00
tangxifan 3fdd5ae8b3 [Script] Use pin constraints in template script 2021-01-19 17:42:25 -07:00
tangxifan 75b99b78e9 [Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks 2021-01-19 17:38:51 -07:00
tangxifan da200658c1 [Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks 2021-01-19 17:29:59 -07:00
tangxifan 0670c2de59 [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00
tangxifan e17a5cbbf2 [Test] Rename to pin constraint to comply with libpcf requirement 2021-01-19 15:52:51 -07:00
tangxifan ecd955124b [Lib] Add libpcf to CMakelist and bug fix 2021-01-19 15:51:14 -07:00
tangxifan 52ac7826eb [Lib] Add a library of parser/writer for pin constraint file (PCF) 2021-01-19 15:45:45 -07:00
tangxifan ab25e1af5f [Test] Add example XML for net mapping between benchmark to FPGA 2021-01-19 09:29:21 -07:00
tangxifan 17c49711d3
Merge pull request #174 from lnis-uofu/dev 
Support Design Constraints for Repack
 2021-01-17 17:41:53 -07:00
tangxifan c7f02601ab [Doc] Add repack design constraints to documentation 2021-01-17 12:59:46 -07:00
tangxifan 8c311b8282 [Tool] Bug fix in repacker for considering design constraints 2021-01-17 12:26:14 -07:00
tangxifan ea9d6bfe91 [Flow] Update the design constraint file to follow bug fix in parser 2021-01-17 10:41:01 -07:00
tangxifan 113119bd8e [Lib] Fix the bug in repack design constraint parser 2021-01-17 10:39:55 -07:00
tangxifan dd74f05a31 [Test] Add repack constraints to tests 2021-01-17 10:35:36 -07:00
tangxifan 12e0efd03e [Script] Add an example openfpga script to use repack design constraints 2021-01-17 10:33:56 -07:00
tangxifan 2efe513122 [Tool] Now repack consider design constraints; test pending 2021-01-16 21:57:17 -07:00
tangxifan d0e05b3575 [Lib] Now use pb_type in design constraints instead of physical tiles 2021-01-16 21:35:43 -07:00