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Bumping the latest changes in yosys sub-module related to yosys synthesis for openfpga quicklogic device

This commit is contained in:
Lalit Sharma 2021-01-20 07:23:51 -08:00
parent 3a69ece199
commit df073c327e
1 changed files with 1 additions and 1 deletions
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2
yosys

@ -1 +1 @@
Subproject commit a0606e09f57df456ba9bcfc6a7cf7b64d814b8e4
Subproject commit 14b993449d5b6e37d69ff523356d05941a78b66e