From df073c327e38de3bf6bbbb4cc3c2f172fb0ef406 Mon Sep 17 00:00:00 2001
From: Lalit Sharma <lsharma@quicklogic.com>
Date: Wed, 20 Jan 2021 07:23:51 -0800
Subject: [PATCH] Bumping the latest changes in yosys sub-module related to
 yosys synthesis for openfpga quicklogic device

---
 yosys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/yosys b/yosys
index a0606e09f..14b993449 160000
--- a/yosys
+++ b/yosys
@@ -1 +1 @@
-Subproject commit a0606e09f57df456ba9bcfc6a7cf7b64d814b8e4
+Subproject commit 14b993449d5b6e37d69ff523356d05941a78b66e