Ganesh Gore
f558437ae1
Added task for vpr_blif flow
2019-08-25 00:23:39 -06:00
Ganesh Gore
2e3f906d40
Solved bug in travis script file
2019-08-23 16:03:21 -06:00
Ganesh Gore
82a186bf7c
Added python3.5 in travis script
2019-08-23 12:45:17 -06:00
Ganesh Gore
28dde899db
Updated Architecture Template
2019-08-23 12:44:45 -06:00
Ganesh Gore
6e7de16ad4
Solved bug in commnad rearrangement
2019-08-22 23:41:25 -06:00
Ganesh Gore
4189ada1eb
Fixed run test file
2019-08-22 17:31:46 -06:00
Ganesh Gore
5027f9c4b3
Added test mode script in travis
2019-08-22 17:03:56 -06:00
Ganesh Gore
8f80cb3c24
Added Sample script to run blif VPR
2019-08-22 17:02:12 -06:00
Ganesh Gore
77e2a7bca3
Added execution time logs in flow script
2019-08-22 17:01:38 -06:00
Ganesh Gore
30cbe38d3d
Added Test Modes - Added blif VPR Option
2019-08-22 17:00:59 -06:00
Ganesh Gore
d5ce1b557e
Made thread logs prettier
2019-08-22 16:56:58 -06:00
Ganesh Gore
764d7039b5
Import utils bug fixing for travis test
2019-08-21 12:42:58 -06:00
Ganesh Gore
2f0acfad23
Updated travis to run regression task
2019-08-21 11:09:53 -06:00
Ganesh Gore
e51ff44710
Added execution time information in logs
2019-08-21 11:08:47 -06:00
Ganesh Gore
a335a57c6c
Added debug option to commnad line arguments
2019-08-21 11:08:13 -06:00
Ganesh Gore
b7484ef178
Removed traces of old template file
2019-08-20 15:58:19 -06:00
Ganesh Gore
afee2229af
Removed unused templates and file from openfpga_flow directory
2019-08-19 21:32:52 -06:00
Ganesh Gore
08b0ef3550
Updated validate_command_line_arguments function
...
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
2019-08-19 21:28:23 -06:00
Ganesh Gore
53941eaf5c
Changed yosys output file name
2019-08-19 19:06:46 -06:00
Ganesh Gore
8d0153d34e
Added gitignore to skip run directory tracking
2019-08-19 19:06:01 -06:00
Ganesh Gore
616d7706c9
Added list of intermidiate files filename
2019-08-19 19:05:08 -06:00
Ganesh Gore
8f8707ff98
Added option to filter results after parsing
2019-08-19 19:04:14 -06:00
Ganesh Gore
5116aa2ae1
Added architecture and replaced variables
2019-08-19 19:02:50 -06:00
Ganesh Gore
cb5b16c949
Moved required files to openfpga folder
2019-08-19 18:57:42 -06:00
Ganesh Gore
6dc05b769b
Added Power Model Files
2019-08-19 18:55:23 -06:00
Ganesh Gore
7f6c1b3e00
Code re-arrangement
...
+ Added support for subdirectory task in openfpga_task
+ Rearranged function order
+ Combined vpr re-route and standrad run function
+ Removed external_call function from fpga_flow script
+ Added .gitignore to task directory
2019-08-18 12:26:05 -06:00
Ganesh Gore
fb29fcfc06
Added build files in .gitignore
2019-08-17 22:59:54 -06:00
Ganesh Gore
12c998c12a
Added dockerignore + minor changes in openfpga_flow script
2019-08-17 16:22:52 -06:00
Ganesh Gore
66bb8a5e4b
Updated RRAM architecture file
2019-08-17 02:20:04 -06:00
Ganesh Gore
7bfc48b8e4
Moved spice and verilog netlist folder location
2019-08-17 01:49:49 -06:00
Ganesh Gore
125d7888df
Merge remote-tracking branch 'origin/spice_model_refactoring' into ganesh_dev
2019-08-16 22:00:41 -06:00
tangxifan
aa7f3bef7f
fixed bugs in configure pb_rr_graph and dependence on testbenches
2019-08-16 18:20:30 -06:00
tangxifan
e456b6f905
replace spice_models with circuit model in bitstream generator
2019-08-16 16:36:49 -06:00
tangxifan
5ece7ab6d0
start refactoring the bitstream part using spice_models
2019-08-16 15:58:14 -06:00
tangxifan
b66e120366
patch on local encoders for unused configuration, avoid chip-burn issues
2019-08-16 15:32:23 -06:00
Ganesh Gore
4865335627
Merge remote-tracking branch 'origin/dev' into ganesh_dev
2019-08-16 14:14:16 -06:00
Ganesh Gore
c43c3cdf25
Added VPR output parse option
2019-08-16 13:36:39 -06:00
Ganesh Gore
effbd332aa
Added task report generation
2019-08-16 10:59:44 -06:00
Ganesh Gore
901932a4fc
First draft: Working openfpga task flow
2019-08-16 09:44:50 -06:00
tangxifan
4eb046760b
still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
2019-08-15 21:57:59 -06:00
Ganesh Gore
5d3708651e
Added fpga_flow and fpga_task script
...
+ Missed local intermediate commits
2019-08-15 14:39:58 -06:00
tangxifan
35ad4a87e5
add travis slack notification
2019-08-14 12:51:17 -06:00
AurelienUoU
8e38aa6019
Merge with heterogeneous for unfracturable LUT bug fix
2019-08-14 10:10:27 -06:00
AurelienUoU
df873903f8
Bug fix for non fracturable LUT
2019-08-14 09:32:15 -06:00
AurelienUoU
30c0f2b6b7
Merge remote-tracking branch 'origin/dev' into heterogeneous
2019-08-14 09:11:54 -06:00
AurelienUoU
90aaed6e1f
Fix regression test
2019-08-14 09:10:13 -06:00
tangxifan
d2d8af5416
bug fixing for pb_type num_conf_bits and num_iopads stats
2019-08-13 17:34:09 -06:00
tangxifan
edfa72a666
try to fix the bug in clock net identification
2019-08-13 16:47:28 -06:00
tangxifan
1118b28397
use single subckt for switch box again, to abolish the multi-module subckt
2019-08-13 16:11:04 -06:00
tangxifan
4cffd8ac2d
keep route file updated with tileable rr_graph
2019-08-13 15:37:42 -06:00