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OpenFPGA
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Merge remote-tracking branch 'origin/dev' into ganesh_dev

This commit is contained in:
Ganesh Gore 2019-08-16 14:14:16 -06:00
parent c43c3cdf25 35ad4a87e5
commit 4865335627
326 changed files with 12339 additions and 150969 deletions
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3
.travis.yml
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@ -104,3 +104,6 @@ after_failure:
after_success:
- .travis/after_success.sh
notifications:
slack:
secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw=

30
Dockerfile
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@ -1,16 +1,16 @@
FROM ubuntu:16.04
RUN apt-get update -qq -y
RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
RUN mkdir -p /release /dev
RUN cd release && git clone --single-branch --branch documentation https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA
RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -CMAKE_BUILD_TYPE=debug && make
RUN rm -rf /var/lib/apt/lists/*
FROM ubuntu:16.04
RUN apt-get update -qq -y
RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gtkwave gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
RUN mkdir -p /release /dev
RUN cd release && git clone --single-branch --branch documentation https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA
RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -CMAKE_BUILD_TYPE=debug && make
RUN rm -rf /var/lib/apt/lists/*
WORKDIR /release/OpenFPGA

49
ERI_demo/ERI.sh Executable file
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@ -0,0 +1,49 @@
#!/bin/bash
# Regression test version 1.0
# Set variables
my_pwd=$PWD
fpga_flow_scripts="${my_pwd}/fpga_flow/scripts"
vpr_path="${my_pwd}/vpr7_x2p/vpr"
benchmark="test_modes"
include_netlists="_include_netlists.v"
compiled_file="compiled_$benchmark"
tb_formal_postfix="_top_formal_verification_random_tb"
verilog_dirname="${vpr_path}/${benchmark}_Verilog"
log_file="${benchmark}_sim.log"
new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh"
template_sh="${PWD}/ERI_demo/eri_demo.sh"
# Remove former log file
rm -f $log_file
rm -f $compiled_file
# Rewite script
cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $template_sh -o $new_reg_sh
cd $my_pwd
# Start the script -> run the fpga generation -> run the simulation -> check the log file
source $new_reg_sh # Leave us in vpr folder
cd $my_pwd
iverilog -o $compiled_file ${verilog_dirname}/SRC/${benchmark}${include_netlists} -s ${benchmark}${tb_formal_postfix}
vvp $compiled_file -j 64 >> $log_file
result=`grep "Succeed" $log_file`
if ["$result" = ""]; then
result=`grep "Failed" $log_file`
if ["$result" = ""]; then
echo "Unexpected error, Verification didn't run"
exit 1
else
echo "Verification failed"
exit 2
fi
else
echo "Verification succeed"
gtkwave ${benchmark}_formal.vcd &
fi

46
ERI_demo/eri_demo.sh Normal file
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@ -0,0 +1,46 @@
#!/bin/bash
# Example of how to run vpr
# Set variables
# For FPGA-Verilog ONLY
benchmark="test_modes"
OpenFPGA_path="OPENFPGAPATHKEYWORD"
verilog_output_dirname="${benchmark}_Verilog"
verilog_output_dirpath="$vpr_path"
tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
# VPR critical inputs
template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml"
blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
vpr_route_chan_width="200"
fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
ff_path="$vpr_path/VerilogNetlists/ff.v"
new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
ff_keyword="GENERATED_DIR_KEYWORD"
ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
arch_ff_keyword="FFPATHKEYWORD"
tb_formal_ext="_formal_random_top_tb.v"
formal_postfix="_top_formal_verification"
# Remove previous designs
rm -rf $verilog_output_dirpath/$verilog_output_dirname
mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
# Move to vpr folder
cd $vpr_path
# Run VPR
./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping --nodisp
cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
cd -

43
README.md
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@ -1,39 +1,30 @@
# Getting Started with FPGA-SPICE
# Getting Started with OpenFPGA <img src="./docs/source/figures/OpenFPGA_logo.png" width="200" align="right">
[![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA)
[![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
## Introduction
FPGA-SPICE is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of heterogeneous architectures.
The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification testbenches/scripts. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.<br />
## Compilation
Dependencies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md).
The different ways of compiling can be found in the **./compilation** folder.
**Compilation Steps:**
1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go inside it*
2. mkdir build && cd build # *Create a folder named build in the OpenPFGA repository*
3. cmake .. -DCMAKE_BUILD_TYPE=debug # *Create a Makefile in this folder using cmake*
4. make # *Compile the tool and its dependencies*
We currently implemented it for:
1. Ubuntu 18.04
2. Red Hat 7.5
3. MacOS High Sierra 10.13.4
Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.
*We currently implemented OpenFPGA for:*<br />
*1. Ubuntu 16.04*<br />
*2. Red Hat 7.5*<br />
*3. MacOS Mojave 10.14.4*<br /><br />
*Please note that those were the versions for which the tool was tested. It might work with earlier versions and other distributions.*
## Documentation
OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options.
## Examples
You can find in the folder **./examples**. This will help you get in touch with the software and test different configurations to see how FPGA-SPICE reacts to them.
./example_x.sh allows to launch the script linked to example_x.xml and .blif.
In all the examples, the CLBs are composed of LUTs, FFs and MUXs as a base.
Example 1 shows a very basic design with only 4 inputs on the LUTs, a FF and a MUX in the CLB (only 1). It implements an inverter and allows the user to see the very core of the .xml file.
Example 2 increases the complexity by having 3x3 CLBs and 4 slices per CLB. The slices provide a feedback to the input structure and input MUXs are added.
## Tutorials
You can find some tutorials in the [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials) folder. This will help you get more familiar with the tool and use OpenFPGA under different configurations.
Through those tutorials, users can learn how to use the flow and install the different dependencies.<br />
The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through training and explain the folder oraganization as well as introducing some tips and commonly used keywords.

1
ace2/CMakeLists.txt
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@ -37,6 +37,7 @@ set_target_properties(libace PROPERTIES PREFIX "") #Avoid extra 'lib' prefix#Cre
# Specify dependency
target_link_libraries(libace
libabc
libvtrutil
${CMAKE_DL_LIBS})
add_executable(ace ${EXEC_SOURCES})

37
ace2/SRC/ace.c
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@ -1,3 +1,6 @@
#include "vtr_assert.h"
#include "vtr_time.h" //For some reason this causes compilation errors if included below the std headers on with g++-5
#include "vtr_assert.h"
#include <stdio.h>
#include <inttypes.h>
@ -50,8 +53,7 @@ void print_status(Abc_Ntk_t * ntk) {
printf("%d: OLD\n", i);
break;
default:
printf("Invalid ABC object info status");
exit(1);
VTR_ASSERT_MSG(false, "Invalid ABC object info status");
}
}
}
@ -169,11 +171,11 @@ int ace_calc_activity(Abc_Ntk_t * ntk, int num_vectors, char * clk_name) {
{
info = Ace_ObjInfo(obj);
if (strcmp(Abc_ObjName(obj), clk_name) != 0) {
assert(info->static_prob >= 0 && info->static_prob <= 1.0);
assert(info->switch_prob >= 0 && info->switch_prob <= 1.0);
assert(info->switch_act >= 0 && info->switch_act <= 1.0);
assert(info->switch_prob <= 2.0 * (1.0 - info->static_prob));
assert(info->switch_prob <= 2.0 * info->static_prob);
VTR_ASSERT(info->static_prob >= 0 && info->static_prob <= 1.0);
VTR_ASSERT(info->switch_prob >= 0 && info->switch_prob <= 1.0);
VTR_ASSERT(info->switch_act >= 0 && info->switch_act <= 1.0);
VTR_ASSERT(info->switch_prob <= 2.0 * (1.0 - info->static_prob));
VTR_ASSERT(info->switch_prob <= 2.0 * info->static_prob);
}
info->status = ACE_DEF;
}
@ -233,11 +235,11 @@ int ace_calc_activity(Abc_Ntk_t * ntk, int num_vectors, char * clk_name) {
Ace_Obj_Info_t * info2 = Ace_ObjInfo(obj);
info2->switch_act = info2->switch_prob;
assert(info2->switch_act >= 0.0);
VTR_ASSERT(info2->switch_act >= 0.0);
}
Abc_NtkForEachPi(ntk, obj, i)
{
assert(Ace_ObjInfo(obj)->switch_act >= 0.0);
VTR_ASSERT(Ace_ObjInfo(obj)->switch_act >= 0.0);
}
/*------------- Calculate switching activities. ---------------------*/
@ -275,7 +277,7 @@ int ace_calc_activity(Abc_Ntk_t * ntk, int num_vectors, char * clk_name) {
Ace_Obj_Info_t * info2 = Ace_ObjInfo(obj);
//Ace_Obj_Info_t * fanin_info2;
assert(Abc_ObjType(obj) == ABC_OBJ_NODE);
VTR_ASSERT(Abc_ObjType(obj) == ABC_OBJ_NODE);
if (Abc_ObjFaninNum(obj) < 1) {
info2->switch_act = 0.0;
@ -284,7 +286,7 @@ int ace_calc_activity(Abc_Ntk_t * ntk, int num_vectors, char * clk_name) {
Vec_Ptr_t * literals = Vec_PtrAlloc(0);
Abc_Obj_t * fanin;
assert(obj->Type == ABC_OBJ_NODE);
VTR_ASSERT(obj->Type == ABC_OBJ_NODE);
Abc_ObjForEachFanin(obj, fanin, j)
{
@ -294,7 +296,7 @@ int ace_calc_activity(Abc_Ntk_t * ntk, int num_vectors, char * clk_name) {
literals);
Vec_PtrFree(literals);
}
assert(info2->switch_act >= 0);
VTR_ASSERT(info2->switch_act >= 0);
}
Vec_PtrFree(nodes_logic);
Vec_PtrFree(latches_in_cycles_vec);
@ -308,21 +310,22 @@ Ace_Obj_Info_t * Ace_ObjInfo(Abc_Obj_t * obj) {
if (st__lookup(ace_info_hash_table, (char *) obj, (char **) &info)) {
return info;
}
assert(0);
VTR_ASSERT(0);
return NULL;
}
void prob_epsilon_fix(double * d) {
if (*d < 0) {
assert(*d > 0 - EPSILON);
VTR_ASSERT(*d > 0 - EPSILON);
*d = 0;
} else if (*d > 1) {
assert(*d < 1 + EPSILON);
VTR_ASSERT(*d < 1 + EPSILON);
*d = 1.;
}
}
int main(int argc, char * argv[]) {
vtr::ScopedFinishTimer t("Ace");
FILE * BLIF = NULL;
FILE * IN_ACT = NULL;
FILE * OUT_ACT = stdout;
@ -351,7 +354,7 @@ int main(int argc, char * argv[]) {
ntk = Io_Read(blif_file_name, IO_FILE_BLIF, 1, 0);
assert(ntk);
VTR_ASSERT(ntk);
printf("Objects in network: %d\n", Abc_NtkObjNum(ntk));
printf("PIs in network: %d\n", Abc_NtkPiNum(ntk));
@ -383,7 +386,7 @@ int main(int argc, char * argv[]) {
// Check Depth
depth = ace_calc_network_depth(ntk);
printf("Max Depth: %d\n", depth);
assert(depth > 0);
VTR_ASSERT(depth > 0);
alloc_and_init_activity_info(ntk);

46
ace2/SRC/bdd.c
View File

@ -1,5 +1,7 @@
#include <inttypes.h>
#include "vtr_assert.h"
#include "ace.h"
#include "misc/vec/vecPtr.h"
#include "bdd.h"
@ -86,7 +88,7 @@ int ace_bdd_build_network_bdds(
int i;
Vec_Ptr_t * nodes;
assert(Vec_PtrSize(inputs) > 0);
VTR_ASSERT(Vec_PtrSize(inputs) > 0);
nodes = Abc_NtkDfsSeq(ntk);
@ -111,8 +113,8 @@ int ace_bdd_build_network_bdds(
switch (info->status)
{
case ACE_SIM:
assert (info->static_prob >= 0.0 && info->static_prob <= 1.0);
assert (info->switch_prob >= 0.0 && info->switch_prob <= 1.0);
VTR_ASSERT (info->static_prob >= 0.0 && info->static_prob <= 1.0);
VTR_ASSERT (info->switch_prob >= 0.0 && info->switch_prob <= 1.0);
if (!st_lookup(leaves, (char*) obj, NULL))
{
@ -128,7 +130,7 @@ int ace_bdd_build_network_bdds(
break;
case ACE_UNDEF:
assert(0);
VTR_ASSERT(0);
if (check_pi_status(obj))
{
while(1)
@ -149,14 +151,14 @@ int ace_bdd_build_network_bdds(
break;
case ACE_DEF:
assert(info->static_prob >= 0 && info->static_prob <= 1.0);
assert(info->switch_prob >= 0 && info->switch_prob <= 1.0);
VTR_ASSERT(info->static_prob >= 0 && info->static_prob <= 1.0);
VTR_ASSERT(info->switch_prob >= 0 && info->switch_prob <= 1.0);
break;
case ACE_NEW:
case ACE_OLD:
default:
assert(0);
VTR_ASSERT(0);
}
}
@ -192,7 +194,7 @@ double calc_cube_switch_prob_recur(DdManager * mgr, DdNode * bdd,
}
/* Get literal index for this bdd node. */
//assert(0);
//VTR_ASSERT(0);
i = Cudd_Regular(bdd)->index;
pi = (Abc_Obj_t*) Vec_PtrEntry((Vec_Ptr_t*) inputs, i);
@ -210,11 +212,11 @@ double calc_cube_switch_prob_recur(DdManager * mgr, DdNode * bdd,
then_prob = calc_cube_switch_prob_recur(mgr, bdd_if1, cube, inputs, visited,
phase);
assert(then_prob + EPSILON >= 0 && then_prob - EPSILON <= 1);
VTR_ASSERT(then_prob + EPSILON >= 0 && then_prob - EPSILON <= 1);
else_prob = calc_cube_switch_prob_recur(mgr, bdd_if0, cube, inputs, visited,
phase);
assert(else_prob + EPSILON >= 0 && else_prob - EPSILON <= 1);
VTR_ASSERT(else_prob + EPSILON >= 0 && else_prob - EPSILON <= 1);
switch (node_get_literal (cube->cube, i)) {
case ZERO:
@ -235,7 +237,7 @@ double calc_cube_switch_prob_recur(DdManager * mgr, DdNode * bdd,
st__insert(visited, (char *) bdd, (char *) current_prob);
assert(*current_prob + EPSILON >= 0 && *current_prob - EPSILON < 1.0);
VTR_ASSERT(*current_prob + EPSILON >= 0 && *current_prob - EPSILON < 1.0);
return (*current_prob);
}
@ -250,7 +252,7 @@ double calc_cube_switch_prob(DdManager * mgr, DdNode * bdd, ace_cube_t * cube,
st__free_table(visited);
assert(sp + EPSILON >= 0. && sp - EPSILON <= 1.0);
VTR_ASSERT(sp + EPSILON >= 0. && sp - EPSILON <= 1.0);
return (sp);
}
@ -264,9 +266,9 @@ double calc_switch_prob_recur(DdManager * mgr, DdNode * bdd_next, DdNode * bdd,
ace_cube_t * cube0, *cube1;
Ace_Obj_Info_t * info;
assert(inputs != NULL);
assert(Vec_PtrSize(inputs) > 0);
assert(P1 >= 0);
VTR_ASSERT(inputs != NULL);
VTR_ASSERT(Vec_PtrSize(inputs) > 0);
VTR_ASSERT(P1 >= 0);
if (bdd == Cudd_ReadLogicZero(mgr)) {
if (phase != 1)
@ -274,7 +276,7 @@ double calc_switch_prob_recur(DdManager * mgr, DdNode * bdd_next, DdNode * bdd,
prob = calc_cube_switch_prob(mgr, bdd_next, cube, inputs, phase);
prob *= P1;
assert(prob + EPSILON >= 0. && prob - EPSILON <= 1.);
VTR_ASSERT(prob + EPSILON >= 0. && prob - EPSILON <= 1.);
return (prob * P1);
} else if (bdd == Cudd_ReadOne(mgr)) {
if (phase != 0)
@ -282,7 +284,7 @@ double calc_switch_prob_recur(DdManager * mgr, DdNode * bdd_next, DdNode * bdd,
prob = calc_cube_switch_prob(mgr, bdd_next, cube, inputs, phase);
prob *= P1;
assert(prob + EPSILON >= 0. && prob - EPSILON <= 1.);
VTR_ASSERT(prob + EPSILON >= 0. && prob - EPSILON <= 1.);
return (prob * P1);
}
@ -315,8 +317,8 @@ double calc_switch_prob_recur(DdManager * mgr, DdNode * bdd_next, DdNode * bdd,
inputs, P1 * (1.0 - info->static_prob), phase);
ace_cube_free(cube0);
assert(switch_prob_t + EPSILON >= 0. && switch_prob_t - EPSILON <= 1.);
assert(switch_prob_e + EPSILON >= 0. && switch_prob_e - EPSILON <= 1.);
VTR_ASSERT(switch_prob_t + EPSILON >= 0. && switch_prob_t - EPSILON <= 1.);
VTR_ASSERT(switch_prob_e + EPSILON >= 0. && switch_prob_e - EPSILON <= 1.);
return (switch_prob_t + switch_prob_e);
}
@ -333,7 +335,7 @@ double ace_bdd_calc_switch_act(DdManager * mgr, Abc_Obj_t * obj,
DdNode * bdd;
d = info->depth;
assert(d > 0);
VTR_ASSERT(d > 0);
d = (int) d * 0.4;
if (d < 1) {
d = 1;
@ -361,10 +363,10 @@ double ace_bdd_calc_switch_act(DdManager * mgr, Abc_Obj_t * obj,
prob_epsilon_fix(&fanin_info->prob0to1);
prob_epsilon_fix(&fanin_info->prob1to0);
assert(
VTR_ASSERT(
fanin_info->prob0to1 + EPSILON >= 0.
&& fanin_info->prob0to1 - EPSILON <= 1.0);
assert(
VTR_ASSERT(
fanin_info->prob1to0 + EPSILON >= 0.
&& fanin_info->prob1to0 - EPSILON <= 1.0);
}

9
ace2/SRC/cube.c
View File

@ -1,3 +1,4 @@
#include "vtr_assert.h"
#include "cube.h"
#include "bdd.h"
@ -16,8 +17,8 @@ ace_cube_t * ace_cube_dup(ace_cube_t * cube) {
int i;
ace_cube_t * cube_copy;
assert(cube != NULL);
assert(cube->num_literals > 0);
VTR_ASSERT(cube != NULL);
VTR_ASSERT(cube->num_literals > 0);
cube_copy = (ace_cube_t*) malloc(sizeof(ace_cube_t));
cube_copy->static_prob = cube->static_prob;
@ -63,8 +64,8 @@ ace_cube_t * ace_cube_new_dc(int num_literals) {
}
void ace_cube_free(ace_cube_t * cube) {
assert(cube != NULL);
assert(cube->cube != NULL);
VTR_ASSERT(cube != NULL);
VTR_ASSERT(cube->cube != NULL);
free(cube->cube);
free(cube);
}

3
ace2/SRC/cycle.c
View File

@ -1,3 +1,4 @@
#include "vtr_assert.h"
#include "cycle.h"
#include "ace.h"
@ -28,7 +29,7 @@ bool in_cycle(Abc_Ntk_t * ntk, int obj_id_to_find, Abc_Obj_t * starting_obj_ptr,
{
// Get BI of latch
fanin_ptr = Abc_ObjFanin0(Abc_ObjFanin0(starting_obj_ptr));
assert(fanin_ptr);
VTR_ASSERT(fanin_ptr);
return (in_cycle(ntk, obj_id_to_find, fanin_ptr, flag));
}

34
ace2/SRC/io_ace.c
View File

@ -1,5 +1,7 @@
#include <stdlib.h>
#include "vtr_assert.h"
#include "ace.h"
#include "io_ace.h"
@ -34,7 +36,7 @@ void ace_io_print_activity(Abc_Ntk_t * ntk, FILE * fp) {
Abc_NtkForEachObj(ntk, obj, i)
{
assert(obj->pCopy);
VTR_ASSERT(obj->pCopy);
obj_new = obj->pCopy;
Ace_Obj_Info_t * info = Ace_ObjInfo(obj);
@ -69,7 +71,7 @@ void ace_io_print_activity(Abc_Ntk_t * ntk, FILE * fp) {
default:
//printf("Unkown Type: %d\n", Abc_ObjType(obj));
//assert(0);
//VTR_ASSERT(0);
break;
}
@ -235,10 +237,10 @@ int ace_io_read_activity(Abc_Ntk_t * ntk, FILE * in_file_desc,
printf("Cannot open input file\n");
error = ACE_ERROR;
} else {
assert(p >= 0.0 && p <= 1.0);
assert(d >= 0.0 && d <= 1.0);
assert(d <= 2.0 * p);
assert(d <= 2.0 * (1.0 - p));
VTR_ASSERT(p >= 0.0 && p <= 1.0);
VTR_ASSERT(d >= 0.0 && d <= 1.0);
VTR_ASSERT(d <= 2.0 * p);
VTR_ASSERT(d <= 2.0 * (1.0 - p));
Abc_NtkForEachPi(ntk, obj_ptr, i)
{
@ -269,7 +271,7 @@ int ace_io_read_activity(Abc_Ntk_t * ntk, FILE * in_file_desc,
// Read real PIs activity values from file
res = fgets(line, ACE_CHAR_BUFFER_SIZE, in_file_desc);
assert(res);
VTR_ASSERT(res);
while (!feof(in_file_desc)) {
sscanf(line, "%s %lf %lf\n", pi_name, &static_prob,
&switch_prob);
@ -283,8 +285,8 @@ int ace_io_read_activity(Abc_Ntk_t * ntk, FILE * in_file_desc,
}
pi_obj_ptr = Abc_NtkObj(ntk, pi_obj_id);
assert(static_prob >= 0.0 && static_prob <= 1.0);
assert(switch_prob >= 0.0 && switch_prob <= 1.0);
VTR_ASSERT(static_prob >= 0.0 && static_prob <= 1.0);
VTR_ASSERT(switch_prob >= 0.0 && switch_prob <= 1.0);
info = Ace_ObjInfo(pi_obj_ptr);
info->static_prob = static_prob;
@ -292,7 +294,7 @@ int ace_io_read_activity(Abc_Ntk_t * ntk, FILE * in_file_desc,
info->switch_act = switch_prob;
res = fgets(line, ACE_CHAR_BUFFER_SIZE, in_file_desc);
assert(res);
VTR_ASSERT(res);
}
} else if (pi_format == ACE_VEC) {
printf("Reading vector file...\n");
@ -305,10 +307,10 @@ int ace_io_read_activity(Abc_Ntk_t * ntk, FILE * in_file_desc,
char* res;
res = fgets(line, ACE_CHAR_BUFFER_SIZE, in_file_desc);
assert(res);
VTR_ASSERT(res);
while (!feof(in_file_desc)) {
res = fgets(line, ACE_CHAR_BUFFER_SIZE, in_file_desc);
assert(res);
VTR_ASSERT(res);
num_vec++;
}
Abc_NtkForEachPi(ntk, obj_ptr, i)
@ -325,7 +327,7 @@ int ace_io_read_activity(Abc_Ntk_t * ntk, FILE * in_file_desc,
num_vec = 0;
res = fgets(line, ACE_CHAR_BUFFER_SIZE, in_file_desc);
assert(res);
VTR_ASSERT(res);
while (!feof(in_file_desc)) {
sscanf(line, "%s\n", vector);
@ -336,7 +338,7 @@ int ace_io_read_activity(Abc_Ntk_t * ntk, FILE * in_file_desc,
error = ACE_ERROR;
break;
}
assert(strlen(vector) == num_Pi);
VTR_ASSERT(strlen(vector) == num_Pi);
if (num_vec == 0) {
Abc_NtkForEachPi(ntk, obj_ptr, i)
@ -364,14 +366,14 @@ int ace_io_read_activity(Abc_Ntk_t * ntk, FILE * in_file_desc,
}
res = fgets(line, ACE_CHAR_BUFFER_SIZE, in_file_desc);
assert(res);
VTR_ASSERT(res);
num_vec++;
}
if (!error) {
Abc_NtkForEachPi(ntk, obj_ptr, i)
{
assert(num_vec > 0);
VTR_ASSERT(num_vec > 0);
info = Ace_ObjInfo(obj_ptr);
info->static_prob = (double) high[i] / (double) num_vec;

29
ace2/SRC/sim.c
View File

@ -1,3 +1,4 @@
#include "vtr_assert.h"
#include "ace.h"
#include "sim.h"
@ -60,7 +61,7 @@ void get_pi_values(Abc_Ntk_t * ntk, Vec_Ptr_t * /*nodes*/, int cycle) {
default:
printf("Bad Value\n");
assert(0);
VTR_ASSERT(0);
break;
}
}
@ -111,7 +112,7 @@ void get_pi_values(Abc_Ntk_t * ntk, Vec_Ptr_t * /*nodes*/, int cycle) {
default:
printf("Bad value\n");
assert(FALSE);
VTR_ASSERT(FALSE);
break;
}
}
@ -131,7 +132,7 @@ int * getFaninValues(Abc_Obj_t * obj_ptr) {
info = Ace_ObjInfo(fanin);
if (info->status == ACE_UNDEF) {
printf("Fan-in is undefined\n");
assert(FALSE);
VTR_ASSERT(FALSE);
} else if (info->status == ACE_NEW) {
break;
}
@ -210,15 +211,15 @@ void evaluate_circuit(Abc_Ntk_t * ntk, Vec_Ptr_t * node_vec, int /*cycle*/) {
case ACE_NEW:
if (Abc_ObjIsNode(obj)) {
faninValues = getFaninValues(obj);
assert(faninValues);
VTR_ASSERT(faninValues);
dd_node = Cudd_Eval((DdManager*) ntk->pManFunc, (DdNode*) obj->pData, faninValues);
assert(Cudd_IsConstant(dd_node));
VTR_ASSERT(Cudd_IsConstant(dd_node));
if (dd_node == Cudd_ReadOne((DdManager*) ntk->pManFunc)) {
value = 1;
} else if (dd_node == Cudd_ReadLogicZero((DdManager*) ntk->pManFunc)) {
value = 0;
} else {
assert(0);
VTR_ASSERT(0);
}
free(faninValues);
} else {
@ -240,12 +241,12 @@ void evaluate_circuit(Abc_Ntk_t * ntk, Vec_Ptr_t * node_vec, int /*cycle*/) {
info->num_ones += info->value;
break;
default:
assert(0);
VTR_ASSERT(0);
break;
}
break;
default:
assert(0);
VTR_ASSERT(0);
break;
}
}
@ -294,8 +295,8 @@ void ace_sim_activities(Abc_Ntk_t * ntk, Vec_Ptr_t * nodes, int max_cycles,
Ace_Obj_Info_t * info;
int i;
assert(max_cycles > 0);
assert(threshold > 0.0);
VTR_ASSERT(max_cycles > 0);
VTR_ASSERT(threshold > 0.0);
// srand((unsigned) time(NULL));
@ -326,12 +327,12 @@ void ace_sim_activities(Abc_Ntk_t * ntk, Vec_Ptr_t * nodes, int max_cycles,
{
info = Ace_ObjInfo(obj);
info->static_prob = info->num_ones / (double) max_cycles;
assert(info->static_prob >= 0.0 && info->static_prob <= 1.0);
VTR_ASSERT(info->static_prob >= 0.0 && info->static_prob <= 1.0);
info->switch_prob = info->num_toggles / (double) max_cycles;
assert(info->switch_prob >= 0.0 && info->switch_prob <= 1.0);
VTR_ASSERT(info->switch_prob >= 0.0 && info->switch_prob <= 1.0);
assert(info->switch_prob - EPSILON <= 2.0 * (1.0 - info->static_prob));
assert(info->switch_prob - EPSILON <= 2.0 * (info->static_prob));
VTR_ASSERT(info->switch_prob - EPSILON <= 2.0 * (1.0 - info->static_prob));
VTR_ASSERT(info->switch_prob - EPSILON <= 2.0 * (info->static_prob));
info->status = ACE_SIM;
}

15
compilation/dependencies.md
View File

@ -1,15 +0,0 @@
Yosys
=========
*Information taken from Yosys' GitHub*
You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. TCL, readline and libffi are optional (see ENABLE_* settings in Makefile). Xdot (graphviz) is used by the show command in yosys to display schematics.
ABC
=========
ABC depends on gcc-4.9. It is precisely this version which is required. If another gcc is used, the compilation will not be finished correctly.
ACE2
=========
ACE2 only needs a compiler to work. Gcc is the one chosen in this case. No issue was ever reported with ACE2 so if you have one, raise an issue so that we can modify it here.

40
compilation/macos_compilation.md
View File

@ -1,40 +0,0 @@
MacOS compilation
==================
*This tutorial has been tested under MacOS High Sierra 10.13.4*
Clone the [OpenFPGA git repository:](https://github.com/LNIS-Projects/OpenFPGA)
`git clone --recurse-submodules https://github.com/LNIS-Projects/OpenFPGA.git `
[//todo]: # (There is a submodule in the repository so move to the OpenFPGA directory and clone that too:)
[//]: # (`git submodule init`)
[//todo]: # (`git submodule update`)
Go to the `VPR` directory and build the tool:
`cd ./OpenFPGA/vpr7_x2p/vpr/`
Note: the graphical interface might not be usable since it requires the X11 library. In this case, open the Makefile and change the line 10 "ENABLE_GRAPHICS = true" to false.
`make `
This will generate vpr and a libvpr.a file.
Enhancements of VPR were made.
In order to see them just type:
`./vpr`
This will show the different options that can be used. Our modifications concern the options starting with fpga_spice and fpga_verilog.
A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog
`source ./go.sh`
This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).
As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.

40
compilation/red_hat_compilation.md
View File

@ -1,40 +0,0 @@
Red Hat compilation
==================
*This tutorial has been tested under Red Hat 7.5*
Clone the [OpenFPGA git repository:](https://github.com/LNIS-Projects/OpenFPGA)
`git clone --recurse-submodules https://github.com/LNIS-Projects/OpenFPGA.git `
[//todo]: # (There is a submodule in the repository so move to the OpenFPGA directory and clone that too:)
[//]: # (`git submodule init`)
[//todo]: # (`git submodule update`)
Go to the `VPR` directory and build the tool:
`cd ./OpenFPGA/vpr7_x2p/vpr/`
Note: the graphical interface might not be usable since it requires the X11 library. In this case, open the Makefile and change the line 10 "ENABLE_GRAPHICS = true" to false.
`make `
This will generate vpr and a libvpr.a file.
Enhancements of VPR were made.
In order to see them just type:
`./vpr`
This will show the different options that can be used. Our modifications concern the options starting with fpga_spice and fpga_verilog.
A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog
`source ./go.sh`
This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).
As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.

37
compilation/ubuntu_compilation.md
View File

@ -1,37 +0,0 @@
Ubuntu compilation
==================
*This tutorial has been tested under Ubuntu 18.04*
Clone the [OpenFPGA git repository:](https://github.com/LNIS-Projects/OpenFPGA)
`git clone --recurse-submodules https://github.com/LNIS-Projects/OpenFPGA.git `
[//todo]: # (There is a submodule in the repository so move to the OpenFPGA directory and clone that too:)
[//]: # (`git submodule init`)
[//todo]: # (`git submodule update`)
Go to the `VPR` directory and build the tool:
`cd ./OpenFPGA/vpr7_x2p/vpr/`
`make `
This will generate vpr and a libvpr.a file.
Enhancements of VPR were made.
In order to see them just type:
`./vpr`
This will show the different options that can be used. Our modifications concern the options starting with fpga_spice and fpga_verilog.
A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog
`source ./go.sh`
This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).
As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.

2
docs/Makefile
View File

@ -3,7 +3,7 @@
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXBUILD = sphinx-build-3.6
SPHINXBUILD = sphinx-build
SOURCEDIR = source
BUILDDIR = build

116
docs/source/arch_lang/circuit_model_examples.rst
View File

@ -13,7 +13,7 @@ Inverters and Buffers
<port type="output" prefix="string" size="int"/>
</circuit_model>
.. note:: customized SPICE netlists are not currently supported for inverters and buffers.
.. note:: customized Verilog/SPICE netlists are not currently supported for inverters and buffers.
* design_technology:
@ -128,7 +128,7 @@ Pass-gate Logic
<port type="output" prefix="string" size="int"/>
</circuit_model>
.. note:: customized SPICE netlists are not currently supported for pass-gate logics.
.. note:: customized Verilog/SPICE netlists are not currently supported for pass-gate logics.
* design_technology:
@ -209,12 +209,30 @@ SRAMs
<port type="output" prefix="string" size="int"/>
</circuit_model>
.. note:: The circuit designs of SRAMs are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-SPICE requires users to provide their customized SRAM SPICE/Verilog netlists. A sample SPICE netlist of SRAM can be found in the directory SpiceNetlists in the released package. FPGA-SPICE assumes that all the LUTs and MUXes employ the SRAM circuit design. Therefore, currently only one SRAM type is allowed to be defined.
.. note:: The circuit designs of SRAMs are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized SRAM Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of SRAM can be found in the directory SpiceNetlists in the released package. FPGA-Verilog/SPICE assumes that all the LUTs and MUXes employ the SRAM circuit design. Therefore, currently only one SRAM type is allowed to be defined.
.. note:: The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
.. note:: The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
.. note:: The support SRAM modules should have a BL and a WL when the memory-bank-style configuration circuit is declared. Note that the WL should be the write/read enable signal, while BL is the data input.
Logic gates
-----
.. code-block:: xml
<circuit_model type="gate" name="string" prefix="string" netlist="string" dump_explicit_port_map="true|false"/>
<design_technology type="cmos" topology="string"/>
<input_buffer exist="string" circuit_model_name="string"/>
<output_buffer exist="string" circuit_model_name="string"/>
<port type="input" prefix="string" lib_name="string" size="int"/>
<port type="output" prefix="string" lib_name="string" size="int"/>
</circuit_model>
.. note:: The circuit model in the type of gate aims to support direct mapping to standard cells or customized cells provided by technology vendors or users.
.. note:: The logic functionality of a gate can be defined through the XML keyword ``topology``. Currently, OpenFPGA supports AND, OR and MUX2 gates. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported.
.. note:: It may happen that the port sequence in generated Verilog netlists has conflicts with the port sequence in standard and customized cells. To avoid this, users can set the XML keyword ``dump_explicit_port_map`` to be true, which enables explicit port mapping are dumped. Users can specify the pin/port name in the standard cell library using the XML keyword ``lib_name``.
Multiplexers
------------
@ -222,8 +240,7 @@ Multiplexers
.. code-block:: xml
<circuit_model type="mux" name="string" prefix="string" is_default="int">
<design_technology type="string" structure="string" num_level="int" ron="float" roff="float"
prog_transistor_size="float"/>
<design_technology type="string" structure="string" num_level="int" add_const_input="string" const_input_val="int" local_encoder="string" ron="float" roff="float" prog_transistor_size="float"/>
<input_buffer exist="string" circuit_model_name="string"/>
<output_buffer exist="string" circuit_model_name="string"/>
<pass_gate_logic type="string" circuit_model_name="string"/>
@ -232,24 +249,31 @@ Multiplexers
<port type="sram" prefix="string" size="int"/>
</circuit_model>
.. note:: customized SPICE netlists are not currently supported for multiplexers.
.. note:: customized Verilog/SPICE netlists are not currently supported for multiplexers.
* design_technology:
* **structure:** can be [tree|multi-level|one-level]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If *multi-level* the following parameter is required:
* **structure:** can be [``tree`` \| ``multi-level`` \| ``one-level``]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5]. If ``multi-level`` the following parameter is required:
* **num_level:** specify the number of levels when multi-level structure is selected, only.
* **add_const_input:** can be [``true`` \| ``false``]. When enabled, an extra input will be added to the multiplexer circuits defined in this ``circuit_model``. For example, an 4-input multiplexer will be turned to a 5-input multiplexer. The extra input will be wired to a constant value, which can be specified through the XML syntax ``const_input_val``. The constant value can be either 0 or 1 (By default it is 0). Note that adding such input will help reducing the leakage power of FPGA and parasitic signal activities, with a limited area overhead.
* **const_input_val:** specify the constant value, to which the extra input will be connected. This syntax is only valid when the ``add_const_input`` is set to true.
* **local_encoder:** can be [``true`` \| ``false``]. When enabled, an local encoder will be added to the multiplexer circuits defined in this ``circuit_model``. The local encoder will be interface the SRAM inputs of multiplexing structure and SRAMs. It can encode the one-hot codes (that drive the select port of multiplexing structure) to a binary code. For example, 8-bit ``00000001`` will be encoded to 3-bit ``000``. This will help reduce the number of SRAM cells used in FPGAs as well as configuration time (especially for scan-chain configuration protocols). But it may cost an area overhead.
* **prog_transistor_size:** valid only when the type of design technology is rram. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node <transistors>.
.. note:: Local encoders are only applicable for one-level and multi-level multiplexers. Tree-like multiplexers are already encoded in their nature.
* If type of design technology is **rram**, then the following parameters are required:
* **prog_transistor_size:** valid only when the type of design technology is ``rram``. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node ``transistors``. If type of design technology is ``rram``, then the following parameters are required:
* **ron:** valid only when the type of design technology is rram. Specify the on-resistance of the RRAM device used in the RRAM-based multiplexer.
* **roff:** valid only when the type of design technology is rram. Specify the off-resistance of the RRAM device used in the RRAM-based multiplexer.
* port: for a multiplexer, the three types of ports, input, output and sram should be defined.
* port: for a multiplexer, the three types of ports, ``input``, ``output`` and ``sram`` should be defined.
.. note:: For tree-like multiplexers, they can be built with standard cell MUX2. To enable this, users should define a ``circuit_model``, which describes a 2-input multiplexer (See details and examples in how to define a logic gate using ``circuit_model``. In this case, the ``circuit_model_name`` in the ``pass_gate_logic`` should be the name of MUX2 ``circuit_model``.
**Mux 1 level example**
@ -319,23 +343,31 @@ Look-Up Tables
.. code-block:: xml
<circuit_model type="lut" name="string" prefix="string" is_default="int" netlist="string"/>
<design_technology type="cmos"/>
<lut_input_buffer exist="string" circuit_model_name="string"/>
<design_technology type="cmos" fracturable_lut="true|false"/>
<input_buffer exist="string" circuit_model_name="string"/>
<output_buffer exist="string" circuit_model_name="string"/>
<lut_input_buffer exist="string" circuit_model_name="string"/>
<lut_intermediate_buffer exist="string" circuit_model_name="string" location_map="string"/>
<lut_input_inverter exist="string" circuit_model_name="string"/>
<pass_gate_logic type="string" circuit_model_name="string"/>
<port type="input" prefix="string" size="int"/>
<port type="output" prefix="string" size="int"/>
<port type="sram" prefix="string" size="int"/>
<port type="input" prefix="string" size="int" tri_state_map="----11" circuit_model_name="string"/>
<port type="output" prefix="string" size="int" lut_frac_level="int" lut_output_mask="int"/>
<port type="sram" prefix="string" size="int" mode_select="true|false" circuit_model_name="string" default_val="0|1"/>
</circuit_model>
.. note:: The SPICE netlists of LUT can be auto-generated or customized.
.. note:: The Verilog/SPICE netlists of LUT can be auto-generated or customized.
The auto-generated LUTs are based on a tree-like multiplexer, whose gates of the transistors are used as the inputs of LUTs and the drains/sources of the transistors are used for configurable memories (SRAMs).
The LUT provided in customized SPICE netlist should have the same decoding methodology as the traditional LUT.
The LUT provided in customized Verilog/SPICE netlist should have the same decoding methodology as the traditional LUT.
Additional design parameters for LUTs:
* **lut_input_buffer:** Specify the buffer for the inputs of a LUT (gates of the internal multiplexer).
* **lut_input_buffer:** Define transistor-level description for the buffer for the inputs of a LUT (gates of the internal multiplexer). Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit.
* **lut_input_inverter:** Define transistor-level description for the inverter for the inputs of a LUT (gates of the internal multiplexer). Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit.
* **lut_intermediate_buffer:** Define transistor-level description for the buffer locating at intermediate stages of internal multiplexer of a LUT. Use keyword circuit_model_name to specify the circuit_model that containing details of the circuit. To customize the location, users can define an integer array in the XML keyword location_map. For example, "-1-1-" indicates buffer inseration to every two stages of the LUT multiplexer tree, considering a 6-input LUT.
Instructions of defining design parameters:
@ -343,7 +375,9 @@ Instructions of defining design parameters:
* **pass_gate_logic:** Specify the pass-gates of the internal multiplexer, the same as the multiplexers.
* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* **port:** three types of ports (input, output and sram) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist. To support customizable LUTs, each type of port contain special keywords. For input ports, the keyword tri_state_map aims to customize which inputs are fixed to constant values when the LUT is in fracturable modes. For example, tri_state_map="----11" indicates that the last two inputs will be fixed to be logic '1' when a 6-input LUT is in fracturable modes. The circuit_model_name of input port is used to specify which logic gates will be used to tri-state the inputs in fracturable LUT modes. It is required to use an AND gate to force logic '0' or an OR gate to force logic '1' for the input ports. For output ports, the keyword lut_frac_level is used to specify the level in LUT multiplexer tree where the output port are wired to. For example, lut_frac_level="4" in a fracturable LUT6 means that the output are potentially wired to the 4th stage of a LUT multiplexer and it is an output of a LUT4. The keyword lut_output_mask describes which fracturable outputs are used. For instance, in a 6-LUT, there are potentially four LUT4 outputs can be wired out. lut_output_mask="0,2" indicates that only the first and the thrid LUT4 outputs will be used in fracturable mode. Note that the size of the output port should be consistent to the length of lut_output_mask.
* **SRAM port for mode selection:** To enable switch between different operating modes, the SRAM bits of a fracturable LUT consists of two parts: configuration memory and mode selecting. The SRAM port for mode selection is specified through the XML keyword mode_select. Note that the size of such SRAM port should be consistent to the number of 1s or 0s in the tri_state_map.
**LUT example**
@ -372,7 +406,7 @@ The code describing this LUT is:
</circuit_model>
**This example shows:**
* The difference between *input_buffer* and *lut_input_buffer* and that they are independent.
* The difference between ``input_buffer`` and ``lut_input_buffer`` and that they are independent.
* How each blocks is defined
Flip-Flops
@ -389,17 +423,17 @@ Flip-Flops
<port type="clock" prefix="string" size="int"/>
</circuit_model>
.. note:: The circuit designs of flip-flops are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-SPICE requires users to provide their customized FF SPICE/Verilog netlists. A sample SPICE netlist of FF can be found in the directory SpiceNetlists in the released package.
.. note:: The circuit designs of flip-flops are highly dependent on the technology node and well optimized by engineers. Therefore, FPGA-Verilog/SPICE requires users to provide their customized FF Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of FF can be found in the directory SpiceNetlists in the released package.
The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
FPGA-SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
FPGA-Verilog/SPICE currently support only one clock domain in the FPGA. Therefore there should be only one clock port to be defined and the size of the clock port should be 1.
Instructions of defining design parameters:
* **circuit_model type:** can be ff or scff. FF is typical Flip-Flop, SCFF is Scan-Chain Flip-Flop
* **port:** three types of ports (input, output and clock) should be defined. If the user provides a customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* **port:** three types of ports (input, output and clock) should be defined. If the user provides a customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
**FF example**
@ -426,9 +460,9 @@ The code describing this FF is:
</circuit_model>
**This example shows:**
* Circuit model type as ff
* The verilog netlist file associated to this component *ff.v*
* 3 ports, *Set*, *Reset* and *clk*, defined as global
* Circuit model type as ``ff``
* The verilog netlist file associated to this component ``ff.v``
* 3 ports, ``Set``, ``Reset`` and ``clk``, defined as global
**SCFF example**
@ -453,9 +487,9 @@ The code describing this FF is:
</circuit_model>
**This example shows:**
* Circuit model type as scff
* The verilog netlist file associated to this component *scff.v*
* 1 port, *clk*, defined as global
* Circuit model type as ``scff``
* The verilog netlist file associated to this component ``scff.v``
* 1 port, ``clk``, defined as global
Hard Logics
-----------
@ -473,18 +507,18 @@ Hard Logics
.. note:: Hard logics are defined for non-configurable resources in FPGA architectures, such as adders, multipliers and RAM blocks.
Their circuit designs are highly dependent on the technology node and well optimized by engineers.
As more functional units are included in FPGA architecture, it is impossible to auto-generate these functional units [3].
Therefore, FPGA-SPICE requires users to provide their customized SPICE netlists. A sample SPICE netlist of a 1-bit adder can be found in the directory SpiceNetlists in the released package.
Therefore, FPGA-Verilog/SPICE requires users to provide their customized Verilog/SPICE netlists. A sample Verilog/SPICE netlist of a 1-bit adder can be found in the directory SpiceNetlists in the released package.
The information of input and output buffer should be clearly specified according to the customized SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
Instructions of defining design parameters:
* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
Routing Wire Segments
---------------------
FPGA-SPICE provides two types of SPICE models for the wire segments in FPGA architecture:
FPGA-Verilog/SPICE provides two types of Verilog/SPICE models for the wire segments in FPGA architecture:
* One type is called **wire**, which targets the local wires inside the logic blocks. The wire has one input and one output, directly connecting the output of a driver and the input of the downstream unit, respectively
* The other type is called **chan_wire**, especially targeting the channel wires. The channel wires have one input and two outputs, one of which is connected to the inputs of Connection Boxes while the other is connected to the inputs of Switch Boxes. Two outputs are created because from the view of layout, the inputs of Connection Boxes are typically connected to the middle point of channel wires, which has less parasitic resistances and capacitances than connected to the ending point.
@ -500,15 +534,15 @@ FPGA-SPICE provides two types of SPICE models for the wire segments in FPGA arch
<wire_param model_type="string" res_val="float" cap_val="float" level="int"/>
</circuit_model>
.. note:: FPGA-SPICE can auto-generate the SPICE model for wires while also allows users to provide their customized SPICE netlists.
.. note:: FPGA-Verilog/SPICE can auto-generate the Verilog/SPICE model for wires while also allows users to provide their customized Verilog/SPICE netlists.
The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
Instructions of defining design parameters:
* **type:** can be [wire|chan_wire]. The SPICE model wire targets the local wire inside the logic block while the chan_wire targets the channel wires in global routing.
* **type:** can be [wire|chan_wire]. The Verilog/SPICE model wire targets the local wire inside the logic block while the chan_wire targets the channel wires in global routing.
* **port:** two types of ports (input and output) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* **port:** two types of ports (input and output) should be defined. If the user provides an customized Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
* **wire_param:**
@ -542,7 +576,7 @@ The code describing this wire is:
**This example shows**
* How to use the *wire_param* for a π-type RC wire model
* How to use this circuit_model to auto-generate the SPICE netlist
* How to use this circuit_model to auto-generate the Verilog/SPICE netlist
I/O pads
--------
@ -560,13 +594,13 @@ I/O pads
</circuit_model>
.. note:: The circuit designs of I/O pads are highly dependent on the technology node and well optimized by engineers.
Therefore, FPGA-SPICE requires users to provide their customized SPICE/Verilog netlists. A sample SPICE netlist of an I/O pad can be found in the directory SpiceNetlists in the released package.
Therefore, FPGA-Verilog/SPICE requires users to provide their customized Verilog/SPICE/Verilog netlists. A sample Verilog/SPICE netlist of an I/O pad can be found in the directory SpiceNetlists in the released package.
The information of input and output buffer should be clearly specified according to the customized netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis.
Instructions of defining design parameters:
* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* **port:** two types of ports (input and output) should be defined. If the user provides a user-defined Verilog/SPICE netlist, the bandwidth of ports should be defined to the same as the Verilog/SPICE netlist.
**IO-pad example**

24
docs/source/arch_lang/circuit_modules.rst
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@ -1,10 +1,10 @@
Define Circuit-level Modules
============================
To support FPGA SPICE, Verily and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks.
To support FPGA Verilog/SPICE, Verily and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks.
The physical modules are defined in XML syntax, similar to the original VPR FPGA architecture description language.
For each module that appears in the FPGA architecture, a circuit model should be defined. In the definition of a circuit model, the user can specify if the SPICE netlist of the module is either auto-generated or user-defined.
For each module that appears in the FPGA architecture, a circuit model should be defined. In the definition of a circuit model, the user can specify if the Verilog/SPICE netlist of the module is either auto-generated or user-defined.
Define circuit_models
---------------------
@ -22,21 +22,21 @@ Define circuit_models
* **circuit_model**: the child node defining transistor-level modeling parameters.
* **type**: can be [ inv_buf | pass_gate | mux | wire | chan_wire | sram | lut | ff | scff | hard_logic | iopad ]. Specify the type of circuit model. The provided types cover all the modules in FPGAs. For the circuit models in the type of mux/wire/chan_wire/lut, FPGA-SPICE can auto-generate SPICE netlists. For the rest, FPGA-SPICE requires a user-defined SPICE netlist.
* **type**: can be [ inv_buf | pass_gate | mux | wire | chan_wire | sram | lut | ff | scff | hard_logic | iopad ]. Specify the type of circuit model. The provided types cover all the modules in FPGAs. For the circuit models in the type of mux/wire/chan_wire/lut, FPGA-Verilog/SPICE can auto-generate Verilog/SPICE netlists. For the rest, FPGA-Verilog/SPICE requires a user-defined Verilog/SPICE netlist.
* **name**: define the name of this circuit model. The name should be unique and will be used to create the sub-circuit of the circuit model in SPICE netlists. Note that for a customized SPICE netlist, the name defined here should be the name of the top-level sub-circuit in the customized SPICE netlist. FPGA-SPICE will check if the given name is conflicted with any reserved words.
* **name**: define the name of this circuit model. The name should be unique and will be used to create the sub-circuit of the circuit model in Verilog/SPICE netlists. Note that for a customized Verilog/SPICE netlist, the name defined here should be the name of the top-level sub-circuit in the customized Verilog/SPICE netlist. FPGA-Verilog/SPICE will check if the given name is conflicted with any reserved words.
* **prefix**: specify the name of the circuit_model to shown in the auto-generated SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique.
* **prefix**: specify the name of the circuit_model to shown in the auto-generated Verilog/SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique.
* **is_default**: can be [1|0], corresponding to [true|false] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-SPICE will find the default spice model defined in the same type and link. For a spice model type, only one spice model can be set as default.
* **is_default**: can be [1|0], corresponding to [true|false] respectively. Specify this circuit model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-Verilog/SPICE will find the default spice model defined in the same type and link. For a spice model type, only one spice model can be set as default.
* **spice_netlist**: specify the path and file name of a customized SPICE netlist. For some modules such as SRAMs, FFs, inpads, and outpads, FPGA-SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined.
* **spice_netlist**: specify the path and file name of a customized Verilog/SPICE netlist. For some modules such as SRAMs, FFs, inpads, and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined.
* **verilog_netlist**: specify the path and file name of a customized Verilog netlist. For some modules such as SRAMs, FFs, inpad and outpads, FPGA-SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined.
* **verilog_netlist**: specify the path and file name of a customized Verilog netlist. For some modules such as SRAMs, FFs, inpad and outpads, FPGA-Verilog/SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design is highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-Verilog/SPICE, the user can also define a custom netlist. Multiplexers cannot be user-defined.
* **dump_structural_verilog**: when the value of this keyword is set to be true, Verilog generator will output gate-level netlists of this module, instead of behavior-level. Gate-level netlists bring more opportunities in layout-level optimization while behavior-level is more suitable for high-speed formal verification and easier in debugging with HDL simulators.
.. note:: If netlist is not specified, FPGA-SPICE auto-generates the SPICE netlists for multiplexers, wires, and LUTs.
.. note:: If netlist is not specified, FPGA-Verilog/SPICE auto-generates the Verilog/SPICE netlists for multiplexers, wires, and LUTs.
.. note:: The user-defined netlists, such as LUTs, the decoding methodology should comply with the auto-generated LUTs (See Section 4.5)
@ -67,7 +67,7 @@ Transistor level
* input_buffer and output_buffer:
* **exist:** [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined SPICE netlist.
* **exist:** [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined Verilog/SPICE netlist.
* **circuit_model_name:** Specify the name of circuit model which is used to implement input/output buffer, the type of specified circuit model should be inv_buf.
@ -79,7 +79,7 @@ Transistor level
* **type:** can be [input|output|sram|clock]. For programmable modules, such as multiplexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined.
* **prefix:** the name of the port. Each port will be shown as <prefix>[i], 0≤i<size in SPICE netlists.
* **prefix:** the name of the port. Each port will be shown as <prefix>[i] in Verilog/SPICE netlists.
* **size:** bandwidth of the port.
@ -96,3 +96,5 @@ Transistor level
* **is_reset:** can be either true or false. Specify if this port controls a reset signal. Only valid when is_global is true. All the reset ports are connected to a global reset voltage stimuli in testbenches.
* **is_config_enable:** can be either true or false. Only valid when is_global is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the config_enable ports are connected to global configuration-enable voltage stimuli in testbenches.
.. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of ``circuit_model`` for more details.

2
docs/source/arch_lang/index.rst
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@ -19,6 +19,4 @@ Extended Architecture Description Language
link_circuit_modules
.. multimode_support

112
docs/source/arch_lang/link_circuit_modules.rst
View File

@ -1,6 +1,6 @@
Link circuit modules
--------------------
Each defined SPICE model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-SPICE creating the SPICE netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
Each defined circuit model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-circuit creating the circuit netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models.
SRAM
====
@ -30,7 +30,7 @@ To link the defined circuit model of SRAM into the FPGA architecture description
Example of a memory organization using memory decoders
.. note:: Currently SPICE only supports standalone memory organization.
.. note:: Currently circuit only supports standalone memory organization.
.. note:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
@ -45,7 +45,7 @@ Switch Boxes
=============
Original VPR architecture description contains an XML node called switchlist under which all the multiplexers of switch blocks are described.
To link a defined SPICE model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions.
To link a defined circuit model to a multiplexer in the switch blocks, a new XML property circuit_model_name should be added to the descriptions.
Here is an example:
@ -59,10 +59,10 @@ Here is an example:
Connection Blocks
================
==================
To link the defined SPICE model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
Therefore, FPGA-SPICE requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined.
To link the defined circuit model of the multiplexer to the Connection Blocks, a circuit_model_name should be added to the definition of Connection Blocks switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
Therefore, FPGA-circuit requires a new XML node called **cblock** under the root XML node architecture, where a switch for connection blocks can be defined.
Here is the example:
@ -87,30 +87,98 @@ Similar to the Switch Boxes and Connection Blocks, the channel wire segments in
* circuit_model_name: should match a circuit model whose type is chan_wire defined under module_circuit_models.
Primitive Blocks inside Configurable Logic Blocks
=================================================
Primitive Blocks inside Multi-mode Configurable Logic Blocks
=============================================================
The architecture description employs a hierarchy of pb_types to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model.
The architecture description employs a hierarchy of ``pb_types`` to depict the sub-modules and complex interconnections inside logic blocks. Each leaf node and interconnection in the pb_type hierarchy should be linked to a circuit model.
Each primitive block, i.e., the leaf ``pb_types``, should be linked to a valid circuit model, using the XML syntax ``circuit_model_name``.
The ``circuit_model_name`` should match the given name of a ``circuit_model`` defined by users.
.. code-block:: xml
<pb_type name="clb" idle_mode_name="ble" physical_mode_name="ble">
<pb_type name="ble">
<pb_type name="lut" circuit_model_name="lut6">
<pb_type name="ff" circuit_model_name="dff">
<!-- Multi-mode BLE -->
<pb_type name="ble" num_pb="10" physical_mode_name="ble_phy"/>
<!-- Physical implementation of BLE shown in Fig. :ref:`` -->
<mode name="ble_phy" disabled_in_packing="true"/>
<!-- Define a 6-input LUT in BLE and link it to circuit model -->
<pb_type name="flut6_phy" circuit_model_name="frac_lut6">
<input name="in" num_pins="6"/>
<output name="lut4_out" num_pins="4"/>
<output name="lut5_out" num_pins="2"/>
<output name="lut6_out" num_pins="1"/>
</pb_type>
<pb_type name="lut4_phy" circuit_model_name="lut4">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
</pb_type>
<pb_type name="adder_phy" num_pb="2" circuit_model_name="adder">
<input name="a" num_pins="1"/>
<input name="b" num_pins="1"/>
<input name="cin" num_pins="1"/>
<output name="cout" num_pins="1"/>
<output name="sumout" num_pins="1"/>
</pb_type>
<pb_type name="ff_phy" num_pb="2" circuit_model_name="dff">
<input name="D" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/>
</pb_type>
<interconnect>
<mux input="lut.out ff.Q" output="ble.out" circuit_model_name="mux_1level">
<!-- Routing multiplexers are omitted in this example. -->
</interconnect>
</pb_type>
<interconnect>
<mux input="ble.out clb.in" output="ble.in" circuit_model_name="mux_2level">
</interconnect>
</mode>
<!-- Arithmetic mode of BLE shown in Fig. 2(b)-->
<mode name="flut4_arithmetic"/>
<pb_type name="flut4_arith" num_pb="4"/>
<!-- Define a virtual 4-input LUT in BLE and link it to physical 6-input LUT defined at LINE 6 -->
<pb_type name="lut4" mode_bits="01" physical_pb_type_name="flut6_phy">
<!-- Define an input port and link it to its physical port defined at LINE 7 -->
<input name="in" num_pins="4" physical_mode_pin="in[3:0]"/>
<!-- Define an output port and link it to its physical port defined at LINE 8 -->
<output name="out" num_pins="1" physical_mode_pin="lut4_out"/>
</pb_type>
<pb_type name="adder" num_pb="2" physical_pb_type_name="adder_phy">
<input name="a" num_pins="1" physical_mode_pin="a"/>
<input name="b" num_pins="1" physical_mode_pin="b"/>
<input name="cin" num_pins="1" physical_mode_pin="cin"/>
<output name="cout" num_pins="1" physical_mode_pin="cout"/>
<output name="sumout" num_pins="1" physical_mode_pin="sumout"/>
</pb_type>
<pb_type name="ff" num_pb="2" physical_pb_type_name="ff_phy">
<input name="D" num_pins="1" physical_mode_pin="D"/>
<output name="Q" num_pins="1" physical_mode_pin="Q"/>
<clock name="clk" num_pins="1" physical_mode_pin="clk"/>
</pb_type>
<interconnect>
<!-- Routing multiplexers are omitted in this example. Full details can be found in [21] -->
</interconnect>
</pb_type>
</mode>
<!-- More operating modes can be defined -->
</pb_type>
* **circuit_model_name:** should match a SPICE model defined under module_circuit_models. For the interconnection type direct, the type of the linked SPICE model should be wire. For mux, the type of linked SPICE model should be mux. For complete, the type of the linked SPICE model can be either mux or wire, depending on the case.
* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the configurable block. This is critical in modeling actual circuit designs and architecture of an FPGA. Typically, only one physical_mode should be specified for each multi-mode ``pb_type``.
* **idle_mode_name:** tell the name of the mode that the pb_type is configured to be by default. This is critical in building SPICE netlists for unused logic blocks.
* **idle_mode_name:** tell the name of the mode that the ``pb_type`` is configured to be by default. This is critical in building circuit netlists for unused logic blocks.
* **physical_mode_name:** tell the name of the mode that describes the physical implementation of the block. This is critical in modeling actual circuit designs and architecture of an FPGA.
* **circuit_model_name:** should match a circuit model defined under ``module_circuit_models``. The ``circuit_model_name`` is mandatory for every leaf ``pb_type`` in a physical_mode ``pb_type``. For the interconnection type direct, the type of the linked circuit model should be wire. For multiplexers, the type of linked circuit model should be ``mux``. For complete, the type of the linked circuit model can be either ``mux`` or ``wire``, depending on the case.
* **mode_bits** specifies the configuration bits for the ``circuit_model`` when operating at an operating mode. The length of ``mode_bits`` should match the ``port`` size defined in ``circuit_model``. The ``mode_bits`` should be derived from circuit designs while users are responsible for its correctness. FPGA-Bitstreamm will add the ``mode_bits`` during bitstream generation.
* **physical_pb_type_name** creates the link on ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid name of leaf ``pb_type`` in physical mode.
* **physical_pb_type_index_factor** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the index of ``pb_type`` will be multipled by the given factor.
* **physical_pb_type_index_offset** aims to align the indices for ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_pb_type_name`` is larger than 1, the index of ``pb_type`` will be shifted by the given factor.
* **physical_mode_pin** creates the linke on ``port`` of ``pb_type`` between operating and physical modes. This syntax is mandatory for every leaf ``pb_type`` in an operating mode ``pb_type``. It should be a valid ``port`` name of leaf ``pb_type`` in physical mode and the port size should also match.
* **physical_mode_pin_rotate_offset** aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset.
.. note::
It is highly recommended that only one physical mode is defined for a multi-mode configurable block. Try not to use nested physical mode definition. This will ease the debugging and lead to clean XML description.
.. note::
Be careful in using ``physical_pb_type_index_factor``, ``physical_pb_type_index_offset`` and ``physical_mode_pin_rotate_offset``! Try to avoid using them unless for highly complex configuration blocks with very deep hierarchy.

4
docs/source/arch_lang/multimode_support.rst
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@ -1,4 +0,0 @@
Modeling Physical Design of Multi-mode Configurable Logic Block Architectures
=============================================================================
Under construction

22
docs/source/eda_flow.rst
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@ -18,7 +18,6 @@ FPGA-Bitstream is the part of the flow in charge of the functional verification
How to compile
==============
Running the Makefile in the root of the released package can compile all the source codes.
Guides can be found in the *compilation* directory in the main folder. We tested it for MacOS High Sierra 10.13.4, Ubuntu 18.04 and Red Hat 7.5. This list is not exhaustive as other distributions could work as well.
As a general rule, the compilation follows these steps:
@ -31,21 +30,24 @@ If you need the full flow:
2) Go into the folder you just cloned and make the different submodules through a global Makefile:
cd OpenFPGA
make
OR
make -j
(if you have multiple cores, this will make the compilation way faster.)
mkdir build (*if folder doesn't already exist*)
cd build
cmake ..
make OR make -j (*if you have multiple cores, this will make the compilation way faster*)
If you only need vpr:
cd OpenFPGA/vpr7_x2p
make/make -j
cd OpenFPGA
mkdir build (if folder doesn't already exist)
cd build
cmake ..
make vpr/make vpr -j
3) Architectures, circuits and already written scripts exist to allow you to test the flow without having to provide any new information to the system. For this:
cd vpr7_x2p (if not done already)
cd vpr7_x2p
cd vpr
source ./go.sh
source ./go_fpga_verilog/spice.sh
go.sh is a script linking to a testing architecture and a simple circuit. The output will be in the folders spice_demo and verilog_demo.
They are scripts linking to a testing architecture and a simple circuit.
4) If you only need to see the new options implemented in vpr, do:
./vpr

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@ -1,4 +1,14 @@
Command-line Options for FPGA Bitstream Generator
=================================================
**Under Construction**
All the command line options of FPGA-Bitstream can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
FPGA-Verilog Supported Option::
--fpga_bitstream_generator
.. csv-table:: Commmand-line Option of FPGA-Bitstream
:header: "Command Options", "Description"
:widths: 15, 30
"--fpga_bitstream_generator", "Turn on the FPGA-Bitstream and output a .bitstream file containing FPGA configuration."

26
docs/source/fpga_verilog/command_line_usage.rst
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@ -8,11 +8,12 @@ FPGA-Verilog Supported Options::
--fpga_verilog
--fpga_verilog_dir <directory_path_of_dumped_verilog_files>
--fpga_verilog_include_timing
--fpga_verilog_init_sim
--fpga_verilog_print_modelsim_autodeck
--fpga_verilog_modelsim_ini_path <string>
--fpga_verilog_include_signal_init
--fpga_verilog_print_modelsim_autodeck <modelsim_ini_path>
--fpga_verilog_print_top_testbench
--fpga_verilog_print_top_auto_testbench <path_to_the_verilog_benchmark>
--fpga_verilog_print_autocheck_top_testbench <reference_verilog_file_path>
--fpga_verilog_print_formal_verification_top_netlist
--fpga_verilog_include_icarus_simulator
.. csv-table:: Commmand-line Options of FPGA-Verilog
@ -20,7 +21,7 @@ FPGA-Verilog Supported Options::
:widths: 15, 30
"--fpga_verilog", "Turn on the FPGA-Verilog."
"--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to. <dir_path> is the destination directory."
"--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to <dir_path> is the destination directory."
"--fpga_verilog_include_timing", "Includes the timings found in the XML file."
"--fpga_verilog_init_sim", "Initializes the simulation for ModelSim."
"--fpga_verilog_print_modelsim_autodeck", "Generates the scripts necessary to the ModelSim simulation."
@ -28,6 +29,21 @@ FPGA-Verilog Supported Options::
"--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA. Determines the type of autodeck."
"--fpga_verilog_print_top_auto_testbench \
<path_to_the_verilog_benchmark>", "Prints the testbench associated with the given benchmark. Determines the type of autodeck."
"--fpga_verilog_dir <dir_path>", "Specify the directory where all the Verilog files will be outputted to. <dir_path> is the destination directory."
"--fpga_verilog_include_timing", "Includes the timings found in the XML architecture description file."
"--fpga_verilog_include_signal_init", "Set all nets to random value to be close of a real power-on case"
"--fpga_verilog_print_modelsim_autodeck <modelsim_ini_path>", "Generates the scripts necessary to the ModelSim simulation and specify the path to modelsim.ini file."
"--fpga_verilog_print_top_testbench", "Prints the full-chip-level testbench for the FPGA, which includes programming phase and operationg phase (random patterns)."
"--fpga_verilog_print_autocheck_top_testbench \
<reference_verilog_file_path>", "Prints a testbench stimulating the generated FPGA and the initial benchmark to compare stimuli responses, which includes programming phase and operationg phase (random patterns)"
"--fpga_verilog_print_formal_verification_top_netlist", "Prints a Verilog top file compliant with formal verification tools. With this top file the FPGA is initialy programmed. It also prints a testbench with random patterns, which can be manually or automatically check regarding previous options."
"--fpga_verilog_include_icarus_simulator", "Activates waveforms .vcd file generation and simulation timeout, which are required for Icarus Verilog simulator"
"--fpga_verilog_print_input_blif_testbench", "Generates a Verilog test-bench to use with input blif file"
"--fpga_verilog_print_report_timing_tcl", "Generates tcl commands to run STA analysis with TO COMPLETE TOOL"
"--fpga_verilog_report_timing_rpt_path <path_to_generate_reports>", "Specifies path where report timing are written"
"--fpga_verilog_print_sdc_pnr", "Generates SDC constraints to PNR"
"--fpga_verilog_print_sdc_analysis", "Generates SDC to run timing analysis in PNR tool"
"--fpga_verilog_print_user_defined_template", "Generates a template of hierarchy modules and their port mapping"
.. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are:

11
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@ -1,15 +1,20 @@
Hierarchy of Verilog Output Files
============================
All the generated Verilog Netlists are located in the <verilog_dir> as you specify in the command-line options. Under the <verilog_dir>, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules.
All the generated Verilog Netlists are located in the <verilog_dir>/SRC as you specify in the command-line options. Under the <verilog_dir>/SRC, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules.
.. csv-table:: Folder hierarchy of FPGA-Verilog
:header: "Folder", "Content"
:header: "File/Folder", "Content"
:widths: 10, 20
"name_top.v", "Contains the top module and calls all the other .v files"
"name.bitstream", "Only if --fpga_verilog_print_top_testbench or --fpga_verilog_print_top_auto_testbench is chosen. Contains the bitstream programming the generated FPGA."
"name_top_tb.v", "Only if --fpga_verilog_print_top_testbench or --fpga_verilog_print_top_auto_testbench is chosen. Contains the testbench used for the simulation."
"name_top_tb.v", "Only if --fpga_verilog_print_top_testbench. Contains a testbench used for the simulation."
"name_autocheck_top_tb.v", "Only if --fpga_verilog_print_autocheck_top_testbench is chosen. Contains a testbench used for the simulation."
"name_formal_random_top_tb.v", "Only if --fpga_verilog_print_formal_verification_top_netlist is chosen. Contains a testbench used for the simulation."
"name_top_formal_verification.v", "Only if --fpga_verilog_print_formal_verification_top_netlist is chosen. Contains a top fil used for formal verification and by name_formal_random_top_tb.v."
"fpga_defines.v", "Contains all the defines set as 'include_timing'"
"name_include_netlists.v", "Contains all the netlists and defines paths used for the simulation."
"lb", "Logic Block. Contains all the CLBs. The logic_block.v includes all the CLB and is called by the top module afterward."
"routing", "Contains all the routing in the circuit. You can find in it the Switch Boxes, the Connection Blocks and the routing needed to connect the different blocks. The routing.v file packs them all and is called by the top module."
"sub_modules", "Contains the modules generated by the flow to build the CLBs."

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@ -15,7 +15,7 @@ In this manual, we will introduce how to use FPGA-SPICE to conduct an accurate p
In the appendix, we introduce the hierarchy of the generated SPICE netlists and testbenches, to help you customize the SPICE netlists. We also attach an example of an architecture XML file for your interest.
The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015`.
The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
FPGA-Verilog
------------
@ -24,7 +24,9 @@ On a second note, it is becoming more and more necessary to have fast access to
This motivates us to generate the Verilog code of the architecture to enable a second level of research concerning the architectures to be explored. This Verilog code encompasses the whole design and is divided into multiple sub-directories for targetted analysis or a global one. This is left to the choice of the user.
In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling a deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section
In this manual, we present FPGA-Verilog. This extension enables the generation of a fully functional Verilog code enabling a deeper understanding of the architectures of the FPGAs. We introduce different options to this module to do the verification of the system. This will be presented in more depth in the FPGA-Bitstream section.
The technical details can be found in our TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
FPGA-Bitstream
--------------

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@ -38,7 +38,7 @@ month={Sept},}
@article{XTang_TCAS1_2016,
title={{A Study on the Programming Structures for RRAM-based FPGA Architectures}},
author={Tang, Xifan and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni},
author={X. Tang and Kim, Gain and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni},
journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
volume={63},
number={4},
@ -106,3 +106,16 @@ month={Sept},}
address = {New York, NY, USA},
keywords = {CAD, FPGA, architecture},
}
@ARTICLE{XTang_TVLSI_2019,
author={X. Tang and E. Giacomin and G. D. Micheli and P. Gaillardon},
journal={{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}},
title={{FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs}},
year={2019},
volume={27},
number={3},
pages={637-650},
doi={10.1109/TVLSI.2018.2883923},
ISSN={1063-8210},
month={March},
}

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@ -1,77 +0,0 @@
# Examples_README
## Example_1
The goal of this example is just to make a first step into the software. The .blif contains only an inverter.
The .xml is currently on <layout auto="1.0"/> which means that the size depends on the .blif. Since the .blif is
almost empty, only 1 CLB will be generated.
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png" alt="Example_1_FPGA" width="60%">
Schematic of the FPGA generated during example_1.
The CLB integrates a 4-inputs LUT, a FF and a MUX.
---
**Things to understand in this example**
Everything won't be explained in detail but few important structures (some common with the VPR project) are to be explained in order to build good architectures.
```xml
<architecture>
<models>
... add models such as the io pads.
</models>
<spice_settings>
... all tech and spice parameters are defined here.
<module_spice_models>
... define the Basic Elements of the architecture and the modules that cannot
be generated (i.e. the Flip-Flop) but need to be called.
</module_spice_models>
</spice_settings>
<cblocks>
... complex blocks
<complexblocklist>
... here we define the hierarchy of the primitive blocks and interconnect them
together
<pb_type>
... defines the primitive block
</pb_type>
<interconnect>
...
</interconnect>
</complexblocklist>
</cblocks>
</architecture>
```
---
## Example_2
Example_2's goal is to introduce the slices, the interconnections which can be generated from it and the manual mode of the layout.
In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry.
There is a feedback-loop from the output of the slices to the input MUXs
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png" alt="Example_2_CLB" width="60%">
Schematic showing the CLB generated in this example.
---
**Things to understand in this example**
```xml
<layout width="3" height="3"/> <!-- Manual mode of the layout allowing us to choose the number of CLBs -->
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in" spice_model_name="mux_2level">
<!-- Defines how we apply the feedback on the inputs of the slices -->
<delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[3:0].in" />
<delay_constant max="53.44e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
</complete>
```
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_3x3.png" alt="Example_2_FPGA" width="60%">

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@ -1,4 +0,0 @@
I0 0.478200 0.190600
clk 0.493600 0.194000
Q0 0.521800 0.190600
n7 0.521800 0.099455

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@ -1,10 +0,0 @@
# Benchmark "inverter.bench" written by ABC on Wed Nov 14 13:52:06 2018
.model inverter.bench
.inputs I0 clk
.outputs Q0
.latch n7 Q0 re clk 0
.names I0 n7
0 1
.end

13
examples/example_1.sh
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@ -1,13 +0,0 @@
#!/bin/sh
# Example of how to run vpr
# The paths need to be absolute hence we modify a keyword with PWD
sed "s:OPENFPGAPATH:${PWD}/..:g" example_1_template.xml > example_1.xml
# Pack, place, and route a heterogeneous FPGA
# Packing uses the AAPack algorithm
../vpr7_x2p/vpr/vpr ./example_1.xml ./example_1.blif --full_stats --nodisp --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_example_1 --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_example_1

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examples/example_1.xml
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@ -1,403 +0,0 @@
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch)
that describe them.
-->
<models>
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0"/>
<!-- <layout width="3" height="3"/> -->
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<!-- Used only when doing monte_carlo simulations
<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
<cmos abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/>
</monte_carlo>
-->
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimulate>
<clock op_freq="auto" sim_slack="0.2" prog_freq="2.5e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimulate>
</parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</transistors>
<module_circuit_models>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="one-level"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" is_default="1" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="on" circuit_model_name="buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/VerilogNetlists/sram.v" >
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
<port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_blwl" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</module_circuit_models>
</spice_settings>
<device>
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
<timing C_ipin_cblock="596e-18" T_ipin_cblock="77.93e-12"/>
<area grid_logic_tile_area="0"/>
<sram area="6">
<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
</cblocks>
<switchlist>
<switch type="mux" name="sb_mux_L4" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
<segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1 </cb>
</segment>
<segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
</segmentlist>
<complexblocklist>
<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
</interconnect>
</mode>
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1" circuit_model_name="iopad" mode_bits="0">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- In this example, to keep the design as simple as possible, we
create a CLB with only a BLE and no feedback-->
<pb_type name="clb" area="53894" opin_to_cb="false">
<pin_equivalence_auto_detect input_ports ="off" output_ports="off"/>
<input name="I" num_pins="4" equivalent="true"/>
<output name="O" num_pins="1" equivalent="false"/>
<clock name="clk" num_pins="1"/>
<!-- fle basically refers to a slice. In this example, we just want one of them but we
leave it in so that we know this architecture can and should be used -->
<pb_type name="fle" num_pb="1" idle_mode_name="n1_lut4" physical_mode_name="n1_lut4">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin -->
<mode name="n1_lut4">
<!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut4">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix, one delay per input -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
127e-12
127e-12
127e-12
127e-12
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="29e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="16e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> -->
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out" circuit_model_name="mux_1level_tapbuf">
<delay_constant max="42.06e-12" in_port="lut4.out" out_port="ble4.out" />
<delay_constant max="42.06e-12" in_port="ff.Q" out_port="ble4.out" />
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect>
</mode>
<!-- 4-LUT mode definition end -->
</pb_type>
<interconnect>
<complete name="crossbar" input="clb.I fle[0:0].out" output="fle[0:0].in" circuit_model_name="mux_2level">
<delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[0:0].in" />
<delay_constant max="53.44e-12" in_port="fle[0:0].out" out_port="fle[0:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[0:0].clk">
</complete>
<direct name="clbouts1" input="fle[0:0].out[0:0]" output="clb.O[0:0]"/>
<!--direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/-->
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<pinlocations pattern="spread"/>
<!-- Place this general purpose logic block in any unspecified column -->
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
<!-- Define fracturable multiplier begin -->
</complexblocklist>
<power>
<local_interconnect C_wire="0"/>
<mux_transistor_size mux_transistor_size="5"/>
<FF_size FF_size="4"/>
<LUT_transistor_size LUT_transistor_size="5"/>
</power>
<clocks>
<clock buffer_size="auto" C_wire="0"/>
</clocks>
</architecture>

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examples/example_1_template.xml
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@ -1,403 +0,0 @@
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch)
that describe them.
-->
<models>
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0"/>
<!-- <layout width="3" height="3"/> -->
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<!-- Used only when doing monte_carlo simulations
<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
<cmos abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/>
</monte_carlo>
-->
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimulate>
<clock op_freq="auto" sim_slack="0.2" prog_freq="2.5e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimulate>
</parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATH/vpr7_x2p/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</transistors>
<module_circuit_models>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="one-level"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" is_default="1" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="on" circuit_model_name="buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="16"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/sram.v" >
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
<port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_blwl" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</module_circuit_models>
</spice_settings>
<device>
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
<timing C_ipin_cblock="596e-18" T_ipin_cblock="77.93e-12"/>
<area grid_logic_tile_area="0"/>
<sram area="6">
<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
</cblocks>
<switchlist>
<switch type="mux" name="sb_mux_L4" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
<segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1 </cb>
</segment>
<segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
</segmentlist>
<complexblocklist>
<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
</interconnect>
</mode>
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1" circuit_model_name="iopad" mode_bits="0">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- In this example, to keep the design as simple as possible, we
create a CLB with only a BLE and no feedback-->
<pb_type name="clb" area="53894" opin_to_cb="false">
<pin_equivalence_auto_detect input_ports ="off" output_ports="off"/>
<input name="I" num_pins="4" equivalent="true"/>
<output name="O" num_pins="1" equivalent="false"/>
<clock name="clk" num_pins="1"/>
<!-- fle basically refers to a slice. In this example, we just want one of them but we
leave it in so that we know this architecture can and should be used -->
<pb_type name="fle" num_pb="1" idle_mode_name="n1_lut4" physical_mode_name="n1_lut4">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin -->
<mode name="n1_lut4">
<!-- Define 4-LUT mode -->
<pb_type name="ble4" num_pb="1">
<input name="in" num_pins="4"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut4">
<input name="in" num_pins="4" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix, one delay per input -->
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
127e-12
127e-12
127e-12
127e-12
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="29e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="16e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
<direct name="direct2" input="lut4.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> -->
</direct>
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out" circuit_model_name="mux_1level_tapbuf">
<delay_constant max="42.06e-12" in_port="lut4.out" out_port="ble4.out" />
<delay_constant max="42.06e-12" in_port="ff.Q" out_port="ble4.out" />
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble4.in"/>
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
</interconnect>
</mode>
<!-- 4-LUT mode definition end -->
</pb_type>
<interconnect>
<complete name="crossbar" input="clb.I fle[0:0].out" output="fle[0:0].in" circuit_model_name="mux_2level">
<delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[0:0].in" />
<delay_constant max="53.44e-12" in_port="fle[0:0].out" out_port="fle[0:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[0:0].clk">
</complete>
<direct name="clbouts1" input="fle[0:0].out[0:0]" output="clb.O[0:0]"/>
<!--direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/-->
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<pinlocations pattern="spread"/>
<!-- Place this general purpose logic block in any unspecified column -->
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
<!-- Define fracturable multiplier begin -->
</complexblocklist>
<power>
<local_interconnect C_wire="0"/>
<mux_transistor_size mux_transistor_size="5"/>
<FF_size FF_size="4"/>
<LUT_transistor_size LUT_transistor_size="5"/>
</power>
<clocks>
<clock buffer_size="auto" C_wire="0"/>
</clocks>
</architecture>

4
examples/example_2.act
View File

@ -1,4 +0,0 @@
I0 0.501800 0.202600
clk 0.488800 0.199600
Q0 0.498200 0.202600
n7 0.498200 0.100935

10
examples/example_2.blif
View File

@ -1,10 +0,0 @@
# Benchmark "example_2.bench" written by ABC on Wed Nov 14 11:42:18 2018
.model example_2.bench
.inputs I0 clk
.outputs Q0
.latch n7 Q0 re clk 0
.names I0 n7
0 1
.end

13
examples/example_2.sh
View File

@ -1,13 +0,0 @@
#!/bin/sh
# Example of how to run vpr
# The paths need to be absolute hence we modify a keyword with PWD
sed "s:OPENFPGAPATH:${PWD}/..:g" example_2_template.xml > example_2.xml
# Pack, place, and route a heterogeneous FPGA
# Packing uses the AAPack algorithm
../vpr7_x2p/vpr/vpr ./example_2.xml ./example_2.blif --full_stats --nodisp --route_chan_width 100 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_example_2 --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_example_2

397
examples/example_2.xml
View File

@ -1,397 +0,0 @@
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch)
that describe them.
-->
<models>
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0"/> <!-- Takes the smallest square possible that fits the number of LUTs needed -->
<!-- <layout width="3" height="3"/> -->
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<!-- Used only when doing monte_carlo simulations
<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
<cmos abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/>
</monte_carlo>
-->
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimulate>
<clock op_freq="auto" sim_slack="0.2" prog_freq="2.5e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimulate>
</parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</transistors>
<module_circuit_models>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="one-level"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" is_default="1" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="on" circuit_model_name="buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="64"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/VerilogNetlists/sram.v" >
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
<port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="/var/tmp/Presentation_OpenFPGA/test/OpenFPGA/examples/../vpr7_x2p/vpr/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_blwl" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</module_circuit_models>
</spice_settings>
<device>
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
<timing C_ipin_cblock="596e-18" T_ipin_cblock="77.93e-12"/>
<area grid_logic_tile_area="0"/>
<sram area="6">
<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
</cblocks>
<switchlist>
<switch type="mux" name="sb_mux_L4" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
<segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1 </cb>
</segment>
<segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
</segmentlist>
<complexblocklist>
<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
</interconnect>
</mode>
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1" circuit_model_name="iopad" mode_bits="0">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<pb_type name="clb" area="53894" opin_to_cb="false">
<pin_equivalence_auto_detect input_ports ="off" output_ports="off"/>
<input name="I" num_pins="40" equivalent="true"/> <!-- Each slice will have 6 inputs but we pass the output of a slice to the next one hence 4x(6-1)= 20 inputs (one input from the first slice is hanging) -->
<output name="O" num_pins="10" equivalent="false"/>
<clock name="clk" num_pins="1"/>
<!-- fle basically refers to a slice. In this example, we just want one of them but we
leave it in so that we know this architecture can and should be used -->
<pb_type name="fle" num_pb="10" idle_mode_name="n1_lut6" physical_mode_name="n1_lut6">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin -->
<mode name="n1_lut6">
<!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut6">
<input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix, one delay per input -->
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
127e-12
127e-12
127e-12
127e-12
127e-12
127e-12
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="29e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="16e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble6.in" output="lut6.in"/>
<direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist-->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out" circuit_model_name="mux_1level_tapbuf">
<delay_constant max="42.06e-12" in_port="lut6.out" out_port="ble6.out" />
<delay_constant max="42.06e-12" in_port="ff.Q" out_port="ble6.out" />
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect>
</mode>
<!-- 6-LUT mode definition end -->
</pb_type>
<interconnect>
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in" circuit_model_name="mux_2level">
<delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[9:0].in" />
<delay_constant max="53.44e-12" in_port="fle[9:0].out" out_port="fle[9:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete>
<direct name="clbouts1" input="fle[9:0].out" output="clb.O[9:0]"/>
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<pinlocations pattern="spread"/>
<!-- Place this general purpose logic block in any unspecified column -->
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
<power>
<local_interconnect C_wire="0"/>
<mux_transistor_size mux_transistor_size="5"/>
<FF_size FF_size="4"/>
<LUT_transistor_size LUT_transistor_size="5"/>
</power>
<clocks>
<clock buffer_size="auto" C_wire="0"/>
</clocks>
</architecture>

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examples/example_2_template.xml
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@ -1,397 +0,0 @@
<architecture>
<!--
ODIN II specific config begins
Describes the types of user-specified netlist blocks (in blif, this corresponds to
".model [type_of_block]") that this architecture supports.
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
already special structures in blif (.names, .input, .output, and .latch)
that describe them.
-->
<models>
<model name="io">
<input_ports>
<port name="outpad"/>
</input_ports>
<output_ports>
<port name="inpad"/>
</output_ports>
</model>
</models>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout auto="1.0"/> <!-- Takes the smallest square possible that fits the number of LUTs needed -->
<!-- <layout width="3" height="3"/> -->
<spice_settings>
<parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<!-- Used only when doing monte_carlo simulations
<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
<cmos abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/>
</monte_carlo>
-->
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimulate>
<clock op_freq="auto" sim_slack="0.2" prog_freq="2.5e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimulate>
</parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATH/vpr7_x2p/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</transistors>
<module_circuit_models>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
<design_technology type="cmos"/>
<input_buffer exist="off"/>
<output_buffer exist="off"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="one-level"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" is_default="1" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="on" circuit_model_name="buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="64"/>
</circuit_model>
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/sram.v" >
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
</circuit_model>
<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="2"/>
<port type="bl" prefix="bl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
<port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="inout" prefix="pad" size="1"/>
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_blwl" default_val="1"/>
<port type="input" prefix="outpad" size="1"/>
<port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
</module_circuit_models>
</spice_settings>
<device>
<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
<timing C_ipin_cblock="596e-18" T_ipin_cblock="77.93e-12"/>
<area grid_logic_tile_area="0"/>
<sram area="6">
<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
<spice organization="standalone" circuit_model_name="sram6T" />
</sram>
<chan_width_distr>
<io width="1.000000"/>
<x distr="uniform" peak="1.000000"/>
<y distr="uniform" peak="1.000000"/>
</chan_width_distr>
<switch_block type="wilton" fs="3"/>
</device>
<cblocks>
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
</switch>
</cblocks>
<switchlist>
<switch type="mux" name="sb_mux_L4" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
</switch>
</switchlist>
<segmentlist>
<segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1 1 1</sb>
<cb type="pattern">1 1 1 1</cb>
</segment>
<segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1 1</sb>
<cb type="pattern">1 1 </cb>
</segment>
<segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
<mux name="sb_mux_L4"/>
<sb type="pattern">1 1</sb>
<cb type="pattern">1</cb>
</segment>
</segmentlist>
<complexblocklist>
<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- physical design description -->
<mode name="io_phy" disabled_in_packing="false">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
</interconnect>
</mode>
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1" circuit_model_name="iopad" mode_bits="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
</interconnect>
</mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1" circuit_model_name="iopad" mode_bits="0">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
</interconnect>
</mode>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<!-- IOs go on the periphery of the FPGA, for consistency,
make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-->
<pinlocations pattern="custom">
<loc side="left">io.outpad io.inpad</loc>
<loc side="top">io.outpad io.inpad</loc>
<loc side="right">io.outpad io.inpad</loc>
<loc side="bottom">io.outpad io.inpad</loc>
</pinlocations>
<!-- Place I/Os on the sides of the FPGA -->
<gridlocations>
<loc type="perimeter" priority="10"/>
</gridlocations>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<pb_type name="clb" area="53894" opin_to_cb="false">
<pin_equivalence_auto_detect input_ports ="off" output_ports="off"/>
<input name="I" num_pins="40" equivalent="true"/> <!-- Each slice will have 6 inputs but we pass the output of a slice to the next one hence 4x(6-1)= 20 inputs (one input from the first slice is hanging) -->
<output name="O" num_pins="10" equivalent="false"/>
<clock name="clk" num_pins="1"/>
<!-- fle basically refers to a slice. In this example, we just want one of them but we
leave it in so that we know this architecture can and should be used -->
<pb_type name="fle" num_pb="10" idle_mode_name="n1_lut6" physical_mode_name="n1_lut6">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- 4-LUT mode definition begin -->
<mode name="n1_lut6">
<!-- Define 6-LUT mode -->
<pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Define LUT -->
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut6">
<input name="in" num_pins="6" port_class="lut_in"/>
<output name="out" num_pins="1" port_class="lut_out"/>
<!-- LUT timing using delay matrix, one delay per input -->
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
127e-12
127e-12
127e-12
127e-12
127e-12
127e-12
</delay_matrix>
</pb_type>
<!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="29e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="16e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble6.in" output="lut6.in"/>
<direct name="direct2" input="lut6.out" output="ff.D">
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist-->
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out" circuit_model_name="mux_1level_tapbuf">
<delay_constant max="42.06e-12" in_port="lut6.out" out_port="ble6.out" />
<delay_constant max="42.06e-12" in_port="ff.Q" out_port="ble6.out" />
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
</interconnect>
</mode>
<!-- 6-LUT mode definition end -->
</pb_type>
<interconnect>
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in" circuit_model_name="mux_2level">
<delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[9:0].in" />
<delay_constant max="53.44e-12" in_port="fle[9:0].out" out_port="fle[9:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
</complete>
<direct name="clbouts1" input="fle[9:0].out" output="clb.O[9:0]"/>
</interconnect>
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
<pinlocations pattern="spread"/>
<!-- Place this general purpose logic block in any unspecified column -->
<gridlocations>
<loc type="fill" priority="1"/>
</gridlocations>
</pb_type>
<!-- Define general purpose logic block (CLB) ends -->
</complexblocklist>
<power>
<local_interconnect C_wire="0"/>
<mux_transistor_size mux_transistor_size="5"/>
<FF_size FF_size="4"/>
<LUT_transistor_size LUT_transistor_size="5"/>
</power>
<clocks>
<clock buffer_size="auto" C_wire="0"/>
</clocks>
</architecture>

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examples/spice_test_example_1/cb_mux_tb/example_1_cbx1_0_cbmux_testbench.sp
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*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
Xmux_2level_tapbuf_size4[0] mux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->outb sram[2]->out sram[3]->out sram[3]->outb gvdd_mux_2level_tapbuf_size4[0] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[0], level=2, select_path_id=0. *****
*****1010*****
Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[0]->out) 0
.nodeset V(sram[0]->outb) vsp
Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[1]->out) 0
.nodeset V(sram[1]->outb) vsp
Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[2]->out) 0
.nodeset V(sram[2]->outb) vsp
Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[3]->out) 0
.nodeset V(sram[3]->outb) vsp
***** Signal mux_2level_tapbuf_size4[0]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[0] gvdd_mux_2level_tapbuf_size4[0] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][0]_rrnode[69] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][0]_rrnode[69] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][0]_rrnode[69] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][0]_rrnode[69] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][0]_rrnode[69] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][0]_rrnode[69] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][0]_rrnode[69] param='mux_2level_tapbuf_size4[0]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[0]_energy_per_cycle param='mux_2level_tapbuf_size4[0]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][0]_rrnode[69] param='mux_2level_tapbuf_size4[0]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[69] param='dynamic_power_cb_mux[1][0]_rrnode[69]*clock_period'
.meas tran dynamic_rise_cb_mux[1][0]_rrnode[69] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_rise_cb_mux[1][0]_rrnode[69]' to='start_rise_cb_mux[1][0]_rrnode[69]+switch_rise_cb_mux[1][0]_rrnode[69]'
.meas tran dynamic_fall_cb_mux[1][0]_rrnode[69] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_fall_cb_mux[1][0]_rrnode[69]' to='start_fall_cb_mux[1][0]_rrnode[69]+switch_fall_cb_mux[1][0]_rrnode[69]'
.meas tran sum_leakage_power_mux[0to0]
+ param='leakage_cb_mux[1][0]_rrnode[69]'
.meas tran sum_energy_per_cycle_mux[0to0]
+ param='energy_per_cycle_cb_mux[1][0]_rrnode[69]'
******* Normal TYPE loads *******
Xload_inv[0]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[1] gvdd_load 0 inv size=1
Xload_inv[2]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[2] gvdd_load 0 inv size=1
Xload_inv[3]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[3] gvdd_load 0 inv size=1
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to0]
+ param='leakage_cb_mux[1][0]_rrnode[69]'
.meas tran sum_energy_per_cycle_cb_mux[0to0]
+ param='energy_per_cycle_cb_mux[1][0]_rrnode[69]'
Xmux_2level_tapbuf_size4[1] mux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->out sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size4[1] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[1], level=2, select_path_id=0. *****
*****1010*****
Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[4]->out) 0
.nodeset V(sram[4]->outb) vsp
Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[5]->out) 0
.nodeset V(sram[5]->outb) vsp
Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[6]->out) 0
.nodeset V(sram[6]->outb) vsp
Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[7]->out) 0
.nodeset V(sram[7]->outb) vsp
***** Signal mux_2level_tapbuf_size4[1]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[1] gvdd_mux_2level_tapbuf_size4[1] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][0]_rrnode[48] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][0]_rrnode[48] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][0]_rrnode[48] param='mux_2level_tapbuf_size4[1]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[1]_energy_per_cycle param='mux_2level_tapbuf_size4[1]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][0]_rrnode[48] param='mux_2level_tapbuf_size4[1]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[48] param='dynamic_power_cb_mux[1][0]_rrnode[48]*clock_period'
.meas tran dynamic_rise_cb_mux[1][0]_rrnode[48] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_rise_cb_mux[1][0]_rrnode[48]' to='start_rise_cb_mux[1][0]_rrnode[48]+switch_rise_cb_mux[1][0]_rrnode[48]'
.meas tran dynamic_fall_cb_mux[1][0]_rrnode[48] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_fall_cb_mux[1][0]_rrnode[48]' to='start_fall_cb_mux[1][0]_rrnode[48]+switch_fall_cb_mux[1][0]_rrnode[48]'
.meas tran sum_leakage_power_mux[0to1]
+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[1][0]_rrnode[48]'
.meas tran sum_energy_per_cycle_mux[0to1]
+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[1][0]_rrnode[48]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to1]
+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[1][0]_rrnode[48]'
.meas tran sum_energy_per_cycle_cb_mux[0to1]
+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[1][0]_rrnode[48]'
Xmux_2level_tapbuf_size4[2] mux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->outb sram[10]->out sram[11]->out sram[11]->outb gvdd_mux_2level_tapbuf_size4[2] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[2], level=2, select_path_id=0. *****
*****1010*****
Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[8]->out) 0
.nodeset V(sram[8]->outb) vsp
Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[9]->out) 0
.nodeset V(sram[9]->outb) vsp
Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[10]->out) 0
.nodeset V(sram[10]->outb) vsp
Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[11]->out) 0
.nodeset V(sram[11]->outb) vsp
***** Signal mux_2level_tapbuf_size4[2]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[2] gvdd_mux_2level_tapbuf_size4[2] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][0]_rrnode[50] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][0]_rrnode[50] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][0]_rrnode[50] param='mux_2level_tapbuf_size4[2]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[2]_energy_per_cycle param='mux_2level_tapbuf_size4[2]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][0]_rrnode[50] param='mux_2level_tapbuf_size4[2]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[50] param='dynamic_power_cb_mux[1][0]_rrnode[50]*clock_period'
.meas tran dynamic_rise_cb_mux[1][0]_rrnode[50] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_rise_cb_mux[1][0]_rrnode[50]' to='start_rise_cb_mux[1][0]_rrnode[50]+switch_rise_cb_mux[1][0]_rrnode[50]'
.meas tran dynamic_fall_cb_mux[1][0]_rrnode[50] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_fall_cb_mux[1][0]_rrnode[50]' to='start_fall_cb_mux[1][0]_rrnode[50]+switch_fall_cb_mux[1][0]_rrnode[50]'
.meas tran sum_leakage_power_mux[0to2]
+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[1][0]_rrnode[50]'
.meas tran sum_energy_per_cycle_mux[0to2]
+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[1][0]_rrnode[50]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to2]
+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[1][0]_rrnode[50]'
.meas tran sum_energy_per_cycle_cb_mux[0to2]
+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[1][0]_rrnode[50]'
Xmux_2level_tapbuf_size4[3] mux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->outb sram[14]->out sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size4[3] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[3], level=2, select_path_id=0. *****
*****1010*****
Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[12]->out) 0
.nodeset V(sram[12]->outb) vsp
Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[13]->out) 0
.nodeset V(sram[13]->outb) vsp
Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[14]->out) 0
.nodeset V(sram[14]->outb) vsp
Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[15]->out) 0
.nodeset V(sram[15]->outb) vsp
***** Signal mux_2level_tapbuf_size4[3]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[3] gvdd_mux_2level_tapbuf_size4[3] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][0]_rrnode[52] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][0]_rrnode[52] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][0]_rrnode[52] param='mux_2level_tapbuf_size4[3]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[3]_energy_per_cycle param='mux_2level_tapbuf_size4[3]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][0]_rrnode[52] param='mux_2level_tapbuf_size4[3]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[52] param='dynamic_power_cb_mux[1][0]_rrnode[52]*clock_period'
.meas tran dynamic_rise_cb_mux[1][0]_rrnode[52] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_rise_cb_mux[1][0]_rrnode[52]' to='start_rise_cb_mux[1][0]_rrnode[52]+switch_rise_cb_mux[1][0]_rrnode[52]'
.meas tran dynamic_fall_cb_mux[1][0]_rrnode[52] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_fall_cb_mux[1][0]_rrnode[52]' to='start_fall_cb_mux[1][0]_rrnode[52]+switch_fall_cb_mux[1][0]_rrnode[52]'
.meas tran sum_leakage_power_mux[0to3]
+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[1][0]_rrnode[52]'
.meas tran sum_energy_per_cycle_mux[0to3]
+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[1][0]_rrnode[52]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to3]
+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[1][0]_rrnode[52]'
.meas tran sum_energy_per_cycle_cb_mux[0to3]
+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[1][0]_rrnode[52]'
Xmux_2level_tapbuf_size4[4] mux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb gvdd_mux_2level_tapbuf_size4[4] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[4], level=2, select_path_id=0. *****
*****1010*****
Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[16]->out) 0
.nodeset V(sram[16]->outb) vsp
Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[17]->out) 0
.nodeset V(sram[17]->outb) vsp
Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[18]->out) 0
.nodeset V(sram[18]->outb) vsp
Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[19]->out) 0
.nodeset V(sram[19]->outb) vsp
***** Signal mux_2level_tapbuf_size4[4]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[4] gvdd_mux_2level_tapbuf_size4[4] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][0]_rrnode[54] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][0]_rrnode[54] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][0]_rrnode[54] param='mux_2level_tapbuf_size4[4]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[4]_energy_per_cycle param='mux_2level_tapbuf_size4[4]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][0]_rrnode[54] param='mux_2level_tapbuf_size4[4]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[54] param='dynamic_power_cb_mux[1][0]_rrnode[54]*clock_period'
.meas tran dynamic_rise_cb_mux[1][0]_rrnode[54] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_rise_cb_mux[1][0]_rrnode[54]' to='start_rise_cb_mux[1][0]_rrnode[54]+switch_rise_cb_mux[1][0]_rrnode[54]'
.meas tran dynamic_fall_cb_mux[1][0]_rrnode[54] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_fall_cb_mux[1][0]_rrnode[54]' to='start_fall_cb_mux[1][0]_rrnode[54]+switch_fall_cb_mux[1][0]_rrnode[54]'
.meas tran sum_leakage_power_mux[0to4]
+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[1][0]_rrnode[54]'
.meas tran sum_energy_per_cycle_mux[0to4]
+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[1][0]_rrnode[54]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to4]
+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[1][0]_rrnode[54]'
.meas tran sum_energy_per_cycle_cb_mux[0to4]
+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[1][0]_rrnode[54]'
Xmux_2level_tapbuf_size4[5] mux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->out sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->outb sram[22]->out sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size4[5] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[5], level=2, select_path_id=0. *****
*****1010*****
Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[20]->out) 0
.nodeset V(sram[20]->outb) vsp
Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[21]->out) 0
.nodeset V(sram[21]->outb) vsp
Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[22]->out) 0
.nodeset V(sram[22]->outb) vsp
Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[23]->out) 0
.nodeset V(sram[23]->outb) vsp
***** Signal mux_2level_tapbuf_size4[5]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[5] gvdd_mux_2level_tapbuf_size4[5] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][0]_rrnode[56] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][0]_rrnode[56] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][0]_rrnode[56] param='mux_2level_tapbuf_size4[5]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[5]_energy_per_cycle param='mux_2level_tapbuf_size4[5]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][0]_rrnode[56] param='mux_2level_tapbuf_size4[5]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[56] param='dynamic_power_cb_mux[1][0]_rrnode[56]*clock_period'
.meas tran dynamic_rise_cb_mux[1][0]_rrnode[56] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_rise_cb_mux[1][0]_rrnode[56]' to='start_rise_cb_mux[1][0]_rrnode[56]+switch_rise_cb_mux[1][0]_rrnode[56]'
.meas tran dynamic_fall_cb_mux[1][0]_rrnode[56] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_fall_cb_mux[1][0]_rrnode[56]' to='start_fall_cb_mux[1][0]_rrnode[56]+switch_fall_cb_mux[1][0]_rrnode[56]'
.meas tran sum_leakage_power_mux[0to5]
+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[1][0]_rrnode[56]'
.meas tran sum_energy_per_cycle_mux[0to5]
+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[1][0]_rrnode[56]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to5]
+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[1][0]_rrnode[56]'
.meas tran sum_energy_per_cycle_cb_mux[0to5]
+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[1][0]_rrnode[56]'
Xmux_2level_tapbuf_size4[6] mux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb gvdd_mux_2level_tapbuf_size4[6] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[6], level=2, select_path_id=0. *****
*****1010*****
Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[24]->out) 0
.nodeset V(sram[24]->outb) vsp
Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[25]->out) 0
.nodeset V(sram[25]->outb) vsp
Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[26]->out) 0
.nodeset V(sram[26]->outb) vsp
Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[27]->out) 0
.nodeset V(sram[27]->outb) vsp
***** Signal mux_2level_tapbuf_size4[6]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[6] gvdd_mux_2level_tapbuf_size4[6] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][0]_rrnode[58] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][0]_rrnode[58] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][0]_rrnode[58] param='mux_2level_tapbuf_size4[6]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[6]_energy_per_cycle param='mux_2level_tapbuf_size4[6]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][0]_rrnode[58] param='mux_2level_tapbuf_size4[6]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[58] param='dynamic_power_cb_mux[1][0]_rrnode[58]*clock_period'
.meas tran dynamic_rise_cb_mux[1][0]_rrnode[58] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_rise_cb_mux[1][0]_rrnode[58]' to='start_rise_cb_mux[1][0]_rrnode[58]+switch_rise_cb_mux[1][0]_rrnode[58]'
.meas tran dynamic_fall_cb_mux[1][0]_rrnode[58] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_fall_cb_mux[1][0]_rrnode[58]' to='start_fall_cb_mux[1][0]_rrnode[58]+switch_fall_cb_mux[1][0]_rrnode[58]'
.meas tran sum_leakage_power_mux[0to6]
+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[1][0]_rrnode[58]'
.meas tran sum_energy_per_cycle_mux[0to6]
+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[1][0]_rrnode[58]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to6]
+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[1][0]_rrnode[58]'
.meas tran sum_energy_per_cycle_cb_mux[0to6]
+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[1][0]_rrnode[58]'
Xmux_2level_tapbuf_size4[7] mux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->out sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->outb sram[30]->out sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size4[7] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[7], level=2, select_path_id=0. *****
*****1010*****
Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[28]->out) 0
.nodeset V(sram[28]->outb) vsp
Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[29]->out) 0
.nodeset V(sram[29]->outb) vsp
Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[30]->out) 0
.nodeset V(sram[30]->outb) vsp
Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[31]->out) 0
.nodeset V(sram[31]->outb) vsp
***** Signal mux_2level_tapbuf_size4[7]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[7] gvdd_mux_2level_tapbuf_size4[7] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][0]_rrnode[60] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][0]_rrnode[60] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][0]_rrnode[60] param='mux_2level_tapbuf_size4[7]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[7]_energy_per_cycle param='mux_2level_tapbuf_size4[7]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][0]_rrnode[60] param='mux_2level_tapbuf_size4[7]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[60] param='dynamic_power_cb_mux[1][0]_rrnode[60]*clock_period'
.meas tran dynamic_rise_cb_mux[1][0]_rrnode[60] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_rise_cb_mux[1][0]_rrnode[60]' to='start_rise_cb_mux[1][0]_rrnode[60]+switch_rise_cb_mux[1][0]_rrnode[60]'
.meas tran dynamic_fall_cb_mux[1][0]_rrnode[60] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_fall_cb_mux[1][0]_rrnode[60]' to='start_fall_cb_mux[1][0]_rrnode[60]+switch_fall_cb_mux[1][0]_rrnode[60]'
.meas tran sum_leakage_power_mux[0to7]
+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[1][0]_rrnode[60]'
.meas tran sum_energy_per_cycle_mux[0to7]
+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[1][0]_rrnode[60]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to7]
+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[1][0]_rrnode[60]'
.meas tran sum_energy_per_cycle_cb_mux[0to7]
+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[1][0]_rrnode[60]'
Xmux_2level_tapbuf_size4[8] mux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->outb sram[34]->out sram[35]->out sram[35]->outb gvdd_mux_2level_tapbuf_size4[8] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[8], level=2, select_path_id=0. *****
*****1010*****
Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[32]->out) 0
.nodeset V(sram[32]->outb) vsp
Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[33]->out) 0
.nodeset V(sram[33]->outb) vsp
Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[34]->out) 0
.nodeset V(sram[34]->outb) vsp
Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[35]->out) 0
.nodeset V(sram[35]->outb) vsp
***** Signal mux_2level_tapbuf_size4[8]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[8] gvdd_mux_2level_tapbuf_size4[8] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][0]_rrnode[62] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][0]_rrnode[62] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][0]_rrnode[62] param='mux_2level_tapbuf_size4[8]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[8]_energy_per_cycle param='mux_2level_tapbuf_size4[8]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][0]_rrnode[62] param='mux_2level_tapbuf_size4[8]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[62] param='dynamic_power_cb_mux[1][0]_rrnode[62]*clock_period'
.meas tran dynamic_rise_cb_mux[1][0]_rrnode[62] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_rise_cb_mux[1][0]_rrnode[62]' to='start_rise_cb_mux[1][0]_rrnode[62]+switch_rise_cb_mux[1][0]_rrnode[62]'
.meas tran dynamic_fall_cb_mux[1][0]_rrnode[62] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_fall_cb_mux[1][0]_rrnode[62]' to='start_fall_cb_mux[1][0]_rrnode[62]+switch_fall_cb_mux[1][0]_rrnode[62]'
.meas tran sum_leakage_power_mux[0to8]
+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[1][0]_rrnode[62]'
.meas tran sum_energy_per_cycle_mux[0to8]
+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[1][0]_rrnode[62]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to8]
+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[1][0]_rrnode[62]'
.meas tran sum_energy_per_cycle_cb_mux[0to8]
+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[1][0]_rrnode[62]'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
***** 2 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '2*clock_period'
***** Generic Measurements for Circuit Parameters *****
.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period'
.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='2*clock_period'
.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period'
.meas tran total_leakage_power_mux[0to8]
+ param='sum_leakage_power_mux[0to8]'
.meas tran total_energy_per_cycle_mux[0to8]
+ param='sum_energy_per_cycle_mux[0to8]'
.meas tran total_leakage_power_cb_mux
+ param='sum_leakage_power_cb_mux[0to8]'
.meas tran total_energy_per_cycle_cb_mux
+ param='sum_energy_per_cycle_cb_mux[0to8]'
.end

683
examples/spice_test_example_1/cb_mux_tb/example_1_cbx1_1_cbmux_testbench.sp
View File

@ -1,683 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
Xmux_2level_tapbuf_size4[0] mux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->outb sram[2]->out sram[3]->out sram[3]->outb gvdd_mux_2level_tapbuf_size4[0] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[0], level=2, select_path_id=0. *****
*****1010*****
Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[0]->out) 0
.nodeset V(sram[0]->outb) vsp
Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[1]->out) 0
.nodeset V(sram[1]->outb) vsp
Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[2]->out) 0
.nodeset V(sram[2]->outb) vsp
Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[3]->out) 0
.nodeset V(sram[3]->outb) vsp
***** Signal mux_2level_tapbuf_size4[0]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[0] gvdd_mux_2level_tapbuf_size4[0] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[89] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[89] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[89] param='mux_2level_tapbuf_size4[0]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[0]_energy_per_cycle param='mux_2level_tapbuf_size4[0]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[89] param='mux_2level_tapbuf_size4[0]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[89] param='dynamic_power_cb_mux[1][1]_rrnode[89]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[89] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_rise_cb_mux[1][1]_rrnode[89]' to='start_rise_cb_mux[1][1]_rrnode[89]+switch_rise_cb_mux[1][1]_rrnode[89]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[89] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_fall_cb_mux[1][1]_rrnode[89]' to='start_fall_cb_mux[1][1]_rrnode[89]+switch_fall_cb_mux[1][1]_rrnode[89]'
.meas tran sum_leakage_power_mux[0to0]
+ param='leakage_cb_mux[1][1]_rrnode[89]'
.meas tran sum_energy_per_cycle_mux[0to0]
+ param='energy_per_cycle_cb_mux[1][1]_rrnode[89]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to0]
+ param='leakage_cb_mux[1][1]_rrnode[89]'
.meas tran sum_energy_per_cycle_cb_mux[0to0]
+ param='energy_per_cycle_cb_mux[1][1]_rrnode[89]'
Xmux_2level_tapbuf_size4[1] mux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->out sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size4[1] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[1], level=2, select_path_id=0. *****
*****1010*****
Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[4]->out) 0
.nodeset V(sram[4]->outb) vsp
Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[5]->out) 0
.nodeset V(sram[5]->outb) vsp
Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[6]->out) 0
.nodeset V(sram[6]->outb) vsp
Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[7]->out) 0
.nodeset V(sram[7]->outb) vsp
***** Signal mux_2level_tapbuf_size4[1]->in[0] density = 0.1906, probability=0.5218.*****
Vmux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[0] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_2level_tapbuf_size4[1]->in[1] density = 0.1906, probability=0.4782.*****
Vmux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[1] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_2level_tapbuf_size4[1]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[1] gvdd_mux_2level_tapbuf_size4[1] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[91] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[91] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[91] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[91] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[91] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[91] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[91] param='mux_2level_tapbuf_size4[1]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='clock_period' to='7*clock_period'
.meas tran mux_2level_tapbuf_size4[1]_energy_per_cycle param='mux_2level_tapbuf_size4[1]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[91] param='mux_2level_tapbuf_size4[1]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[91] param='dynamic_power_cb_mux[1][1]_rrnode[91]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[91] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_rise_cb_mux[1][1]_rrnode[91]' to='start_rise_cb_mux[1][1]_rrnode[91]+switch_rise_cb_mux[1][1]_rrnode[91]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[91] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_fall_cb_mux[1][1]_rrnode[91]' to='start_fall_cb_mux[1][1]_rrnode[91]+switch_fall_cb_mux[1][1]_rrnode[91]'
.meas tran sum_leakage_power_mux[0to1]
+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[1][1]_rrnode[91]'
.meas tran sum_energy_per_cycle_mux[0to1]
+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[91]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to1]
+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[1][1]_rrnode[91]'
.meas tran sum_energy_per_cycle_cb_mux[0to1]
+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[91]'
Xmux_2level_tapbuf_size4[2] mux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->outb sram[10]->out sram[11]->out sram[11]->outb gvdd_mux_2level_tapbuf_size4[2] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[2], level=2, select_path_id=0. *****
*****1010*****
Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[8]->out) 0
.nodeset V(sram[8]->outb) vsp
Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[9]->out) 0
.nodeset V(sram[9]->outb) vsp
Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[10]->out) 0
.nodeset V(sram[10]->outb) vsp
Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[11]->out) 0
.nodeset V(sram[11]->outb) vsp
***** Signal mux_2level_tapbuf_size4[2]->in[0] density = 0.1906, probability=0.5218.*****
Vmux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[0] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_2level_tapbuf_size4[2]->in[1] density = 0.1906, probability=0.5218.*****
Vmux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[1] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_2level_tapbuf_size4[2]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[2] gvdd_mux_2level_tapbuf_size4[2] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[93] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[93] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[93] param='mux_2level_tapbuf_size4[2]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='clock_period' to='7*clock_period'
.meas tran mux_2level_tapbuf_size4[2]_energy_per_cycle param='mux_2level_tapbuf_size4[2]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[93] param='mux_2level_tapbuf_size4[2]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[93] param='dynamic_power_cb_mux[1][1]_rrnode[93]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[93] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_rise_cb_mux[1][1]_rrnode[93]' to='start_rise_cb_mux[1][1]_rrnode[93]+switch_rise_cb_mux[1][1]_rrnode[93]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[93] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_fall_cb_mux[1][1]_rrnode[93]' to='start_fall_cb_mux[1][1]_rrnode[93]+switch_fall_cb_mux[1][1]_rrnode[93]'
.meas tran sum_leakage_power_mux[0to2]
+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[1][1]_rrnode[93]'
.meas tran sum_energy_per_cycle_mux[0to2]
+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[93]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to2]
+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[1][1]_rrnode[93]'
.meas tran sum_energy_per_cycle_cb_mux[0to2]
+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[93]'
Xmux_2level_tapbuf_size4[3] mux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->outb sram[14]->out sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size4[3] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[3], level=2, select_path_id=0. *****
*****1010*****
Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[12]->out) 0
.nodeset V(sram[12]->outb) vsp
Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[13]->out) 0
.nodeset V(sram[13]->outb) vsp
Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[14]->out) 0
.nodeset V(sram[14]->outb) vsp
Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[15]->out) 0
.nodeset V(sram[15]->outb) vsp
***** Signal mux_2level_tapbuf_size4[3]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[3] gvdd_mux_2level_tapbuf_size4[3] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[95] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[95] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[95] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[95] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[95] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[95] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[95] param='mux_2level_tapbuf_size4[3]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[3]_energy_per_cycle param='mux_2level_tapbuf_size4[3]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[95] param='mux_2level_tapbuf_size4[3]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[95] param='dynamic_power_cb_mux[1][1]_rrnode[95]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[95] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_rise_cb_mux[1][1]_rrnode[95]' to='start_rise_cb_mux[1][1]_rrnode[95]+switch_rise_cb_mux[1][1]_rrnode[95]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[95] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_fall_cb_mux[1][1]_rrnode[95]' to='start_fall_cb_mux[1][1]_rrnode[95]+switch_fall_cb_mux[1][1]_rrnode[95]'
.meas tran sum_leakage_power_mux[0to3]
+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[1][1]_rrnode[95]'
.meas tran sum_energy_per_cycle_mux[0to3]
+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[95]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to3]
+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[1][1]_rrnode[95]'
.meas tran sum_energy_per_cycle_cb_mux[0to3]
+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[95]'
Xmux_2level_tapbuf_size4[4] mux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb gvdd_mux_2level_tapbuf_size4[4] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[4], level=2, select_path_id=0. *****
*****1010*****
Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[16]->out) 0
.nodeset V(sram[16]->outb) vsp
Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[17]->out) 0
.nodeset V(sram[17]->outb) vsp
Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[18]->out) 0
.nodeset V(sram[18]->outb) vsp
Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[19]->out) 0
.nodeset V(sram[19]->outb) vsp
***** Signal mux_2level_tapbuf_size4[4]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[4] gvdd_mux_2level_tapbuf_size4[4] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[97] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[97] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[97] param='mux_2level_tapbuf_size4[4]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[4]_energy_per_cycle param='mux_2level_tapbuf_size4[4]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[97] param='mux_2level_tapbuf_size4[4]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[97] param='dynamic_power_cb_mux[1][1]_rrnode[97]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[97] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_rise_cb_mux[1][1]_rrnode[97]' to='start_rise_cb_mux[1][1]_rrnode[97]+switch_rise_cb_mux[1][1]_rrnode[97]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[97] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_fall_cb_mux[1][1]_rrnode[97]' to='start_fall_cb_mux[1][1]_rrnode[97]+switch_fall_cb_mux[1][1]_rrnode[97]'
.meas tran sum_leakage_power_mux[0to4]
+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[1][1]_rrnode[97]'
.meas tran sum_energy_per_cycle_mux[0to4]
+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[97]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to4]
+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[1][1]_rrnode[97]'
.meas tran sum_energy_per_cycle_cb_mux[0to4]
+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[97]'
Xmux_2level_tapbuf_size4[5] mux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->out sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->outb sram[22]->out sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size4[5] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[5], level=2, select_path_id=0. *****
*****1010*****
Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[20]->out) 0
.nodeset V(sram[20]->outb) vsp
Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[21]->out) 0
.nodeset V(sram[21]->outb) vsp
Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[22]->out) 0
.nodeset V(sram[22]->outb) vsp
Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[23]->out) 0
.nodeset V(sram[23]->outb) vsp
***** Signal mux_2level_tapbuf_size4[5]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[5] gvdd_mux_2level_tapbuf_size4[5] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[99] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[99] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[99] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[99] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[99] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[99] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[99] param='mux_2level_tapbuf_size4[5]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[5]_energy_per_cycle param='mux_2level_tapbuf_size4[5]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[99] param='mux_2level_tapbuf_size4[5]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[99] param='dynamic_power_cb_mux[1][1]_rrnode[99]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[99] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_rise_cb_mux[1][1]_rrnode[99]' to='start_rise_cb_mux[1][1]_rrnode[99]+switch_rise_cb_mux[1][1]_rrnode[99]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[99] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_fall_cb_mux[1][1]_rrnode[99]' to='start_fall_cb_mux[1][1]_rrnode[99]+switch_fall_cb_mux[1][1]_rrnode[99]'
.meas tran sum_leakage_power_mux[0to5]
+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[1][1]_rrnode[99]'
.meas tran sum_energy_per_cycle_mux[0to5]
+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[99]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to5]
+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[1][1]_rrnode[99]'
.meas tran sum_energy_per_cycle_cb_mux[0to5]
+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[99]'
Xmux_2level_tapbuf_size4[6] mux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb gvdd_mux_2level_tapbuf_size4[6] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[6], level=2, select_path_id=0. *****
*****1010*****
Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[24]->out) 0
.nodeset V(sram[24]->outb) vsp
Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[25]->out) 0
.nodeset V(sram[25]->outb) vsp
Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[26]->out) 0
.nodeset V(sram[26]->outb) vsp
Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[27]->out) 0
.nodeset V(sram[27]->outb) vsp
***** Signal mux_2level_tapbuf_size4[6]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[6] gvdd_mux_2level_tapbuf_size4[6] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[101] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[101] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[101] param='mux_2level_tapbuf_size4[6]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[6]_energy_per_cycle param='mux_2level_tapbuf_size4[6]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[101] param='mux_2level_tapbuf_size4[6]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[101] param='dynamic_power_cb_mux[1][1]_rrnode[101]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[101] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_rise_cb_mux[1][1]_rrnode[101]' to='start_rise_cb_mux[1][1]_rrnode[101]+switch_rise_cb_mux[1][1]_rrnode[101]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[101] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_fall_cb_mux[1][1]_rrnode[101]' to='start_fall_cb_mux[1][1]_rrnode[101]+switch_fall_cb_mux[1][1]_rrnode[101]'
.meas tran sum_leakage_power_mux[0to6]
+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[1][1]_rrnode[101]'
.meas tran sum_energy_per_cycle_mux[0to6]
+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[101]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to6]
+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[1][1]_rrnode[101]'
.meas tran sum_energy_per_cycle_cb_mux[0to6]
+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[101]'
Xmux_2level_tapbuf_size4[7] mux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->out sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->outb sram[30]->out sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size4[7] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[7], level=2, select_path_id=0. *****
*****1010*****
Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[28]->out) 0
.nodeset V(sram[28]->outb) vsp
Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[29]->out) 0
.nodeset V(sram[29]->outb) vsp
Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[30]->out) 0
.nodeset V(sram[30]->outb) vsp
Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[31]->out) 0
.nodeset V(sram[31]->outb) vsp
***** Signal mux_2level_tapbuf_size4[7]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[2] density = 0.1906, probability=0.4782.*****
Vmux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[2] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_2level_tapbuf_size4[7]->in[3] density = 0.1906, probability=0.4782.*****
Vmux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->in[3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgvdd_mux_2level_tapbuf_size4[7] gvdd_mux_2level_tapbuf_size4[7] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[103] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[103] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[103] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[103] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[103] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[103] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[103] param='mux_2level_tapbuf_size4[7]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='clock_period' to='7*clock_period'
.meas tran mux_2level_tapbuf_size4[7]_energy_per_cycle param='mux_2level_tapbuf_size4[7]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[103] param='mux_2level_tapbuf_size4[7]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[103] param='dynamic_power_cb_mux[1][1]_rrnode[103]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[103] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_rise_cb_mux[1][1]_rrnode[103]' to='start_rise_cb_mux[1][1]_rrnode[103]+switch_rise_cb_mux[1][1]_rrnode[103]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[103] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_fall_cb_mux[1][1]_rrnode[103]' to='start_fall_cb_mux[1][1]_rrnode[103]+switch_fall_cb_mux[1][1]_rrnode[103]'
.meas tran sum_leakage_power_mux[0to7]
+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[1][1]_rrnode[103]'
.meas tran sum_energy_per_cycle_mux[0to7]
+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[103]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to7]
+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[1][1]_rrnode[103]'
.meas tran sum_energy_per_cycle_cb_mux[0to7]
+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[103]'
Xmux_2level_tapbuf_size4[8] mux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->outb sram[34]->out sram[35]->out sram[35]->outb gvdd_mux_2level_tapbuf_size4[8] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[8], level=2, select_path_id=0. *****
*****1010*****
Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[32]->out) 0
.nodeset V(sram[32]->outb) vsp
Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[33]->out) 0
.nodeset V(sram[33]->outb) vsp
Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[34]->out) 0
.nodeset V(sram[34]->outb) vsp
Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[35]->out) 0
.nodeset V(sram[35]->outb) vsp
***** Signal mux_2level_tapbuf_size4[8]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[8] gvdd_mux_2level_tapbuf_size4[8] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[67] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[67] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[67] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[67] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[67] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[67] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[67] param='mux_2level_tapbuf_size4[8]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[8]_energy_per_cycle param='mux_2level_tapbuf_size4[8]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[67] param='mux_2level_tapbuf_size4[8]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[67] param='dynamic_power_cb_mux[1][1]_rrnode[67]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[67] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_rise_cb_mux[1][1]_rrnode[67]' to='start_rise_cb_mux[1][1]_rrnode[67]+switch_rise_cb_mux[1][1]_rrnode[67]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[67] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_fall_cb_mux[1][1]_rrnode[67]' to='start_fall_cb_mux[1][1]_rrnode[67]+switch_fall_cb_mux[1][1]_rrnode[67]'
.meas tran sum_leakage_power_mux[0to8]
+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[1][1]_rrnode[67]'
.meas tran sum_energy_per_cycle_mux[0to8]
+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[67]'
******* Normal TYPE loads *******
Xload_inv[0]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[1] gvdd_load 0 inv size=1
Xload_inv[2]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[2] gvdd_load 0 inv size=1
Xload_inv[3]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[3] gvdd_load 0 inv size=1
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to8]
+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[1][1]_rrnode[67]'
.meas tran sum_energy_per_cycle_cb_mux[0to8]
+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[67]'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period'
.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='7*clock_period'
.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period'
.meas tran total_leakage_power_mux[0to8]
+ param='sum_leakage_power_mux[0to8]'
.meas tran total_energy_per_cycle_mux[0to8]
+ param='sum_energy_per_cycle_mux[0to8]'
.meas tran total_leakage_power_cb_mux
+ param='sum_leakage_power_cb_mux[0to8]'
.meas tran total_energy_per_cycle_cb_mux
+ param='sum_energy_per_cycle_cb_mux[0to8]'
.end

675
examples/spice_test_example_1/cb_mux_tb/example_1_cby0_1_cbmux_testbench.sp
View File

@ -1,675 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
Xmux_2level_tapbuf_size4[0] mux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->out sram[0]->out sram[0]->outb sram[1]->outb sram[1]->out sram[2]->out sram[2]->outb sram[3]->outb sram[3]->out gvdd_mux_2level_tapbuf_size4[0] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[0], level=2, select_path_id=3. *****
*****0101*****
Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[0]->out) 0
.nodeset V(sram[0]->outb) vsp
Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[1]->out) 0
.nodeset V(sram[1]->outb) vsp
Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[2]->out) 0
.nodeset V(sram[2]->outb) vsp
Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[3]->out) 0
.nodeset V(sram[3]->outb) vsp
***** Signal mux_2level_tapbuf_size4[0]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[3] density = 0.1906, probability=0.4782.*****
Vmux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->in[3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgvdd_mux_2level_tapbuf_size4[0] gvdd_mux_2level_tapbuf_size4[0] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[0][1]_rrnode[70] trig v(mux_2level_tapbuf_size4[0]->in[3]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[0][1]_rrnode[70] trig v(mux_2level_tapbuf_size4[0]->in[3]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[0][1]_rrnode[70] when v(mux_2level_tapbuf_size4[0]->in[3])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[0][1]_rrnode[70] trig v(mux_2level_tapbuf_size4[0]->in[3]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[0][1]_rrnode[70] when v(mux_2level_tapbuf_size4[0]->in[3])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[0][1]_rrnode[70] trig v(mux_2level_tapbuf_size4[0]->in[3]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from=0 to='clock_period'
.meas tran leakage_cb_mux[0][1]_rrnode[70] param='mux_2level_tapbuf_size4[0]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='clock_period' to='7*clock_period'
.meas tran mux_2level_tapbuf_size4[0]_energy_per_cycle param='mux_2level_tapbuf_size4[0]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[0][1]_rrnode[70] param='mux_2level_tapbuf_size4[0]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[70] param='dynamic_power_cb_mux[0][1]_rrnode[70]*clock_period'
.meas tran dynamic_rise_cb_mux[0][1]_rrnode[70] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_rise_cb_mux[0][1]_rrnode[70]' to='start_rise_cb_mux[0][1]_rrnode[70]+switch_rise_cb_mux[0][1]_rrnode[70]'
.meas tran dynamic_fall_cb_mux[0][1]_rrnode[70] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_fall_cb_mux[0][1]_rrnode[70]' to='start_fall_cb_mux[0][1]_rrnode[70]+switch_fall_cb_mux[0][1]_rrnode[70]'
.meas tran sum_leakage_power_mux[0to0]
+ param='leakage_cb_mux[0][1]_rrnode[70]'
.meas tran sum_energy_per_cycle_mux[0to0]
+ param='energy_per_cycle_cb_mux[0][1]_rrnode[70]'
******* Normal TYPE loads *******
Xload_inv[0]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[1] gvdd_load 0 inv size=1
Xload_inv[2]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[2] gvdd_load 0 inv size=1
Xload_inv[3]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[3] gvdd_load 0 inv size=1
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to0]
+ param='leakage_cb_mux[0][1]_rrnode[70]'
.meas tran sum_energy_per_cycle_cb_mux[0to0]
+ param='energy_per_cycle_cb_mux[0][1]_rrnode[70]'
Xmux_2level_tapbuf_size4[1] mux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->out sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size4[1] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[1], level=2, select_path_id=0. *****
*****1010*****
Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[4]->out) 0
.nodeset V(sram[4]->outb) vsp
Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[5]->out) 0
.nodeset V(sram[5]->outb) vsp
Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[6]->out) 0
.nodeset V(sram[6]->outb) vsp
Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[7]->out) 0
.nodeset V(sram[7]->outb) vsp
***** Signal mux_2level_tapbuf_size4[1]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[1] gvdd_mux_2level_tapbuf_size4[1] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[0][1]_rrnode[16] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[0][1]_rrnode[16] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from=0 to='clock_period'
.meas tran leakage_cb_mux[0][1]_rrnode[16] param='mux_2level_tapbuf_size4[1]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[1]_energy_per_cycle param='mux_2level_tapbuf_size4[1]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[0][1]_rrnode[16] param='mux_2level_tapbuf_size4[1]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[16] param='dynamic_power_cb_mux[0][1]_rrnode[16]*clock_period'
.meas tran dynamic_rise_cb_mux[0][1]_rrnode[16] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_rise_cb_mux[0][1]_rrnode[16]' to='start_rise_cb_mux[0][1]_rrnode[16]+switch_rise_cb_mux[0][1]_rrnode[16]'
.meas tran dynamic_fall_cb_mux[0][1]_rrnode[16] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_fall_cb_mux[0][1]_rrnode[16]' to='start_fall_cb_mux[0][1]_rrnode[16]+switch_fall_cb_mux[0][1]_rrnode[16]'
.meas tran sum_leakage_power_mux[0to1]
+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[0][1]_rrnode[16]'
.meas tran sum_energy_per_cycle_mux[0to1]
+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[0][1]_rrnode[16]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to1]
+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[0][1]_rrnode[16]'
.meas tran sum_energy_per_cycle_cb_mux[0to1]
+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[0][1]_rrnode[16]'
Xmux_2level_tapbuf_size4[2] mux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->outb sram[10]->out sram[11]->out sram[11]->outb gvdd_mux_2level_tapbuf_size4[2] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[2], level=2, select_path_id=0. *****
*****1010*****
Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[8]->out) 0
.nodeset V(sram[8]->outb) vsp
Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[9]->out) 0
.nodeset V(sram[9]->outb) vsp
Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[10]->out) 0
.nodeset V(sram[10]->outb) vsp
Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[11]->out) 0
.nodeset V(sram[11]->outb) vsp
***** Signal mux_2level_tapbuf_size4[2]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[2] gvdd_mux_2level_tapbuf_size4[2] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[0][1]_rrnode[18] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[0][1]_rrnode[18] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from=0 to='clock_period'
.meas tran leakage_cb_mux[0][1]_rrnode[18] param='mux_2level_tapbuf_size4[2]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[2]_energy_per_cycle param='mux_2level_tapbuf_size4[2]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[0][1]_rrnode[18] param='mux_2level_tapbuf_size4[2]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[18] param='dynamic_power_cb_mux[0][1]_rrnode[18]*clock_period'
.meas tran dynamic_rise_cb_mux[0][1]_rrnode[18] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_rise_cb_mux[0][1]_rrnode[18]' to='start_rise_cb_mux[0][1]_rrnode[18]+switch_rise_cb_mux[0][1]_rrnode[18]'
.meas tran dynamic_fall_cb_mux[0][1]_rrnode[18] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_fall_cb_mux[0][1]_rrnode[18]' to='start_fall_cb_mux[0][1]_rrnode[18]+switch_fall_cb_mux[0][1]_rrnode[18]'
.meas tran sum_leakage_power_mux[0to2]
+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[0][1]_rrnode[18]'
.meas tran sum_energy_per_cycle_mux[0to2]
+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[0][1]_rrnode[18]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to2]
+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[0][1]_rrnode[18]'
.meas tran sum_energy_per_cycle_cb_mux[0to2]
+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[0][1]_rrnode[18]'
Xmux_2level_tapbuf_size4[3] mux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->outb sram[14]->out sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size4[3] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[3], level=2, select_path_id=0. *****
*****1010*****
Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[12]->out) 0
.nodeset V(sram[12]->outb) vsp
Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[13]->out) 0
.nodeset V(sram[13]->outb) vsp
Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[14]->out) 0
.nodeset V(sram[14]->outb) vsp
Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[15]->out) 0
.nodeset V(sram[15]->outb) vsp
***** Signal mux_2level_tapbuf_size4[3]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[3] gvdd_mux_2level_tapbuf_size4[3] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[0][1]_rrnode[20] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[0][1]_rrnode[20] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from=0 to='clock_period'
.meas tran leakage_cb_mux[0][1]_rrnode[20] param='mux_2level_tapbuf_size4[3]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[3]_energy_per_cycle param='mux_2level_tapbuf_size4[3]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[0][1]_rrnode[20] param='mux_2level_tapbuf_size4[3]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[20] param='dynamic_power_cb_mux[0][1]_rrnode[20]*clock_period'
.meas tran dynamic_rise_cb_mux[0][1]_rrnode[20] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_rise_cb_mux[0][1]_rrnode[20]' to='start_rise_cb_mux[0][1]_rrnode[20]+switch_rise_cb_mux[0][1]_rrnode[20]'
.meas tran dynamic_fall_cb_mux[0][1]_rrnode[20] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_fall_cb_mux[0][1]_rrnode[20]' to='start_fall_cb_mux[0][1]_rrnode[20]+switch_fall_cb_mux[0][1]_rrnode[20]'
.meas tran sum_leakage_power_mux[0to3]
+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[0][1]_rrnode[20]'
.meas tran sum_energy_per_cycle_mux[0to3]
+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[0][1]_rrnode[20]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to3]
+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[0][1]_rrnode[20]'
.meas tran sum_energy_per_cycle_cb_mux[0to3]
+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[0][1]_rrnode[20]'
Xmux_2level_tapbuf_size4[4] mux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb gvdd_mux_2level_tapbuf_size4[4] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[4], level=2, select_path_id=0. *****
*****1010*****
Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[16]->out) 0
.nodeset V(sram[16]->outb) vsp
Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[17]->out) 0
.nodeset V(sram[17]->outb) vsp
Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[18]->out) 0
.nodeset V(sram[18]->outb) vsp
Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[19]->out) 0
.nodeset V(sram[19]->outb) vsp
***** Signal mux_2level_tapbuf_size4[4]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[4] gvdd_mux_2level_tapbuf_size4[4] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[0][1]_rrnode[22] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[0][1]_rrnode[22] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from=0 to='clock_period'
.meas tran leakage_cb_mux[0][1]_rrnode[22] param='mux_2level_tapbuf_size4[4]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[4]_energy_per_cycle param='mux_2level_tapbuf_size4[4]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[0][1]_rrnode[22] param='mux_2level_tapbuf_size4[4]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[22] param='dynamic_power_cb_mux[0][1]_rrnode[22]*clock_period'
.meas tran dynamic_rise_cb_mux[0][1]_rrnode[22] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_rise_cb_mux[0][1]_rrnode[22]' to='start_rise_cb_mux[0][1]_rrnode[22]+switch_rise_cb_mux[0][1]_rrnode[22]'
.meas tran dynamic_fall_cb_mux[0][1]_rrnode[22] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_fall_cb_mux[0][1]_rrnode[22]' to='start_fall_cb_mux[0][1]_rrnode[22]+switch_fall_cb_mux[0][1]_rrnode[22]'
.meas tran sum_leakage_power_mux[0to4]
+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[0][1]_rrnode[22]'
.meas tran sum_energy_per_cycle_mux[0to4]
+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[0][1]_rrnode[22]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to4]
+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[0][1]_rrnode[22]'
.meas tran sum_energy_per_cycle_cb_mux[0to4]
+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[0][1]_rrnode[22]'
Xmux_2level_tapbuf_size4[5] mux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->out sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->outb sram[22]->out sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size4[5] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[5], level=2, select_path_id=0. *****
*****1010*****
Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[20]->out) 0
.nodeset V(sram[20]->outb) vsp
Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[21]->out) 0
.nodeset V(sram[21]->outb) vsp
Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[22]->out) 0
.nodeset V(sram[22]->outb) vsp
Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[23]->out) 0
.nodeset V(sram[23]->outb) vsp
***** Signal mux_2level_tapbuf_size4[5]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[5] gvdd_mux_2level_tapbuf_size4[5] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[0][1]_rrnode[24] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[0][1]_rrnode[24] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from=0 to='clock_period'
.meas tran leakage_cb_mux[0][1]_rrnode[24] param='mux_2level_tapbuf_size4[5]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[5]_energy_per_cycle param='mux_2level_tapbuf_size4[5]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[0][1]_rrnode[24] param='mux_2level_tapbuf_size4[5]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[24] param='dynamic_power_cb_mux[0][1]_rrnode[24]*clock_period'
.meas tran dynamic_rise_cb_mux[0][1]_rrnode[24] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_rise_cb_mux[0][1]_rrnode[24]' to='start_rise_cb_mux[0][1]_rrnode[24]+switch_rise_cb_mux[0][1]_rrnode[24]'
.meas tran dynamic_fall_cb_mux[0][1]_rrnode[24] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_fall_cb_mux[0][1]_rrnode[24]' to='start_fall_cb_mux[0][1]_rrnode[24]+switch_fall_cb_mux[0][1]_rrnode[24]'
.meas tran sum_leakage_power_mux[0to5]
+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[0][1]_rrnode[24]'
.meas tran sum_energy_per_cycle_mux[0to5]
+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[0][1]_rrnode[24]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to5]
+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[0][1]_rrnode[24]'
.meas tran sum_energy_per_cycle_cb_mux[0to5]
+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[0][1]_rrnode[24]'
Xmux_2level_tapbuf_size4[6] mux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb gvdd_mux_2level_tapbuf_size4[6] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[6], level=2, select_path_id=0. *****
*****1010*****
Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[24]->out) 0
.nodeset V(sram[24]->outb) vsp
Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[25]->out) 0
.nodeset V(sram[25]->outb) vsp
Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[26]->out) 0
.nodeset V(sram[26]->outb) vsp
Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[27]->out) 0
.nodeset V(sram[27]->outb) vsp
***** Signal mux_2level_tapbuf_size4[6]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[6] gvdd_mux_2level_tapbuf_size4[6] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[0][1]_rrnode[26] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[0][1]_rrnode[26] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from=0 to='clock_period'
.meas tran leakage_cb_mux[0][1]_rrnode[26] param='mux_2level_tapbuf_size4[6]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[6]_energy_per_cycle param='mux_2level_tapbuf_size4[6]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[0][1]_rrnode[26] param='mux_2level_tapbuf_size4[6]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[26] param='dynamic_power_cb_mux[0][1]_rrnode[26]*clock_period'
.meas tran dynamic_rise_cb_mux[0][1]_rrnode[26] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_rise_cb_mux[0][1]_rrnode[26]' to='start_rise_cb_mux[0][1]_rrnode[26]+switch_rise_cb_mux[0][1]_rrnode[26]'
.meas tran dynamic_fall_cb_mux[0][1]_rrnode[26] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_fall_cb_mux[0][1]_rrnode[26]' to='start_fall_cb_mux[0][1]_rrnode[26]+switch_fall_cb_mux[0][1]_rrnode[26]'
.meas tran sum_leakage_power_mux[0to6]
+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[0][1]_rrnode[26]'
.meas tran sum_energy_per_cycle_mux[0to6]
+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[0][1]_rrnode[26]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to6]
+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[0][1]_rrnode[26]'
.meas tran sum_energy_per_cycle_cb_mux[0to6]
+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[0][1]_rrnode[26]'
Xmux_2level_tapbuf_size4[7] mux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->out sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->outb sram[30]->out sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size4[7] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[7], level=2, select_path_id=0. *****
*****1010*****
Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[28]->out) 0
.nodeset V(sram[28]->outb) vsp
Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[29]->out) 0
.nodeset V(sram[29]->outb) vsp
Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[30]->out) 0
.nodeset V(sram[30]->outb) vsp
Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[31]->out) 0
.nodeset V(sram[31]->outb) vsp
***** Signal mux_2level_tapbuf_size4[7]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[3] density = 0.1906, probability=0.4782.*****
Vmux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->in[3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgvdd_mux_2level_tapbuf_size4[7] gvdd_mux_2level_tapbuf_size4[7] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[0][1]_rrnode[28] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[0][1]_rrnode[28] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from=0 to='clock_period'
.meas tran leakage_cb_mux[0][1]_rrnode[28] param='mux_2level_tapbuf_size4[7]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='clock_period' to='7*clock_period'
.meas tran mux_2level_tapbuf_size4[7]_energy_per_cycle param='mux_2level_tapbuf_size4[7]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[0][1]_rrnode[28] param='mux_2level_tapbuf_size4[7]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[28] param='dynamic_power_cb_mux[0][1]_rrnode[28]*clock_period'
.meas tran dynamic_rise_cb_mux[0][1]_rrnode[28] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_rise_cb_mux[0][1]_rrnode[28]' to='start_rise_cb_mux[0][1]_rrnode[28]+switch_rise_cb_mux[0][1]_rrnode[28]'
.meas tran dynamic_fall_cb_mux[0][1]_rrnode[28] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_fall_cb_mux[0][1]_rrnode[28]' to='start_fall_cb_mux[0][1]_rrnode[28]+switch_fall_cb_mux[0][1]_rrnode[28]'
.meas tran sum_leakage_power_mux[0to7]
+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[0][1]_rrnode[28]'
.meas tran sum_energy_per_cycle_mux[0to7]
+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[0][1]_rrnode[28]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to7]
+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[0][1]_rrnode[28]'
.meas tran sum_energy_per_cycle_cb_mux[0to7]
+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[0][1]_rrnode[28]'
Xmux_2level_tapbuf_size4[8] mux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->outb sram[34]->out sram[35]->out sram[35]->outb gvdd_mux_2level_tapbuf_size4[8] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[8], level=2, select_path_id=0. *****
*****1010*****
Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[32]->out) 0
.nodeset V(sram[32]->outb) vsp
Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[33]->out) 0
.nodeset V(sram[33]->outb) vsp
Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[34]->out) 0
.nodeset V(sram[34]->outb) vsp
Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[35]->out) 0
.nodeset V(sram[35]->outb) vsp
***** Signal mux_2level_tapbuf_size4[8]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[8] gvdd_mux_2level_tapbuf_size4[8] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[0][1]_rrnode[30] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[0][1]_rrnode[30] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from=0 to='clock_period'
.meas tran leakage_cb_mux[0][1]_rrnode[30] param='mux_2level_tapbuf_size4[8]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[8]_energy_per_cycle param='mux_2level_tapbuf_size4[8]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[0][1]_rrnode[30] param='mux_2level_tapbuf_size4[8]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[30] param='dynamic_power_cb_mux[0][1]_rrnode[30]*clock_period'
.meas tran dynamic_rise_cb_mux[0][1]_rrnode[30] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_rise_cb_mux[0][1]_rrnode[30]' to='start_rise_cb_mux[0][1]_rrnode[30]+switch_rise_cb_mux[0][1]_rrnode[30]'
.meas tran dynamic_fall_cb_mux[0][1]_rrnode[30] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_fall_cb_mux[0][1]_rrnode[30]' to='start_fall_cb_mux[0][1]_rrnode[30]+switch_fall_cb_mux[0][1]_rrnode[30]'
.meas tran sum_leakage_power_mux[0to8]
+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[0][1]_rrnode[30]'
.meas tran sum_energy_per_cycle_mux[0to8]
+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[0][1]_rrnode[30]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to8]
+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[0][1]_rrnode[30]'
.meas tran sum_energy_per_cycle_cb_mux[0to8]
+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[0][1]_rrnode[30]'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period'
.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='7*clock_period'
.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period'
.meas tran total_leakage_power_mux[0to8]
+ param='sum_leakage_power_mux[0to8]'
.meas tran total_energy_per_cycle_mux[0to8]
+ param='sum_energy_per_cycle_mux[0to8]'
.meas tran total_leakage_power_cb_mux
+ param='sum_leakage_power_cb_mux[0to8]'
.meas tran total_energy_per_cycle_cb_mux
+ param='sum_energy_per_cycle_cb_mux[0to8]'
.end

671
examples/spice_test_example_1/cb_mux_tb/example_1_cby1_1_cbmux_testbench.sp
View File

@ -1,671 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
Xmux_2level_tapbuf_size4[0] mux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->outb sram[2]->out sram[3]->out sram[3]->outb gvdd_mux_2level_tapbuf_size4[0] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[0], level=2, select_path_id=0. *****
*****1010*****
Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[0]->out) 0
.nodeset V(sram[0]->outb) vsp
Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[1]->out) 0
.nodeset V(sram[1]->outb) vsp
Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[2]->out) 0
.nodeset V(sram[2]->outb) vsp
Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[3]->out) 0
.nodeset V(sram[3]->outb) vsp
***** Signal mux_2level_tapbuf_size4[0]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[0]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[0] gvdd_mux_2level_tapbuf_size4[0] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[121] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[121] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[121] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[121] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[121] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[121] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[121] param='mux_2level_tapbuf_size4[0]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[0]_energy_per_cycle param='mux_2level_tapbuf_size4[0]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[121] param='mux_2level_tapbuf_size4[0]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[121] param='dynamic_power_cb_mux[1][1]_rrnode[121]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[121] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_rise_cb_mux[1][1]_rrnode[121]' to='start_rise_cb_mux[1][1]_rrnode[121]+switch_rise_cb_mux[1][1]_rrnode[121]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[121] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_fall_cb_mux[1][1]_rrnode[121]' to='start_fall_cb_mux[1][1]_rrnode[121]+switch_fall_cb_mux[1][1]_rrnode[121]'
.meas tran sum_leakage_power_mux[0to0]
+ param='leakage_cb_mux[1][1]_rrnode[121]'
.meas tran sum_energy_per_cycle_mux[0to0]
+ param='energy_per_cycle_cb_mux[1][1]_rrnode[121]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to0]
+ param='leakage_cb_mux[1][1]_rrnode[121]'
.meas tran sum_energy_per_cycle_cb_mux[0to0]
+ param='energy_per_cycle_cb_mux[1][1]_rrnode[121]'
Xmux_2level_tapbuf_size4[1] mux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->out sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size4[1] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[1], level=2, select_path_id=0. *****
*****1010*****
Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[4]->out) 0
.nodeset V(sram[4]->outb) vsp
Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[5]->out) 0
.nodeset V(sram[5]->outb) vsp
Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[6]->out) 0
.nodeset V(sram[6]->outb) vsp
Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[7]->out) 0
.nodeset V(sram[7]->outb) vsp
***** Signal mux_2level_tapbuf_size4[1]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[1]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[1] gvdd_mux_2level_tapbuf_size4[1] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[123] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[123] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[123] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[123] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[123] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[123] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[123] param='mux_2level_tapbuf_size4[1]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[1]_energy_per_cycle param='mux_2level_tapbuf_size4[1]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[123] param='mux_2level_tapbuf_size4[1]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[123] param='dynamic_power_cb_mux[1][1]_rrnode[123]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[123] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_rise_cb_mux[1][1]_rrnode[123]' to='start_rise_cb_mux[1][1]_rrnode[123]+switch_rise_cb_mux[1][1]_rrnode[123]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[123] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_fall_cb_mux[1][1]_rrnode[123]' to='start_fall_cb_mux[1][1]_rrnode[123]+switch_fall_cb_mux[1][1]_rrnode[123]'
.meas tran sum_leakage_power_mux[0to1]
+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[1][1]_rrnode[123]'
.meas tran sum_energy_per_cycle_mux[0to1]
+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[123]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to1]
+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[1][1]_rrnode[123]'
.meas tran sum_energy_per_cycle_cb_mux[0to1]
+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[123]'
Xmux_2level_tapbuf_size4[2] mux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->outb sram[10]->out sram[11]->out sram[11]->outb gvdd_mux_2level_tapbuf_size4[2] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[2], level=2, select_path_id=0. *****
*****1010*****
Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[8]->out) 0
.nodeset V(sram[8]->outb) vsp
Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[9]->out) 0
.nodeset V(sram[9]->outb) vsp
Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[10]->out) 0
.nodeset V(sram[10]->outb) vsp
Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[11]->out) 0
.nodeset V(sram[11]->outb) vsp
***** Signal mux_2level_tapbuf_size4[2]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[2]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[2] gvdd_mux_2level_tapbuf_size4[2] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[125] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[125] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[125] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[125] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[125] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[125] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[125] param='mux_2level_tapbuf_size4[2]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[2]_energy_per_cycle param='mux_2level_tapbuf_size4[2]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[125] param='mux_2level_tapbuf_size4[2]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[125] param='dynamic_power_cb_mux[1][1]_rrnode[125]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[125] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_rise_cb_mux[1][1]_rrnode[125]' to='start_rise_cb_mux[1][1]_rrnode[125]+switch_rise_cb_mux[1][1]_rrnode[125]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[125] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_fall_cb_mux[1][1]_rrnode[125]' to='start_fall_cb_mux[1][1]_rrnode[125]+switch_fall_cb_mux[1][1]_rrnode[125]'
.meas tran sum_leakage_power_mux[0to2]
+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[1][1]_rrnode[125]'
.meas tran sum_energy_per_cycle_mux[0to2]
+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[125]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to2]
+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[1][1]_rrnode[125]'
.meas tran sum_energy_per_cycle_cb_mux[0to2]
+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[125]'
Xmux_2level_tapbuf_size4[3] mux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->outb sram[14]->out sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size4[3] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[3], level=2, select_path_id=0. *****
*****1010*****
Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[12]->out) 0
.nodeset V(sram[12]->outb) vsp
Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[13]->out) 0
.nodeset V(sram[13]->outb) vsp
Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[14]->out) 0
.nodeset V(sram[14]->outb) vsp
Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[15]->out) 0
.nodeset V(sram[15]->outb) vsp
***** Signal mux_2level_tapbuf_size4[3]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[3]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[3] gvdd_mux_2level_tapbuf_size4[3] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[127] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[127] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[127] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[127] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[127] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[127] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[127] param='mux_2level_tapbuf_size4[3]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[3]_energy_per_cycle param='mux_2level_tapbuf_size4[3]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[127] param='mux_2level_tapbuf_size4[3]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[127] param='dynamic_power_cb_mux[1][1]_rrnode[127]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[127] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_rise_cb_mux[1][1]_rrnode[127]' to='start_rise_cb_mux[1][1]_rrnode[127]+switch_rise_cb_mux[1][1]_rrnode[127]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[127] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_fall_cb_mux[1][1]_rrnode[127]' to='start_fall_cb_mux[1][1]_rrnode[127]+switch_fall_cb_mux[1][1]_rrnode[127]'
.meas tran sum_leakage_power_mux[0to3]
+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[1][1]_rrnode[127]'
.meas tran sum_energy_per_cycle_mux[0to3]
+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[127]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to3]
+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[1][1]_rrnode[127]'
.meas tran sum_energy_per_cycle_cb_mux[0to3]
+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[127]'
Xmux_2level_tapbuf_size4[4] mux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb gvdd_mux_2level_tapbuf_size4[4] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[4], level=2, select_path_id=0. *****
*****1010*****
Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[16]->out) 0
.nodeset V(sram[16]->outb) vsp
Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[17]->out) 0
.nodeset V(sram[17]->outb) vsp
Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[18]->out) 0
.nodeset V(sram[18]->outb) vsp
Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[19]->out) 0
.nodeset V(sram[19]->outb) vsp
***** Signal mux_2level_tapbuf_size4[4]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[4]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[4] gvdd_mux_2level_tapbuf_size4[4] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[129] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[129] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[129] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[129] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[129] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[129] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[129] param='mux_2level_tapbuf_size4[4]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[4]_energy_per_cycle param='mux_2level_tapbuf_size4[4]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[129] param='mux_2level_tapbuf_size4[4]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[129] param='dynamic_power_cb_mux[1][1]_rrnode[129]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[129] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_rise_cb_mux[1][1]_rrnode[129]' to='start_rise_cb_mux[1][1]_rrnode[129]+switch_rise_cb_mux[1][1]_rrnode[129]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[129] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_fall_cb_mux[1][1]_rrnode[129]' to='start_fall_cb_mux[1][1]_rrnode[129]+switch_fall_cb_mux[1][1]_rrnode[129]'
.meas tran sum_leakage_power_mux[0to4]
+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[1][1]_rrnode[129]'
.meas tran sum_energy_per_cycle_mux[0to4]
+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[129]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to4]
+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[1][1]_rrnode[129]'
.meas tran sum_energy_per_cycle_cb_mux[0to4]
+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[129]'
Xmux_2level_tapbuf_size4[5] mux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->out sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->outb sram[22]->out sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size4[5] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[5], level=2, select_path_id=0. *****
*****1010*****
Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[20]->out) 0
.nodeset V(sram[20]->outb) vsp
Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[21]->out) 0
.nodeset V(sram[21]->outb) vsp
Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[22]->out) 0
.nodeset V(sram[22]->outb) vsp
Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[23]->out) 0
.nodeset V(sram[23]->outb) vsp
***** Signal mux_2level_tapbuf_size4[5]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[5]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[5] gvdd_mux_2level_tapbuf_size4[5] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[131] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[131] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[131] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[131] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[131] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[131] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[131] param='mux_2level_tapbuf_size4[5]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[5]_energy_per_cycle param='mux_2level_tapbuf_size4[5]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[131] param='mux_2level_tapbuf_size4[5]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[131] param='dynamic_power_cb_mux[1][1]_rrnode[131]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[131] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_rise_cb_mux[1][1]_rrnode[131]' to='start_rise_cb_mux[1][1]_rrnode[131]+switch_rise_cb_mux[1][1]_rrnode[131]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[131] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_fall_cb_mux[1][1]_rrnode[131]' to='start_fall_cb_mux[1][1]_rrnode[131]+switch_fall_cb_mux[1][1]_rrnode[131]'
.meas tran sum_leakage_power_mux[0to5]
+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[1][1]_rrnode[131]'
.meas tran sum_energy_per_cycle_mux[0to5]
+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[131]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to5]
+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[1][1]_rrnode[131]'
.meas tran sum_energy_per_cycle_cb_mux[0to5]
+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[131]'
Xmux_2level_tapbuf_size4[6] mux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb gvdd_mux_2level_tapbuf_size4[6] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[6], level=2, select_path_id=0. *****
*****1010*****
Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[24]->out) 0
.nodeset V(sram[24]->outb) vsp
Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[25]->out) 0
.nodeset V(sram[25]->outb) vsp
Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[26]->out) 0
.nodeset V(sram[26]->outb) vsp
Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[27]->out) 0
.nodeset V(sram[27]->outb) vsp
***** Signal mux_2level_tapbuf_size4[6]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[6]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[6] gvdd_mux_2level_tapbuf_size4[6] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[133] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[133] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[133] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[133] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[133] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[133] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[133] param='mux_2level_tapbuf_size4[6]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[6]_energy_per_cycle param='mux_2level_tapbuf_size4[6]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[133] param='mux_2level_tapbuf_size4[6]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[133] param='dynamic_power_cb_mux[1][1]_rrnode[133]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[133] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_rise_cb_mux[1][1]_rrnode[133]' to='start_rise_cb_mux[1][1]_rrnode[133]+switch_rise_cb_mux[1][1]_rrnode[133]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[133] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_fall_cb_mux[1][1]_rrnode[133]' to='start_fall_cb_mux[1][1]_rrnode[133]+switch_fall_cb_mux[1][1]_rrnode[133]'
.meas tran sum_leakage_power_mux[0to6]
+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[1][1]_rrnode[133]'
.meas tran sum_energy_per_cycle_mux[0to6]
+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[133]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to6]
+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[1][1]_rrnode[133]'
.meas tran sum_energy_per_cycle_cb_mux[0to6]
+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[133]'
Xmux_2level_tapbuf_size4[7] mux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->out sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->outb sram[30]->out sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size4[7] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[7], level=2, select_path_id=0. *****
*****1010*****
Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[28]->out) 0
.nodeset V(sram[28]->outb) vsp
Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[29]->out) 0
.nodeset V(sram[29]->outb) vsp
Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[30]->out) 0
.nodeset V(sram[30]->outb) vsp
Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[31]->out) 0
.nodeset V(sram[31]->outb) vsp
***** Signal mux_2level_tapbuf_size4[7]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[7]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[7] gvdd_mux_2level_tapbuf_size4[7] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[135] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[135] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[135] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[135] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[135] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[135] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[135] param='mux_2level_tapbuf_size4[7]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[7]_energy_per_cycle param='mux_2level_tapbuf_size4[7]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[135] param='mux_2level_tapbuf_size4[7]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[135] param='dynamic_power_cb_mux[1][1]_rrnode[135]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[135] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_rise_cb_mux[1][1]_rrnode[135]' to='start_rise_cb_mux[1][1]_rrnode[135]+switch_rise_cb_mux[1][1]_rrnode[135]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[135] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_fall_cb_mux[1][1]_rrnode[135]' to='start_fall_cb_mux[1][1]_rrnode[135]+switch_fall_cb_mux[1][1]_rrnode[135]'
.meas tran sum_leakage_power_mux[0to7]
+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[1][1]_rrnode[135]'
.meas tran sum_energy_per_cycle_mux[0to7]
+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[135]'
******* IO_TYPE loads *******
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to7]
+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[1][1]_rrnode[135]'
.meas tran sum_energy_per_cycle_cb_mux[0to7]
+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[135]'
Xmux_2level_tapbuf_size4[8] mux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->outb sram[34]->out sram[35]->out sram[35]->outb gvdd_mux_2level_tapbuf_size4[8] 0 mux_2level_tapbuf_size4
***** SRAM bits for MUX[8], level=2, select_path_id=0. *****
*****1010*****
Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[32]->out) 0
.nodeset V(sram[32]->outb) vsp
Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[33]->out) 0
.nodeset V(sram[33]->outb) vsp
Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[34]->out) 0
.nodeset V(sram[34]->outb) vsp
Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[35]->out) 0
.nodeset V(sram[35]->outb) vsp
***** Signal mux_2level_tapbuf_size4[8]->in[0] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[0] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[1] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[1] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[2] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[2] 0
+ 0
***** Signal mux_2level_tapbuf_size4[8]->in[3] density = 0, probability=0.*****
Vmux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->in[3] 0
+ 0
Vgvdd_mux_2level_tapbuf_size4[8] gvdd_mux_2level_tapbuf_size4[8] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_cb_mux[1][1]_rrnode[68] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_cb_mux[1][1]_rrnode[68] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_cb_mux[1][1]_rrnode[68] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_cb_mux[1][1]_rrnode[68] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_cb_mux[1][1]_rrnode[68] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_cb_mux[1][1]_rrnode[68] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_tapbuf_size4[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from=0 to='clock_period'
.meas tran leakage_cb_mux[1][1]_rrnode[68] param='mux_2level_tapbuf_size4[8]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_tapbuf_size4[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='clock_period' to='2*clock_period'
.meas tran mux_2level_tapbuf_size4[8]_energy_per_cycle param='mux_2level_tapbuf_size4[8]_dynamic_power*clock_period'
.meas tran dynamic_power_cb_mux[1][1]_rrnode[68] param='mux_2level_tapbuf_size4[8]_dynamic_power'
.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[68] param='dynamic_power_cb_mux[1][1]_rrnode[68]*clock_period'
.meas tran dynamic_rise_cb_mux[1][1]_rrnode[68] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_rise_cb_mux[1][1]_rrnode[68]' to='start_rise_cb_mux[1][1]_rrnode[68]+switch_rise_cb_mux[1][1]_rrnode[68]'
.meas tran dynamic_fall_cb_mux[1][1]_rrnode[68] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_fall_cb_mux[1][1]_rrnode[68]' to='start_fall_cb_mux[1][1]_rrnode[68]+switch_fall_cb_mux[1][1]_rrnode[68]'
.meas tran sum_leakage_power_mux[0to8]
+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[1][1]_rrnode[68]'
.meas tran sum_energy_per_cycle_mux[0to8]
+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[68]'
******* Normal TYPE loads *******
Xload_inv[0]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[1] gvdd_load 0 inv size=1
Xload_inv[2]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[2] gvdd_load 0 inv size=1
Xload_inv[3]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[3] gvdd_load 0 inv size=1
******* END loads *******
.meas tran sum_leakage_power_cb_mux[0to8]
+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[1][1]_rrnode[68]'
.meas tran sum_energy_per_cycle_cb_mux[0to8]
+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[68]'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
***** 2 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '2*clock_period'
***** Generic Measurements for Circuit Parameters *****
.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period'
.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='2*clock_period'
.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period'
.meas tran total_leakage_power_mux[0to8]
+ param='sum_leakage_power_mux[0to8]'
.meas tran total_energy_per_cycle_mux[0to8]
+ param='sum_energy_per_cycle_mux[0to8]'
.meas tran total_leakage_power_cb_mux
+ param='sum_leakage_power_cb_mux[0to8]'
.meas tran total_energy_per_cycle_cb_mux
+ param='sum_energy_per_cycle_cb_mux[0to8]'
.end

268
examples/spice_test_example_1/cb_tb/example_1_cbx1_0_cb_testbench.sp
View File

@ -1,268 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_sram_cbs
****** Include subckt netlists: Connection Box X-channel [1][0] *****
.include './spice_test_example_1/subckt/cbx_1_0.sp'
***** Call defined Connection Box[1][0] *****
Xcbx[1][0]
+ chanx[1][0]_midout[0]
+ chanx[1][0]_midout[1]
+ chanx[1][0]_midout[2]
+ chanx[1][0]_midout[3]
+ chanx[1][0]_midout[4]
+ chanx[1][0]_midout[5]
+ chanx[1][0]_midout[6]
+ chanx[1][0]_midout[7]
+ chanx[1][0]_midout[8]
+ chanx[1][0]_midout[9]
+ chanx[1][0]_midout[10]
+ chanx[1][0]_midout[11]
+ chanx[1][0]_midout[12]
+ chanx[1][0]_midout[13]
+ chanx[1][0]_midout[14]
+ chanx[1][0]_midout[15]
+ chanx[1][0]_midout[16]
+ chanx[1][0]_midout[17]
+ chanx[1][0]_midout[18]
+ chanx[1][0]_midout[19]
+ chanx[1][0]_midout[20]
+ chanx[1][0]_midout[21]
+ chanx[1][0]_midout[22]
+ chanx[1][0]_midout[23]
+ chanx[1][0]_midout[24]
+ chanx[1][0]_midout[25]
+ chanx[1][0]_midout[26]
+ chanx[1][0]_midout[27]
+ chanx[1][0]_midout[28]
+ chanx[1][0]_midout[29]
+ grid[1][1]_pin[0][2][2]
+ grid[1][0]_pin[0][0][0]
+ grid[1][0]_pin[0][0][2]
+ grid[1][0]_pin[0][0][4]
+ grid[1][0]_pin[0][0][6]
+ grid[1][0]_pin[0][0][8]
+ grid[1][0]_pin[0][0][10]
+ grid[1][0]_pin[0][0][12]
+ grid[1][0]_pin[0][0][14]
+ gvdd_cbx[1][0] 0 cbx[1][0]
***** Signal chanx[1][0]_midout[0] density = 0, probability=0.*****
Vchanx[1][0]_midout[0] chanx[1][0]_midout[0] 0
+ 0
***** Signal chanx[1][0]_midout[1] density = 0, probability=0.*****
Vchanx[1][0]_midout[1] chanx[1][0]_midout[1] 0
+ 0
***** Signal chanx[1][0]_midout[2] density = 0, probability=0.*****
Vchanx[1][0]_midout[2] chanx[1][0]_midout[2] 0
+ 0
***** Signal chanx[1][0]_midout[3] density = 0, probability=0.*****
Vchanx[1][0]_midout[3] chanx[1][0]_midout[3] 0
+ 0
***** Signal chanx[1][0]_midout[4] density = 0, probability=0.*****
Vchanx[1][0]_midout[4] chanx[1][0]_midout[4] 0
+ 0
***** Signal chanx[1][0]_midout[5] density = 0, probability=0.*****
Vchanx[1][0]_midout[5] chanx[1][0]_midout[5] 0
+ 0
***** Signal chanx[1][0]_midout[6] density = 0, probability=0.*****
Vchanx[1][0]_midout[6] chanx[1][0]_midout[6] 0
+ 0
***** Signal chanx[1][0]_midout[7] density = 0, probability=0.*****
Vchanx[1][0]_midout[7] chanx[1][0]_midout[7] 0
+ 0
***** Signal chanx[1][0]_midout[8] density = 0, probability=0.*****
Vchanx[1][0]_midout[8] chanx[1][0]_midout[8] 0
+ 0
***** Signal chanx[1][0]_midout[9] density = 0, probability=0.*****
Vchanx[1][0]_midout[9] chanx[1][0]_midout[9] 0
+ 0
***** Signal chanx[1][0]_midout[10] density = 0, probability=0.*****
Vchanx[1][0]_midout[10] chanx[1][0]_midout[10] 0
+ 0
***** Signal chanx[1][0]_midout[11] density = 0, probability=0.*****
Vchanx[1][0]_midout[11] chanx[1][0]_midout[11] 0
+ 0
***** Signal chanx[1][0]_midout[12] density = 0, probability=0.*****
Vchanx[1][0]_midout[12] chanx[1][0]_midout[12] 0
+ 0
***** Signal chanx[1][0]_midout[13] density = 0, probability=0.*****
Vchanx[1][0]_midout[13] chanx[1][0]_midout[13] 0
+ 0
***** Signal chanx[1][0]_midout[14] density = 0, probability=0.*****
Vchanx[1][0]_midout[14] chanx[1][0]_midout[14] 0
+ 0
***** Signal chanx[1][0]_midout[15] density = 0, probability=0.*****
Vchanx[1][0]_midout[15] chanx[1][0]_midout[15] 0
+ 0
***** Signal chanx[1][0]_midout[16] density = 0, probability=0.*****
Vchanx[1][0]_midout[16] chanx[1][0]_midout[16] 0
+ 0
***** Signal chanx[1][0]_midout[17] density = 0, probability=0.*****
Vchanx[1][0]_midout[17] chanx[1][0]_midout[17] 0
+ 0
***** Signal chanx[1][0]_midout[18] density = 0, probability=0.*****
Vchanx[1][0]_midout[18] chanx[1][0]_midout[18] 0
+ 0
***** Signal chanx[1][0]_midout[19] density = 0, probability=0.*****
Vchanx[1][0]_midout[19] chanx[1][0]_midout[19] 0
+ 0
***** Signal chanx[1][0]_midout[20] density = 0, probability=0.*****
Vchanx[1][0]_midout[20] chanx[1][0]_midout[20] 0
+ 0
***** Signal chanx[1][0]_midout[21] density = 0, probability=0.*****
Vchanx[1][0]_midout[21] chanx[1][0]_midout[21] 0
+ 0
***** Signal chanx[1][0]_midout[22] density = 0, probability=0.*****
Vchanx[1][0]_midout[22] chanx[1][0]_midout[22] 0
+ 0
***** Signal chanx[1][0]_midout[23] density = 0, probability=0.*****
Vchanx[1][0]_midout[23] chanx[1][0]_midout[23] 0
+ 0
***** Signal chanx[1][0]_midout[24] density = 0, probability=0.*****
Vchanx[1][0]_midout[24] chanx[1][0]_midout[24] 0
+ 0
***** Signal chanx[1][0]_midout[25] density = 0, probability=0.*****
Vchanx[1][0]_midout[25] chanx[1][0]_midout[25] 0
+ 0
***** Signal chanx[1][0]_midout[26] density = 0, probability=0.*****
Vchanx[1][0]_midout[26] chanx[1][0]_midout[26] 0
+ 0
***** Signal chanx[1][0]_midout[27] density = 0, probability=0.*****
Vchanx[1][0]_midout[27] chanx[1][0]_midout[27] 0
+ 0
***** Signal chanx[1][0]_midout[28] density = 0, probability=0.*****
Vchanx[1][0]_midout[28] chanx[1][0]_midout[28] 0
+ 0
***** Signal chanx[1][0]_midout[29] density = 0, probability=0.*****
Vchanx[1][0]_midout[29] chanx[1][0]_midout[29] 0
+ 0
******* Normal TYPE loads *******
Xload_inv[0]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[1] gvdd_load 0 inv size=1
Xload_inv[2]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[2] gvdd_load 0 inv size=1
Xload_inv[3]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[3] gvdd_load 0 inv size=1
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
***** Voltage supplies *****
***** Voltage supplies *****
Vgvdd_cb[1][0] gvdd_cbx[1][0] 0 vsp
Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp
***** 2 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '2*clock_period'
***** Generic Measurements for Circuit Parameters *****
***** Measurements *****
***** Leakage Power Measurement *****
.meas tran leakage_power_cb avg p(Vgvdd_cb[1][0]) from=0 to='clock_period'
.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period'
***** Dynamic Power Measurement *****
.meas tran dynamic_power_cb avg p(Vgvdd_cb[1][0]) from='clock_period' to='2*clock_period'
.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period'
.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='2*clock_period'
.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
.end

280
examples/spice_test_example_1/cb_tb/example_1_cbx1_1_cb_testbench.sp
View File

@ -1,280 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_sram_cbs
****** Include subckt netlists: Connection Box X-channel [1][1] *****
.include './spice_test_example_1/subckt/cbx_1_1.sp'
***** Call defined Connection Box[1][1] *****
Xcbx[1][1]
+ chanx[1][1]_midout[0]
+ chanx[1][1]_midout[1]
+ chanx[1][1]_midout[2]
+ chanx[1][1]_midout[3]
+ chanx[1][1]_midout[4]
+ chanx[1][1]_midout[5]
+ chanx[1][1]_midout[6]
+ chanx[1][1]_midout[7]
+ chanx[1][1]_midout[8]
+ chanx[1][1]_midout[9]
+ chanx[1][1]_midout[10]
+ chanx[1][1]_midout[11]
+ chanx[1][1]_midout[12]
+ chanx[1][1]_midout[13]
+ chanx[1][1]_midout[14]
+ chanx[1][1]_midout[15]
+ chanx[1][1]_midout[16]
+ chanx[1][1]_midout[17]
+ chanx[1][1]_midout[18]
+ chanx[1][1]_midout[19]
+ chanx[1][1]_midout[20]
+ chanx[1][1]_midout[21]
+ chanx[1][1]_midout[22]
+ chanx[1][1]_midout[23]
+ chanx[1][1]_midout[24]
+ chanx[1][1]_midout[25]
+ chanx[1][1]_midout[26]
+ chanx[1][1]_midout[27]
+ chanx[1][1]_midout[28]
+ chanx[1][1]_midout[29]
+ grid[1][2]_pin[0][2][0]
+ grid[1][2]_pin[0][2][2]
+ grid[1][2]_pin[0][2][4]
+ grid[1][2]_pin[0][2][6]
+ grid[1][2]_pin[0][2][8]
+ grid[1][2]_pin[0][2][10]
+ grid[1][2]_pin[0][2][12]
+ grid[1][2]_pin[0][2][14]
+ grid[1][1]_pin[0][0][0]
+ gvdd_cbx[1][1] 0 cbx[1][1]
***** Signal chanx[1][1]_midout[0] density = 0.1906, probability=0.5218.*****
Vchanx[1][1]_midout[0] chanx[1][1]_midout[0] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal chanx[1][1]_midout[1] density = 0.1906, probability=0.4782.*****
Vchanx[1][1]_midout[1] chanx[1][1]_midout[1] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal chanx[1][1]_midout[2] density = 0.1906, probability=0.5218.*****
Vchanx[1][1]_midout[2] chanx[1][1]_midout[2] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal chanx[1][1]_midout[3] density = 0.1906, probability=0.5218.*****
Vchanx[1][1]_midout[3] chanx[1][1]_midout[3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal chanx[1][1]_midout[4] density = 0, probability=0.*****
Vchanx[1][1]_midout[4] chanx[1][1]_midout[4] 0
+ 0
***** Signal chanx[1][1]_midout[5] density = 0, probability=0.*****
Vchanx[1][1]_midout[5] chanx[1][1]_midout[5] 0
+ 0
***** Signal chanx[1][1]_midout[6] density = 0, probability=0.*****
Vchanx[1][1]_midout[6] chanx[1][1]_midout[6] 0
+ 0
***** Signal chanx[1][1]_midout[7] density = 0, probability=0.*****
Vchanx[1][1]_midout[7] chanx[1][1]_midout[7] 0
+ 0
***** Signal chanx[1][1]_midout[8] density = 0, probability=0.*****
Vchanx[1][1]_midout[8] chanx[1][1]_midout[8] 0
+ 0
***** Signal chanx[1][1]_midout[9] density = 0, probability=0.*****
Vchanx[1][1]_midout[9] chanx[1][1]_midout[9] 0
+ 0
***** Signal chanx[1][1]_midout[10] density = 0, probability=0.*****
Vchanx[1][1]_midout[10] chanx[1][1]_midout[10] 0
+ 0
***** Signal chanx[1][1]_midout[11] density = 0, probability=0.*****
Vchanx[1][1]_midout[11] chanx[1][1]_midout[11] 0
+ 0
***** Signal chanx[1][1]_midout[12] density = 0, probability=0.*****
Vchanx[1][1]_midout[12] chanx[1][1]_midout[12] 0
+ 0
***** Signal chanx[1][1]_midout[13] density = 0, probability=0.*****
Vchanx[1][1]_midout[13] chanx[1][1]_midout[13] 0
+ 0
***** Signal chanx[1][1]_midout[14] density = 0, probability=0.*****
Vchanx[1][1]_midout[14] chanx[1][1]_midout[14] 0
+ 0
***** Signal chanx[1][1]_midout[15] density = 0, probability=0.*****
Vchanx[1][1]_midout[15] chanx[1][1]_midout[15] 0
+ 0
***** Signal chanx[1][1]_midout[16] density = 0, probability=0.*****
Vchanx[1][1]_midout[16] chanx[1][1]_midout[16] 0
+ 0
***** Signal chanx[1][1]_midout[17] density = 0, probability=0.*****
Vchanx[1][1]_midout[17] chanx[1][1]_midout[17] 0
+ 0
***** Signal chanx[1][1]_midout[18] density = 0, probability=0.*****
Vchanx[1][1]_midout[18] chanx[1][1]_midout[18] 0
+ 0
***** Signal chanx[1][1]_midout[19] density = 0, probability=0.*****
Vchanx[1][1]_midout[19] chanx[1][1]_midout[19] 0
+ 0
***** Signal chanx[1][1]_midout[20] density = 0, probability=0.*****
Vchanx[1][1]_midout[20] chanx[1][1]_midout[20] 0
+ 0
***** Signal chanx[1][1]_midout[21] density = 0, probability=0.*****
Vchanx[1][1]_midout[21] chanx[1][1]_midout[21] 0
+ 0
***** Signal chanx[1][1]_midout[22] density = 0, probability=0.*****
Vchanx[1][1]_midout[22] chanx[1][1]_midout[22] 0
+ 0
***** Signal chanx[1][1]_midout[23] density = 0, probability=0.*****
Vchanx[1][1]_midout[23] chanx[1][1]_midout[23] 0
+ 0
***** Signal chanx[1][1]_midout[24] density = 0, probability=0.*****
Vchanx[1][1]_midout[24] chanx[1][1]_midout[24] 0
+ 0
***** Signal chanx[1][1]_midout[25] density = 0, probability=0.*****
Vchanx[1][1]_midout[25] chanx[1][1]_midout[25] 0
+ 0
***** Signal chanx[1][1]_midout[26] density = 0, probability=0.*****
Vchanx[1][1]_midout[26] chanx[1][1]_midout[26] 0
+ 0
***** Signal chanx[1][1]_midout[27] density = 0, probability=0.*****
Vchanx[1][1]_midout[27] chanx[1][1]_midout[27] 0
+ 0
***** Signal chanx[1][1]_midout[28] density = 0.1906, probability=0.4782.*****
Vchanx[1][1]_midout[28] chanx[1][1]_midout[28] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal chanx[1][1]_midout[29] density = 0.1906, probability=0.4782.*****
Vchanx[1][1]_midout[29] chanx[1][1]_midout[29] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* Normal TYPE loads *******
Xload_inv[0]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[1] gvdd_load 0 inv size=1
Xload_inv[2]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[2] gvdd_load 0 inv size=1
Xload_inv[3]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[3] gvdd_load 0 inv size=1
******* END loads *******
***** Voltage supplies *****
***** Voltage supplies *****
Vgvdd_cb[1][1] gvdd_cbx[1][1] 0 vsp
Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
***** Measurements *****
***** Leakage Power Measurement *****
.meas tran leakage_power_cb avg p(Vgvdd_cb[1][1]) from=0 to='clock_period'
.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period'
***** Dynamic Power Measurement *****
.meas tran dynamic_power_cb avg p(Vgvdd_cb[1][1]) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period'
.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
.end

270
examples/spice_test_example_1/cb_tb/example_1_cby0_1_cb_testbench.sp
View File

@ -1,270 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_sram_cbs
****** Include subckt netlists: Connection Box Y-channel [0][1] *****
.include './spice_test_example_1/subckt/cby_0_1.sp'
***** Call defined Connection Box[0][1] *****
Xcby[0][1]
+ chany[0][1]_midout[0]
+ chany[0][1]_midout[1]
+ chany[0][1]_midout[2]
+ chany[0][1]_midout[3]
+ chany[0][1]_midout[4]
+ chany[0][1]_midout[5]
+ chany[0][1]_midout[6]
+ chany[0][1]_midout[7]
+ chany[0][1]_midout[8]
+ chany[0][1]_midout[9]
+ chany[0][1]_midout[10]
+ chany[0][1]_midout[11]
+ chany[0][1]_midout[12]
+ chany[0][1]_midout[13]
+ chany[0][1]_midout[14]
+ chany[0][1]_midout[15]
+ chany[0][1]_midout[16]
+ chany[0][1]_midout[17]
+ chany[0][1]_midout[18]
+ chany[0][1]_midout[19]
+ chany[0][1]_midout[20]
+ chany[0][1]_midout[21]
+ chany[0][1]_midout[22]
+ chany[0][1]_midout[23]
+ chany[0][1]_midout[24]
+ chany[0][1]_midout[25]
+ chany[0][1]_midout[26]
+ chany[0][1]_midout[27]
+ chany[0][1]_midout[28]
+ chany[0][1]_midout[29]
+ grid[1][1]_pin[0][3][3]
+ grid[0][1]_pin[0][1][0]
+ grid[0][1]_pin[0][1][2]
+ grid[0][1]_pin[0][1][4]
+ grid[0][1]_pin[0][1][6]
+ grid[0][1]_pin[0][1][8]
+ grid[0][1]_pin[0][1][10]
+ grid[0][1]_pin[0][1][12]
+ grid[0][1]_pin[0][1][14]
+ gvdd_cby[0][1] 0 cby[0][1]
***** Signal chany[0][1]_midout[0] density = 0, probability=0.*****
Vchany[0][1]_midout[0] chany[0][1]_midout[0] 0
+ 0
***** Signal chany[0][1]_midout[1] density = 0, probability=0.*****
Vchany[0][1]_midout[1] chany[0][1]_midout[1] 0
+ 0
***** Signal chany[0][1]_midout[2] density = 0, probability=0.*****
Vchany[0][1]_midout[2] chany[0][1]_midout[2] 0
+ 0
***** Signal chany[0][1]_midout[3] density = 0, probability=0.*****
Vchany[0][1]_midout[3] chany[0][1]_midout[3] 0
+ 0
***** Signal chany[0][1]_midout[4] density = 0, probability=0.*****
Vchany[0][1]_midout[4] chany[0][1]_midout[4] 0
+ 0
***** Signal chany[0][1]_midout[5] density = 0, probability=0.*****
Vchany[0][1]_midout[5] chany[0][1]_midout[5] 0
+ 0
***** Signal chany[0][1]_midout[6] density = 0, probability=0.*****
Vchany[0][1]_midout[6] chany[0][1]_midout[6] 0
+ 0
***** Signal chany[0][1]_midout[7] density = 0, probability=0.*****
Vchany[0][1]_midout[7] chany[0][1]_midout[7] 0
+ 0
***** Signal chany[0][1]_midout[8] density = 0, probability=0.*****
Vchany[0][1]_midout[8] chany[0][1]_midout[8] 0
+ 0
***** Signal chany[0][1]_midout[9] density = 0, probability=0.*****
Vchany[0][1]_midout[9] chany[0][1]_midout[9] 0
+ 0
***** Signal chany[0][1]_midout[10] density = 0, probability=0.*****
Vchany[0][1]_midout[10] chany[0][1]_midout[10] 0
+ 0
***** Signal chany[0][1]_midout[11] density = 0, probability=0.*****
Vchany[0][1]_midout[11] chany[0][1]_midout[11] 0
+ 0
***** Signal chany[0][1]_midout[12] density = 0, probability=0.*****
Vchany[0][1]_midout[12] chany[0][1]_midout[12] 0
+ 0
***** Signal chany[0][1]_midout[13] density = 0, probability=0.*****
Vchany[0][1]_midout[13] chany[0][1]_midout[13] 0
+ 0
***** Signal chany[0][1]_midout[14] density = 0, probability=0.*****
Vchany[0][1]_midout[14] chany[0][1]_midout[14] 0
+ 0
***** Signal chany[0][1]_midout[15] density = 0, probability=0.*****
Vchany[0][1]_midout[15] chany[0][1]_midout[15] 0
+ 0
***** Signal chany[0][1]_midout[16] density = 0, probability=0.*****
Vchany[0][1]_midout[16] chany[0][1]_midout[16] 0
+ 0
***** Signal chany[0][1]_midout[17] density = 0, probability=0.*****
Vchany[0][1]_midout[17] chany[0][1]_midout[17] 0
+ 0
***** Signal chany[0][1]_midout[18] density = 0, probability=0.*****
Vchany[0][1]_midout[18] chany[0][1]_midout[18] 0
+ 0
***** Signal chany[0][1]_midout[19] density = 0, probability=0.*****
Vchany[0][1]_midout[19] chany[0][1]_midout[19] 0
+ 0
***** Signal chany[0][1]_midout[20] density = 0, probability=0.*****
Vchany[0][1]_midout[20] chany[0][1]_midout[20] 0
+ 0
***** Signal chany[0][1]_midout[21] density = 0, probability=0.*****
Vchany[0][1]_midout[21] chany[0][1]_midout[21] 0
+ 0
***** Signal chany[0][1]_midout[22] density = 0, probability=0.*****
Vchany[0][1]_midout[22] chany[0][1]_midout[22] 0
+ 0
***** Signal chany[0][1]_midout[23] density = 0, probability=0.*****
Vchany[0][1]_midout[23] chany[0][1]_midout[23] 0
+ 0
***** Signal chany[0][1]_midout[24] density = 0, probability=0.*****
Vchany[0][1]_midout[24] chany[0][1]_midout[24] 0
+ 0
***** Signal chany[0][1]_midout[25] density = 0, probability=0.*****
Vchany[0][1]_midout[25] chany[0][1]_midout[25] 0
+ 0
***** Signal chany[0][1]_midout[26] density = 0, probability=0.*****
Vchany[0][1]_midout[26] chany[0][1]_midout[26] 0
+ 0
***** Signal chany[0][1]_midout[27] density = 0.1906, probability=0.4782.*****
Vchany[0][1]_midout[27] chany[0][1]_midout[27] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal chany[0][1]_midout[28] density = 0, probability=0.*****
Vchany[0][1]_midout[28] chany[0][1]_midout[28] 0
+ 0
***** Signal chany[0][1]_midout[29] density = 0, probability=0.*****
Vchany[0][1]_midout[29] chany[0][1]_midout[29] 0
+ 0
******* Normal TYPE loads *******
Xload_inv[0]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[1] gvdd_load 0 inv size=1
Xload_inv[2]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[2] gvdd_load 0 inv size=1
Xload_inv[3]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[3] gvdd_load 0 inv size=1
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
***** Voltage supplies *****
***** Voltage supplies *****
Vgvdd_cb[0][1] gvdd_cby[0][1] 0 vsp
Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
***** Measurements *****
***** Leakage Power Measurement *****
.meas tran leakage_power_cb avg p(Vgvdd_cb[0][1]) from=0 to='clock_period'
.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period'
***** Dynamic Power Measurement *****
.meas tran dynamic_power_cb avg p(Vgvdd_cb[0][1]) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period'
.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
.end

276
examples/spice_test_example_1/cb_tb/example_1_cby1_1_cb_testbench.sp
View File

@ -1,276 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_sram_cbs
****** Include subckt netlists: Connection Box Y-channel [1][1] *****
.include './spice_test_example_1/subckt/cby_1_1.sp'
***** Call defined Connection Box[1][1] *****
Xcby[1][1]
+ chany[1][1]_midout[0]
+ chany[1][1]_midout[1]
+ chany[1][1]_midout[2]
+ chany[1][1]_midout[3]
+ chany[1][1]_midout[4]
+ chany[1][1]_midout[5]
+ chany[1][1]_midout[6]
+ chany[1][1]_midout[7]
+ chany[1][1]_midout[8]
+ chany[1][1]_midout[9]
+ chany[1][1]_midout[10]
+ chany[1][1]_midout[11]
+ chany[1][1]_midout[12]
+ chany[1][1]_midout[13]
+ chany[1][1]_midout[14]
+ chany[1][1]_midout[15]
+ chany[1][1]_midout[16]
+ chany[1][1]_midout[17]
+ chany[1][1]_midout[18]
+ chany[1][1]_midout[19]
+ chany[1][1]_midout[20]
+ chany[1][1]_midout[21]
+ chany[1][1]_midout[22]
+ chany[1][1]_midout[23]
+ chany[1][1]_midout[24]
+ chany[1][1]_midout[25]
+ chany[1][1]_midout[26]
+ chany[1][1]_midout[27]
+ chany[1][1]_midout[28]
+ chany[1][1]_midout[29]
+ grid[2][1]_pin[0][3][0]
+ grid[2][1]_pin[0][3][2]
+ grid[2][1]_pin[0][3][4]
+ grid[2][1]_pin[0][3][6]
+ grid[2][1]_pin[0][3][8]
+ grid[2][1]_pin[0][3][10]
+ grid[2][1]_pin[0][3][12]
+ grid[2][1]_pin[0][3][14]
+ grid[1][1]_pin[0][1][1]
+ grid[1][1]_pin[0][1][5]
+ gvdd_cby[1][1] 0 cby[1][1]
***** Signal chany[1][1]_midout[0] density = 0, probability=0.*****
Vchany[1][1]_midout[0] chany[1][1]_midout[0] 0
+ 0
***** Signal chany[1][1]_midout[1] density = 0, probability=0.*****
Vchany[1][1]_midout[1] chany[1][1]_midout[1] 0
+ 0
***** Signal chany[1][1]_midout[2] density = 0, probability=0.*****
Vchany[1][1]_midout[2] chany[1][1]_midout[2] 0
+ 0
***** Signal chany[1][1]_midout[3] density = 0, probability=0.*****
Vchany[1][1]_midout[3] chany[1][1]_midout[3] 0
+ 0
***** Signal chany[1][1]_midout[4] density = 0, probability=0.*****
Vchany[1][1]_midout[4] chany[1][1]_midout[4] 0
+ 0
***** Signal chany[1][1]_midout[5] density = 0, probability=0.*****
Vchany[1][1]_midout[5] chany[1][1]_midout[5] 0
+ 0
***** Signal chany[1][1]_midout[6] density = 0, probability=0.*****
Vchany[1][1]_midout[6] chany[1][1]_midout[6] 0
+ 0
***** Signal chany[1][1]_midout[7] density = 0, probability=0.*****
Vchany[1][1]_midout[7] chany[1][1]_midout[7] 0
+ 0
***** Signal chany[1][1]_midout[8] density = 0, probability=0.*****
Vchany[1][1]_midout[8] chany[1][1]_midout[8] 0
+ 0
***** Signal chany[1][1]_midout[9] density = 0, probability=0.*****
Vchany[1][1]_midout[9] chany[1][1]_midout[9] 0
+ 0
***** Signal chany[1][1]_midout[10] density = 0, probability=0.*****
Vchany[1][1]_midout[10] chany[1][1]_midout[10] 0
+ 0
***** Signal chany[1][1]_midout[11] density = 0, probability=0.*****
Vchany[1][1]_midout[11] chany[1][1]_midout[11] 0
+ 0
***** Signal chany[1][1]_midout[12] density = 0, probability=0.*****
Vchany[1][1]_midout[12] chany[1][1]_midout[12] 0
+ 0
***** Signal chany[1][1]_midout[13] density = 0, probability=0.*****
Vchany[1][1]_midout[13] chany[1][1]_midout[13] 0
+ 0
***** Signal chany[1][1]_midout[14] density = 0, probability=0.*****
Vchany[1][1]_midout[14] chany[1][1]_midout[14] 0
+ 0
***** Signal chany[1][1]_midout[15] density = 0, probability=0.*****
Vchany[1][1]_midout[15] chany[1][1]_midout[15] 0
+ 0
***** Signal chany[1][1]_midout[16] density = 0, probability=0.*****
Vchany[1][1]_midout[16] chany[1][1]_midout[16] 0
+ 0
***** Signal chany[1][1]_midout[17] density = 0, probability=0.*****
Vchany[1][1]_midout[17] chany[1][1]_midout[17] 0
+ 0
***** Signal chany[1][1]_midout[18] density = 0, probability=0.*****
Vchany[1][1]_midout[18] chany[1][1]_midout[18] 0
+ 0
***** Signal chany[1][1]_midout[19] density = 0, probability=0.*****
Vchany[1][1]_midout[19] chany[1][1]_midout[19] 0
+ 0
***** Signal chany[1][1]_midout[20] density = 0, probability=0.*****
Vchany[1][1]_midout[20] chany[1][1]_midout[20] 0
+ 0
***** Signal chany[1][1]_midout[21] density = 0, probability=0.*****
Vchany[1][1]_midout[21] chany[1][1]_midout[21] 0
+ 0
***** Signal chany[1][1]_midout[22] density = 0, probability=0.*****
Vchany[1][1]_midout[22] chany[1][1]_midout[22] 0
+ 0
***** Signal chany[1][1]_midout[23] density = 0, probability=0.*****
Vchany[1][1]_midout[23] chany[1][1]_midout[23] 0
+ 0
***** Signal chany[1][1]_midout[24] density = 0, probability=0.*****
Vchany[1][1]_midout[24] chany[1][1]_midout[24] 0
+ 0
***** Signal chany[1][1]_midout[25] density = 0, probability=0.*****
Vchany[1][1]_midout[25] chany[1][1]_midout[25] 0
+ 0
***** Signal chany[1][1]_midout[26] density = 0, probability=0.*****
Vchany[1][1]_midout[26] chany[1][1]_midout[26] 0
+ 0
***** Signal chany[1][1]_midout[27] density = 0, probability=0.*****
Vchany[1][1]_midout[27] chany[1][1]_midout[27] 0
+ 0
***** Signal chany[1][1]_midout[28] density = 0, probability=0.*****
Vchany[1][1]_midout[28] chany[1][1]_midout[28] 0
+ 0
***** Signal chany[1][1]_midout[29] density = 0, probability=0.*****
Vchany[1][1]_midout[29] chany[1][1]_midout[29] 0
+ 0
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* IO_TYPE loads *******
******* END loads *******
******* Normal TYPE loads *******
Xload_inv[0]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[1] gvdd_load 0 inv size=1
Xload_inv[2]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[2] gvdd_load 0 inv size=1
Xload_inv[3]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[3] gvdd_load 0 inv size=1
******* END loads *******
******* Normal TYPE loads *******
Xload_inv[4]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[0] gvdd_load 0 inv size=1
Xload_inv[5]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[1] gvdd_load 0 inv size=1
Xload_inv[6]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[2] gvdd_load 0 inv size=1
Xload_inv[7]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[3] gvdd_load 0 inv size=1
******* END loads *******
***** Voltage supplies *****
***** Voltage supplies *****
Vgvdd_cb[1][1] gvdd_cby[1][1] 0 vsp
Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp
***** 2 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '2*clock_period'
***** Generic Measurements for Circuit Parameters *****
***** Measurements *****
***** Leakage Power Measurement *****
.meas tran leakage_power_cb avg p(Vgvdd_cb[1][1]) from=0 to='clock_period'
.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period'
***** Dynamic Power Measurement *****
.meas tran dynamic_power_cb avg p(Vgvdd_cb[1][1]) from='clock_period' to='2*clock_period'
.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period'
.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='2*clock_period'
.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
.end

361
examples/spice_test_example_1/example_1.bitstream
View File

@ -1,361 +0,0 @@
0, // Configuration bit No.: 364, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 361
1, // Configuration bit No.: 363, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 361
0, // Configuration bit No.: 362, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 361
1, // Configuration bit No.: 361, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 361
0, // Configuration bit No.: 360, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 357
1, // Configuration bit No.: 359, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 357
0, // Configuration bit No.: 358, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 357
1, // Configuration bit No.: 357, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 357
0, // Configuration bit No.: 356, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 353
1, // Configuration bit No.: 355, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 353
0, // Configuration bit No.: 354, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 353
1, // Configuration bit No.: 353, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 353
0, // Configuration bit No.: 352, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 349
1, // Configuration bit No.: 351, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 349
0, // Configuration bit No.: 350, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 349
1, // Configuration bit No.: 349, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 349
0, // Configuration bit No.: 348, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 345
1, // Configuration bit No.: 347, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 345
0, // Configuration bit No.: 346, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 345
1, // Configuration bit No.: 345, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 345
0, // Configuration bit No.: 344, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 341
1, // Configuration bit No.: 343, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 341
0, // Configuration bit No.: 342, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 341
1, // Configuration bit No.: 341, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 341
0, // Configuration bit No.: 340, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 337
1, // Configuration bit No.: 339, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 337
0, // Configuration bit No.: 338, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 337
1, // Configuration bit No.: 337, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 337
0, // Configuration bit No.: 336, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 333
1, // Configuration bit No.: 335, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 333
0, // Configuration bit No.: 334, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 333
1, // Configuration bit No.: 333, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 333
0, // Configuration bit No.: 332, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 329
1, // Configuration bit No.: 331, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 329
0, // Configuration bit No.: 330, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 329
1, // Configuration bit No.: 329, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 329
0, // Configuration bit No.: 328, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 325
1, // Configuration bit No.: 327, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 325
0, // Configuration bit No.: 326, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 325
1, // Configuration bit No.: 325, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 325
0, // Configuration bit No.: 324, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 321
1, // Configuration bit No.: 323, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 321
0, // Configuration bit No.: 322, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 321
1, // Configuration bit No.: 321, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 321
0, // Configuration bit No.: 320, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 317
1, // Configuration bit No.: 319, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 317
0, // Configuration bit No.: 318, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 317
1, // Configuration bit No.: 317, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 317
0, // Configuration bit No.: 316, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 313
1, // Configuration bit No.: 315, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 313
0, // Configuration bit No.: 314, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 313
1, // Configuration bit No.: 313, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 313
0, // Configuration bit No.: 312, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 309
1, // Configuration bit No.: 311, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 309
0, // Configuration bit No.: 310, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 309
1, // Configuration bit No.: 309, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 309
0, // Configuration bit No.: 308, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 305
1, // Configuration bit No.: 307, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 305
0, // Configuration bit No.: 306, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 305
1, // Configuration bit No.: 305, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 305
0, // Configuration bit No.: 304, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 301
1, // Configuration bit No.: 303, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 301
0, // Configuration bit No.: 302, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 301
1, // Configuration bit No.: 301, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 301
0, // Configuration bit No.: 300, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 297
1, // Configuration bit No.: 299, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 297
0, // Configuration bit No.: 298, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 297
1, // Configuration bit No.: 297, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 297
1, // Configuration bit No.: 296, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 293
0, // Configuration bit No.: 295, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 293
1, // Configuration bit No.: 294, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 293
0, // Configuration bit No.: 293, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 293
0, // Configuration bit No.: 292, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 289
1, // Configuration bit No.: 291, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 289
0, // Configuration bit No.: 290, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 289
1, // Configuration bit No.: 289, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 289
0, // Configuration bit No.: 288, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 285
1, // Configuration bit No.: 287, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 285
0, // Configuration bit No.: 286, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 285
1, // Configuration bit No.: 285, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 285
0, // Configuration bit No.: 284, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 281
1, // Configuration bit No.: 283, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 281
0, // Configuration bit No.: 282, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 281
1, // Configuration bit No.: 281, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 281
0, // Configuration bit No.: 280, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 277
1, // Configuration bit No.: 279, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 277
0, // Configuration bit No.: 278, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 277
1, // Configuration bit No.: 277, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 277
0, // Configuration bit No.: 276, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 273
1, // Configuration bit No.: 275, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 273
0, // Configuration bit No.: 274, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 273
1, // Configuration bit No.: 273, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 273
0, // Configuration bit No.: 272, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 269
1, // Configuration bit No.: 271, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 269
0, // Configuration bit No.: 270, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 269
1, // Configuration bit No.: 269, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 269
0, // Configuration bit No.: 268, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 265
1, // Configuration bit No.: 267, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 265
0, // Configuration bit No.: 266, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 265
1, // Configuration bit No.: 265, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 265
0, // Configuration bit No.: 264, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 261
1, // Configuration bit No.: 263, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 261
0, // Configuration bit No.: 262, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 261
1, // Configuration bit No.: 261, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 261
0, // Configuration bit No.: 260, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 257
1, // Configuration bit No.: 259, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 257
0, // Configuration bit No.: 258, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 257
1, // Configuration bit No.: 257, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 257
0, // Configuration bit No.: 256, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 253
1, // Configuration bit No.: 255, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 253
0, // Configuration bit No.: 254, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 253
1, // Configuration bit No.: 253, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 253
0, // Configuration bit No.: 252, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 249
1, // Configuration bit No.: 251, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 249
0, // Configuration bit No.: 250, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 249
1, // Configuration bit No.: 249, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 249
0, // Configuration bit No.: 248, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 245
1, // Configuration bit No.: 247, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 245
0, // Configuration bit No.: 246, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 245
1, // Configuration bit No.: 245, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 245
0, // Configuration bit No.: 244, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 241
1, // Configuration bit No.: 243, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 241
0, // Configuration bit No.: 242, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 241
1, // Configuration bit No.: 241, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 241
0, // Configuration bit No.: 240, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 237
1, // Configuration bit No.: 239, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 237
0, // Configuration bit No.: 238, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 237
1, // Configuration bit No.: 237, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 237
0, // Configuration bit No.: 236, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 233
1, // Configuration bit No.: 235, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 233
0, // Configuration bit No.: 234, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 233
1, // Configuration bit No.: 233, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 233
0, // Configuration bit No.: 232, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 229
1, // Configuration bit No.: 231, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 229
0, // Configuration bit No.: 230, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 229
1, // Configuration bit No.: 229, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 229
0, // Configuration bit No.: 228, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 225
1, // Configuration bit No.: 227, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 225
0, // Configuration bit No.: 226, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 225
1, // Configuration bit No.: 225, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 225
0, // Configuration bit No.: 224, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 221
1, // Configuration bit No.: 223, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 221
0, // Configuration bit No.: 222, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 221
1, // Configuration bit No.: 221, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 221
1, // Configuration bit No.: 217, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 217
1, // Configuration bit No.: 216, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 216
1, // Configuration bit No.: 215, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 215
1, // Configuration bit No.: 214, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 214
1, // Configuration bit No.: 213, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 213
1, // Configuration bit No.: 212, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 212
1, // Configuration bit No.: 211, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 211
1, // Configuration bit No.: 210, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 210
1, // Configuration bit No.: 209, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 209
1, // Configuration bit No.: 208, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 208
1, // Configuration bit No.: 207, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 207
1, // Configuration bit No.: 206, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 206
0, // Configuration bit No.: 207, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 205
0, // Configuration bit No.: 206, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 205
1, // Configuration bit No.: 205, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 205
0, // Configuration bit No.: 204, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 202
0, // Configuration bit No.: 203, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 202
1, // Configuration bit No.: 202, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 202
0, // Configuration bit No.: 201, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 199
1, // Configuration bit No.: 200, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 199
0, // Configuration bit No.: 199, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 199
1, // Configuration bit No.: 196, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 196
1, // Configuration bit No.: 195, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 195
1, // Configuration bit No.: 194, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 194
1, // Configuration bit No.: 193, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 193
1, // Configuration bit No.: 192, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 192
1, // Configuration bit No.: 191, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 191
1, // Configuration bit No.: 190, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 190
1, // Configuration bit No.: 189, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 189
1, // Configuration bit No.: 188, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 188
1, // Configuration bit No.: 187, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 187
1, // Configuration bit No.: 186, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 186
1, // Configuration bit No.: 185, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 185
1, // Configuration bit No.: 184, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 184
1, // Configuration bit No.: 183, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 183
0, // Configuration bit No.: 184, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 182
0, // Configuration bit No.: 183, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 182
1, // Configuration bit No.: 182, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 182
1, // Configuration bit No.: 179, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 179
1, // Configuration bit No.: 178, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 178
1, // Configuration bit No.: 177, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 177
1, // Configuration bit No.: 176, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 176
1, // Configuration bit No.: 175, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 175
1, // Configuration bit No.: 174, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 174
1, // Configuration bit No.: 173, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 173
1, // Configuration bit No.: 172, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 172
1, // Configuration bit No.: 171, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 171
1, // Configuration bit No.: 170, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 170
1, // Configuration bit No.: 169, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 169
1, // Configuration bit No.: 168, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 168
1, // Configuration bit No.: 167, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 167
1, // Configuration bit No.: 166, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 166
0, // Configuration bit No.: 167, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 165
0, // Configuration bit No.: 166, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 165
1, // Configuration bit No.: 165, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 165
1, // Configuration bit No.: 162, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 162
1, // Configuration bit No.: 161, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 161
1, // Configuration bit No.: 160, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 160
1, // Configuration bit No.: 159, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 159
1, // Configuration bit No.: 158, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 158
1, // Configuration bit No.: 157, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 157
1, // Configuration bit No.: 156, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 156
1, // Configuration bit No.: 155, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 155
1, // Configuration bit No.: 154, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 154
1, // Configuration bit No.: 153, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 153
1, // Configuration bit No.: 152, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 152
1, // Configuration bit No.: 151, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 151
1, // Configuration bit No.: 150, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 150
1, // Configuration bit No.: 149, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 149
0, // Configuration bit No.: 150, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 148
0, // Configuration bit No.: 149, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 148
1, // Configuration bit No.: 148, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 148
1, // Configuration bit No.: 145, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 145
0, // Configuration bit No.: 144, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 144
1, // Configuration bit No.: 143, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 143
1, // Configuration bit No.: 142, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 142
1, // Configuration bit No.: 141, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 141
1, // Configuration bit No.: 140, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 140
1, // Configuration bit No.: 139, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 139
1, // Configuration bit No.: 138, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 138
1, // Configuration bit No.: 137, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 137
1, // Configuration bit No.: 136, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 136
1, // Configuration bit No.: 135, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 135
1, // Configuration bit No.: 134, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 134
1, // Configuration bit No.: 133, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 133
1, // Configuration bit No.: 132, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 132
0, // Configuration bit No.: 133, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 131
0, // Configuration bit No.: 132, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 131
1, // Configuration bit No.: 131, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 131
1, // Configuration bit No.: 128, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 128
1, // Configuration bit No.: 127, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 127
1, // Configuration bit No.: 126, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 126
1, // Configuration bit No.: 125, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 125
1, // Configuration bit No.: 124, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 124
1, // Configuration bit No.: 123, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 123
1, // Configuration bit No.: 122, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 122
1, // Configuration bit No.: 121, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 121
1, // Configuration bit No.: 120, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 120
1, // Configuration bit No.: 119, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 119
1, // Configuration bit No.: 118, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 118
1, // Configuration bit No.: 117, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 117
0, // Configuration bit No.: 118, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 116
0, // Configuration bit No.: 117, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 116
1, // Configuration bit No.: 116, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 116
0, // Configuration bit No.: 115, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 113
0, // Configuration bit No.: 114, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 113
1, // Configuration bit No.: 113, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 113
0, // Configuration bit No.: 112, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 110
0, // Configuration bit No.: 111, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 110
1, // Configuration bit No.: 110, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 110
1, // Configuration bit No.: 107, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 107
1, // Configuration bit No.: 106, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 106
1, // Configuration bit No.: 105, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 105
1, // Configuration bit No.: 104, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 104
1, // Configuration bit No.: 103, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 103
1, // Configuration bit No.: 102, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 102
1, // Configuration bit No.: 101, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 101
1, // Configuration bit No.: 100, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 100
1, // Configuration bit No.: 99, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 99
1, // Configuration bit No.: 98, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 98
1, // Configuration bit No.: 97, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 97
1, // Configuration bit No.: 96, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 96
1, // Configuration bit No.: 95, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 95
1, // Configuration bit No.: 94, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 94
0, // Configuration bit No.: 95, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 93
0, // Configuration bit No.: 94, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 93
1, // Configuration bit No.: 93, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 93
1, // Configuration bit No.: 90, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 90
1, // Configuration bit No.: 89, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 89
1, // Configuration bit No.: 88, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 88
1, // Configuration bit No.: 87, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 87
1, // Configuration bit No.: 86, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 86
1, // Configuration bit No.: 85, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 85
1, // Configuration bit No.: 84, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 84
1, // Configuration bit No.: 83, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 83
1, // Configuration bit No.: 82, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 82
1, // Configuration bit No.: 81, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 81
1, // Configuration bit No.: 80, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 80
1, // Configuration bit No.: 79, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 79
1, // Configuration bit No.: 78, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 78
1, // Configuration bit No.: 77, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 77
0, // Configuration bit No.: 78, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 76
0, // Configuration bit No.: 77, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 76
1, // Configuration bit No.: 76, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 76
1, // Configuration bit No.: 73, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 73
1, // Configuration bit No.: 72, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 72
1, // Configuration bit No.: 71, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 71
1, // Configuration bit No.: 70, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 70
1, // Configuration bit No.: 69, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 69
1, // Configuration bit No.: 68, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 68
0, // Configuration bit No.: 67, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 67
1, // Configuration bit No.: 66, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 66
1, // Configuration bit No.: 65, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 65
1, // Configuration bit No.: 64, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 64
1, // Configuration bit No.: 63, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 63
1, // Configuration bit No.: 62, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 62
1, // Configuration bit No.: 61, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 61
1, // Configuration bit No.: 60, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 60
1, // Configuration bit No.: 59, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 59
1, // Configuration bit No.: 58, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 58
1, // Configuration bit No.: 57, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 57
1, // Configuration bit No.: 56, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 56
1, // Configuration bit No.: 55, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 55
1, // Configuration bit No.: 54, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 54
1, // Configuration bit No.: 53, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 53
1, // Configuration bit No.: 52, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 52
1, // Configuration bit No.: 51, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 51
1, // Configuration bit No.: 50, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 50
1, // Configuration bit No.: 49, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 49
1, // Configuration bit No.: 48, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 48
1, // Configuration bit No.: 47, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 47
1, // Configuration bit No.: 46, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 46
1, // Configuration bit No.: 45, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 45
1, // Configuration bit No.: 44, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 44
1, // Configuration bit No.: 43, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 43
1, // Configuration bit No.: 42, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 42
0, // Configuration bit No.: 46, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 41
0, // Configuration bit No.: 45, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 41
1, // Configuration bit No.: 44, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 41
0, // Configuration bit No.: 43, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 41
0, // Configuration bit No.: 42, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 41
1, // Configuration bit No.: 41, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 41
0, // Configuration bit No.: 40, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 35
0, // Configuration bit No.: 39, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 35
1, // Configuration bit No.: 38, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 35
0, // Configuration bit No.: 37, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 35
0, // Configuration bit No.: 36, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 35
1, // Configuration bit No.: 35, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 35
0, // Configuration bit No.: 34, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 29
0, // Configuration bit No.: 33, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 29
1, // Configuration bit No.: 32, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 29
0, // Configuration bit No.: 31, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 29
0, // Configuration bit No.: 30, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 29
1, // Configuration bit No.: 29, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 29
0, // Configuration bit No.: 28, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 23
0, // Configuration bit No.: 27, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 23
1, // Configuration bit No.: 26, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 23
0, // Configuration bit No.: 25, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 23
1, // Configuration bit No.: 24, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 23
0, // Configuration bit No.: 23, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 23
1, // Configuration bit No.: 17, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 17
1, // Configuration bit No.: 31, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16
0, // Configuration bit No.: 30, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16
1, // Configuration bit No.: 29, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16
0, // Configuration bit No.: 28, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16
1, // Configuration bit No.: 27, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16
0, // Configuration bit No.: 26, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16
1, // Configuration bit No.: 25, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16
0, // Configuration bit No.: 24, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16
1, // Configuration bit No.: 23, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16
0, // Configuration bit No.: 22, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16
1, // Configuration bit No.: 21, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16
0, // Configuration bit No.: 20, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16
1, // Configuration bit No.: 19, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16
0, // Configuration bit No.: 18, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16
1, // Configuration bit No.: 17, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16
0, // Configuration bit No.: 16, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16

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examples/spice_test_example_1/grid_tb/example_1_grid1_1_grid_testbench.sp
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@ -1,177 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA Grid Testbench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
****** Include subckt netlists: Look-Up Tables (LUTs) *****
.include './spice_test_example_1/subckt/luts.sp'
****** Include subckt netlists: Grid[1][1] *****
.include './spice_test_example_1/subckt/grid_1_1.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_local_interc gvdd_io gvdd_hardlogic
.global gvdd_sram_local_routing
.global gvdd_sram_luts
.global gvdd_sram_io
***** Global VDD ports of Look-Up Table *****
.global
+ gvdd_lut4[0]
***** Global VDD ports of Flip-flop *****
.global
+ gvdd_dff[0]
***** Global VDD ports of iopad *****
***** Global VDD ports of hard_logic *****
Xgrid[1][1]
+ grid[1][1]_pin[0][0][0]
+ grid[1][1]_pin[0][0][4]
+ grid[1][1]_pin[0][1][1]
+ grid[1][1]_pin[0][1][5]
+ grid[1][1]_pin[0][2][2]
+ grid[1][1]_pin[0][3][3]
+ gvdd 0 grid[1][1]
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
Vgvdd_local_interc gvdd_local_interc 0 vsp
Vgvdd_sram_luts gvdd_sram_luts 0 vsp
Vgvdd_sram_local_routing gvdd_sram_local_routing 0 vsp
Vgvdd_sram_io gvdd_sram_io 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
***** Global VDD for Hard Logics *****
***** Global VDD for Look-Up Tables (LUTs) *****
Vgvdd_lut4[0] gvdd_lut4[0] 0 vsp
Rgvdd_lut4[0]_huge gvdd_lut4[0] 0 'vsp/10e-15'
***** Global VDD for Flip-flops (FFs) *****
Vgvdd_dff[0] gvdd_dff[0] 0 vsp
Rgvdd_dff[0]_huge gvdd_dff[0] 0 'vsp/10e-15'
Vgrid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0] 0
+ 0
Xgrid[1][1]_pin[0][0][4]_inv[0] grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[0] gvdd_load 0 inv size=1
Xgrid[1][1]_pin[0][0][4]_inv[1] grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[1] gvdd_load 0 inv size=1
Xgrid[1][1]_pin[0][0][4]_inv[2] grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[2] gvdd_load 0 inv size=1
Xgrid[1][1]_pin[0][0][4]_inv[3] grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[3] gvdd_load 0 inv size=1
Vgrid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1] 0
+ 0
Vgrid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5] 0
+ 0
Vgrid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2] 0
+ 0
Vgrid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
.measure tran leakage_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from=0 to='clock_period'
.measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period'
.measure tran leakage_power_local_routing avg p(Vgvdd_local_interc) from=0 to='clock_period'
.measure tran leakage_power_lut4[0] avg p(Vgvdd_lut4[0]) from=0 to='clock_period'
.measure tran leakage_power_lut4[0to0]
+ param = 'leakage_power_lut4[0]'
.measure tran total_leakage_power_lut4
+ param = 'leakage_power_lut4[0to0]'
.measure tran leakage_power_dff[0] avg p(Vgvdd_dff[0]) from=0 to='clock_period'
.measure tran leakage_power_dff[0to0]
+ param = 'leakage_power_dff[0]'
.measure tran total_leakage_power_dff
+ param = 'leakage_power_dff[0to0]'
.measure tran dynamic_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from='clock_period' to='7*clock_period'
.measure tran total_energy_per_cycle_sram_local_routing param='dynamic_power_sram_local_routing*clock_period'
.measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='7*clock_period'
.measure tran total_energy_per_cycle_sram_luts param='dynamic_power_sram_luts*clock_period'
.measure tran dynamic_power_local_interc avg p(Vgvdd_local_interc) from='clock_period' to='7*clock_period'
.measure tran total_energy_per_cycle_local_routing param='dynamic_power_local_interc*clock_period'
.measure tran dynamic_power_lut4[0] avg p(Vgvdd_lut4[0]) from='clock_period' to='7*clock_period'
.measure tran dynamic_power_lut4[0to0]
+ param = 'dynamic_power_lut4[0]'
.measure tran total_dynamic_power_lut4
+ param = 'dynamic_power_lut4[0to0]'
.measure tran total_energy_per_cycle_lut4
+ param = 'dynamic_power_lut4[0to0]*clock_period'
.measure tran dynamic_power_dff[0] avg p(Vgvdd_dff[0]) from='clock_period' to='7*clock_period'
.measure tran dynamic_power_dff[0to0]
+ param = 'dynamic_power_dff[0]'
.measure tran total_dynamic_power_dff
+ param = 'dynamic_power_dff[0to0]'
.measure tran total_energy_per_cycle_dff
+ param = 'dynamic_power_dff[0to0]*clock_period'
.end

130
examples/spice_test_example_1/hardlogic_tb/example_1_grid1_1_hardlogic_testbench.sp
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@ -1,130 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA Hard Logic Testbench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_load
***** Global VDD ports of Flip-flop *****
.global
+ gvdd_dff[0]
***** Global VDD ports of hard_logic *****
***** Global VDD ports of iopad *****
.global gvdd_sram_io
***** Hardlogic[1]: logical_block_index[3], gvdd_index[0]*****
Xhardlogic_dff[0]
***** BEGIN Global ports of SPICE_MODEL(static_dff) *****
+ Set[0] Reset[0] clk[0]
***** END Global ports of SPICE_MODEL(static_dff) *****
+ hardlogic_dff[0]->D[0]
+ hardlogic_dff[0]->Q[0]
+ gvdd_dff[0] ggnd
+ static_dff
Vhardlogic_dff[0]->D[0] hardlogic_dff[0]->D[0] 0
+ pulse(vsp 0 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*20.1096*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '20.1096*clock_period')
Xload_inv[0]_no0 hardlogic_dff[0]->Q[0] hardlogic_dff[0]->Q[0]_out[0] gvdd_load 0 inv size=1
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
***** Global VDD for FFs *****
Vgvdd_dff[0] gvdd_dff[0] 0 vsp
Rgvdd_dff[0]_huge gvdd_dff[0] 0 'vsp/10e-15'
***** Global VDD for Hardlogics *****
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
.measure tran leakage_power_dff[0] avg p(Vgvdd_dff[0]) from=0 to='clock_period'
.measure tran leakage_power_dff[0to0]
+ param = 'leakage_power_dff[0]'
.measure tran total_leakage_power_dff
+ param = 'leakage_power_dff[0to0]'
.measure tran dynamic_power_dff[0] avg p(Vgvdd_dff[0]) from='clock_period' to='7*clock_period'
.measure tran dynamic_power_dff[0to0]
+ param = 'dynamic_power_dff[0]'
.measure tran total_dynamic_power_dff
+ param = 'dynamic_power_dff[0to0]'
.measure tran total_energy_per_cycle_dff
+ param = 'dynamic_power_dff[0to0]*clock_period'
.end

73
examples/spice_test_example_1/include/design_params.sp
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@ -1,73 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Parameters for Circuit Designs *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Technology Library ******
.lib '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/subvt_fpga/process/tsmc40nm/toplevel.l' TOP_TT
****** Transistor Parameters ******
.param beta=2
.param nl=4e-08
.param wn=1.4e-07
.param pl=4e-08
.param wp=1.4e-07
.param io_nl=2.7e-07
.param io_wn=3.2e-07
.param io_pl=2.7e-07
.param io_wp=3.2e-07
.param vsp=0.9
.param io_vsp=2.5
***** Parameters for Circuits *****
***** Parameters for SPICE MODEL: INVTX1 *****
***** Parameters for SPICE MODEL: buf4 *****
***** Parameters for SPICE MODEL: tap_buf4 *****
***** Parameters for SPICE MODEL: TGATE *****
***** Parameters for SPICE MODEL: chan_segment *****
.param chan_segment_wire_param_res_val=101
.param chan_segment_wire_param_cap_val=2.25e-14
***** Parameters for SPICE MODEL: direct_interc *****
.param direct_interc_wire_param_res_val=0
.param direct_interc_wire_param_cap_val=0
***** Parameters for SPICE MODEL: mux_1level_tapbuf *****
.param mux_1level_tapbuf_input_buf_size=1
.param mux_1level_tapbuf_output_buf_size=1
.param mux_1level_tapbuf_pgl_pmos_size=2
.param mux_1level_tapbuf_pgl_nmos_size=1
***** Parameters for SPICE MODEL: mux_2level *****
.param mux_2level_input_buf_size=1
.param mux_2level_output_buf_size=1
.param mux_2level_pgl_pmos_size=2
.param mux_2level_pgl_nmos_size=1
***** Parameters for SPICE MODEL: mux_2level_tapbuf *****
.param mux_2level_tapbuf_input_buf_size=1
.param mux_2level_tapbuf_output_buf_size=1
.param mux_2level_tapbuf_pgl_pmos_size=2
.param mux_2level_tapbuf_pgl_nmos_size=1
***** Parameters for SPICE MODEL: static_dff *****
.param static_dff_input_buf_size=1
.param static_dff_output_buf_size=1
.param static_dff_pgl_pmos_size=1.41483e-38
.param static_dff_pgl_nmos_size=0
***** Parameters for SPICE MODEL: lut4 *****
.param lut4_input_buf_size=1
.param lut4_output_buf_size=1
.param lut4_pgl_pmos_size=2
.param lut4_pgl_nmos_size=1
***** Parameters for SPICE MODEL: sram6T *****
.param sram6T_input_buf_size=1
.param sram6T_output_buf_size=1
.param sram6T_pgl_pmos_size=1.41552e-38
.param sram6T_pgl_nmos_size=0
***** Parameters for SPICE MODEL: sram6T_blwl *****
.param sram6T_blwl_input_buf_size=1
.param sram6T_blwl_output_buf_size=1
.param sram6T_blwl_pgl_pmos_size=1.41575e-38
.param sram6T_blwl_pgl_nmos_size=0
***** Parameters for SPICE MODEL: iopad *****
.param iopad_input_buf_size=1
.param iopad_output_buf_size=1
.param iopad_pgl_pmos_size=1.41608e-38
.param iopad_pgl_nmos_size=0

22
examples/spice_test_example_1/include/meas_params.sp
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@ -1,22 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Parameters for measurement *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Parameters For Slew Measurement *****
***** Rising Edge *****
.param slew_upper_thres_pct_rise=0.95
.param slew_lower_thres_pct_rise=0.05
***** Falling Edge *****
.param slew_upper_thres_pct_fall=0.05
.param slew_lower_thres_pct_fall=0.95
***** Parameters For Delay Measurement *****
***** Rising Edge *****
.param input_thres_pct_rise=0.5
.param output_thres_pct_rise=0.5
***** Falling Edge *****
.param input_thres_pct_fall=0.5
.param output_thres_pct_fall=0.5

17
examples/spice_test_example_1/include/stimulate_params.sp
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@ -1,17 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Parameters for Stimulations *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Frequency *****
.param clock_period=4.68274e-10
***** Parameters For Input Stimulations *****
.param input_slew_pct_rise='2.5e-11/clock_period'
.param input_slew_pct_fall='2.5e-11/clock_period'
***** Parameters For Clock Stimulations *****
***** Slew *****
.param clock_slew_pct_rise='2e-11/clock_period'
.param clock_slew_pct_fall='2e-11/clock_period'

133
examples/spice_test_example_1/lut_tb/example_1_grid1_1_lut_testbench.sp
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@ -1,133 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA LUT Testbench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
****** Include subckt netlists: Look-Up Tables (LUTs) *****
.include './spice_test_example_1/subckt/luts.sp'
****** Include subckt netlists: Grid[1][1] *****
.include './spice_test_example_1/subckt/grid_1_1.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_sram_luts
.global gvdd_load
***** Global VDD ports of Look-Up Table *****
.global
+ gvdd_lut4[0]
***** LUT[0]: logical_block_index[4], gvdd_index[0]*****
Xlut[0] lut[0]->in[0] lut[0]->in[1] lut[0]->in[2] lut[0]->in[3] lut[0]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_lut4[0]
Vlut[0]->in[0] lut[0]->in[0] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vlut[0]->in[1] lut[0]->in[1] 0
+ 0
Vlut[0]->in[2] lut[0]->in[2] 0
+ 0
Vlut[0]->in[3] lut[0]->in[3] 0
+ 0
Xload_inv[0]_no0 lut[0]->out lut[0]->out_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 lut[0]->out lut[0]->out_out[1] gvdd_load 0 inv size=1
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for LUTs SRAMs *****
Vgvdd_sram_luts gvdd_sram_luts 0 vsp
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
***** Global VDD for Look-Up Tables (LUTs) *****
Vgvdd_lut4[0] gvdd_lut4[0] 0 vsp
Rgvdd_lut4[0]_huge gvdd_lut4[0] 0 'vsp/10e-15'
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
.measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period'
.measure tran leakage_power_lut4[0] avg p(Vgvdd_lut4[0]) from=0 to='clock_period'
.measure tran leakage_power_lut4[0to0]
+ param = 'leakage_power_lut4[0]'
.measure tran total_leakage_power_lut4
+ param = 'leakage_power_lut4[0to0]'
.measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='7*clock_period'
.measure tran energy_per_cycle_sram_luts param='dynamic_power_sram_luts*clock_period'
.measure tran dynamic_power_lut4[0] avg p(Vgvdd_lut4[0]) from='clock_period' to='7*clock_period'
.measure tran dynamic_power_lut4[0to0]
+ param = 'dynamic_power_lut4[0]'
.measure tran total_dynamic_power_lut4
+ param = 'dynamic_power_lut4[0to0]'
.measure tran total_energy_per_cycle_lut4
+ param = 'dynamic_power_lut4[0to0]*clock_period'
.end

458
examples/spice_test_example_1/pb_mux_tb/example_1_grid1_1_pbmux_testbench.sp
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@ -1,458 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
Xmux_2level_size5[0] mux_2level_size5[0]->in[0] mux_2level_size5[0]->in[1] mux_2level_size5[0]->in[2] mux_2level_size5[0]->in[3] mux_2level_size5[0]->in[4] mux_2level_size5[0]->out sram[0]->out sram[0]->outb sram[1]->outb sram[1]->out sram[2]->out sram[2]->outb sram[3]->outb sram[3]->out sram[4]->out sram[4]->outb sram[5]->out sram[5]->outb gvdd_mux_2level_size5[0] 0 mux_2level_size5
***** SRAM bits for MUX[0], level=2, select_path_id=3. *****
*****010100*****
Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[0]->out) 0
.nodeset V(sram[0]->outb) vsp
Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[1]->out) 0
.nodeset V(sram[1]->outb) vsp
Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[2]->out) 0
.nodeset V(sram[2]->outb) vsp
Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[3]->out) 0
.nodeset V(sram[3]->outb) vsp
Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[4]->out) 0
.nodeset V(sram[4]->outb) vsp
Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[5]->out) 0
.nodeset V(sram[5]->outb) vsp
***** Signal mux_2level_size5[0]->in[0] density = 0, probability=0.*****
Vmux_2level_size5[0]->in[0] mux_2level_size5[0]->in[0] 0
+ 0
***** Signal mux_2level_size5[0]->in[1] density = 0, probability=0.*****
Vmux_2level_size5[0]->in[1] mux_2level_size5[0]->in[1] 0
+ 0
***** Signal mux_2level_size5[0]->in[2] density = 0, probability=0.*****
Vmux_2level_size5[0]->in[2] mux_2level_size5[0]->in[2] 0
+ 0
***** Signal mux_2level_size5[0]->in[3] density = 0.1906, probability=0.4782.*****
Vmux_2level_size5[0]->in[3] mux_2level_size5[0]->in[3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_2level_size5[0]->in[4] density = 0.1906, probability=0.5218.*****
Vmux_2level_size5[0]->in[4] mux_2level_size5[0]->in[4] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgvdd_mux_2level_size5[0] gvdd_mux_2level_size5[0] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar trig v(mux_2level_size5[0]->in[3]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_size5[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar trig v(mux_2level_size5[0]->in[3]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_size5[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar when v(mux_2level_size5[0]->in[3])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar trig v(mux_2level_size5[0]->in[3]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_size5[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar when v(mux_2level_size5[0]->in[3])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar trig v(mux_2level_size5[0]->in[3]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_size5[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_size5[0]_leakage_power avg p(Vgvdd_mux_2level_size5[0]) from=0 to='clock_period'
.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar param='mux_2level_size5[0]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_size5[0]_dynamic_power avg p(Vgvdd_mux_2level_size5[0]) from='clock_period' to='7*clock_period'
.meas tran mux_2level_size5[0]_energy_per_cycle param='mux_2level_size5[0]_dynamic_power*clock_period'
.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar param='mux_2level_size5[0]_dynamic_power'
.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar*clock_period'
.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar avg p(Vgvdd_mux_2level_size5[0]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar'
.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar avg p(Vgvdd_mux_2level_size5[0]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar'
.meas tran sum_leakage_power_mux[0to0]
+ param='leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar'
.meas tran sum_energy_per_cycle_mux[0to0]
+ param='energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar'
Xload_inv[0]_no0 mux_2level_size5[0]->out mux_2level_size5[0]->out_out[0] gvdd_load 0 inv size=5
.meas tran sum_leakage_power_pb_mux[0to0]
+ param='leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar'
.meas tran sum_energy_per_cycle_pb_mux[0to0]
+ param='energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar'
Xmux_2level_size5[1] mux_2level_size5[1]->in[0] mux_2level_size5[1]->in[1] mux_2level_size5[1]->in[2] mux_2level_size5[1]->in[3] mux_2level_size5[1]->in[4] mux_2level_size5[1]->out sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb sram[8]->out sram[8]->outb sram[9]->outb sram[9]->out sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb gvdd_mux_2level_size5[1] 0 mux_2level_size5
***** SRAM bits for MUX[1], level=2, select_path_id=0. *****
*****100100*****
Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[6]->out) 0
.nodeset V(sram[6]->outb) vsp
Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[7]->out) 0
.nodeset V(sram[7]->outb) vsp
Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[8]->out) 0
.nodeset V(sram[8]->outb) vsp
Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[9]->out) 0
.nodeset V(sram[9]->outb) vsp
Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[10]->out) 0
.nodeset V(sram[10]->outb) vsp
Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[11]->out) 0
.nodeset V(sram[11]->outb) vsp
***** Signal mux_2level_size5[1]->in[0] density = 0, probability=0.*****
Vmux_2level_size5[1]->in[0] mux_2level_size5[1]->in[0] 0
+ 0
***** Signal mux_2level_size5[1]->in[1] density = 0, probability=0.*****
Vmux_2level_size5[1]->in[1] mux_2level_size5[1]->in[1] 0
+ 0
***** Signal mux_2level_size5[1]->in[2] density = 0, probability=0.*****
Vmux_2level_size5[1]->in[2] mux_2level_size5[1]->in[2] 0
+ 0
***** Signal mux_2level_size5[1]->in[3] density = 0.1906, probability=0.4782.*****
Vmux_2level_size5[1]->in[3] mux_2level_size5[1]->in[3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_2level_size5[1]->in[4] density = 0.1906, probability=0.5218.*****
Vmux_2level_size5[1]->in[4] mux_2level_size5[1]->in[4] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgvdd_mux_2level_size5[1] gvdd_mux_2level_size5[1] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar trig v(mux_2level_size5[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_size5[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar trig v(mux_2level_size5[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_size5[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar when v(mux_2level_size5[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar trig v(mux_2level_size5[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_size5[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar when v(mux_2level_size5[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar trig v(mux_2level_size5[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_size5[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_size5[1]_leakage_power avg p(Vgvdd_mux_2level_size5[1]) from=0 to='clock_period'
.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar param='mux_2level_size5[1]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_size5[1]_dynamic_power avg p(Vgvdd_mux_2level_size5[1]) from='clock_period' to='7*clock_period'
.meas tran mux_2level_size5[1]_energy_per_cycle param='mux_2level_size5[1]_dynamic_power*clock_period'
.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar param='mux_2level_size5[1]_dynamic_power'
.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar*clock_period'
.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar avg p(Vgvdd_mux_2level_size5[1]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar'
.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar avg p(Vgvdd_mux_2level_size5[1]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar'
.meas tran sum_leakage_power_mux[0to1]
+ param='sum_leakage_power_mux[0to0]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar'
.meas tran sum_energy_per_cycle_mux[0to1]
+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar'
Xload_inv[1]_no0 mux_2level_size5[1]->out mux_2level_size5[1]->out_out[0] gvdd_load 0 inv size=5
.meas tran sum_leakage_power_pb_mux[0to1]
+ param='sum_leakage_power_pb_mux[0to0]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar'
.meas tran sum_energy_per_cycle_pb_mux[0to1]
+ param='sum_energy_per_cycle_pb_mux[0to0]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar'
Xmux_2level_size5[2] mux_2level_size5[2]->in[0] mux_2level_size5[2]->in[1] mux_2level_size5[2]->in[2] mux_2level_size5[2]->in[3] mux_2level_size5[2]->in[4] mux_2level_size5[2]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb sram[15]->outb sram[15]->out sram[16]->out sram[16]->outb sram[17]->out sram[17]->outb gvdd_mux_2level_size5[2] 0 mux_2level_size5
***** SRAM bits for MUX[2], level=2, select_path_id=0. *****
*****100100*****
Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[12]->out) 0
.nodeset V(sram[12]->outb) vsp
Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[13]->out) 0
.nodeset V(sram[13]->outb) vsp
Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[14]->out) 0
.nodeset V(sram[14]->outb) vsp
Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[15]->out) 0
.nodeset V(sram[15]->outb) vsp
Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[16]->out) 0
.nodeset V(sram[16]->outb) vsp
Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[17]->out) 0
.nodeset V(sram[17]->outb) vsp
***** Signal mux_2level_size5[2]->in[0] density = 0, probability=0.*****
Vmux_2level_size5[2]->in[0] mux_2level_size5[2]->in[0] 0
+ 0
***** Signal mux_2level_size5[2]->in[1] density = 0, probability=0.*****
Vmux_2level_size5[2]->in[1] mux_2level_size5[2]->in[1] 0
+ 0
***** Signal mux_2level_size5[2]->in[2] density = 0, probability=0.*****
Vmux_2level_size5[2]->in[2] mux_2level_size5[2]->in[2] 0
+ 0
***** Signal mux_2level_size5[2]->in[3] density = 0.1906, probability=0.4782.*****
Vmux_2level_size5[2]->in[3] mux_2level_size5[2]->in[3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_2level_size5[2]->in[4] density = 0.1906, probability=0.5218.*****
Vmux_2level_size5[2]->in[4] mux_2level_size5[2]->in[4] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgvdd_mux_2level_size5[2] gvdd_mux_2level_size5[2] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar trig v(mux_2level_size5[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_size5[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar trig v(mux_2level_size5[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_size5[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar when v(mux_2level_size5[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar trig v(mux_2level_size5[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_size5[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar when v(mux_2level_size5[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar trig v(mux_2level_size5[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_size5[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_size5[2]_leakage_power avg p(Vgvdd_mux_2level_size5[2]) from=0 to='clock_period'
.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar param='mux_2level_size5[2]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_size5[2]_dynamic_power avg p(Vgvdd_mux_2level_size5[2]) from='clock_period' to='7*clock_period'
.meas tran mux_2level_size5[2]_energy_per_cycle param='mux_2level_size5[2]_dynamic_power*clock_period'
.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar param='mux_2level_size5[2]_dynamic_power'
.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar*clock_period'
.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar avg p(Vgvdd_mux_2level_size5[2]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar'
.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar avg p(Vgvdd_mux_2level_size5[2]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar'
.meas tran sum_leakage_power_mux[0to2]
+ param='sum_leakage_power_mux[0to1]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar'
.meas tran sum_energy_per_cycle_mux[0to2]
+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar'
Xload_inv[2]_no0 mux_2level_size5[2]->out mux_2level_size5[2]->out_out[0] gvdd_load 0 inv size=5
.meas tran sum_leakage_power_pb_mux[0to2]
+ param='sum_leakage_power_pb_mux[0to1]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar'
.meas tran sum_energy_per_cycle_pb_mux[0to2]
+ param='sum_energy_per_cycle_pb_mux[0to1]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar'
Xmux_2level_size5[3] mux_2level_size5[3]->in[0] mux_2level_size5[3]->in[1] mux_2level_size5[3]->in[2] mux_2level_size5[3]->in[3] mux_2level_size5[3]->in[4] mux_2level_size5[3]->out sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb sram[20]->out sram[20]->outb sram[21]->outb sram[21]->out sram[22]->out sram[22]->outb sram[23]->out sram[23]->outb gvdd_mux_2level_size5[3] 0 mux_2level_size5
***** SRAM bits for MUX[3], level=2, select_path_id=0. *****
*****100100*****
Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[18]->out) 0
.nodeset V(sram[18]->outb) vsp
Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[19]->out) 0
.nodeset V(sram[19]->outb) vsp
Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[20]->out) 0
.nodeset V(sram[20]->outb) vsp
Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[21]->out) 0
.nodeset V(sram[21]->outb) vsp
Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[22]->out) 0
.nodeset V(sram[22]->outb) vsp
Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[23]->out) 0
.nodeset V(sram[23]->outb) vsp
***** Signal mux_2level_size5[3]->in[0] density = 0, probability=0.*****
Vmux_2level_size5[3]->in[0] mux_2level_size5[3]->in[0] 0
+ 0
***** Signal mux_2level_size5[3]->in[1] density = 0, probability=0.*****
Vmux_2level_size5[3]->in[1] mux_2level_size5[3]->in[1] 0
+ 0
***** Signal mux_2level_size5[3]->in[2] density = 0, probability=0.*****
Vmux_2level_size5[3]->in[2] mux_2level_size5[3]->in[2] 0
+ 0
***** Signal mux_2level_size5[3]->in[3] density = 0.1906, probability=0.4782.*****
Vmux_2level_size5[3]->in[3] mux_2level_size5[3]->in[3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_2level_size5[3]->in[4] density = 0.1906, probability=0.5218.*****
Vmux_2level_size5[3]->in[4] mux_2level_size5[3]->in[4] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgvdd_mux_2level_size5[3] gvdd_mux_2level_size5[3] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar trig v(mux_2level_size5[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_size5[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar trig v(mux_2level_size5[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_size5[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar when v(mux_2level_size5[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar trig v(mux_2level_size5[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_2level_size5[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar when v(mux_2level_size5[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar trig v(mux_2level_size5[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_2level_size5[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_2level_size5[3]_leakage_power avg p(Vgvdd_mux_2level_size5[3]) from=0 to='clock_period'
.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar param='mux_2level_size5[3]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_2level_size5[3]_dynamic_power avg p(Vgvdd_mux_2level_size5[3]) from='clock_period' to='7*clock_period'
.meas tran mux_2level_size5[3]_energy_per_cycle param='mux_2level_size5[3]_dynamic_power*clock_period'
.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar param='mux_2level_size5[3]_dynamic_power'
.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar*clock_period'
.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar avg p(Vgvdd_mux_2level_size5[3]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar'
.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar avg p(Vgvdd_mux_2level_size5[3]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar'
.meas tran sum_leakage_power_mux[0to3]
+ param='sum_leakage_power_mux[0to2]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar'
.meas tran sum_energy_per_cycle_mux[0to3]
+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar'
Xload_inv[3]_no0 mux_2level_size5[3]->out mux_2level_size5[3]->out_out[0] gvdd_load 0 inv size=5
.meas tran sum_leakage_power_pb_mux[0to3]
+ param='sum_leakage_power_pb_mux[0to2]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar'
.meas tran sum_energy_per_cycle_pb_mux[0to3]
+ param='sum_energy_per_cycle_pb_mux[0to2]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar'
Xmux_1level_tapbuf_size2[4] mux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->out sram[24]->outb sram[24]->out gvdd_mux_1level_tapbuf_size2[4] 0 mux_1level_tapbuf_size2
***** SRAM bits for MUX[4], level=1, select_path_id=0. *****
*****1*****
Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T
.nodeset V(sram[24]->out) 0
.nodeset V(sram[24]->outb) vsp
***** Signal mux_1level_tapbuf_size2[4]->in[0] density = 0.1906, probability=0.5218.*****
Vmux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[0] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal mux_1level_tapbuf_size2[4]->in[1] density = 0.099455, probability=0.5218.*****
Vmux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->in[1] 0
+ pulse(vsp 0 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*20.1096*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '20.1096*clock_period')
Vgvdd_mux_1level_tapbuf_size2[4] gvdd_mux_1level_tapbuf_size2[4] 0 vsp
***** Measurements *****
***** Rise delay *****
.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall delay *****
.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Rise timing period *****
.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period'
+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period'
***** Fall timing period *****
.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period'
+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period'
***** Leakage Power Measurement *****
.meas tran mux_1level_tapbuf_size2[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from=0 to='clock_period'
.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 param='mux_1level_tapbuf_size2[4]_leakage_power'
***** Dynamic Power Measurement *****
.meas tran mux_1level_tapbuf_size2[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='clock_period' to='7*clock_period'
.meas tran mux_1level_tapbuf_size2[4]_energy_per_cycle param='mux_1level_tapbuf_size2[4]_dynamic_power*clock_period'
.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 param='mux_1level_tapbuf_size2[4]_dynamic_power'
.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1*clock_period'
.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1'
.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1'
.meas tran sum_leakage_power_mux[0to4]
+ param='sum_leakage_power_mux[0to3]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1'
.meas tran sum_energy_per_cycle_mux[0to4]
+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1'
Xload_inv[4]_no0 mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_out[0] gvdd_load 0 inv size=1
Xload_inv[5]_no0 mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_out[1] gvdd_load 0 inv size=1
Xload_inv[6]_no0 mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_out[2] gvdd_load 0 inv size=1
Xload_inv[7]_no0 mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_out[3] gvdd_load 0 inv size=1
Xload_inv[8]_no0 mux_1level_tapbuf_size2[4]->out load_inv[8]_out gvdd_load 0 inv size=1
Xload_inv[9]_no0 mux_1level_tapbuf_size2[4]->out load_inv[9]_out gvdd_load 0 inv size=1
Xload_inv[10]_no0 mux_1level_tapbuf_size2[4]->out load_inv[10]_out gvdd_load 0 inv size=1
Xload_inv[11]_no0 mux_1level_tapbuf_size2[4]->out load_inv[11]_out gvdd_load 0 inv size=1
.meas tran sum_leakage_power_pb_mux[0to4]
+ param='sum_leakage_power_pb_mux[0to3]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1'
.meas tran sum_energy_per_cycle_pb_mux[0to4]
+ param='sum_energy_per_cycle_pb_mux[0to3]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period'
.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='7*clock_period'
.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period'
.meas tran total_leakage_power_mux[0to4]
+ param='sum_leakage_power_mux[0to4]'
.meas tran total_energy_per_cycle_mux[0to4]
+ param='sum_energy_per_cycle_mux[0to4]'
.meas tran total_leakage_power_pb_mux
+ param='sum_leakage_power_pb_mux[0to4]'
.meas tran total_energy_per_cycle_pb_mux
+ param='sum_energy_per_cycle_pb_mux[0to4]'
.end

64
examples/spice_test_example_1/run_hspice_sim.sh
View File

@ -1,64 +0,0 @@
echo Number of clock cycles in simulation: 7
echo Simulation progress: 0 Finish, 21 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/top_tb/example_1_top.sp -o ./spice_test_example_1/results/example_1_top.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 1 Finish, 20 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/grid_tb/example_1_grid1_1_grid_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_grid_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 2 Finish, 19 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/hardlogic_tb/example_1_grid1_1_hardlogic_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_hardlogic_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 3 Finish, 18 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/lut_tb/example_1_grid1_1_lut_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_lut_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 4 Finish, 17 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb1_1_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_1_sb_testbench.lis
echo Number of clock cycles in simulation: 2
echo Simulation progress: 5 Finish, 16 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb1_0_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_0_sb_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 6 Finish, 15 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb0_1_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_1_sb_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 7 Finish, 14 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb0_0_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_0_sb_testbench.lis
echo Number of clock cycles in simulation: 2
echo Simulation progress: 8 Finish, 13 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cby1_1_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cby1_1_cb_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 9 Finish, 12 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cby0_1_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cby0_1_cb_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 10 Finish, 11 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cbx1_1_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_1_cb_testbench.lis
echo Number of clock cycles in simulation: 2
echo Simulation progress: 11 Finish, 10 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cbx1_0_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_0_cb_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 12 Finish, 9 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb1_1_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_1_sbmux_testbench.lis
echo Number of clock cycles in simulation: 2
echo Simulation progress: 13 Finish, 8 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb1_0_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_0_sbmux_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 14 Finish, 7 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb0_1_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_1_sbmux_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 15 Finish, 6 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb0_0_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_0_sbmux_testbench.lis
echo Number of clock cycles in simulation: 2
echo Simulation progress: 16 Finish, 5 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cby1_1_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cby1_1_cbmux_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 17 Finish, 4 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cby0_1_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cby0_1_cbmux_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 18 Finish, 3 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cbx1_1_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_1_cbmux_testbench.lis
echo Number of clock cycles in simulation: 2
echo Simulation progress: 19 Finish, 2 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cbx1_0_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_0_cbmux_testbench.lis
echo Number of clock cycles in simulation: 7
echo Simulation progress: 20 Finish, 1 to go, total 21
hspice64 -mt 8 -i ./spice_test_example_1/pb_mux_tb/example_1_grid1_1_pbmux_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_pbmux_testbench.lis
echo Simulation progress: 21 Finish, 0 to go, total 21

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@ -1,399 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_sram_sbs
****** Include subckt netlists: Switch Block[0][0] *****
.include './spice_test_example_1/subckt/sb_0_0.sp'
***** Call defined Switch Box[0][0] *****
Xsb[0][0]
+ chany[0][1]_out[0] chany[0][1]_in[1] chany[0][1]_out[2] chany[0][1]_in[3] chany[0][1]_out[4] chany[0][1]_in[5] chany[0][1]_out[6] chany[0][1]_in[7] chany[0][1]_out[8] chany[0][1]_in[9] chany[0][1]_out[10] chany[0][1]_in[11] chany[0][1]_out[12] chany[0][1]_in[13] chany[0][1]_out[14] chany[0][1]_in[15] chany[0][1]_out[16] chany[0][1]_in[17] chany[0][1]_out[18] chany[0][1]_in[19] chany[0][1]_out[20] chany[0][1]_in[21] chany[0][1]_out[22] chany[0][1]_in[23] chany[0][1]_out[24] chany[0][1]_in[25] chany[0][1]_out[26] chany[0][1]_in[27] chany[0][1]_out[28] chany[0][1]_in[29]
+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15]
+ chanx[1][0]_out[0] chanx[1][0]_in[1] chanx[1][0]_out[2] chanx[1][0]_in[3] chanx[1][0]_out[4] chanx[1][0]_in[5] chanx[1][0]_out[6] chanx[1][0]_in[7] chanx[1][0]_out[8] chanx[1][0]_in[9] chanx[1][0]_out[10] chanx[1][0]_in[11] chanx[1][0]_out[12] chanx[1][0]_in[13] chanx[1][0]_out[14] chanx[1][0]_in[15] chanx[1][0]_out[16] chanx[1][0]_in[17] chanx[1][0]_out[18] chanx[1][0]_in[19] chanx[1][0]_out[20] chanx[1][0]_in[21] chanx[1][0]_out[22] chanx[1][0]_in[23] chanx[1][0]_out[24] chanx[1][0]_in[25] chanx[1][0]_out[26] chanx[1][0]_in[27] chanx[1][0]_out[28] chanx[1][0]_in[29]
+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15]
+
+
+
+
+ gvdd_sb[0][0] 0 sb[0][0]
**** Load for rr_node[197] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=0, type=5 *****
Xchan_chany[0][1]_out[0]_loadlvl[0]_out chany[0][1]_out[0] chany[0][1]_out[0]_loadlvl[0]_out chany[0][1]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[0]_no0 chany[0][1]_out[0]_loadlvl[0]_out chany[0][1]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 chany[0][1]_out[0]_loadlvl[0]_midout chany[0][1]_out[0]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[1] density = 0, probability=0.*****
Vchany[0][1]_in[1] chany[0][1]_in[1] 0
+ 0
**** Load for rr_node[199] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=2, type=5 *****
Xchan_chany[0][1]_out[2]_loadlvl[0]_out chany[0][1]_out[2] chany[0][1]_out[2]_loadlvl[0]_out chany[0][1]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[2]_no0 chany[0][1]_out[2]_loadlvl[0]_out chany[0][1]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[3]_no0 chany[0][1]_out[2]_loadlvl[0]_midout chany[0][1]_out[2]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[3] density = 0, probability=0.*****
Vchany[0][1]_in[3] chany[0][1]_in[3] 0
+ 0
**** Load for rr_node[201] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=4, type=5 *****
Xchan_chany[0][1]_out[4]_loadlvl[0]_out chany[0][1]_out[4] chany[0][1]_out[4]_loadlvl[0]_out chany[0][1]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[4]_no0 chany[0][1]_out[4]_loadlvl[0]_out chany[0][1]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[5]_no0 chany[0][1]_out[4]_loadlvl[0]_midout chany[0][1]_out[4]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[5] density = 0, probability=0.*****
Vchany[0][1]_in[5] chany[0][1]_in[5] 0
+ 0
**** Load for rr_node[203] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=6, type=5 *****
Xchan_chany[0][1]_out[6]_loadlvl[0]_out chany[0][1]_out[6] chany[0][1]_out[6]_loadlvl[0]_out chany[0][1]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[6]_no0 chany[0][1]_out[6]_loadlvl[0]_out chany[0][1]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[7]_no0 chany[0][1]_out[6]_loadlvl[0]_midout chany[0][1]_out[6]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[8]_no0 chany[0][1]_out[6]_loadlvl[0]_midout chany[0][1]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[7] density = 0, probability=0.*****
Vchany[0][1]_in[7] chany[0][1]_in[7] 0
+ 0
**** Load for rr_node[205] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=8, type=5 *****
Xchan_chany[0][1]_out[8]_loadlvl[0]_out chany[0][1]_out[8] chany[0][1]_out[8]_loadlvl[0]_out chany[0][1]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[9]_no0 chany[0][1]_out[8]_loadlvl[0]_out chany[0][1]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[10]_no0 chany[0][1]_out[8]_loadlvl[0]_midout chany[0][1]_out[8]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[9] density = 0, probability=0.*****
Vchany[0][1]_in[9] chany[0][1]_in[9] 0
+ 0
**** Load for rr_node[207] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=10, type=5 *****
Xchan_chany[0][1]_out[10]_loadlvl[0]_out chany[0][1]_out[10] chany[0][1]_out[10]_loadlvl[0]_out chany[0][1]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[11]_no0 chany[0][1]_out[10]_loadlvl[0]_out chany[0][1]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[12]_no0 chany[0][1]_out[10]_loadlvl[0]_midout chany[0][1]_out[10]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[13]_no0 chany[0][1]_out[10]_loadlvl[0]_midout chany[0][1]_out[10]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[11] density = 0, probability=0.*****
Vchany[0][1]_in[11] chany[0][1]_in[11] 0
+ 0
**** Load for rr_node[209] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=12, type=5 *****
Xchan_chany[0][1]_out[12]_loadlvl[0]_out chany[0][1]_out[12] chany[0][1]_out[12]_loadlvl[0]_out chany[0][1]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[14]_no0 chany[0][1]_out[12]_loadlvl[0]_out chany[0][1]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[15]_no0 chany[0][1]_out[12]_loadlvl[0]_midout chany[0][1]_out[12]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[13] density = 0, probability=0.*****
Vchany[0][1]_in[13] chany[0][1]_in[13] 0
+ 0
**** Load for rr_node[211] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=14, type=5 *****
Xchan_chany[0][1]_out[14]_loadlvl[0]_out chany[0][1]_out[14] chany[0][1]_out[14]_loadlvl[0]_out chany[0][1]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[16]_no0 chany[0][1]_out[14]_loadlvl[0]_out chany[0][1]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[17]_no0 chany[0][1]_out[14]_loadlvl[0]_midout chany[0][1]_out[14]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[15] density = 0, probability=0.*****
Vchany[0][1]_in[15] chany[0][1]_in[15] 0
+ 0
**** Load for rr_node[213] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=16, type=5 *****
Xchan_chany[0][1]_out[16]_loadlvl[0]_out chany[0][1]_out[16] chany[0][1]_out[16]_loadlvl[0]_out chany[0][1]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[18]_no0 chany[0][1]_out[16]_loadlvl[0]_out chany[0][1]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[19]_no0 chany[0][1]_out[16]_loadlvl[0]_midout chany[0][1]_out[16]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[17] density = 0, probability=0.*****
Vchany[0][1]_in[17] chany[0][1]_in[17] 0
+ 0
**** Load for rr_node[215] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=18, type=5 *****
Xchan_chany[0][1]_out[18]_loadlvl[0]_out chany[0][1]_out[18] chany[0][1]_out[18]_loadlvl[0]_out chany[0][1]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[20]_no0 chany[0][1]_out[18]_loadlvl[0]_out chany[0][1]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[21]_no0 chany[0][1]_out[18]_loadlvl[0]_midout chany[0][1]_out[18]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[19] density = 0, probability=0.*****
Vchany[0][1]_in[19] chany[0][1]_in[19] 0
+ 0
**** Load for rr_node[217] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=20, type=5 *****
Xchan_chany[0][1]_out[20]_loadlvl[0]_out chany[0][1]_out[20] chany[0][1]_out[20]_loadlvl[0]_out chany[0][1]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[22]_no0 chany[0][1]_out[20]_loadlvl[0]_out chany[0][1]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[23]_no0 chany[0][1]_out[20]_loadlvl[0]_midout chany[0][1]_out[20]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[21] density = 0, probability=0.*****
Vchany[0][1]_in[21] chany[0][1]_in[21] 0
+ 0
**** Load for rr_node[219] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=22, type=5 *****
Xchan_chany[0][1]_out[22]_loadlvl[0]_out chany[0][1]_out[22] chany[0][1]_out[22]_loadlvl[0]_out chany[0][1]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[24]_no0 chany[0][1]_out[22]_loadlvl[0]_out chany[0][1]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[25]_no0 chany[0][1]_out[22]_loadlvl[0]_midout chany[0][1]_out[22]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[23] density = 0, probability=0.*****
Vchany[0][1]_in[23] chany[0][1]_in[23] 0
+ 0
**** Load for rr_node[221] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=24, type=5 *****
Xchan_chany[0][1]_out[24]_loadlvl[0]_out chany[0][1]_out[24] chany[0][1]_out[24]_loadlvl[0]_out chany[0][1]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[26]_no0 chany[0][1]_out[24]_loadlvl[0]_out chany[0][1]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[27]_no0 chany[0][1]_out[24]_loadlvl[0]_midout chany[0][1]_out[24]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[25] density = 0, probability=0.*****
Vchany[0][1]_in[25] chany[0][1]_in[25] 0
+ 0
**** Load for rr_node[223] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=26, type=5 *****
Xchan_chany[0][1]_out[26]_loadlvl[0]_out chany[0][1]_out[26] chany[0][1]_out[26]_loadlvl[0]_out chany[0][1]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[28]_no0 chany[0][1]_out[26]_loadlvl[0]_out chany[0][1]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[29]_no0 chany[0][1]_out[26]_loadlvl[0]_midout chany[0][1]_out[26]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[30]_no0 chany[0][1]_out[26]_loadlvl[0]_midout chany[0][1]_out[26]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[27] density = 0.1906, probability=0.4782.*****
Vchany[0][1]_in[27] chany[0][1]_in[27] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
**** Load for rr_node[225] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=28, type=5 *****
Xchan_chany[0][1]_out[28]_loadlvl[0]_out chany[0][1]_out[28] chany[0][1]_out[28]_loadlvl[0]_out chany[0][1]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[31]_no0 chany[0][1]_out[28]_loadlvl[0]_out chany[0][1]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[32]_no0 chany[0][1]_out[28]_loadlvl[0]_midout chany[0][1]_out[28]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[29] density = 0, probability=0.*****
Vchany[0][1]_in[29] chany[0][1]_in[29] 0
+ 0
Vgrid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][1] 0
+ 0
Vgrid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][3] 0
+ 0
Vgrid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][5] 0
+ 0
Vgrid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][7] 0
+ 0
Vgrid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][9] 0
+ 0
Vgrid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][11] 0
+ 0
Vgrid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][13] 0
+ 0
Vgrid[0][1]_pin[0][1][15] grid[0][1]_pin[0][1][15] 0
+ 0
**** Load for rr_node[137] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=0, type=4 *****
Xchan_chanx[1][0]_out[0]_loadlvl[0]_out chanx[1][0]_out[0] chanx[1][0]_out[0]_loadlvl[0]_out chanx[1][0]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[33]_no0 chanx[1][0]_out[0]_loadlvl[0]_out chanx[1][0]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[34]_no0 chanx[1][0]_out[0]_loadlvl[0]_midout chanx[1][0]_out[0]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[35]_no0 chanx[1][0]_out[0]_loadlvl[0]_midout chanx[1][0]_out[0]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[1] density = 0, probability=0.*****
Vchanx[1][0]_in[1] chanx[1][0]_in[1] 0
+ 0
**** Load for rr_node[139] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=2, type=4 *****
Xchan_chanx[1][0]_out[2]_loadlvl[0]_out chanx[1][0]_out[2] chanx[1][0]_out[2]_loadlvl[0]_out chanx[1][0]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[36]_no0 chanx[1][0]_out[2]_loadlvl[0]_out chanx[1][0]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[37]_no0 chanx[1][0]_out[2]_loadlvl[0]_midout chanx[1][0]_out[2]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[3] density = 0, probability=0.*****
Vchanx[1][0]_in[3] chanx[1][0]_in[3] 0
+ 0
**** Load for rr_node[141] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=4, type=4 *****
Xchan_chanx[1][0]_out[4]_loadlvl[0]_out chanx[1][0]_out[4] chanx[1][0]_out[4]_loadlvl[0]_out chanx[1][0]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[38]_no0 chanx[1][0]_out[4]_loadlvl[0]_out chanx[1][0]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[39]_no0 chanx[1][0]_out[4]_loadlvl[0]_midout chanx[1][0]_out[4]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[5] density = 0, probability=0.*****
Vchanx[1][0]_in[5] chanx[1][0]_in[5] 0
+ 0
**** Load for rr_node[143] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=6, type=4 *****
Xchan_chanx[1][0]_out[6]_loadlvl[0]_out chanx[1][0]_out[6] chanx[1][0]_out[6]_loadlvl[0]_out chanx[1][0]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[40]_no0 chanx[1][0]_out[6]_loadlvl[0]_out chanx[1][0]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[41]_no0 chanx[1][0]_out[6]_loadlvl[0]_midout chanx[1][0]_out[6]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[42]_no0 chanx[1][0]_out[6]_loadlvl[0]_midout chanx[1][0]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[7] density = 0, probability=0.*****
Vchanx[1][0]_in[7] chanx[1][0]_in[7] 0
+ 0
**** Load for rr_node[145] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=8, type=4 *****
Xchan_chanx[1][0]_out[8]_loadlvl[0]_out chanx[1][0]_out[8] chanx[1][0]_out[8]_loadlvl[0]_out chanx[1][0]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[43]_no0 chanx[1][0]_out[8]_loadlvl[0]_out chanx[1][0]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[44]_no0 chanx[1][0]_out[8]_loadlvl[0]_midout chanx[1][0]_out[8]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[9] density = 0, probability=0.*****
Vchanx[1][0]_in[9] chanx[1][0]_in[9] 0
+ 0
**** Load for rr_node[147] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=10, type=4 *****
Xchan_chanx[1][0]_out[10]_loadlvl[0]_out chanx[1][0]_out[10] chanx[1][0]_out[10]_loadlvl[0]_out chanx[1][0]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[45]_no0 chanx[1][0]_out[10]_loadlvl[0]_out chanx[1][0]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[46]_no0 chanx[1][0]_out[10]_loadlvl[0]_midout chanx[1][0]_out[10]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[11] density = 0, probability=0.*****
Vchanx[1][0]_in[11] chanx[1][0]_in[11] 0
+ 0
**** Load for rr_node[149] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=12, type=4 *****
Xchan_chanx[1][0]_out[12]_loadlvl[0]_out chanx[1][0]_out[12] chanx[1][0]_out[12]_loadlvl[0]_out chanx[1][0]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[47]_no0 chanx[1][0]_out[12]_loadlvl[0]_out chanx[1][0]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[48]_no0 chanx[1][0]_out[12]_loadlvl[0]_midout chanx[1][0]_out[12]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[13] density = 0, probability=0.*****
Vchanx[1][0]_in[13] chanx[1][0]_in[13] 0
+ 0
**** Load for rr_node[151] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=14, type=4 *****
Xchan_chanx[1][0]_out[14]_loadlvl[0]_out chanx[1][0]_out[14] chanx[1][0]_out[14]_loadlvl[0]_out chanx[1][0]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[49]_no0 chanx[1][0]_out[14]_loadlvl[0]_out chanx[1][0]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[50]_no0 chanx[1][0]_out[14]_loadlvl[0]_midout chanx[1][0]_out[14]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[15] density = 0, probability=0.*****
Vchanx[1][0]_in[15] chanx[1][0]_in[15] 0
+ 0
**** Load for rr_node[153] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=16, type=4 *****
Xchan_chanx[1][0]_out[16]_loadlvl[0]_out chanx[1][0]_out[16] chanx[1][0]_out[16]_loadlvl[0]_out chanx[1][0]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[51]_no0 chanx[1][0]_out[16]_loadlvl[0]_out chanx[1][0]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[52]_no0 chanx[1][0]_out[16]_loadlvl[0]_midout chanx[1][0]_out[16]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[17] density = 0, probability=0.*****
Vchanx[1][0]_in[17] chanx[1][0]_in[17] 0
+ 0
**** Load for rr_node[155] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=18, type=4 *****
Xchan_chanx[1][0]_out[18]_loadlvl[0]_out chanx[1][0]_out[18] chanx[1][0]_out[18]_loadlvl[0]_out chanx[1][0]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[53]_no0 chanx[1][0]_out[18]_loadlvl[0]_out chanx[1][0]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[54]_no0 chanx[1][0]_out[18]_loadlvl[0]_midout chanx[1][0]_out[18]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[19] density = 0, probability=0.*****
Vchanx[1][0]_in[19] chanx[1][0]_in[19] 0
+ 0
**** Load for rr_node[157] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=20, type=4 *****
Xchan_chanx[1][0]_out[20]_loadlvl[0]_out chanx[1][0]_out[20] chanx[1][0]_out[20]_loadlvl[0]_out chanx[1][0]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[55]_no0 chanx[1][0]_out[20]_loadlvl[0]_out chanx[1][0]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[56]_no0 chanx[1][0]_out[20]_loadlvl[0]_midout chanx[1][0]_out[20]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[21] density = 0, probability=0.*****
Vchanx[1][0]_in[21] chanx[1][0]_in[21] 0
+ 0
**** Load for rr_node[159] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=22, type=4 *****
Xchan_chanx[1][0]_out[22]_loadlvl[0]_out chanx[1][0]_out[22] chanx[1][0]_out[22]_loadlvl[0]_out chanx[1][0]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[57]_no0 chanx[1][0]_out[22]_loadlvl[0]_out chanx[1][0]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[58]_no0 chanx[1][0]_out[22]_loadlvl[0]_midout chanx[1][0]_out[22]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[59]_no0 chanx[1][0]_out[22]_loadlvl[0]_midout chanx[1][0]_out[22]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[23] density = 0, probability=0.*****
Vchanx[1][0]_in[23] chanx[1][0]_in[23] 0
+ 0
**** Load for rr_node[161] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=24, type=4 *****
Xchan_chanx[1][0]_out[24]_loadlvl[0]_out chanx[1][0]_out[24] chanx[1][0]_out[24]_loadlvl[0]_out chanx[1][0]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[60]_no0 chanx[1][0]_out[24]_loadlvl[0]_out chanx[1][0]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[61]_no0 chanx[1][0]_out[24]_loadlvl[0]_midout chanx[1][0]_out[24]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[25] density = 0, probability=0.*****
Vchanx[1][0]_in[25] chanx[1][0]_in[25] 0
+ 0
**** Load for rr_node[163] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=26, type=4 *****
Xchan_chanx[1][0]_out[26]_loadlvl[0]_out chanx[1][0]_out[26] chanx[1][0]_out[26]_loadlvl[0]_out chanx[1][0]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[62]_no0 chanx[1][0]_out[26]_loadlvl[0]_out chanx[1][0]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[63]_no0 chanx[1][0]_out[26]_loadlvl[0]_midout chanx[1][0]_out[26]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[27] density = 0, probability=0.*****
Vchanx[1][0]_in[27] chanx[1][0]_in[27] 0
+ 0
**** Load for rr_node[165] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=28, type=4 *****
Xchan_chanx[1][0]_out[28]_loadlvl[0]_out chanx[1][0]_out[28] chanx[1][0]_out[28]_loadlvl[0]_out chanx[1][0]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[64]_no0 chanx[1][0]_out[28]_loadlvl[0]_out chanx[1][0]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[65]_no0 chanx[1][0]_out[28]_loadlvl[0]_midout chanx[1][0]_out[28]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[29] density = 0, probability=0.*****
Vchanx[1][0]_in[29] chanx[1][0]_in[29] 0
+ 0
Vgrid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][1] 0
+ 0
Vgrid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][3] 0
+ 0
Vgrid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][5] 0
+ 0
Vgrid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][7] 0
+ 0
Vgrid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][9] 0
+ 0
Vgrid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][11] 0
+ 0
Vgrid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][13] 0
+ 0
Vgrid[1][0]_pin[0][0][15] grid[1][0]_pin[0][0][15] 0
+ 0
***** Voltage supplies *****
Vgvdd_sb[0][0] gvdd_sb[0][0] 0 vsp
Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
***** Measurements *****
***** Leakage Power Measurement *****
.meas tran leakage_power_sb avg p(Vgvdd_sb[0][0]) from=0 to='clock_period'
.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period'
***** Dynamic Power Measurement *****
.meas tran dynamic_power_sb avg p(Vgvdd_sb[0][0]) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period'
.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
.end

409
examples/spice_test_example_1/sb_tb/example_1_sb0_1_sb_testbench.sp
View File

@ -1,409 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_sram_sbs
****** Include subckt netlists: Switch Block[0][1] *****
.include './spice_test_example_1/subckt/sb_0_1.sp'
***** Call defined Switch Box[0][1] *****
Xsb[0][1]
+
+
+ chanx[1][1]_out[0] chanx[1][1]_in[1] chanx[1][1]_out[2] chanx[1][1]_in[3] chanx[1][1]_out[4] chanx[1][1]_in[5] chanx[1][1]_out[6] chanx[1][1]_in[7] chanx[1][1]_out[8] chanx[1][1]_in[9] chanx[1][1]_out[10] chanx[1][1]_in[11] chanx[1][1]_out[12] chanx[1][1]_in[13] chanx[1][1]_out[14] chanx[1][1]_in[15] chanx[1][1]_out[16] chanx[1][1]_in[17] chanx[1][1]_out[18] chanx[1][1]_in[19] chanx[1][1]_out[20] chanx[1][1]_in[21] chanx[1][1]_out[22] chanx[1][1]_in[23] chanx[1][1]_out[24] chanx[1][1]_in[25] chanx[1][1]_out[26] chanx[1][1]_in[27] chanx[1][1]_out[28] chanx[1][1]_in[29]
+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4]
+ chany[0][1]_in[0] chany[0][1]_out[1] chany[0][1]_in[2] chany[0][1]_out[3] chany[0][1]_in[4] chany[0][1]_out[5] chany[0][1]_in[6] chany[0][1]_out[7] chany[0][1]_in[8] chany[0][1]_out[9] chany[0][1]_in[10] chany[0][1]_out[11] chany[0][1]_in[12] chany[0][1]_out[13] chany[0][1]_in[14] chany[0][1]_out[15] chany[0][1]_in[16] chany[0][1]_out[17] chany[0][1]_in[18] chany[0][1]_out[19] chany[0][1]_in[20] chany[0][1]_out[21] chany[0][1]_in[22] chany[0][1]_out[23] chany[0][1]_in[24] chany[0][1]_out[25] chany[0][1]_in[26] chany[0][1]_out[27] chany[0][1]_in[28] chany[0][1]_out[29]
+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15]
+
+
+ gvdd_sb[0][1] 0 sb[0][1]
**** Load for rr_node[167] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=4 *****
Xchan_chanx[1][1]_out[0]_loadlvl[0]_out chanx[1][1]_out[0] chanx[1][1]_out[0]_loadlvl[0]_out chanx[1][1]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[0]_no0 chanx[1][1]_out[0]_loadlvl[0]_out chanx[1][1]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 chanx[1][1]_out[0]_loadlvl[0]_midout chanx[1][1]_out[0]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[1] density = 0.1906, probability=0.4782.*****
Vchanx[1][1]_in[1] chanx[1][1]_in[1] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
**** Load for rr_node[169] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=4 *****
Xchan_chanx[1][1]_out[2]_loadlvl[0]_out chanx[1][1]_out[2] chanx[1][1]_out[2]_loadlvl[0]_out chanx[1][1]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[2]_no0 chanx[1][1]_out[2]_loadlvl[0]_out chanx[1][1]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[3]_no0 chanx[1][1]_out[2]_loadlvl[0]_midout chanx[1][1]_out[2]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[3] density = 0.1906, probability=0.5218.*****
Vchanx[1][1]_in[3] chanx[1][1]_in[3] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
**** Load for rr_node[171] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=4 *****
Xchan_chanx[1][1]_out[4]_loadlvl[0]_out chanx[1][1]_out[4] chanx[1][1]_out[4]_loadlvl[0]_out chanx[1][1]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[4]_no0 chanx[1][1]_out[4]_loadlvl[0]_out chanx[1][1]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[5]_no0 chanx[1][1]_out[4]_loadlvl[0]_midout chanx[1][1]_out[4]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[5] density = 0, probability=0.*****
Vchanx[1][1]_in[5] chanx[1][1]_in[5] 0
+ 0
**** Load for rr_node[173] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=4 *****
Xchan_chanx[1][1]_out[6]_loadlvl[0]_out chanx[1][1]_out[6] chanx[1][1]_out[6]_loadlvl[0]_out chanx[1][1]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[6]_no0 chanx[1][1]_out[6]_loadlvl[0]_out chanx[1][1]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[7]_no0 chanx[1][1]_out[6]_loadlvl[0]_midout chanx[1][1]_out[6]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[8]_no0 chanx[1][1]_out[6]_loadlvl[0]_midout chanx[1][1]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[7] density = 0, probability=0.*****
Vchanx[1][1]_in[7] chanx[1][1]_in[7] 0
+ 0
**** Load for rr_node[175] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=4 *****
Xchan_chanx[1][1]_out[8]_loadlvl[0]_out chanx[1][1]_out[8] chanx[1][1]_out[8]_loadlvl[0]_out chanx[1][1]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[9]_no0 chanx[1][1]_out[8]_loadlvl[0]_out chanx[1][1]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[10]_no0 chanx[1][1]_out[8]_loadlvl[0]_midout chanx[1][1]_out[8]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[9] density = 0, probability=0.*****
Vchanx[1][1]_in[9] chanx[1][1]_in[9] 0
+ 0
**** Load for rr_node[177] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=4 *****
Xchan_chanx[1][1]_out[10]_loadlvl[0]_out chanx[1][1]_out[10] chanx[1][1]_out[10]_loadlvl[0]_out chanx[1][1]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[11]_no0 chanx[1][1]_out[10]_loadlvl[0]_out chanx[1][1]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[12]_no0 chanx[1][1]_out[10]_loadlvl[0]_midout chanx[1][1]_out[10]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[11] density = 0, probability=0.*****
Vchanx[1][1]_in[11] chanx[1][1]_in[11] 0
+ 0
**** Load for rr_node[179] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=4 *****
Xchan_chanx[1][1]_out[12]_loadlvl[0]_out chanx[1][1]_out[12] chanx[1][1]_out[12]_loadlvl[0]_out chanx[1][1]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[13]_no0 chanx[1][1]_out[12]_loadlvl[0]_out chanx[1][1]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[14]_no0 chanx[1][1]_out[12]_loadlvl[0]_midout chanx[1][1]_out[12]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[15]_no0 chanx[1][1]_out[12]_loadlvl[0]_midout chanx[1][1]_out[12]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
Xload_inv[16]_no0 chanx[1][1]_out[12]_loadlvl[0]_midout chanx[1][1]_out[12]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[13] density = 0, probability=0.*****
Vchanx[1][1]_in[13] chanx[1][1]_in[13] 0
+ 0
**** Load for rr_node[181] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=4 *****
Xchan_chanx[1][1]_out[14]_loadlvl[0]_out chanx[1][1]_out[14] chanx[1][1]_out[14]_loadlvl[0]_out chanx[1][1]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[17]_no0 chanx[1][1]_out[14]_loadlvl[0]_out chanx[1][1]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[18]_no0 chanx[1][1]_out[14]_loadlvl[0]_midout chanx[1][1]_out[14]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[15] density = 0, probability=0.*****
Vchanx[1][1]_in[15] chanx[1][1]_in[15] 0
+ 0
**** Load for rr_node[183] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=4 *****
Xchan_chanx[1][1]_out[16]_loadlvl[0]_out chanx[1][1]_out[16] chanx[1][1]_out[16]_loadlvl[0]_out chanx[1][1]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[19]_no0 chanx[1][1]_out[16]_loadlvl[0]_out chanx[1][1]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[20]_no0 chanx[1][1]_out[16]_loadlvl[0]_midout chanx[1][1]_out[16]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[17] density = 0, probability=0.*****
Vchanx[1][1]_in[17] chanx[1][1]_in[17] 0
+ 0
**** Load for rr_node[185] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=4 *****
Xchan_chanx[1][1]_out[18]_loadlvl[0]_out chanx[1][1]_out[18] chanx[1][1]_out[18]_loadlvl[0]_out chanx[1][1]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[21]_no0 chanx[1][1]_out[18]_loadlvl[0]_out chanx[1][1]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[22]_no0 chanx[1][1]_out[18]_loadlvl[0]_midout chanx[1][1]_out[18]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[19] density = 0, probability=0.*****
Vchanx[1][1]_in[19] chanx[1][1]_in[19] 0
+ 0
**** Load for rr_node[187] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=4 *****
Xchan_chanx[1][1]_out[20]_loadlvl[0]_out chanx[1][1]_out[20] chanx[1][1]_out[20]_loadlvl[0]_out chanx[1][1]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[23]_no0 chanx[1][1]_out[20]_loadlvl[0]_out chanx[1][1]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[24]_no0 chanx[1][1]_out[20]_loadlvl[0]_midout chanx[1][1]_out[20]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[21] density = 0, probability=0.*****
Vchanx[1][1]_in[21] chanx[1][1]_in[21] 0
+ 0
**** Load for rr_node[189] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=4 *****
Xchan_chanx[1][1]_out[22]_loadlvl[0]_out chanx[1][1]_out[22] chanx[1][1]_out[22]_loadlvl[0]_out chanx[1][1]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[25]_no0 chanx[1][1]_out[22]_loadlvl[0]_out chanx[1][1]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[26]_no0 chanx[1][1]_out[22]_loadlvl[0]_midout chanx[1][1]_out[22]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[23] density = 0, probability=0.*****
Vchanx[1][1]_in[23] chanx[1][1]_in[23] 0
+ 0
**** Load for rr_node[191] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=4 *****
Xchan_chanx[1][1]_out[24]_loadlvl[0]_out chanx[1][1]_out[24] chanx[1][1]_out[24]_loadlvl[0]_out chanx[1][1]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[27]_no0 chanx[1][1]_out[24]_loadlvl[0]_out chanx[1][1]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[28]_no0 chanx[1][1]_out[24]_loadlvl[0]_midout chanx[1][1]_out[24]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[25] density = 0, probability=0.*****
Vchanx[1][1]_in[25] chanx[1][1]_in[25] 0
+ 0
**** Load for rr_node[193] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=4 *****
Xchan_chanx[1][1]_out[26]_loadlvl[0]_out chanx[1][1]_out[26] chanx[1][1]_out[26]_loadlvl[0]_out chanx[1][1]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[29]_no0 chanx[1][1]_out[26]_loadlvl[0]_out chanx[1][1]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[30]_no0 chanx[1][1]_out[26]_loadlvl[0]_midout chanx[1][1]_out[26]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[27] density = 0, probability=0.*****
Vchanx[1][1]_in[27] chanx[1][1]_in[27] 0
+ 0
**** Load for rr_node[195] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=4 *****
Xchan_chanx[1][1]_out[28]_loadlvl[0]_out chanx[1][1]_out[28] chanx[1][1]_out[28]_loadlvl[0]_out chanx[1][1]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[31]_no0 chanx[1][1]_out[28]_loadlvl[0]_out chanx[1][1]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[32]_no0 chanx[1][1]_out[28]_loadlvl[0]_midout chanx[1][1]_out[28]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[29] density = 0.1906, probability=0.4782.*****
Vchanx[1][1]_in[29] chanx[1][1]_in[29] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgrid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][1] 0
+ 0
Vgrid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][3] 0
+ 0
Vgrid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][5] 0
+ 0
Vgrid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][7] 0
+ 0
Vgrid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][9] 0
+ 0
Vgrid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][11] 0
+ 0
Vgrid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][13] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgrid[1][2]_pin[0][2][15] grid[1][2]_pin[0][2][15] 0
+ 0
Vgrid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Signal chany[0][1]_in[0] density = 0, probability=0.*****
Vchany[0][1]_in[0] chany[0][1]_in[0] 0
+ 0
**** Load for rr_node[198] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=1, type=5 *****
Xchan_chany[0][1]_out[1]_loadlvl[0]_out chany[0][1]_out[1] chany[0][1]_out[1]_loadlvl[0]_out chany[0][1]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[33]_no0 chany[0][1]_out[1]_loadlvl[0]_out chany[0][1]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[34]_no0 chany[0][1]_out[1]_loadlvl[0]_midout chany[0][1]_out[1]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[2] density = 0, probability=0.*****
Vchany[0][1]_in[2] chany[0][1]_in[2] 0
+ 0
**** Load for rr_node[200] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=3, type=5 *****
Xchan_chany[0][1]_out[3]_loadlvl[0]_out chany[0][1]_out[3] chany[0][1]_out[3]_loadlvl[0]_out chany[0][1]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[35]_no0 chany[0][1]_out[3]_loadlvl[0]_out chany[0][1]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[36]_no0 chany[0][1]_out[3]_loadlvl[0]_midout chany[0][1]_out[3]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[4] density = 0, probability=0.*****
Vchany[0][1]_in[4] chany[0][1]_in[4] 0
+ 0
**** Load for rr_node[202] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=5, type=5 *****
Xchan_chany[0][1]_out[5]_loadlvl[0]_out chany[0][1]_out[5] chany[0][1]_out[5]_loadlvl[0]_out chany[0][1]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[37]_no0 chany[0][1]_out[5]_loadlvl[0]_out chany[0][1]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[38]_no0 chany[0][1]_out[5]_loadlvl[0]_midout chany[0][1]_out[5]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[6] density = 0, probability=0.*****
Vchany[0][1]_in[6] chany[0][1]_in[6] 0
+ 0
**** Load for rr_node[204] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=7, type=5 *****
Xchan_chany[0][1]_out[7]_loadlvl[0]_out chany[0][1]_out[7] chany[0][1]_out[7]_loadlvl[0]_out chany[0][1]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[39]_no0 chany[0][1]_out[7]_loadlvl[0]_out chany[0][1]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[40]_no0 chany[0][1]_out[7]_loadlvl[0]_midout chany[0][1]_out[7]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[41]_no0 chany[0][1]_out[7]_loadlvl[0]_midout chany[0][1]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[8] density = 0, probability=0.*****
Vchany[0][1]_in[8] chany[0][1]_in[8] 0
+ 0
**** Load for rr_node[206] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=9, type=5 *****
Xchan_chany[0][1]_out[9]_loadlvl[0]_out chany[0][1]_out[9] chany[0][1]_out[9]_loadlvl[0]_out chany[0][1]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[42]_no0 chany[0][1]_out[9]_loadlvl[0]_out chany[0][1]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[43]_no0 chany[0][1]_out[9]_loadlvl[0]_midout chany[0][1]_out[9]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[10] density = 0, probability=0.*****
Vchany[0][1]_in[10] chany[0][1]_in[10] 0
+ 0
**** Load for rr_node[208] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=11, type=5 *****
Xchan_chany[0][1]_out[11]_loadlvl[0]_out chany[0][1]_out[11] chany[0][1]_out[11]_loadlvl[0]_out chany[0][1]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[44]_no0 chany[0][1]_out[11]_loadlvl[0]_out chany[0][1]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[45]_no0 chany[0][1]_out[11]_loadlvl[0]_midout chany[0][1]_out[11]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[46]_no0 chany[0][1]_out[11]_loadlvl[0]_midout chany[0][1]_out[11]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[12] density = 0, probability=0.*****
Vchany[0][1]_in[12] chany[0][1]_in[12] 0
+ 0
**** Load for rr_node[210] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=13, type=5 *****
Xchan_chany[0][1]_out[13]_loadlvl[0]_out chany[0][1]_out[13] chany[0][1]_out[13]_loadlvl[0]_out chany[0][1]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[47]_no0 chany[0][1]_out[13]_loadlvl[0]_out chany[0][1]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[48]_no0 chany[0][1]_out[13]_loadlvl[0]_midout chany[0][1]_out[13]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[14] density = 0, probability=0.*****
Vchany[0][1]_in[14] chany[0][1]_in[14] 0
+ 0
**** Load for rr_node[212] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=15, type=5 *****
Xchan_chany[0][1]_out[15]_loadlvl[0]_out chany[0][1]_out[15] chany[0][1]_out[15]_loadlvl[0]_out chany[0][1]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[49]_no0 chany[0][1]_out[15]_loadlvl[0]_out chany[0][1]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[50]_no0 chany[0][1]_out[15]_loadlvl[0]_midout chany[0][1]_out[15]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[16] density = 0, probability=0.*****
Vchany[0][1]_in[16] chany[0][1]_in[16] 0
+ 0
**** Load for rr_node[214] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=17, type=5 *****
Xchan_chany[0][1]_out[17]_loadlvl[0]_out chany[0][1]_out[17] chany[0][1]_out[17]_loadlvl[0]_out chany[0][1]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[51]_no0 chany[0][1]_out[17]_loadlvl[0]_out chany[0][1]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[52]_no0 chany[0][1]_out[17]_loadlvl[0]_midout chany[0][1]_out[17]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[18] density = 0, probability=0.*****
Vchany[0][1]_in[18] chany[0][1]_in[18] 0
+ 0
**** Load for rr_node[216] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=19, type=5 *****
Xchan_chany[0][1]_out[19]_loadlvl[0]_out chany[0][1]_out[19] chany[0][1]_out[19]_loadlvl[0]_out chany[0][1]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[53]_no0 chany[0][1]_out[19]_loadlvl[0]_out chany[0][1]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[54]_no0 chany[0][1]_out[19]_loadlvl[0]_midout chany[0][1]_out[19]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[20] density = 0, probability=0.*****
Vchany[0][1]_in[20] chany[0][1]_in[20] 0
+ 0
**** Load for rr_node[218] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=21, type=5 *****
Xchan_chany[0][1]_out[21]_loadlvl[0]_out chany[0][1]_out[21] chany[0][1]_out[21]_loadlvl[0]_out chany[0][1]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[55]_no0 chany[0][1]_out[21]_loadlvl[0]_out chany[0][1]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[56]_no0 chany[0][1]_out[21]_loadlvl[0]_midout chany[0][1]_out[21]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[22] density = 0, probability=0.*****
Vchany[0][1]_in[22] chany[0][1]_in[22] 0
+ 0
**** Load for rr_node[220] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=23, type=5 *****
Xchan_chany[0][1]_out[23]_loadlvl[0]_out chany[0][1]_out[23] chany[0][1]_out[23]_loadlvl[0]_out chany[0][1]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[57]_no0 chany[0][1]_out[23]_loadlvl[0]_out chany[0][1]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[58]_no0 chany[0][1]_out[23]_loadlvl[0]_midout chany[0][1]_out[23]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[24] density = 0, probability=0.*****
Vchany[0][1]_in[24] chany[0][1]_in[24] 0
+ 0
**** Load for rr_node[222] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=25, type=5 *****
Xchan_chany[0][1]_out[25]_loadlvl[0]_out chany[0][1]_out[25] chany[0][1]_out[25]_loadlvl[0]_out chany[0][1]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[59]_no0 chany[0][1]_out[25]_loadlvl[0]_out chany[0][1]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[60]_no0 chany[0][1]_out[25]_loadlvl[0]_midout chany[0][1]_out[25]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[26] density = 0, probability=0.*****
Vchany[0][1]_in[26] chany[0][1]_in[26] 0
+ 0
**** Load for rr_node[224] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=27, type=5 *****
Xchan_chany[0][1]_out[27]_loadlvl[0]_out chany[0][1]_out[27] chany[0][1]_out[27]_loadlvl[0]_out chany[0][1]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[61]_no0 chany[0][1]_out[27]_loadlvl[0]_out chany[0][1]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[62]_no0 chany[0][1]_out[27]_loadlvl[0]_midout chany[0][1]_out[27]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[63]_no0 chany[0][1]_out[27]_loadlvl[0]_midout chany[0][1]_out[27]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[0][1]_in[28] density = 0, probability=0.*****
Vchany[0][1]_in[28] chany[0][1]_in[28] 0
+ 0
**** Load for rr_node[226] *****
**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=29, type=5 *****
Xchan_chany[0][1]_out[29]_loadlvl[0]_out chany[0][1]_out[29] chany[0][1]_out[29]_loadlvl[0]_out chany[0][1]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[64]_no0 chany[0][1]_out[29]_loadlvl[0]_out chany[0][1]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[65]_no0 chany[0][1]_out[29]_loadlvl[0]_midout chany[0][1]_out[29]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Vgrid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][1] 0
+ 0
Vgrid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][3] 0
+ 0
Vgrid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][5] 0
+ 0
Vgrid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][7] 0
+ 0
Vgrid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][9] 0
+ 0
Vgrid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][11] 0
+ 0
Vgrid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][13] 0
+ 0
Vgrid[0][1]_pin[0][1][15] grid[0][1]_pin[0][1][15] 0
+ 0
***** Voltage supplies *****
Vgvdd_sb[0][1] gvdd_sb[0][1] 0 vsp
Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
***** Measurements *****
***** Leakage Power Measurement *****
.meas tran leakage_power_sb avg p(Vgvdd_sb[0][1]) from=0 to='clock_period'
.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period'
***** Dynamic Power Measurement *****
.meas tran dynamic_power_sb avg p(Vgvdd_sb[0][1]) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period'
.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
.end

381
examples/spice_test_example_1/sb_tb/example_1_sb1_0_sb_testbench.sp
View File

@ -1,381 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_sram_sbs
****** Include subckt netlists: Switch Block[1][0] *****
.include './spice_test_example_1/subckt/sb_1_0.sp'
***** Call defined Switch Box[1][0] *****
Xsb[1][0]
+ chany[1][1]_out[0] chany[1][1]_in[1] chany[1][1]_out[2] chany[1][1]_in[3] chany[1][1]_out[4] chany[1][1]_in[5] chany[1][1]_out[6] chany[1][1]_in[7] chany[1][1]_out[8] chany[1][1]_in[9] chany[1][1]_out[10] chany[1][1]_in[11] chany[1][1]_out[12] chany[1][1]_in[13] chany[1][1]_out[14] chany[1][1]_in[15] chany[1][1]_out[16] chany[1][1]_in[17] chany[1][1]_out[18] chany[1][1]_in[19] chany[1][1]_out[20] chany[1][1]_in[21] chany[1][1]_out[22] chany[1][1]_in[23] chany[1][1]_out[24] chany[1][1]_in[25] chany[1][1]_out[26] chany[1][1]_in[27] chany[1][1]_out[28] chany[1][1]_in[29]
+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15]
+
+
+
+
+ chanx[1][0]_in[0] chanx[1][0]_out[1] chanx[1][0]_in[2] chanx[1][0]_out[3] chanx[1][0]_in[4] chanx[1][0]_out[5] chanx[1][0]_in[6] chanx[1][0]_out[7] chanx[1][0]_in[8] chanx[1][0]_out[9] chanx[1][0]_in[10] chanx[1][0]_out[11] chanx[1][0]_in[12] chanx[1][0]_out[13] chanx[1][0]_in[14] chanx[1][0]_out[15] chanx[1][0]_in[16] chanx[1][0]_out[17] chanx[1][0]_in[18] chanx[1][0]_out[19] chanx[1][0]_in[20] chanx[1][0]_out[21] chanx[1][0]_in[22] chanx[1][0]_out[23] chanx[1][0]_in[24] chanx[1][0]_out[25] chanx[1][0]_in[26] chanx[1][0]_out[27] chanx[1][0]_in[28] chanx[1][0]_out[29]
+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15]
+ gvdd_sb[1][0] 0 sb[1][0]
**** Load for rr_node[227] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=5 *****
Xchan_chany[1][1]_out[0]_loadlvl[0]_out chany[1][1]_out[0] chany[1][1]_out[0]_loadlvl[0]_out chany[1][1]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[0]_no0 chany[1][1]_out[0]_loadlvl[0]_out chany[1][1]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 chany[1][1]_out[0]_loadlvl[0]_midout chany[1][1]_out[0]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[1] density = 0, probability=0.*****
Vchany[1][1]_in[1] chany[1][1]_in[1] 0
+ 0
**** Load for rr_node[229] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=5 *****
Xchan_chany[1][1]_out[2]_loadlvl[0]_out chany[1][1]_out[2] chany[1][1]_out[2]_loadlvl[0]_out chany[1][1]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[2]_no0 chany[1][1]_out[2]_loadlvl[0]_out chany[1][1]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[3] density = 0, probability=0.*****
Vchany[1][1]_in[3] chany[1][1]_in[3] 0
+ 0
**** Load for rr_node[231] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=5 *****
Xchan_chany[1][1]_out[4]_loadlvl[0]_out chany[1][1]_out[4] chany[1][1]_out[4]_loadlvl[0]_out chany[1][1]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[3]_no0 chany[1][1]_out[4]_loadlvl[0]_out chany[1][1]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[5] density = 0, probability=0.*****
Vchany[1][1]_in[5] chany[1][1]_in[5] 0
+ 0
**** Load for rr_node[233] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=5 *****
Xchan_chany[1][1]_out[6]_loadlvl[0]_out chany[1][1]_out[6] chany[1][1]_out[6]_loadlvl[0]_out chany[1][1]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[4]_no0 chany[1][1]_out[6]_loadlvl[0]_out chany[1][1]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[7] density = 0, probability=0.*****
Vchany[1][1]_in[7] chany[1][1]_in[7] 0
+ 0
**** Load for rr_node[235] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=5 *****
Xchan_chany[1][1]_out[8]_loadlvl[0]_out chany[1][1]_out[8] chany[1][1]_out[8]_loadlvl[0]_out chany[1][1]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[5]_no0 chany[1][1]_out[8]_loadlvl[0]_out chany[1][1]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[9] density = 0, probability=0.*****
Vchany[1][1]_in[9] chany[1][1]_in[9] 0
+ 0
**** Load for rr_node[237] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=5 *****
Xchan_chany[1][1]_out[10]_loadlvl[0]_out chany[1][1]_out[10] chany[1][1]_out[10]_loadlvl[0]_out chany[1][1]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[6]_no0 chany[1][1]_out[10]_loadlvl[0]_out chany[1][1]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[11] density = 0, probability=0.*****
Vchany[1][1]_in[11] chany[1][1]_in[11] 0
+ 0
**** Load for rr_node[239] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=5 *****
Xchan_chany[1][1]_out[12]_loadlvl[0]_out chany[1][1]_out[12] chany[1][1]_out[12]_loadlvl[0]_out chany[1][1]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[7]_no0 chany[1][1]_out[12]_loadlvl[0]_out chany[1][1]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[13] density = 0, probability=0.*****
Vchany[1][1]_in[13] chany[1][1]_in[13] 0
+ 0
**** Load for rr_node[241] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=5 *****
Xchan_chany[1][1]_out[14]_loadlvl[0]_out chany[1][1]_out[14] chany[1][1]_out[14]_loadlvl[0]_out chany[1][1]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[8]_no0 chany[1][1]_out[14]_loadlvl[0]_out chany[1][1]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[15] density = 0, probability=0.*****
Vchany[1][1]_in[15] chany[1][1]_in[15] 0
+ 0
**** Load for rr_node[243] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=5 *****
Xchan_chany[1][1]_out[16]_loadlvl[0]_out chany[1][1]_out[16] chany[1][1]_out[16]_loadlvl[0]_out chany[1][1]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[9]_no0 chany[1][1]_out[16]_loadlvl[0]_out chany[1][1]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[10]_no0 chany[1][1]_out[16]_loadlvl[0]_midout chany[1][1]_out[16]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[17] density = 0, probability=0.*****
Vchany[1][1]_in[17] chany[1][1]_in[17] 0
+ 0
**** Load for rr_node[245] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=5 *****
Xchan_chany[1][1]_out[18]_loadlvl[0]_out chany[1][1]_out[18] chany[1][1]_out[18]_loadlvl[0]_out chany[1][1]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[11]_no0 chany[1][1]_out[18]_loadlvl[0]_out chany[1][1]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[19] density = 0, probability=0.*****
Vchany[1][1]_in[19] chany[1][1]_in[19] 0
+ 0
**** Load for rr_node[247] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=5 *****
Xchan_chany[1][1]_out[20]_loadlvl[0]_out chany[1][1]_out[20] chany[1][1]_out[20]_loadlvl[0]_out chany[1][1]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[12]_no0 chany[1][1]_out[20]_loadlvl[0]_out chany[1][1]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[21] density = 0, probability=0.*****
Vchany[1][1]_in[21] chany[1][1]_in[21] 0
+ 0
**** Load for rr_node[249] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=5 *****
Xchan_chany[1][1]_out[22]_loadlvl[0]_out chany[1][1]_out[22] chany[1][1]_out[22]_loadlvl[0]_out chany[1][1]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[13]_no0 chany[1][1]_out[22]_loadlvl[0]_out chany[1][1]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[23] density = 0, probability=0.*****
Vchany[1][1]_in[23] chany[1][1]_in[23] 0
+ 0
**** Load for rr_node[251] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=5 *****
Xchan_chany[1][1]_out[24]_loadlvl[0]_out chany[1][1]_out[24] chany[1][1]_out[24]_loadlvl[0]_out chany[1][1]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[14]_no0 chany[1][1]_out[24]_loadlvl[0]_out chany[1][1]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[25] density = 0, probability=0.*****
Vchany[1][1]_in[25] chany[1][1]_in[25] 0
+ 0
**** Load for rr_node[253] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=5 *****
Xchan_chany[1][1]_out[26]_loadlvl[0]_out chany[1][1]_out[26] chany[1][1]_out[26]_loadlvl[0]_out chany[1][1]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[15]_no0 chany[1][1]_out[26]_loadlvl[0]_out chany[1][1]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[27] density = 0, probability=0.*****
Vchany[1][1]_in[27] chany[1][1]_in[27] 0
+ 0
**** Load for rr_node[255] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=5 *****
Xchan_chany[1][1]_out[28]_loadlvl[0]_out chany[1][1]_out[28] chany[1][1]_out[28]_loadlvl[0]_out chany[1][1]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[16]_no0 chany[1][1]_out[28]_loadlvl[0]_out chany[1][1]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[29] density = 0, probability=0.*****
Vchany[1][1]_in[29] chany[1][1]_in[29] 0
+ 0
Vgrid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][1] 0
+ 0
Vgrid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][3] 0
+ 0
Vgrid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][5] 0
+ 0
Vgrid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][7] 0
+ 0
Vgrid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][9] 0
+ 0
Vgrid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][11] 0
+ 0
Vgrid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][13] 0
+ 0
Vgrid[2][1]_pin[0][3][15] grid[2][1]_pin[0][3][15] 0
+ 0
***** Signal chanx[1][0]_in[0] density = 0, probability=0.*****
Vchanx[1][0]_in[0] chanx[1][0]_in[0] 0
+ 0
**** Load for rr_node[138] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=1, type=4 *****
Xchan_chanx[1][0]_out[1]_loadlvl[0]_out chanx[1][0]_out[1] chanx[1][0]_out[1]_loadlvl[0]_out chanx[1][0]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[17]_no0 chanx[1][0]_out[1]_loadlvl[0]_out chanx[1][0]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[18]_no0 chanx[1][0]_out[1]_loadlvl[0]_midout chanx[1][0]_out[1]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[19]_no0 chanx[1][0]_out[1]_loadlvl[0]_midout chanx[1][0]_out[1]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[2] density = 0, probability=0.*****
Vchanx[1][0]_in[2] chanx[1][0]_in[2] 0
+ 0
**** Load for rr_node[140] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=3, type=4 *****
Xchan_chanx[1][0]_out[3]_loadlvl[0]_out chanx[1][0]_out[3] chanx[1][0]_out[3]_loadlvl[0]_out chanx[1][0]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[20]_no0 chanx[1][0]_out[3]_loadlvl[0]_out chanx[1][0]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[21]_no0 chanx[1][0]_out[3]_loadlvl[0]_midout chanx[1][0]_out[3]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[4] density = 0, probability=0.*****
Vchanx[1][0]_in[4] chanx[1][0]_in[4] 0
+ 0
**** Load for rr_node[142] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=5, type=4 *****
Xchan_chanx[1][0]_out[5]_loadlvl[0]_out chanx[1][0]_out[5] chanx[1][0]_out[5]_loadlvl[0]_out chanx[1][0]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[22]_no0 chanx[1][0]_out[5]_loadlvl[0]_out chanx[1][0]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[23]_no0 chanx[1][0]_out[5]_loadlvl[0]_midout chanx[1][0]_out[5]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[6] density = 0, probability=0.*****
Vchanx[1][0]_in[6] chanx[1][0]_in[6] 0
+ 0
**** Load for rr_node[144] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=7, type=4 *****
Xchan_chanx[1][0]_out[7]_loadlvl[0]_out chanx[1][0]_out[7] chanx[1][0]_out[7]_loadlvl[0]_out chanx[1][0]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[24]_no0 chanx[1][0]_out[7]_loadlvl[0]_out chanx[1][0]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[25]_no0 chanx[1][0]_out[7]_loadlvl[0]_midout chanx[1][0]_out[7]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[26]_no0 chanx[1][0]_out[7]_loadlvl[0]_midout chanx[1][0]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[8] density = 0, probability=0.*****
Vchanx[1][0]_in[8] chanx[1][0]_in[8] 0
+ 0
**** Load for rr_node[146] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=9, type=4 *****
Xchan_chanx[1][0]_out[9]_loadlvl[0]_out chanx[1][0]_out[9] chanx[1][0]_out[9]_loadlvl[0]_out chanx[1][0]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[27]_no0 chanx[1][0]_out[9]_loadlvl[0]_out chanx[1][0]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[28]_no0 chanx[1][0]_out[9]_loadlvl[0]_midout chanx[1][0]_out[9]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[10] density = 0, probability=0.*****
Vchanx[1][0]_in[10] chanx[1][0]_in[10] 0
+ 0
**** Load for rr_node[148] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=11, type=4 *****
Xchan_chanx[1][0]_out[11]_loadlvl[0]_out chanx[1][0]_out[11] chanx[1][0]_out[11]_loadlvl[0]_out chanx[1][0]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[29]_no0 chanx[1][0]_out[11]_loadlvl[0]_out chanx[1][0]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[30]_no0 chanx[1][0]_out[11]_loadlvl[0]_midout chanx[1][0]_out[11]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[12] density = 0, probability=0.*****
Vchanx[1][0]_in[12] chanx[1][0]_in[12] 0
+ 0
**** Load for rr_node[150] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=13, type=4 *****
Xchan_chanx[1][0]_out[13]_loadlvl[0]_out chanx[1][0]_out[13] chanx[1][0]_out[13]_loadlvl[0]_out chanx[1][0]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[31]_no0 chanx[1][0]_out[13]_loadlvl[0]_out chanx[1][0]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[32]_no0 chanx[1][0]_out[13]_loadlvl[0]_midout chanx[1][0]_out[13]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[14] density = 0, probability=0.*****
Vchanx[1][0]_in[14] chanx[1][0]_in[14] 0
+ 0
**** Load for rr_node[152] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=15, type=4 *****
Xchan_chanx[1][0]_out[15]_loadlvl[0]_out chanx[1][0]_out[15] chanx[1][0]_out[15]_loadlvl[0]_out chanx[1][0]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[33]_no0 chanx[1][0]_out[15]_loadlvl[0]_out chanx[1][0]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[34]_no0 chanx[1][0]_out[15]_loadlvl[0]_midout chanx[1][0]_out[15]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[16] density = 0, probability=0.*****
Vchanx[1][0]_in[16] chanx[1][0]_in[16] 0
+ 0
**** Load for rr_node[154] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=17, type=4 *****
Xchan_chanx[1][0]_out[17]_loadlvl[0]_out chanx[1][0]_out[17] chanx[1][0]_out[17]_loadlvl[0]_out chanx[1][0]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[35]_no0 chanx[1][0]_out[17]_loadlvl[0]_out chanx[1][0]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[36]_no0 chanx[1][0]_out[17]_loadlvl[0]_midout chanx[1][0]_out[17]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[18] density = 0, probability=0.*****
Vchanx[1][0]_in[18] chanx[1][0]_in[18] 0
+ 0
**** Load for rr_node[156] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=19, type=4 *****
Xchan_chanx[1][0]_out[19]_loadlvl[0]_out chanx[1][0]_out[19] chanx[1][0]_out[19]_loadlvl[0]_out chanx[1][0]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[37]_no0 chanx[1][0]_out[19]_loadlvl[0]_out chanx[1][0]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[38]_no0 chanx[1][0]_out[19]_loadlvl[0]_midout chanx[1][0]_out[19]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[20] density = 0, probability=0.*****
Vchanx[1][0]_in[20] chanx[1][0]_in[20] 0
+ 0
**** Load for rr_node[158] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=21, type=4 *****
Xchan_chanx[1][0]_out[21]_loadlvl[0]_out chanx[1][0]_out[21] chanx[1][0]_out[21]_loadlvl[0]_out chanx[1][0]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[39]_no0 chanx[1][0]_out[21]_loadlvl[0]_out chanx[1][0]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[40]_no0 chanx[1][0]_out[21]_loadlvl[0]_midout chanx[1][0]_out[21]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[22] density = 0, probability=0.*****
Vchanx[1][0]_in[22] chanx[1][0]_in[22] 0
+ 0
**** Load for rr_node[160] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=23, type=4 *****
Xchan_chanx[1][0]_out[23]_loadlvl[0]_out chanx[1][0]_out[23] chanx[1][0]_out[23]_loadlvl[0]_out chanx[1][0]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[41]_no0 chanx[1][0]_out[23]_loadlvl[0]_out chanx[1][0]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[42]_no0 chanx[1][0]_out[23]_loadlvl[0]_midout chanx[1][0]_out[23]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[43]_no0 chanx[1][0]_out[23]_loadlvl[0]_midout chanx[1][0]_out[23]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[24] density = 0, probability=0.*****
Vchanx[1][0]_in[24] chanx[1][0]_in[24] 0
+ 0
**** Load for rr_node[162] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=25, type=4 *****
Xchan_chanx[1][0]_out[25]_loadlvl[0]_out chanx[1][0]_out[25] chanx[1][0]_out[25]_loadlvl[0]_out chanx[1][0]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[44]_no0 chanx[1][0]_out[25]_loadlvl[0]_out chanx[1][0]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[45]_no0 chanx[1][0]_out[25]_loadlvl[0]_midout chanx[1][0]_out[25]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[26] density = 0, probability=0.*****
Vchanx[1][0]_in[26] chanx[1][0]_in[26] 0
+ 0
**** Load for rr_node[164] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=27, type=4 *****
Xchan_chanx[1][0]_out[27]_loadlvl[0]_out chanx[1][0]_out[27] chanx[1][0]_out[27]_loadlvl[0]_out chanx[1][0]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[46]_no0 chanx[1][0]_out[27]_loadlvl[0]_out chanx[1][0]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[47]_no0 chanx[1][0]_out[27]_loadlvl[0]_midout chanx[1][0]_out[27]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][0]_in[28] density = 0, probability=0.*****
Vchanx[1][0]_in[28] chanx[1][0]_in[28] 0
+ 0
**** Load for rr_node[166] *****
**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=29, type=4 *****
Xchan_chanx[1][0]_out[29]_loadlvl[0]_out chanx[1][0]_out[29] chanx[1][0]_out[29]_loadlvl[0]_out chanx[1][0]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[48]_no0 chanx[1][0]_out[29]_loadlvl[0]_out chanx[1][0]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[49]_no0 chanx[1][0]_out[29]_loadlvl[0]_midout chanx[1][0]_out[29]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Vgrid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][1] 0
+ 0
Vgrid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][3] 0
+ 0
Vgrid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][5] 0
+ 0
Vgrid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][7] 0
+ 0
Vgrid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][9] 0
+ 0
Vgrid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][11] 0
+ 0
Vgrid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][13] 0
+ 0
Vgrid[1][0]_pin[0][0][15] grid[1][0]_pin[0][0][15] 0
+ 0
***** Voltage supplies *****
Vgvdd_sb[1][0] gvdd_sb[1][0] 0 vsp
Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp
***** 2 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '2*clock_period'
***** Generic Measurements for Circuit Parameters *****
***** Measurements *****
***** Leakage Power Measurement *****
.meas tran leakage_power_sb avg p(Vgvdd_sb[1][0]) from=0 to='clock_period'
.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period'
***** Dynamic Power Measurement *****
.meas tran dynamic_power_sb avg p(Vgvdd_sb[1][0]) from='clock_period' to='2*clock_period'
.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period'
.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='2*clock_period'
.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
.end

393
examples/spice_test_example_1/sb_tb/example_1_sb1_1_sb_testbench.sp
View File

@ -1,393 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_1 *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
****** Include Header file: circuit design parameters *****
.include './spice_test_example_1/include/design_params.sp'
****** Include Header file: measurement parameters *****
.include './spice_test_example_1/include/meas_params.sp'
****** Include Header file: stimulation parameters *****
.include './spice_test_example_1/include/stimulate_params.sp'
****** Include subckt netlists: NMOS and PMOS *****
.include './spice_test_example_1/subckt/nmos_pmos.sp'
****** Include subckt netlists: Inverters, Buffers *****
.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp'
****** Include subckt netlists: Multiplexers *****
.include './spice_test_example_1/subckt/muxes.sp'
****** Include subckt netlists: Wires *****
.include './spice_test_example_1/subckt/wires.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp'
.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp'
.temp 25
.option fast
***** Generic global ports *****
***** VDD, GND *****
.global gvdd
.global ggnd
***** Global set ports *****
.global gset gset_inv
***** Global reset ports *****
.global greset greset_inv
***** Configuration done ports *****
.global gconfig_done gconfig_done_inv
***** Global SRAM input *****
.global sram->in
***** Global Clock Signals *****
.global gclock
.global gclock_inv
***** User-defined global ports ******
.global
***** BEGIN Global ports *****
+ zin[0] clk[0] Reset[0] Set[0]
***** END Global ports *****
.global gvdd_sram_sbs
****** Include subckt netlists: Switch Block[1][1] *****
.include './spice_test_example_1/subckt/sb_1_1.sp'
***** Call defined Switch Box[1][1] *****
Xsb[1][1]
+
+
+
+
+ chany[1][1]_in[0] chany[1][1]_out[1] chany[1][1]_in[2] chany[1][1]_out[3] chany[1][1]_in[4] chany[1][1]_out[5] chany[1][1]_in[6] chany[1][1]_out[7] chany[1][1]_in[8] chany[1][1]_out[9] chany[1][1]_in[10] chany[1][1]_out[11] chany[1][1]_in[12] chany[1][1]_out[13] chany[1][1]_in[14] chany[1][1]_out[15] chany[1][1]_in[16] chany[1][1]_out[17] chany[1][1]_in[18] chany[1][1]_out[19] chany[1][1]_in[20] chany[1][1]_out[21] chany[1][1]_in[22] chany[1][1]_out[23] chany[1][1]_in[24] chany[1][1]_out[25] chany[1][1]_in[26] chany[1][1]_out[27] chany[1][1]_in[28] chany[1][1]_out[29]
+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15]
+ chanx[1][1]_in[0] chanx[1][1]_out[1] chanx[1][1]_in[2] chanx[1][1]_out[3] chanx[1][1]_in[4] chanx[1][1]_out[5] chanx[1][1]_in[6] chanx[1][1]_out[7] chanx[1][1]_in[8] chanx[1][1]_out[9] chanx[1][1]_in[10] chanx[1][1]_out[11] chanx[1][1]_in[12] chanx[1][1]_out[13] chanx[1][1]_in[14] chanx[1][1]_out[15] chanx[1][1]_in[16] chanx[1][1]_out[17] chanx[1][1]_in[18] chanx[1][1]_out[19] chanx[1][1]_in[20] chanx[1][1]_out[21] chanx[1][1]_in[22] chanx[1][1]_out[23] chanx[1][1]_in[24] chanx[1][1]_out[25] chanx[1][1]_in[26] chanx[1][1]_out[27] chanx[1][1]_in[28] chanx[1][1]_out[29]
+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4]
+ gvdd_sb[1][1] 0 sb[1][1]
***** Signal chany[1][1]_in[0] density = 0, probability=0.*****
Vchany[1][1]_in[0] chany[1][1]_in[0] 0
+ 0
**** Load for rr_node[228] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=5 *****
Xchan_chany[1][1]_out[1]_loadlvl[0]_out chany[1][1]_out[1] chany[1][1]_out[1]_loadlvl[0]_out chany[1][1]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[0]_no0 chany[1][1]_out[1]_loadlvl[0]_out chany[1][1]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[1]_no0 chany[1][1]_out[1]_loadlvl[0]_midout chany[1][1]_out[1]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[2] density = 0, probability=0.*****
Vchany[1][1]_in[2] chany[1][1]_in[2] 0
+ 0
**** Load for rr_node[230] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=5 *****
Xchan_chany[1][1]_out[3]_loadlvl[0]_out chany[1][1]_out[3] chany[1][1]_out[3]_loadlvl[0]_out chany[1][1]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[2]_no0 chany[1][1]_out[3]_loadlvl[0]_out chany[1][1]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[4] density = 0, probability=0.*****
Vchany[1][1]_in[4] chany[1][1]_in[4] 0
+ 0
**** Load for rr_node[232] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=5 *****
Xchan_chany[1][1]_out[5]_loadlvl[0]_out chany[1][1]_out[5] chany[1][1]_out[5]_loadlvl[0]_out chany[1][1]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[3]_no0 chany[1][1]_out[5]_loadlvl[0]_out chany[1][1]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[6] density = 0, probability=0.*****
Vchany[1][1]_in[6] chany[1][1]_in[6] 0
+ 0
**** Load for rr_node[234] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=5 *****
Xchan_chany[1][1]_out[7]_loadlvl[0]_out chany[1][1]_out[7] chany[1][1]_out[7]_loadlvl[0]_out chany[1][1]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[4]_no0 chany[1][1]_out[7]_loadlvl[0]_out chany[1][1]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[8] density = 0, probability=0.*****
Vchany[1][1]_in[8] chany[1][1]_in[8] 0
+ 0
**** Load for rr_node[236] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=5 *****
Xchan_chany[1][1]_out[9]_loadlvl[0]_out chany[1][1]_out[9] chany[1][1]_out[9]_loadlvl[0]_out chany[1][1]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[5]_no0 chany[1][1]_out[9]_loadlvl[0]_out chany[1][1]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[10] density = 0, probability=0.*****
Vchany[1][1]_in[10] chany[1][1]_in[10] 0
+ 0
**** Load for rr_node[238] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=5 *****
Xchan_chany[1][1]_out[11]_loadlvl[0]_out chany[1][1]_out[11] chany[1][1]_out[11]_loadlvl[0]_out chany[1][1]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[6]_no0 chany[1][1]_out[11]_loadlvl[0]_out chany[1][1]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[12] density = 0, probability=0.*****
Vchany[1][1]_in[12] chany[1][1]_in[12] 0
+ 0
**** Load for rr_node[240] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=5 *****
Xchan_chany[1][1]_out[13]_loadlvl[0]_out chany[1][1]_out[13] chany[1][1]_out[13]_loadlvl[0]_out chany[1][1]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[7]_no0 chany[1][1]_out[13]_loadlvl[0]_out chany[1][1]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[14] density = 0, probability=0.*****
Vchany[1][1]_in[14] chany[1][1]_in[14] 0
+ 0
**** Load for rr_node[242] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=5 *****
Xchan_chany[1][1]_out[15]_loadlvl[0]_out chany[1][1]_out[15] chany[1][1]_out[15]_loadlvl[0]_out chany[1][1]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[8]_no0 chany[1][1]_out[15]_loadlvl[0]_out chany[1][1]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[16] density = 0, probability=0.*****
Vchany[1][1]_in[16] chany[1][1]_in[16] 0
+ 0
**** Load for rr_node[244] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=5 *****
Xchan_chany[1][1]_out[17]_loadlvl[0]_out chany[1][1]_out[17] chany[1][1]_out[17]_loadlvl[0]_out chany[1][1]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[9]_no0 chany[1][1]_out[17]_loadlvl[0]_out chany[1][1]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[10]_no0 chany[1][1]_out[17]_loadlvl[0]_midout chany[1][1]_out[17]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[18] density = 0, probability=0.*****
Vchany[1][1]_in[18] chany[1][1]_in[18] 0
+ 0
**** Load for rr_node[246] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=5 *****
Xchan_chany[1][1]_out[19]_loadlvl[0]_out chany[1][1]_out[19] chany[1][1]_out[19]_loadlvl[0]_out chany[1][1]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[11]_no0 chany[1][1]_out[19]_loadlvl[0]_out chany[1][1]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[20] density = 0, probability=0.*****
Vchany[1][1]_in[20] chany[1][1]_in[20] 0
+ 0
**** Load for rr_node[248] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=5 *****
Xchan_chany[1][1]_out[21]_loadlvl[0]_out chany[1][1]_out[21] chany[1][1]_out[21]_loadlvl[0]_out chany[1][1]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[12]_no0 chany[1][1]_out[21]_loadlvl[0]_out chany[1][1]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[22] density = 0, probability=0.*****
Vchany[1][1]_in[22] chany[1][1]_in[22] 0
+ 0
**** Load for rr_node[250] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=5 *****
Xchan_chany[1][1]_out[23]_loadlvl[0]_out chany[1][1]_out[23] chany[1][1]_out[23]_loadlvl[0]_out chany[1][1]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[13]_no0 chany[1][1]_out[23]_loadlvl[0]_out chany[1][1]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[24] density = 0, probability=0.*****
Vchany[1][1]_in[24] chany[1][1]_in[24] 0
+ 0
**** Load for rr_node[252] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=5 *****
Xchan_chany[1][1]_out[25]_loadlvl[0]_out chany[1][1]_out[25] chany[1][1]_out[25]_loadlvl[0]_out chany[1][1]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[14]_no0 chany[1][1]_out[25]_loadlvl[0]_out chany[1][1]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[26] density = 0, probability=0.*****
Vchany[1][1]_in[26] chany[1][1]_in[26] 0
+ 0
**** Load for rr_node[254] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=5 *****
Xchan_chany[1][1]_out[27]_loadlvl[0]_out chany[1][1]_out[27] chany[1][1]_out[27]_loadlvl[0]_out chany[1][1]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[15]_no0 chany[1][1]_out[27]_loadlvl[0]_out chany[1][1]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
***** Signal chany[1][1]_in[28] density = 0, probability=0.*****
Vchany[1][1]_in[28] chany[1][1]_in[28] 0
+ 0
**** Load for rr_node[256] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=5 *****
Xchan_chany[1][1]_out[29]_loadlvl[0]_out chany[1][1]_out[29] chany[1][1]_out[29]_loadlvl[0]_out chany[1][1]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[16]_no0 chany[1][1]_out[29]_loadlvl[0]_out chany[1][1]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Vgrid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][1] 0
+ 0
Vgrid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][3] 0
+ 0
Vgrid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][5] 0
+ 0
Vgrid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][7] 0
+ 0
Vgrid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][9] 0
+ 0
Vgrid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][11] 0
+ 0
Vgrid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][13] 0
+ 0
Vgrid[2][1]_pin[0][3][15] grid[2][1]_pin[0][3][15] 0
+ 0
***** Signal chanx[1][1]_in[0] density = 0.1906, probability=0.5218.*****
Vchanx[1][1]_in[0] chanx[1][1]_in[0] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
**** Load for rr_node[168] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=4 *****
Xchan_chanx[1][1]_out[1]_loadlvl[0]_out chanx[1][1]_out[1] chanx[1][1]_out[1]_loadlvl[0]_out chanx[1][1]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[17]_no0 chanx[1][1]_out[1]_loadlvl[0]_out chanx[1][1]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[18]_no0 chanx[1][1]_out[1]_loadlvl[0]_midout chanx[1][1]_out[1]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[2] density = 0.1906, probability=0.5218.*****
Vchanx[1][1]_in[2] chanx[1][1]_in[2] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
**** Load for rr_node[170] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=4 *****
Xchan_chanx[1][1]_out[3]_loadlvl[0]_out chanx[1][1]_out[3] chanx[1][1]_out[3]_loadlvl[0]_out chanx[1][1]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[19]_no0 chanx[1][1]_out[3]_loadlvl[0]_out chanx[1][1]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[20]_no0 chanx[1][1]_out[3]_loadlvl[0]_midout chanx[1][1]_out[3]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[4] density = 0, probability=0.*****
Vchanx[1][1]_in[4] chanx[1][1]_in[4] 0
+ 0
**** Load for rr_node[172] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=4 *****
Xchan_chanx[1][1]_out[5]_loadlvl[0]_out chanx[1][1]_out[5] chanx[1][1]_out[5]_loadlvl[0]_out chanx[1][1]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[21]_no0 chanx[1][1]_out[5]_loadlvl[0]_out chanx[1][1]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[22]_no0 chanx[1][1]_out[5]_loadlvl[0]_midout chanx[1][1]_out[5]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[6] density = 0, probability=0.*****
Vchanx[1][1]_in[6] chanx[1][1]_in[6] 0
+ 0
**** Load for rr_node[174] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=4 *****
Xchan_chanx[1][1]_out[7]_loadlvl[0]_out chanx[1][1]_out[7] chanx[1][1]_out[7]_loadlvl[0]_out chanx[1][1]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[23]_no0 chanx[1][1]_out[7]_loadlvl[0]_out chanx[1][1]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[24]_no0 chanx[1][1]_out[7]_loadlvl[0]_midout chanx[1][1]_out[7]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[25]_no0 chanx[1][1]_out[7]_loadlvl[0]_midout chanx[1][1]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[8] density = 0, probability=0.*****
Vchanx[1][1]_in[8] chanx[1][1]_in[8] 0
+ 0
**** Load for rr_node[176] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=4 *****
Xchan_chanx[1][1]_out[9]_loadlvl[0]_out chanx[1][1]_out[9] chanx[1][1]_out[9]_loadlvl[0]_out chanx[1][1]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[26]_no0 chanx[1][1]_out[9]_loadlvl[0]_out chanx[1][1]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[27]_no0 chanx[1][1]_out[9]_loadlvl[0]_midout chanx[1][1]_out[9]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[10] density = 0, probability=0.*****
Vchanx[1][1]_in[10] chanx[1][1]_in[10] 0
+ 0
**** Load for rr_node[178] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=4 *****
Xchan_chanx[1][1]_out[11]_loadlvl[0]_out chanx[1][1]_out[11] chanx[1][1]_out[11]_loadlvl[0]_out chanx[1][1]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0
Xload_inv[28]_no0 chanx[1][1]_out[11]_loadlvl[0]_out chanx[1][1]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[29]_no0 chanx[1][1]_out[11]_loadlvl[0]_midout chanx[1][1]_out[11]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[12] density = 0, probability=0.*****
Vchanx[1][1]_in[12] chanx[1][1]_in[12] 0
+ 0
**** Load for rr_node[180] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=4 *****
Xchan_chanx[1][1]_out[13]_loadlvl[0]_out chanx[1][1]_out[13] chanx[1][1]_out[13]_loadlvl[0]_out chanx[1][1]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[30]_no0 chanx[1][1]_out[13]_loadlvl[0]_out chanx[1][1]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[31]_no0 chanx[1][1]_out[13]_loadlvl[0]_midout chanx[1][1]_out[13]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Xload_inv[32]_no0 chanx[1][1]_out[13]_loadlvl[0]_midout chanx[1][1]_out[13]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1
Xload_inv[33]_no0 chanx[1][1]_out[13]_loadlvl[0]_midout chanx[1][1]_out[13]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[14] density = 0, probability=0.*****
Vchanx[1][1]_in[14] chanx[1][1]_in[14] 0
+ 0
**** Load for rr_node[182] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=4 *****
Xchan_chanx[1][1]_out[15]_loadlvl[0]_out chanx[1][1]_out[15] chanx[1][1]_out[15]_loadlvl[0]_out chanx[1][1]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[34]_no0 chanx[1][1]_out[15]_loadlvl[0]_out chanx[1][1]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[35]_no0 chanx[1][1]_out[15]_loadlvl[0]_midout chanx[1][1]_out[15]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[16] density = 0, probability=0.*****
Vchanx[1][1]_in[16] chanx[1][1]_in[16] 0
+ 0
**** Load for rr_node[184] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=4 *****
Xchan_chanx[1][1]_out[17]_loadlvl[0]_out chanx[1][1]_out[17] chanx[1][1]_out[17]_loadlvl[0]_out chanx[1][1]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[36]_no0 chanx[1][1]_out[17]_loadlvl[0]_out chanx[1][1]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[37]_no0 chanx[1][1]_out[17]_loadlvl[0]_midout chanx[1][1]_out[17]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[18] density = 0, probability=0.*****
Vchanx[1][1]_in[18] chanx[1][1]_in[18] 0
+ 0
**** Load for rr_node[186] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=4 *****
Xchan_chanx[1][1]_out[19]_loadlvl[0]_out chanx[1][1]_out[19] chanx[1][1]_out[19]_loadlvl[0]_out chanx[1][1]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[38]_no0 chanx[1][1]_out[19]_loadlvl[0]_out chanx[1][1]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[39]_no0 chanx[1][1]_out[19]_loadlvl[0]_midout chanx[1][1]_out[19]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[20] density = 0, probability=0.*****
Vchanx[1][1]_in[20] chanx[1][1]_in[20] 0
+ 0
**** Load for rr_node[188] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=4 *****
Xchan_chanx[1][1]_out[21]_loadlvl[0]_out chanx[1][1]_out[21] chanx[1][1]_out[21]_loadlvl[0]_out chanx[1][1]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1
Xload_inv[40]_no0 chanx[1][1]_out[21]_loadlvl[0]_out chanx[1][1]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[41]_no0 chanx[1][1]_out[21]_loadlvl[0]_midout chanx[1][1]_out[21]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[22] density = 0, probability=0.*****
Vchanx[1][1]_in[22] chanx[1][1]_in[22] 0
+ 0
**** Load for rr_node[190] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=4 *****
Xchan_chanx[1][1]_out[23]_loadlvl[0]_out chanx[1][1]_out[23] chanx[1][1]_out[23]_loadlvl[0]_out chanx[1][1]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[42]_no0 chanx[1][1]_out[23]_loadlvl[0]_out chanx[1][1]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[43]_no0 chanx[1][1]_out[23]_loadlvl[0]_midout chanx[1][1]_out[23]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[24] density = 0, probability=0.*****
Vchanx[1][1]_in[24] chanx[1][1]_in[24] 0
+ 0
**** Load for rr_node[192] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=4 *****
Xchan_chanx[1][1]_out[25]_loadlvl[0]_out chanx[1][1]_out[25] chanx[1][1]_out[25]_loadlvl[0]_out chanx[1][1]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[44]_no0 chanx[1][1]_out[25]_loadlvl[0]_out chanx[1][1]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[45]_no0 chanx[1][1]_out[25]_loadlvl[0]_midout chanx[1][1]_out[25]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[26] density = 0, probability=0.*****
Vchanx[1][1]_in[26] chanx[1][1]_in[26] 0
+ 0
**** Load for rr_node[194] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=4 *****
Xchan_chanx[1][1]_out[27]_loadlvl[0]_out chanx[1][1]_out[27] chanx[1][1]_out[27]_loadlvl[0]_out chanx[1][1]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[46]_no0 chanx[1][1]_out[27]_loadlvl[0]_out chanx[1][1]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[47]_no0 chanx[1][1]_out[27]_loadlvl[0]_midout chanx[1][1]_out[27]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
***** Signal chanx[1][1]_in[28] density = 0.1906, probability=0.4782.*****
Vchanx[1][1]_in[28] chanx[1][1]_in[28] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
**** Load for rr_node[196] *****
**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=4 *****
Xchan_chanx[1][1]_out[29]_loadlvl[0]_out chanx[1][1]_out[29] chanx[1][1]_out[29]_loadlvl[0]_out chanx[1][1]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2
Xload_inv[48]_no0 chanx[1][1]_out[29]_loadlvl[0]_out chanx[1][1]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1
Xload_inv[49]_no0 chanx[1][1]_out[29]_loadlvl[0]_midout chanx[1][1]_out[29]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1
Vgrid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][1] 0
+ 0
Vgrid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][3] 0
+ 0
Vgrid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][5] 0
+ 0
Vgrid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][7] 0
+ 0
Vgrid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][9] 0
+ 0
Vgrid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][11] 0
+ 0
Vgrid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][13] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
Vgrid[1][2]_pin[0][2][15] grid[1][2]_pin[0][2][15] 0
+ 0
Vgrid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4] 0
+ pulse(0 vsp 'clock_period'
+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period'
+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period')
***** Voltage supplies *****
Vgvdd_sb[1][1] gvdd_sb[1][1] 0 vsp
Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp
***** 7 Clock Simulation, accuracy=1e-13 *****
.tran 1e-13 '7*clock_period'
***** Generic Measurements for Circuit Parameters *****
***** Measurements *****
***** Leakage Power Measurement *****
.meas tran leakage_power_sb avg p(Vgvdd_sb[1][1]) from=0 to='clock_period'
.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period'
***** Dynamic Power Measurement *****
.meas tran dynamic_power_sb avg p(Vgvdd_sb[1][1]) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period'
.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='7*clock_period'
.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period'
***** Global VDD port *****
Vgvdd gvdd 0 vsp
***** Global GND port *****
Vggnd ggnd 0 0
***** Global Net for reset signal *****
Vgreset greset 0 0
Vgreset_inv greset_inv 0 vsp
***** Global Net for set signal *****
Vgset gset 0 0
Vgset_inv gset_inv 0 vsp
***** Global Net for configuration done signal *****
Vgconfig_done gconfig_done 0 0
Vgconfig_done_inv gconfig_done_inv 0 vsp
***** Global Clock signal *****
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock gclock 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** pulse(vlow vhigh tdelay trise tfall pulse_width period *****
Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period'
+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period'
+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period')
***** Connecting Global ports *****
Rzin[0] zin[0] ggnd 0
Rshortwireclk[0] clk[0] gclock 0
RshortwireReset[0] Reset[0] greset 0
RshortwireSet[0] Set[0] gset 0
***** End Connecting Global ports *****
***** Global Inputs for SRAMs *****
***** Global Inputs for SRAMs *****
Vsram->in sram->in 0 0
.nodeset V(sram->in) 0
***** Global VDD for SRAMs *****
Vgvdd_sram gvdd_sram 0 vsp
***** Global VDD for load inverters *****
Vgvdd_load gvdd_load 0 vsp
.end

185
examples/spice_test_example_1/subckt/cbx_1_0.sp
View File

@ -1,185 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Connection Block X-channel [1][0] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
.subckt cbx[1][0]
+ chanx[1][0]_midout[0]
+ chanx[1][0]_midout[1]
+ chanx[1][0]_midout[2]
+ chanx[1][0]_midout[3]
+ chanx[1][0]_midout[4]
+ chanx[1][0]_midout[5]
+ chanx[1][0]_midout[6]
+ chanx[1][0]_midout[7]
+ chanx[1][0]_midout[8]
+ chanx[1][0]_midout[9]
+ chanx[1][0]_midout[10]
+ chanx[1][0]_midout[11]
+ chanx[1][0]_midout[12]
+ chanx[1][0]_midout[13]
+ chanx[1][0]_midout[14]
+ chanx[1][0]_midout[15]
+ chanx[1][0]_midout[16]
+ chanx[1][0]_midout[17]
+ chanx[1][0]_midout[18]
+ chanx[1][0]_midout[19]
+ chanx[1][0]_midout[20]
+ chanx[1][0]_midout[21]
+ chanx[1][0]_midout[22]
+ chanx[1][0]_midout[23]
+ chanx[1][0]_midout[24]
+ chanx[1][0]_midout[25]
+ chanx[1][0]_midout[26]
+ chanx[1][0]_midout[27]
+ chanx[1][0]_midout[28]
+ chanx[1][0]_midout[29]
+ grid[1][1]_pin[0][2][2]
+ grid[1][0]_pin[0][0][0]
+ grid[1][0]_pin[0][0][2]
+ grid[1][0]_pin[0][0][4]
+ grid[1][0]_pin[0][0][6]
+ grid[1][0]_pin[0][0][8]
+ grid[1][0]_pin[0][0][10]
+ grid[1][0]_pin[0][0][12]
+ grid[1][0]_pin[0][0][14]
+ svdd sgnd
Xmux_2level_tapbuf_size4[0] chanx[1][0]_midout[6] chanx[1][0]_midout[7] chanx[1][0]_midout[22] chanx[1][0]_midout[23] grid[1][1]_pin[0][2][2] sram[217]->outb sram[217]->out sram[218]->out sram[218]->outb sram[219]->outb sram[219]->out sram[220]->out sram[220]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[0], level=2, select_path_id=0. *****
*****1010*****
Xsram[217] sram->in sram[217]->out sram[217]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[217]->out) 0
.nodeset V(sram[217]->outb) vsp
Xsram[218] sram->in sram[218]->out sram[218]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[218]->out) 0
.nodeset V(sram[218]->outb) vsp
Xsram[219] sram->in sram[219]->out sram[219]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[219]->out) 0
.nodeset V(sram[219]->outb) vsp
Xsram[220] sram->in sram[220]->out sram[220]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[220]->out) 0
.nodeset V(sram[220]->outb) vsp
Xmux_2level_tapbuf_size4[1] chanx[1][0]_midout[0] chanx[1][0]_midout[1] chanx[1][0]_midout[14] chanx[1][0]_midout[15] grid[1][0]_pin[0][0][0] sram[221]->outb sram[221]->out sram[222]->out sram[222]->outb sram[223]->outb sram[223]->out sram[224]->out sram[224]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[1], level=2, select_path_id=0. *****
*****1010*****
Xsram[221] sram->in sram[221]->out sram[221]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[221]->out) 0
.nodeset V(sram[221]->outb) vsp
Xsram[222] sram->in sram[222]->out sram[222]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[222]->out) 0
.nodeset V(sram[222]->outb) vsp
Xsram[223] sram->in sram[223]->out sram[223]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[223]->out) 0
.nodeset V(sram[223]->outb) vsp
Xsram[224] sram->in sram[224]->out sram[224]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[224]->out) 0
.nodeset V(sram[224]->outb) vsp
Xmux_2level_tapbuf_size4[2] chanx[1][0]_midout[0] chanx[1][0]_midout[1] chanx[1][0]_midout[16] chanx[1][0]_midout[17] grid[1][0]_pin[0][0][2] sram[225]->outb sram[225]->out sram[226]->out sram[226]->outb sram[227]->outb sram[227]->out sram[228]->out sram[228]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[2], level=2, select_path_id=0. *****
*****1010*****
Xsram[225] sram->in sram[225]->out sram[225]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[225]->out) 0
.nodeset V(sram[225]->outb) vsp
Xsram[226] sram->in sram[226]->out sram[226]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[226]->out) 0
.nodeset V(sram[226]->outb) vsp
Xsram[227] sram->in sram[227]->out sram[227]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[227]->out) 0
.nodeset V(sram[227]->outb) vsp
Xsram[228] sram->in sram[228]->out sram[228]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[228]->out) 0
.nodeset V(sram[228]->outb) vsp
Xmux_2level_tapbuf_size4[3] chanx[1][0]_midout[2] chanx[1][0]_midout[3] chanx[1][0]_midout[18] chanx[1][0]_midout[19] grid[1][0]_pin[0][0][4] sram[229]->outb sram[229]->out sram[230]->out sram[230]->outb sram[231]->outb sram[231]->out sram[232]->out sram[232]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[3], level=2, select_path_id=0. *****
*****1010*****
Xsram[229] sram->in sram[229]->out sram[229]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[229]->out) 0
.nodeset V(sram[229]->outb) vsp
Xsram[230] sram->in sram[230]->out sram[230]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[230]->out) 0
.nodeset V(sram[230]->outb) vsp
Xsram[231] sram->in sram[231]->out sram[231]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[231]->out) 0
.nodeset V(sram[231]->outb) vsp
Xsram[232] sram->in sram[232]->out sram[232]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[232]->out) 0
.nodeset V(sram[232]->outb) vsp
Xmux_2level_tapbuf_size4[4] chanx[1][0]_midout[4] chanx[1][0]_midout[5] chanx[1][0]_midout[20] chanx[1][0]_midout[21] grid[1][0]_pin[0][0][6] sram[233]->outb sram[233]->out sram[234]->out sram[234]->outb sram[235]->outb sram[235]->out sram[236]->out sram[236]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[4], level=2, select_path_id=0. *****
*****1010*****
Xsram[233] sram->in sram[233]->out sram[233]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[233]->out) 0
.nodeset V(sram[233]->outb) vsp
Xsram[234] sram->in sram[234]->out sram[234]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[234]->out) 0
.nodeset V(sram[234]->outb) vsp
Xsram[235] sram->in sram[235]->out sram[235]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[235]->out) 0
.nodeset V(sram[235]->outb) vsp
Xsram[236] sram->in sram[236]->out sram[236]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[236]->out) 0
.nodeset V(sram[236]->outb) vsp
Xmux_2level_tapbuf_size4[5] chanx[1][0]_midout[6] chanx[1][0]_midout[7] chanx[1][0]_midout[22] chanx[1][0]_midout[23] grid[1][0]_pin[0][0][8] sram[237]->outb sram[237]->out sram[238]->out sram[238]->outb sram[239]->outb sram[239]->out sram[240]->out sram[240]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[5], level=2, select_path_id=0. *****
*****1010*****
Xsram[237] sram->in sram[237]->out sram[237]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[237]->out) 0
.nodeset V(sram[237]->outb) vsp
Xsram[238] sram->in sram[238]->out sram[238]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[238]->out) 0
.nodeset V(sram[238]->outb) vsp
Xsram[239] sram->in sram[239]->out sram[239]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[239]->out) 0
.nodeset V(sram[239]->outb) vsp
Xsram[240] sram->in sram[240]->out sram[240]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[240]->out) 0
.nodeset V(sram[240]->outb) vsp
Xmux_2level_tapbuf_size4[6] chanx[1][0]_midout[8] chanx[1][0]_midout[9] chanx[1][0]_midout[24] chanx[1][0]_midout[25] grid[1][0]_pin[0][0][10] sram[241]->outb sram[241]->out sram[242]->out sram[242]->outb sram[243]->outb sram[243]->out sram[244]->out sram[244]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[6], level=2, select_path_id=0. *****
*****1010*****
Xsram[241] sram->in sram[241]->out sram[241]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[241]->out) 0
.nodeset V(sram[241]->outb) vsp
Xsram[242] sram->in sram[242]->out sram[242]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[242]->out) 0
.nodeset V(sram[242]->outb) vsp
Xsram[243] sram->in sram[243]->out sram[243]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[243]->out) 0
.nodeset V(sram[243]->outb) vsp
Xsram[244] sram->in sram[244]->out sram[244]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[244]->out) 0
.nodeset V(sram[244]->outb) vsp
Xmux_2level_tapbuf_size4[7] chanx[1][0]_midout[10] chanx[1][0]_midout[11] chanx[1][0]_midout[26] chanx[1][0]_midout[27] grid[1][0]_pin[0][0][12] sram[245]->outb sram[245]->out sram[246]->out sram[246]->outb sram[247]->outb sram[247]->out sram[248]->out sram[248]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[7], level=2, select_path_id=0. *****
*****1010*****
Xsram[245] sram->in sram[245]->out sram[245]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[245]->out) 0
.nodeset V(sram[245]->outb) vsp
Xsram[246] sram->in sram[246]->out sram[246]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[246]->out) 0
.nodeset V(sram[246]->outb) vsp
Xsram[247] sram->in sram[247]->out sram[247]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[247]->out) 0
.nodeset V(sram[247]->outb) vsp
Xsram[248] sram->in sram[248]->out sram[248]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[248]->out) 0
.nodeset V(sram[248]->outb) vsp
Xmux_2level_tapbuf_size4[8] chanx[1][0]_midout[12] chanx[1][0]_midout[13] chanx[1][0]_midout[28] chanx[1][0]_midout[29] grid[1][0]_pin[0][0][14] sram[249]->outb sram[249]->out sram[250]->out sram[250]->outb sram[251]->outb sram[251]->out sram[252]->out sram[252]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[8], level=2, select_path_id=0. *****
*****1010*****
Xsram[249] sram->in sram[249]->out sram[249]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[249]->out) 0
.nodeset V(sram[249]->outb) vsp
Xsram[250] sram->in sram[250]->out sram[250]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[250]->out) 0
.nodeset V(sram[250]->outb) vsp
Xsram[251] sram->in sram[251]->out sram[251]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[251]->out) 0
.nodeset V(sram[251]->outb) vsp
Xsram[252] sram->in sram[252]->out sram[252]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[252]->out) 0
.nodeset V(sram[252]->outb) vsp
.eom

185
examples/spice_test_example_1/subckt/cbx_1_1.sp
View File

@ -1,185 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Connection Block X-channel [1][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
.subckt cbx[1][1]
+ chanx[1][1]_midout[0]
+ chanx[1][1]_midout[1]
+ chanx[1][1]_midout[2]
+ chanx[1][1]_midout[3]
+ chanx[1][1]_midout[4]
+ chanx[1][1]_midout[5]
+ chanx[1][1]_midout[6]
+ chanx[1][1]_midout[7]
+ chanx[1][1]_midout[8]
+ chanx[1][1]_midout[9]
+ chanx[1][1]_midout[10]
+ chanx[1][1]_midout[11]
+ chanx[1][1]_midout[12]
+ chanx[1][1]_midout[13]
+ chanx[1][1]_midout[14]
+ chanx[1][1]_midout[15]
+ chanx[1][1]_midout[16]
+ chanx[1][1]_midout[17]
+ chanx[1][1]_midout[18]
+ chanx[1][1]_midout[19]
+ chanx[1][1]_midout[20]
+ chanx[1][1]_midout[21]
+ chanx[1][1]_midout[22]
+ chanx[1][1]_midout[23]
+ chanx[1][1]_midout[24]
+ chanx[1][1]_midout[25]
+ chanx[1][1]_midout[26]
+ chanx[1][1]_midout[27]
+ chanx[1][1]_midout[28]
+ chanx[1][1]_midout[29]
+ grid[1][2]_pin[0][2][0]
+ grid[1][2]_pin[0][2][2]
+ grid[1][2]_pin[0][2][4]
+ grid[1][2]_pin[0][2][6]
+ grid[1][2]_pin[0][2][8]
+ grid[1][2]_pin[0][2][10]
+ grid[1][2]_pin[0][2][12]
+ grid[1][2]_pin[0][2][14]
+ grid[1][1]_pin[0][0][0]
+ svdd sgnd
Xmux_2level_tapbuf_size4[9] chanx[1][1]_midout[6] chanx[1][1]_midout[7] chanx[1][1]_midout[12] chanx[1][1]_midout[13] grid[1][2]_pin[0][2][0] sram[253]->outb sram[253]->out sram[254]->out sram[254]->outb sram[255]->outb sram[255]->out sram[256]->out sram[256]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[9], level=2, select_path_id=0. *****
*****1010*****
Xsram[253] sram->in sram[253]->out sram[253]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[253]->out) 0
.nodeset V(sram[253]->outb) vsp
Xsram[254] sram->in sram[254]->out sram[254]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[254]->out) 0
.nodeset V(sram[254]->outb) vsp
Xsram[255] sram->in sram[255]->out sram[255]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[255]->out) 0
.nodeset V(sram[255]->outb) vsp
Xsram[256] sram->in sram[256]->out sram[256]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[256]->out) 0
.nodeset V(sram[256]->outb) vsp
Xmux_2level_tapbuf_size4[10] chanx[1][1]_midout[0] chanx[1][1]_midout[1] chanx[1][1]_midout[18] chanx[1][1]_midout[19] grid[1][2]_pin[0][2][2] sram[257]->outb sram[257]->out sram[258]->out sram[258]->outb sram[259]->outb sram[259]->out sram[260]->out sram[260]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[10], level=2, select_path_id=0. *****
*****1010*****
Xsram[257] sram->in sram[257]->out sram[257]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[257]->out) 0
.nodeset V(sram[257]->outb) vsp
Xsram[258] sram->in sram[258]->out sram[258]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[258]->out) 0
.nodeset V(sram[258]->outb) vsp
Xsram[259] sram->in sram[259]->out sram[259]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[259]->out) 0
.nodeset V(sram[259]->outb) vsp
Xsram[260] sram->in sram[260]->out sram[260]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[260]->out) 0
.nodeset V(sram[260]->outb) vsp
Xmux_2level_tapbuf_size4[11] chanx[1][1]_midout[2] chanx[1][1]_midout[3] chanx[1][1]_midout[16] chanx[1][1]_midout[17] grid[1][2]_pin[0][2][4] sram[261]->outb sram[261]->out sram[262]->out sram[262]->outb sram[263]->outb sram[263]->out sram[264]->out sram[264]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[11], level=2, select_path_id=0. *****
*****1010*****
Xsram[261] sram->in sram[261]->out sram[261]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[261]->out) 0
.nodeset V(sram[261]->outb) vsp
Xsram[262] sram->in sram[262]->out sram[262]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[262]->out) 0
.nodeset V(sram[262]->outb) vsp
Xsram[263] sram->in sram[263]->out sram[263]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[263]->out) 0
.nodeset V(sram[263]->outb) vsp
Xsram[264] sram->in sram[264]->out sram[264]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[264]->out) 0
.nodeset V(sram[264]->outb) vsp
Xmux_2level_tapbuf_size4[12] chanx[1][1]_midout[4] chanx[1][1]_midout[5] chanx[1][1]_midout[20] chanx[1][1]_midout[21] grid[1][2]_pin[0][2][6] sram[265]->outb sram[265]->out sram[266]->out sram[266]->outb sram[267]->outb sram[267]->out sram[268]->out sram[268]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[12], level=2, select_path_id=0. *****
*****1010*****
Xsram[265] sram->in sram[265]->out sram[265]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[265]->out) 0
.nodeset V(sram[265]->outb) vsp
Xsram[266] sram->in sram[266]->out sram[266]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[266]->out) 0
.nodeset V(sram[266]->outb) vsp
Xsram[267] sram->in sram[267]->out sram[267]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[267]->out) 0
.nodeset V(sram[267]->outb) vsp
Xsram[268] sram->in sram[268]->out sram[268]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[268]->out) 0
.nodeset V(sram[268]->outb) vsp
Xmux_2level_tapbuf_size4[13] chanx[1][1]_midout[10] chanx[1][1]_midout[11] chanx[1][1]_midout[22] chanx[1][1]_midout[23] grid[1][2]_pin[0][2][8] sram[269]->outb sram[269]->out sram[270]->out sram[270]->outb sram[271]->outb sram[271]->out sram[272]->out sram[272]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[13], level=2, select_path_id=0. *****
*****1010*****
Xsram[269] sram->in sram[269]->out sram[269]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[269]->out) 0
.nodeset V(sram[269]->outb) vsp
Xsram[270] sram->in sram[270]->out sram[270]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[270]->out) 0
.nodeset V(sram[270]->outb) vsp
Xsram[271] sram->in sram[271]->out sram[271]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[271]->out) 0
.nodeset V(sram[271]->outb) vsp
Xsram[272] sram->in sram[272]->out sram[272]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[272]->out) 0
.nodeset V(sram[272]->outb) vsp
Xmux_2level_tapbuf_size4[14] chanx[1][1]_midout[8] chanx[1][1]_midout[9] chanx[1][1]_midout[24] chanx[1][1]_midout[25] grid[1][2]_pin[0][2][10] sram[273]->outb sram[273]->out sram[274]->out sram[274]->outb sram[275]->outb sram[275]->out sram[276]->out sram[276]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[14], level=2, select_path_id=0. *****
*****1010*****
Xsram[273] sram->in sram[273]->out sram[273]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[273]->out) 0
.nodeset V(sram[273]->outb) vsp
Xsram[274] sram->in sram[274]->out sram[274]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[274]->out) 0
.nodeset V(sram[274]->outb) vsp
Xsram[275] sram->in sram[275]->out sram[275]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[275]->out) 0
.nodeset V(sram[275]->outb) vsp
Xsram[276] sram->in sram[276]->out sram[276]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[276]->out) 0
.nodeset V(sram[276]->outb) vsp
Xmux_2level_tapbuf_size4[15] chanx[1][1]_midout[14] chanx[1][1]_midout[15] chanx[1][1]_midout[26] chanx[1][1]_midout[27] grid[1][2]_pin[0][2][12] sram[277]->outb sram[277]->out sram[278]->out sram[278]->outb sram[279]->outb sram[279]->out sram[280]->out sram[280]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[15], level=2, select_path_id=0. *****
*****1010*****
Xsram[277] sram->in sram[277]->out sram[277]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[277]->out) 0
.nodeset V(sram[277]->outb) vsp
Xsram[278] sram->in sram[278]->out sram[278]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[278]->out) 0
.nodeset V(sram[278]->outb) vsp
Xsram[279] sram->in sram[279]->out sram[279]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[279]->out) 0
.nodeset V(sram[279]->outb) vsp
Xsram[280] sram->in sram[280]->out sram[280]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[280]->out) 0
.nodeset V(sram[280]->outb) vsp
Xmux_2level_tapbuf_size4[16] chanx[1][1]_midout[12] chanx[1][1]_midout[13] chanx[1][1]_midout[28] chanx[1][1]_midout[29] grid[1][2]_pin[0][2][14] sram[281]->outb sram[281]->out sram[282]->out sram[282]->outb sram[283]->outb sram[283]->out sram[284]->out sram[284]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[16], level=2, select_path_id=0. *****
*****1010*****
Xsram[281] sram->in sram[281]->out sram[281]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[281]->out) 0
.nodeset V(sram[281]->outb) vsp
Xsram[282] sram->in sram[282]->out sram[282]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[282]->out) 0
.nodeset V(sram[282]->outb) vsp
Xsram[283] sram->in sram[283]->out sram[283]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[283]->out) 0
.nodeset V(sram[283]->outb) vsp
Xsram[284] sram->in sram[284]->out sram[284]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[284]->out) 0
.nodeset V(sram[284]->outb) vsp
Xmux_2level_tapbuf_size4[17] chanx[1][1]_midout[6] chanx[1][1]_midout[7] chanx[1][1]_midout[12] chanx[1][1]_midout[13] grid[1][1]_pin[0][0][0] sram[285]->outb sram[285]->out sram[286]->out sram[286]->outb sram[287]->outb sram[287]->out sram[288]->out sram[288]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[17], level=2, select_path_id=0. *****
*****1010*****
Xsram[285] sram->in sram[285]->out sram[285]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[285]->out) 0
.nodeset V(sram[285]->outb) vsp
Xsram[286] sram->in sram[286]->out sram[286]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[286]->out) 0
.nodeset V(sram[286]->outb) vsp
Xsram[287] sram->in sram[287]->out sram[287]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[287]->out) 0
.nodeset V(sram[287]->outb) vsp
Xsram[288] sram->in sram[288]->out sram[288]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[288]->out) 0
.nodeset V(sram[288]->outb) vsp
.eom

185
examples/spice_test_example_1/subckt/cby_0_1.sp
View File

@ -1,185 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Connection Block Y-channel [0][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
.subckt cby[0][1]
+ chany[0][1]_midout[0]
+ chany[0][1]_midout[1]
+ chany[0][1]_midout[2]
+ chany[0][1]_midout[3]
+ chany[0][1]_midout[4]
+ chany[0][1]_midout[5]
+ chany[0][1]_midout[6]
+ chany[0][1]_midout[7]
+ chany[0][1]_midout[8]
+ chany[0][1]_midout[9]
+ chany[0][1]_midout[10]
+ chany[0][1]_midout[11]
+ chany[0][1]_midout[12]
+ chany[0][1]_midout[13]
+ chany[0][1]_midout[14]
+ chany[0][1]_midout[15]
+ chany[0][1]_midout[16]
+ chany[0][1]_midout[17]
+ chany[0][1]_midout[18]
+ chany[0][1]_midout[19]
+ chany[0][1]_midout[20]
+ chany[0][1]_midout[21]
+ chany[0][1]_midout[22]
+ chany[0][1]_midout[23]
+ chany[0][1]_midout[24]
+ chany[0][1]_midout[25]
+ chany[0][1]_midout[26]
+ chany[0][1]_midout[27]
+ chany[0][1]_midout[28]
+ chany[0][1]_midout[29]
+ grid[1][1]_pin[0][3][3]
+ grid[0][1]_pin[0][1][0]
+ grid[0][1]_pin[0][1][2]
+ grid[0][1]_pin[0][1][4]
+ grid[0][1]_pin[0][1][6]
+ grid[0][1]_pin[0][1][8]
+ grid[0][1]_pin[0][1][10]
+ grid[0][1]_pin[0][1][12]
+ grid[0][1]_pin[0][1][14]
+ svdd sgnd
Xmux_2level_tapbuf_size4[18] chany[0][1]_midout[10] chany[0][1]_midout[11] chany[0][1]_midout[26] chany[0][1]_midout[27] grid[1][1]_pin[0][3][3] sram[289]->out sram[289]->outb sram[290]->outb sram[290]->out sram[291]->out sram[291]->outb sram[292]->outb sram[292]->out svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[18], level=2, select_path_id=3. *****
*****0101*****
Xsram[289] sram->in sram[289]->out sram[289]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[289]->out) 0
.nodeset V(sram[289]->outb) vsp
Xsram[290] sram->in sram[290]->out sram[290]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[290]->out) 0
.nodeset V(sram[290]->outb) vsp
Xsram[291] sram->in sram[291]->out sram[291]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[291]->out) 0
.nodeset V(sram[291]->outb) vsp
Xsram[292] sram->in sram[292]->out sram[292]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[292]->out) 0
.nodeset V(sram[292]->outb) vsp
Xmux_2level_tapbuf_size4[19] chany[0][1]_midout[0] chany[0][1]_midout[1] chany[0][1]_midout[14] chany[0][1]_midout[15] grid[0][1]_pin[0][1][0] sram[293]->outb sram[293]->out sram[294]->out sram[294]->outb sram[295]->outb sram[295]->out sram[296]->out sram[296]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[19], level=2, select_path_id=0. *****
*****1010*****
Xsram[293] sram->in sram[293]->out sram[293]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[293]->out) 0
.nodeset V(sram[293]->outb) vsp
Xsram[294] sram->in sram[294]->out sram[294]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[294]->out) 0
.nodeset V(sram[294]->outb) vsp
Xsram[295] sram->in sram[295]->out sram[295]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[295]->out) 0
.nodeset V(sram[295]->outb) vsp
Xsram[296] sram->in sram[296]->out sram[296]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[296]->out) 0
.nodeset V(sram[296]->outb) vsp
Xmux_2level_tapbuf_size4[20] chany[0][1]_midout[2] chany[0][1]_midout[3] chany[0][1]_midout[16] chany[0][1]_midout[17] grid[0][1]_pin[0][1][2] sram[297]->outb sram[297]->out sram[298]->out sram[298]->outb sram[299]->outb sram[299]->out sram[300]->out sram[300]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[20], level=2, select_path_id=0. *****
*****1010*****
Xsram[297] sram->in sram[297]->out sram[297]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[297]->out) 0
.nodeset V(sram[297]->outb) vsp
Xsram[298] sram->in sram[298]->out sram[298]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[298]->out) 0
.nodeset V(sram[298]->outb) vsp
Xsram[299] sram->in sram[299]->out sram[299]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[299]->out) 0
.nodeset V(sram[299]->outb) vsp
Xsram[300] sram->in sram[300]->out sram[300]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[300]->out) 0
.nodeset V(sram[300]->outb) vsp
Xmux_2level_tapbuf_size4[21] chany[0][1]_midout[4] chany[0][1]_midout[5] chany[0][1]_midout[18] chany[0][1]_midout[19] grid[0][1]_pin[0][1][4] sram[301]->outb sram[301]->out sram[302]->out sram[302]->outb sram[303]->outb sram[303]->out sram[304]->out sram[304]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[21], level=2, select_path_id=0. *****
*****1010*****
Xsram[301] sram->in sram[301]->out sram[301]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[301]->out) 0
.nodeset V(sram[301]->outb) vsp
Xsram[302] sram->in sram[302]->out sram[302]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[302]->out) 0
.nodeset V(sram[302]->outb) vsp
Xsram[303] sram->in sram[303]->out sram[303]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[303]->out) 0
.nodeset V(sram[303]->outb) vsp
Xsram[304] sram->in sram[304]->out sram[304]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[304]->out) 0
.nodeset V(sram[304]->outb) vsp
Xmux_2level_tapbuf_size4[22] chany[0][1]_midout[6] chany[0][1]_midout[7] chany[0][1]_midout[20] chany[0][1]_midout[21] grid[0][1]_pin[0][1][6] sram[305]->outb sram[305]->out sram[306]->out sram[306]->outb sram[307]->outb sram[307]->out sram[308]->out sram[308]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[22], level=2, select_path_id=0. *****
*****1010*****
Xsram[305] sram->in sram[305]->out sram[305]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[305]->out) 0
.nodeset V(sram[305]->outb) vsp
Xsram[306] sram->in sram[306]->out sram[306]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[306]->out) 0
.nodeset V(sram[306]->outb) vsp
Xsram[307] sram->in sram[307]->out sram[307]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[307]->out) 0
.nodeset V(sram[307]->outb) vsp
Xsram[308] sram->in sram[308]->out sram[308]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[308]->out) 0
.nodeset V(sram[308]->outb) vsp
Xmux_2level_tapbuf_size4[23] chany[0][1]_midout[6] chany[0][1]_midout[7] chany[0][1]_midout[22] chany[0][1]_midout[23] grid[0][1]_pin[0][1][8] sram[309]->outb sram[309]->out sram[310]->out sram[310]->outb sram[311]->outb sram[311]->out sram[312]->out sram[312]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[23], level=2, select_path_id=0. *****
*****1010*****
Xsram[309] sram->in sram[309]->out sram[309]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[309]->out) 0
.nodeset V(sram[309]->outb) vsp
Xsram[310] sram->in sram[310]->out sram[310]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[310]->out) 0
.nodeset V(sram[310]->outb) vsp
Xsram[311] sram->in sram[311]->out sram[311]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[311]->out) 0
.nodeset V(sram[311]->outb) vsp
Xsram[312] sram->in sram[312]->out sram[312]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[312]->out) 0
.nodeset V(sram[312]->outb) vsp
Xmux_2level_tapbuf_size4[24] chany[0][1]_midout[8] chany[0][1]_midout[9] chany[0][1]_midout[24] chany[0][1]_midout[25] grid[0][1]_pin[0][1][10] sram[313]->outb sram[313]->out sram[314]->out sram[314]->outb sram[315]->outb sram[315]->out sram[316]->out sram[316]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[24], level=2, select_path_id=0. *****
*****1010*****
Xsram[313] sram->in sram[313]->out sram[313]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[313]->out) 0
.nodeset V(sram[313]->outb) vsp
Xsram[314] sram->in sram[314]->out sram[314]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[314]->out) 0
.nodeset V(sram[314]->outb) vsp
Xsram[315] sram->in sram[315]->out sram[315]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[315]->out) 0
.nodeset V(sram[315]->outb) vsp
Xsram[316] sram->in sram[316]->out sram[316]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[316]->out) 0
.nodeset V(sram[316]->outb) vsp
Xmux_2level_tapbuf_size4[25] chany[0][1]_midout[10] chany[0][1]_midout[11] chany[0][1]_midout[26] chany[0][1]_midout[27] grid[0][1]_pin[0][1][12] sram[317]->outb sram[317]->out sram[318]->out sram[318]->outb sram[319]->outb sram[319]->out sram[320]->out sram[320]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[25], level=2, select_path_id=0. *****
*****1010*****
Xsram[317] sram->in sram[317]->out sram[317]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[317]->out) 0
.nodeset V(sram[317]->outb) vsp
Xsram[318] sram->in sram[318]->out sram[318]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[318]->out) 0
.nodeset V(sram[318]->outb) vsp
Xsram[319] sram->in sram[319]->out sram[319]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[319]->out) 0
.nodeset V(sram[319]->outb) vsp
Xsram[320] sram->in sram[320]->out sram[320]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[320]->out) 0
.nodeset V(sram[320]->outb) vsp
Xmux_2level_tapbuf_size4[26] chany[0][1]_midout[12] chany[0][1]_midout[13] chany[0][1]_midout[28] chany[0][1]_midout[29] grid[0][1]_pin[0][1][14] sram[321]->outb sram[321]->out sram[322]->out sram[322]->outb sram[323]->outb sram[323]->out sram[324]->out sram[324]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[26], level=2, select_path_id=0. *****
*****1010*****
Xsram[321] sram->in sram[321]->out sram[321]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[321]->out) 0
.nodeset V(sram[321]->outb) vsp
Xsram[322] sram->in sram[322]->out sram[322]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[322]->out) 0
.nodeset V(sram[322]->outb) vsp
Xsram[323] sram->in sram[323]->out sram[323]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[323]->out) 0
.nodeset V(sram[323]->outb) vsp
Xsram[324] sram->in sram[324]->out sram[324]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[324]->out) 0
.nodeset V(sram[324]->outb) vsp
.eom

186
examples/spice_test_example_1/subckt/cby_1_1.sp
View File

@ -1,186 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Connection Block Y-channel [1][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
.subckt cby[1][1]
+ chany[1][1]_midout[0]
+ chany[1][1]_midout[1]
+ chany[1][1]_midout[2]
+ chany[1][1]_midout[3]
+ chany[1][1]_midout[4]
+ chany[1][1]_midout[5]
+ chany[1][1]_midout[6]
+ chany[1][1]_midout[7]
+ chany[1][1]_midout[8]
+ chany[1][1]_midout[9]
+ chany[1][1]_midout[10]
+ chany[1][1]_midout[11]
+ chany[1][1]_midout[12]
+ chany[1][1]_midout[13]
+ chany[1][1]_midout[14]
+ chany[1][1]_midout[15]
+ chany[1][1]_midout[16]
+ chany[1][1]_midout[17]
+ chany[1][1]_midout[18]
+ chany[1][1]_midout[19]
+ chany[1][1]_midout[20]
+ chany[1][1]_midout[21]
+ chany[1][1]_midout[22]
+ chany[1][1]_midout[23]
+ chany[1][1]_midout[24]
+ chany[1][1]_midout[25]
+ chany[1][1]_midout[26]
+ chany[1][1]_midout[27]
+ chany[1][1]_midout[28]
+ chany[1][1]_midout[29]
+ grid[2][1]_pin[0][3][0]
+ grid[2][1]_pin[0][3][2]
+ grid[2][1]_pin[0][3][4]
+ grid[2][1]_pin[0][3][6]
+ grid[2][1]_pin[0][3][8]
+ grid[2][1]_pin[0][3][10]
+ grid[2][1]_pin[0][3][12]
+ grid[2][1]_pin[0][3][14]
+ grid[1][1]_pin[0][1][1]
+ grid[1][1]_pin[0][1][5]
+ svdd sgnd
Xmux_2level_tapbuf_size4[27] chany[1][1]_midout[6] chany[1][1]_midout[7] chany[1][1]_midout[18] chany[1][1]_midout[19] grid[2][1]_pin[0][3][0] sram[325]->outb sram[325]->out sram[326]->out sram[326]->outb sram[327]->outb sram[327]->out sram[328]->out sram[328]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[27], level=2, select_path_id=0. *****
*****1010*****
Xsram[325] sram->in sram[325]->out sram[325]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[325]->out) 0
.nodeset V(sram[325]->outb) vsp
Xsram[326] sram->in sram[326]->out sram[326]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[326]->out) 0
.nodeset V(sram[326]->outb) vsp
Xsram[327] sram->in sram[327]->out sram[327]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[327]->out) 0
.nodeset V(sram[327]->outb) vsp
Xsram[328] sram->in sram[328]->out sram[328]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[328]->out) 0
.nodeset V(sram[328]->outb) vsp
Xmux_2level_tapbuf_size4[28] chany[1][1]_midout[0] chany[1][1]_midout[1] chany[1][1]_midout[16] chany[1][1]_midout[17] grid[2][1]_pin[0][3][2] sram[329]->outb sram[329]->out sram[330]->out sram[330]->outb sram[331]->outb sram[331]->out sram[332]->out sram[332]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[28], level=2, select_path_id=0. *****
*****1010*****
Xsram[329] sram->in sram[329]->out sram[329]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[329]->out) 0
.nodeset V(sram[329]->outb) vsp
Xsram[330] sram->in sram[330]->out sram[330]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[330]->out) 0
.nodeset V(sram[330]->outb) vsp
Xsram[331] sram->in sram[331]->out sram[331]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[331]->out) 0
.nodeset V(sram[331]->outb) vsp
Xsram[332] sram->in sram[332]->out sram[332]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[332]->out) 0
.nodeset V(sram[332]->outb) vsp
Xmux_2level_tapbuf_size4[29] chany[1][1]_midout[2] chany[1][1]_midout[3] chany[1][1]_midout[20] chany[1][1]_midout[21] grid[2][1]_pin[0][3][4] sram[333]->outb sram[333]->out sram[334]->out sram[334]->outb sram[335]->outb sram[335]->out sram[336]->out sram[336]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[29], level=2, select_path_id=0. *****
*****1010*****
Xsram[333] sram->in sram[333]->out sram[333]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[333]->out) 0
.nodeset V(sram[333]->outb) vsp
Xsram[334] sram->in sram[334]->out sram[334]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[334]->out) 0
.nodeset V(sram[334]->outb) vsp
Xsram[335] sram->in sram[335]->out sram[335]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[335]->out) 0
.nodeset V(sram[335]->outb) vsp
Xsram[336] sram->in sram[336]->out sram[336]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[336]->out) 0
.nodeset V(sram[336]->outb) vsp
Xmux_2level_tapbuf_size4[30] chany[1][1]_midout[4] chany[1][1]_midout[5] chany[1][1]_midout[22] chany[1][1]_midout[23] grid[2][1]_pin[0][3][6] sram[337]->outb sram[337]->out sram[338]->out sram[338]->outb sram[339]->outb sram[339]->out sram[340]->out sram[340]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[30], level=2, select_path_id=0. *****
*****1010*****
Xsram[337] sram->in sram[337]->out sram[337]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[337]->out) 0
.nodeset V(sram[337]->outb) vsp
Xsram[338] sram->in sram[338]->out sram[338]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[338]->out) 0
.nodeset V(sram[338]->outb) vsp
Xsram[339] sram->in sram[339]->out sram[339]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[339]->out) 0
.nodeset V(sram[339]->outb) vsp
Xsram[340] sram->in sram[340]->out sram[340]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[340]->out) 0
.nodeset V(sram[340]->outb) vsp
Xmux_2level_tapbuf_size4[31] chany[1][1]_midout[10] chany[1][1]_midout[11] chany[1][1]_midout[22] chany[1][1]_midout[23] grid[2][1]_pin[0][3][8] sram[341]->outb sram[341]->out sram[342]->out sram[342]->outb sram[343]->outb sram[343]->out sram[344]->out sram[344]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[31], level=2, select_path_id=0. *****
*****1010*****
Xsram[341] sram->in sram[341]->out sram[341]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[341]->out) 0
.nodeset V(sram[341]->outb) vsp
Xsram[342] sram->in sram[342]->out sram[342]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[342]->out) 0
.nodeset V(sram[342]->outb) vsp
Xsram[343] sram->in sram[343]->out sram[343]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[343]->out) 0
.nodeset V(sram[343]->outb) vsp
Xsram[344] sram->in sram[344]->out sram[344]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[344]->out) 0
.nodeset V(sram[344]->outb) vsp
Xmux_2level_tapbuf_size4[32] chany[1][1]_midout[8] chany[1][1]_midout[9] chany[1][1]_midout[24] chany[1][1]_midout[25] grid[2][1]_pin[0][3][10] sram[345]->outb sram[345]->out sram[346]->out sram[346]->outb sram[347]->outb sram[347]->out sram[348]->out sram[348]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[32], level=2, select_path_id=0. *****
*****1010*****
Xsram[345] sram->in sram[345]->out sram[345]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[345]->out) 0
.nodeset V(sram[345]->outb) vsp
Xsram[346] sram->in sram[346]->out sram[346]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[346]->out) 0
.nodeset V(sram[346]->outb) vsp
Xsram[347] sram->in sram[347]->out sram[347]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[347]->out) 0
.nodeset V(sram[347]->outb) vsp
Xsram[348] sram->in sram[348]->out sram[348]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[348]->out) 0
.nodeset V(sram[348]->outb) vsp
Xmux_2level_tapbuf_size4[33] chany[1][1]_midout[14] chany[1][1]_midout[15] chany[1][1]_midout[26] chany[1][1]_midout[27] grid[2][1]_pin[0][3][12] sram[349]->outb sram[349]->out sram[350]->out sram[350]->outb sram[351]->outb sram[351]->out sram[352]->out sram[352]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[33], level=2, select_path_id=0. *****
*****1010*****
Xsram[349] sram->in sram[349]->out sram[349]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[349]->out) 0
.nodeset V(sram[349]->outb) vsp
Xsram[350] sram->in sram[350]->out sram[350]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[350]->out) 0
.nodeset V(sram[350]->outb) vsp
Xsram[351] sram->in sram[351]->out sram[351]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[351]->out) 0
.nodeset V(sram[351]->outb) vsp
Xsram[352] sram->in sram[352]->out sram[352]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[352]->out) 0
.nodeset V(sram[352]->outb) vsp
Xmux_2level_tapbuf_size4[34] chany[1][1]_midout[12] chany[1][1]_midout[13] chany[1][1]_midout[28] chany[1][1]_midout[29] grid[2][1]_pin[0][3][14] sram[353]->outb sram[353]->out sram[354]->out sram[354]->outb sram[355]->outb sram[355]->out sram[356]->out sram[356]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[34], level=2, select_path_id=0. *****
*****1010*****
Xsram[353] sram->in sram[353]->out sram[353]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[353]->out) 0
.nodeset V(sram[353]->outb) vsp
Xsram[354] sram->in sram[354]->out sram[354]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[354]->out) 0
.nodeset V(sram[354]->outb) vsp
Xsram[355] sram->in sram[355]->out sram[355]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[355]->out) 0
.nodeset V(sram[355]->outb) vsp
Xsram[356] sram->in sram[356]->out sram[356]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[356]->out) 0
.nodeset V(sram[356]->outb) vsp
Xmux_2level_tapbuf_size4[35] chany[1][1]_midout[0] chany[1][1]_midout[1] chany[1][1]_midout[16] chany[1][1]_midout[17] grid[1][1]_pin[0][1][1] sram[357]->outb sram[357]->out sram[358]->out sram[358]->outb sram[359]->outb sram[359]->out sram[360]->out sram[360]->outb svdd sgnd mux_2level_tapbuf_size4
***** SRAM bits for MUX[35], level=2, select_path_id=0. *****
*****1010*****
Xsram[357] sram->in sram[357]->out sram[357]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[357]->out) 0
.nodeset V(sram[357]->outb) vsp
Xsram[358] sram->in sram[358]->out sram[358]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[358]->out) 0
.nodeset V(sram[358]->outb) vsp
Xsram[359] sram->in sram[359]->out sram[359]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[359]->out) 0
.nodeset V(sram[359]->outb) vsp
Xsram[360] sram->in sram[360]->out sram[360]->outb gvdd_sram_cbs sgnd sram6T
.nodeset V(sram[360]->out) 0
.nodeset V(sram[360]->outb) vsp
.eom

45
examples/spice_test_example_1/subckt/chanx_1_0.sp
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@ -1,45 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Channel X-direction [1][0] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Subckt for Channel X [1][0] *****
.subckt chanx[1][0]
+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29
+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29
+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29
+ svdd sgnd
Xtrack_seg[0] in0 out0 mid_out0 svdd sgnd chan_segment_seg0
Xtrack_seg[1] in1 out1 mid_out1 svdd sgnd chan_segment_seg0
Xtrack_seg[2] in2 out2 mid_out2 svdd sgnd chan_segment_seg0
Xtrack_seg[3] in3 out3 mid_out3 svdd sgnd chan_segment_seg0
Xtrack_seg[4] in4 out4 mid_out4 svdd sgnd chan_segment_seg0
Xtrack_seg[5] in5 out5 mid_out5 svdd sgnd chan_segment_seg0
Xtrack_seg[6] in6 out6 mid_out6 svdd sgnd chan_segment_seg0
Xtrack_seg[7] in7 out7 mid_out7 svdd sgnd chan_segment_seg0
Xtrack_seg[8] in8 out8 mid_out8 svdd sgnd chan_segment_seg0
Xtrack_seg[9] in9 out9 mid_out9 svdd sgnd chan_segment_seg0
Xtrack_seg[10] in10 out10 mid_out10 svdd sgnd chan_segment_seg0
Xtrack_seg[11] in11 out11 mid_out11 svdd sgnd chan_segment_seg0
Xtrack_seg[12] in12 out12 mid_out12 svdd sgnd chan_segment_seg1
Xtrack_seg[13] in13 out13 mid_out13 svdd sgnd chan_segment_seg1
Xtrack_seg[14] in14 out14 mid_out14 svdd sgnd chan_segment_seg1
Xtrack_seg[15] in15 out15 mid_out15 svdd sgnd chan_segment_seg1
Xtrack_seg[16] in16 out16 mid_out16 svdd sgnd chan_segment_seg1
Xtrack_seg[17] in17 out17 mid_out17 svdd sgnd chan_segment_seg1
Xtrack_seg[18] in18 out18 mid_out18 svdd sgnd chan_segment_seg1
Xtrack_seg[19] in19 out19 mid_out19 svdd sgnd chan_segment_seg1
Xtrack_seg[20] in20 out20 mid_out20 svdd sgnd chan_segment_seg1
Xtrack_seg[21] in21 out21 mid_out21 svdd sgnd chan_segment_seg1
Xtrack_seg[22] in22 out22 mid_out22 svdd sgnd chan_segment_seg2
Xtrack_seg[23] in23 out23 mid_out23 svdd sgnd chan_segment_seg2
Xtrack_seg[24] in24 out24 mid_out24 svdd sgnd chan_segment_seg2
Xtrack_seg[25] in25 out25 mid_out25 svdd sgnd chan_segment_seg2
Xtrack_seg[26] in26 out26 mid_out26 svdd sgnd chan_segment_seg2
Xtrack_seg[27] in27 out27 mid_out27 svdd sgnd chan_segment_seg2
Xtrack_seg[28] in28 out28 mid_out28 svdd sgnd chan_segment_seg2
Xtrack_seg[29] in29 out29 mid_out29 svdd sgnd chan_segment_seg2
.eom

45
examples/spice_test_example_1/subckt/chanx_1_1.sp
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@ -1,45 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Channel X-direction [1][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Subckt for Channel X [1][1] *****
.subckt chanx[1][1]
+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29
+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29
+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29
+ svdd sgnd
Xtrack_seg[30] in0 out0 mid_out0 svdd sgnd chan_segment_seg0
Xtrack_seg[31] in1 out1 mid_out1 svdd sgnd chan_segment_seg0
Xtrack_seg[32] in2 out2 mid_out2 svdd sgnd chan_segment_seg0
Xtrack_seg[33] in3 out3 mid_out3 svdd sgnd chan_segment_seg0
Xtrack_seg[34] in4 out4 mid_out4 svdd sgnd chan_segment_seg0
Xtrack_seg[35] in5 out5 mid_out5 svdd sgnd chan_segment_seg0
Xtrack_seg[36] in6 out6 mid_out6 svdd sgnd chan_segment_seg0
Xtrack_seg[37] in7 out7 mid_out7 svdd sgnd chan_segment_seg0
Xtrack_seg[38] in8 out8 mid_out8 svdd sgnd chan_segment_seg0
Xtrack_seg[39] in9 out9 mid_out9 svdd sgnd chan_segment_seg0
Xtrack_seg[40] in10 out10 mid_out10 svdd sgnd chan_segment_seg0
Xtrack_seg[41] in11 out11 mid_out11 svdd sgnd chan_segment_seg0
Xtrack_seg[42] in12 out12 mid_out12 svdd sgnd chan_segment_seg1
Xtrack_seg[43] in13 out13 mid_out13 svdd sgnd chan_segment_seg1
Xtrack_seg[44] in14 out14 mid_out14 svdd sgnd chan_segment_seg1
Xtrack_seg[45] in15 out15 mid_out15 svdd sgnd chan_segment_seg1
Xtrack_seg[46] in16 out16 mid_out16 svdd sgnd chan_segment_seg1
Xtrack_seg[47] in17 out17 mid_out17 svdd sgnd chan_segment_seg1
Xtrack_seg[48] in18 out18 mid_out18 svdd sgnd chan_segment_seg1
Xtrack_seg[49] in19 out19 mid_out19 svdd sgnd chan_segment_seg1
Xtrack_seg[50] in20 out20 mid_out20 svdd sgnd chan_segment_seg1
Xtrack_seg[51] in21 out21 mid_out21 svdd sgnd chan_segment_seg1
Xtrack_seg[52] in22 out22 mid_out22 svdd sgnd chan_segment_seg2
Xtrack_seg[53] in23 out23 mid_out23 svdd sgnd chan_segment_seg2
Xtrack_seg[54] in24 out24 mid_out24 svdd sgnd chan_segment_seg2
Xtrack_seg[55] in25 out25 mid_out25 svdd sgnd chan_segment_seg2
Xtrack_seg[56] in26 out26 mid_out26 svdd sgnd chan_segment_seg2
Xtrack_seg[57] in27 out27 mid_out27 svdd sgnd chan_segment_seg2
Xtrack_seg[58] in28 out28 mid_out28 svdd sgnd chan_segment_seg2
Xtrack_seg[59] in29 out29 mid_out29 svdd sgnd chan_segment_seg2
.eom

45
examples/spice_test_example_1/subckt/chany_0_1.sp
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@ -1,45 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Channel Y-direction [0][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Subckt for Channel Y [0][1] *****
.subckt chany[0][1]
+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29
+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29
+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29
+ svdd sgnd
Xtrack_seg[60] in0 out0 mid_out0 svdd sgnd chan_segment_seg0
Xtrack_seg[61] in1 out1 mid_out1 svdd sgnd chan_segment_seg0
Xtrack_seg[62] in2 out2 mid_out2 svdd sgnd chan_segment_seg0
Xtrack_seg[63] in3 out3 mid_out3 svdd sgnd chan_segment_seg0
Xtrack_seg[64] in4 out4 mid_out4 svdd sgnd chan_segment_seg0
Xtrack_seg[65] in5 out5 mid_out5 svdd sgnd chan_segment_seg0
Xtrack_seg[66] in6 out6 mid_out6 svdd sgnd chan_segment_seg0
Xtrack_seg[67] in7 out7 mid_out7 svdd sgnd chan_segment_seg0
Xtrack_seg[68] in8 out8 mid_out8 svdd sgnd chan_segment_seg0
Xtrack_seg[69] in9 out9 mid_out9 svdd sgnd chan_segment_seg0
Xtrack_seg[70] in10 out10 mid_out10 svdd sgnd chan_segment_seg0
Xtrack_seg[71] in11 out11 mid_out11 svdd sgnd chan_segment_seg0
Xtrack_seg[72] in12 out12 mid_out12 svdd sgnd chan_segment_seg1
Xtrack_seg[73] in13 out13 mid_out13 svdd sgnd chan_segment_seg1
Xtrack_seg[74] in14 out14 mid_out14 svdd sgnd chan_segment_seg1
Xtrack_seg[75] in15 out15 mid_out15 svdd sgnd chan_segment_seg1
Xtrack_seg[76] in16 out16 mid_out16 svdd sgnd chan_segment_seg1
Xtrack_seg[77] in17 out17 mid_out17 svdd sgnd chan_segment_seg1
Xtrack_seg[78] in18 out18 mid_out18 svdd sgnd chan_segment_seg1
Xtrack_seg[79] in19 out19 mid_out19 svdd sgnd chan_segment_seg1
Xtrack_seg[80] in20 out20 mid_out20 svdd sgnd chan_segment_seg1
Xtrack_seg[81] in21 out21 mid_out21 svdd sgnd chan_segment_seg1
Xtrack_seg[82] in22 out22 mid_out22 svdd sgnd chan_segment_seg2
Xtrack_seg[83] in23 out23 mid_out23 svdd sgnd chan_segment_seg2
Xtrack_seg[84] in24 out24 mid_out24 svdd sgnd chan_segment_seg2
Xtrack_seg[85] in25 out25 mid_out25 svdd sgnd chan_segment_seg2
Xtrack_seg[86] in26 out26 mid_out26 svdd sgnd chan_segment_seg2
Xtrack_seg[87] in27 out27 mid_out27 svdd sgnd chan_segment_seg2
Xtrack_seg[88] in28 out28 mid_out28 svdd sgnd chan_segment_seg2
Xtrack_seg[89] in29 out29 mid_out29 svdd sgnd chan_segment_seg2
.eom

45
examples/spice_test_example_1/subckt/chany_1_1.sp
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@ -1,45 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Channel Y-direction [1][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Subckt for Channel Y [1][1] *****
.subckt chany[1][1]
+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29
+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29
+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29
+ svdd sgnd
Xtrack_seg[90] in0 out0 mid_out0 svdd sgnd chan_segment_seg0
Xtrack_seg[91] in1 out1 mid_out1 svdd sgnd chan_segment_seg0
Xtrack_seg[92] in2 out2 mid_out2 svdd sgnd chan_segment_seg0
Xtrack_seg[93] in3 out3 mid_out3 svdd sgnd chan_segment_seg0
Xtrack_seg[94] in4 out4 mid_out4 svdd sgnd chan_segment_seg0
Xtrack_seg[95] in5 out5 mid_out5 svdd sgnd chan_segment_seg0
Xtrack_seg[96] in6 out6 mid_out6 svdd sgnd chan_segment_seg0
Xtrack_seg[97] in7 out7 mid_out7 svdd sgnd chan_segment_seg0
Xtrack_seg[98] in8 out8 mid_out8 svdd sgnd chan_segment_seg0
Xtrack_seg[99] in9 out9 mid_out9 svdd sgnd chan_segment_seg0
Xtrack_seg[100] in10 out10 mid_out10 svdd sgnd chan_segment_seg0
Xtrack_seg[101] in11 out11 mid_out11 svdd sgnd chan_segment_seg0
Xtrack_seg[102] in12 out12 mid_out12 svdd sgnd chan_segment_seg1
Xtrack_seg[103] in13 out13 mid_out13 svdd sgnd chan_segment_seg1
Xtrack_seg[104] in14 out14 mid_out14 svdd sgnd chan_segment_seg1
Xtrack_seg[105] in15 out15 mid_out15 svdd sgnd chan_segment_seg1
Xtrack_seg[106] in16 out16 mid_out16 svdd sgnd chan_segment_seg1
Xtrack_seg[107] in17 out17 mid_out17 svdd sgnd chan_segment_seg1
Xtrack_seg[108] in18 out18 mid_out18 svdd sgnd chan_segment_seg1
Xtrack_seg[109] in19 out19 mid_out19 svdd sgnd chan_segment_seg1
Xtrack_seg[110] in20 out20 mid_out20 svdd sgnd chan_segment_seg1
Xtrack_seg[111] in21 out21 mid_out21 svdd sgnd chan_segment_seg1
Xtrack_seg[112] in22 out22 mid_out22 svdd sgnd chan_segment_seg2
Xtrack_seg[113] in23 out23 mid_out23 svdd sgnd chan_segment_seg2
Xtrack_seg[114] in24 out24 mid_out24 svdd sgnd chan_segment_seg2
Xtrack_seg[115] in25 out25 mid_out25 svdd sgnd chan_segment_seg2
Xtrack_seg[116] in26 out26 mid_out26 svdd sgnd chan_segment_seg2
Xtrack_seg[117] in27 out27 mid_out27 svdd sgnd chan_segment_seg2
Xtrack_seg[118] in28 out28 mid_out28 svdd sgnd chan_segment_seg2
Xtrack_seg[119] in29 out29 mid_out29 svdd sgnd chan_segment_seg2
.eom

221
examples/spice_test_example_1/subckt/grid_0_1.sp
View File

@ -1,221 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Phyiscal Logic Block [0][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Grid[0][1] type_descriptor: io[0] *****
.subckt grid[0][1]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[0]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[0] sram[41]->outb sram[41]->out gvdd_iopad[0] sgnd iopad
***** SRAM bits for IOPAD[0] *****
*****1*****
Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[41]->out) 0
.nodeset V(sram[41]->outb) vsp
.eom
.subckt grid[0][1]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[0]_mode[io_phy]_iopad[0]
Xdirect_interc[14] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[15] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[0][1] type_descriptor: io[1] *****
.subckt grid[0][1]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[1]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[1] sram[42]->outb sram[42]->out gvdd_iopad[1] sgnd iopad
***** SRAM bits for IOPAD[1] *****
*****1*****
Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[42]->out) 0
.nodeset V(sram[42]->outb) vsp
.eom
.subckt grid[0][1]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[1]_mode[io_phy]_iopad[0]
Xdirect_interc[16] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[17] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[0][1] type_descriptor: io[2] *****
.subckt grid[0][1]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[2]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[2] sram[43]->outb sram[43]->out gvdd_iopad[2] sgnd iopad
***** SRAM bits for IOPAD[2] *****
*****1*****
Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[43]->out) 0
.nodeset V(sram[43]->outb) vsp
.eom
.subckt grid[0][1]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[2]_mode[io_phy]_iopad[0]
Xdirect_interc[18] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[19] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[0][1] type_descriptor: io[3] *****
.subckt grid[0][1]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[3]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[3] sram[44]->outb sram[44]->out gvdd_iopad[3] sgnd iopad
***** SRAM bits for IOPAD[3] *****
*****1*****
Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[44]->out) 0
.nodeset V(sram[44]->outb) vsp
.eom
.subckt grid[0][1]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[3]_mode[io_phy]_iopad[0]
Xdirect_interc[20] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[21] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[0][1] type_descriptor: io[4] *****
.subckt grid[0][1]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[4]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[4] sram[45]->outb sram[45]->out gvdd_iopad[4] sgnd iopad
***** SRAM bits for IOPAD[4] *****
*****1*****
Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[45]->out) 0
.nodeset V(sram[45]->outb) vsp
.eom
.subckt grid[0][1]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[4]_mode[io_phy]_iopad[0]
Xdirect_interc[22] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[23] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[0][1] type_descriptor: io[5] *****
.subckt grid[0][1]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[5]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[5] sram[46]->outb sram[46]->out gvdd_iopad[5] sgnd iopad
***** SRAM bits for IOPAD[5] *****
*****1*****
Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[46]->out) 0
.nodeset V(sram[46]->outb) vsp
.eom
.subckt grid[0][1]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[5]_mode[io_phy]_iopad[0]
Xdirect_interc[24] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[25] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[0][1] type_descriptor: io[6] *****
.subckt grid[0][1]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[6]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[6] sram[47]->outb sram[47]->out gvdd_iopad[6] sgnd iopad
***** SRAM bits for IOPAD[6] *****
*****1*****
Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[47]->out) 0
.nodeset V(sram[47]->outb) vsp
.eom
.subckt grid[0][1]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[6]_mode[io_phy]_iopad[0]
Xdirect_interc[26] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[27] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[0][1] type_descriptor: io[7] *****
.subckt grid[0][1]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[7]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[7] sram[48]->outb sram[48]->out gvdd_iopad[7] sgnd iopad
***** SRAM bits for IOPAD[7] *****
*****1*****
Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[48]->out) 0
.nodeset V(sram[48]->outb) vsp
.eom
.subckt grid[0][1]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[7]_mode[io_phy]_iopad[0]
Xdirect_interc[28] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[29] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[0][1], Capactity: 8 *****
***** Top Protocol *****
.subckt grid[0][1]
+ right_height[0]_pin[0]
+ right_height[0]_pin[1]
+ right_height[0]_pin[2]
+ right_height[0]_pin[3]
+ right_height[0]_pin[4]
+ right_height[0]_pin[5]
+ right_height[0]_pin[6]
+ right_height[0]_pin[7]
+ right_height[0]_pin[8]
+ right_height[0]_pin[9]
+ right_height[0]_pin[10]
+ right_height[0]_pin[11]
+ right_height[0]_pin[12]
+ right_height[0]_pin[13]
+ right_height[0]_pin[14]
+ right_height[0]_pin[15]
+ svdd sgnd
Xgrid[0][1][0]
+ right_height[0]_pin[0]
+ right_height[0]_pin[1]
+ svdd sgnd grid[0][1]_io[0]_mode[io_phy]
Xgrid[0][1][1]
+ right_height[0]_pin[2]
+ right_height[0]_pin[3]
+ svdd sgnd grid[0][1]_io[1]_mode[io_phy]
Xgrid[0][1][2]
+ right_height[0]_pin[4]
+ right_height[0]_pin[5]
+ svdd sgnd grid[0][1]_io[2]_mode[io_phy]
Xgrid[0][1][3]
+ right_height[0]_pin[6]
+ right_height[0]_pin[7]
+ svdd sgnd grid[0][1]_io[3]_mode[io_phy]
Xgrid[0][1][4]
+ right_height[0]_pin[8]
+ right_height[0]_pin[9]
+ svdd sgnd grid[0][1]_io[4]_mode[io_phy]
Xgrid[0][1][5]
+ right_height[0]_pin[10]
+ right_height[0]_pin[11]
+ svdd sgnd grid[0][1]_io[5]_mode[io_phy]
Xgrid[0][1][6]
+ right_height[0]_pin[12]
+ right_height[0]_pin[13]
+ svdd sgnd grid[0][1]_io[6]_mode[io_phy]
Xgrid[0][1][7]
+ right_height[0]_pin[14]
+ right_height[0]_pin[15]
+ svdd sgnd grid[0][1]_io[7]_mode[io_phy]
.eom

221
examples/spice_test_example_1/subckt/grid_1_0.sp
View File

@ -1,221 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Phyiscal Logic Block [1][0] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Grid[1][0] type_descriptor: io[0] *****
.subckt grid[1][0]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[16]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[16] sram[57]->outb sram[57]->out gvdd_iopad[16] sgnd iopad
***** SRAM bits for IOPAD[16] *****
*****1*****
Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[57]->out) 0
.nodeset V(sram[57]->outb) vsp
.eom
.subckt grid[1][0]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[0]_mode[io_phy]_iopad[0]
Xdirect_interc[46] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[47] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][0] type_descriptor: io[1] *****
.subckt grid[1][0]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[17]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[17] sram[58]->outb sram[58]->out gvdd_iopad[17] sgnd iopad
***** SRAM bits for IOPAD[17] *****
*****1*****
Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[58]->out) 0
.nodeset V(sram[58]->outb) vsp
.eom
.subckt grid[1][0]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[1]_mode[io_phy]_iopad[0]
Xdirect_interc[48] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[49] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][0] type_descriptor: io[2] *****
.subckt grid[1][0]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[18]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[18] sram[59]->outb sram[59]->out gvdd_iopad[18] sgnd iopad
***** SRAM bits for IOPAD[18] *****
*****1*****
Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[59]->out) 0
.nodeset V(sram[59]->outb) vsp
.eom
.subckt grid[1][0]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[2]_mode[io_phy]_iopad[0]
Xdirect_interc[50] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[51] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][0] type_descriptor: io[3] *****
.subckt grid[1][0]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[19]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[19] sram[60]->outb sram[60]->out gvdd_iopad[19] sgnd iopad
***** SRAM bits for IOPAD[19] *****
*****1*****
Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[60]->out) 0
.nodeset V(sram[60]->outb) vsp
.eom
.subckt grid[1][0]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[3]_mode[io_phy]_iopad[0]
Xdirect_interc[52] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[53] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][0] type_descriptor: io[4] *****
.subckt grid[1][0]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[20]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[20] sram[61]->outb sram[61]->out gvdd_iopad[20] sgnd iopad
***** SRAM bits for IOPAD[20] *****
*****1*****
Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[61]->out) 0
.nodeset V(sram[61]->outb) vsp
.eom
.subckt grid[1][0]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[4]_mode[io_phy]_iopad[0]
Xdirect_interc[54] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[55] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][0] type_descriptor: io[5] *****
.subckt grid[1][0]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[21]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[21] sram[62]->outb sram[62]->out gvdd_iopad[21] sgnd iopad
***** SRAM bits for IOPAD[21] *****
*****1*****
Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[62]->out) 0
.nodeset V(sram[62]->outb) vsp
.eom
.subckt grid[1][0]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[5]_mode[io_phy]_iopad[0]
Xdirect_interc[56] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[57] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][0] type_descriptor: io[6] *****
.subckt grid[1][0]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[22]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[22] sram[63]->outb sram[63]->out gvdd_iopad[22] sgnd iopad
***** SRAM bits for IOPAD[22] *****
*****1*****
Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[63]->out) 0
.nodeset V(sram[63]->outb) vsp
.eom
.subckt grid[1][0]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[6]_mode[io_phy]_iopad[0]
Xdirect_interc[58] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[59] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][0] type_descriptor: io[7] *****
.subckt grid[1][0]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[23]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[23] sram[64]->outb sram[64]->out gvdd_iopad[23] sgnd iopad
***** SRAM bits for IOPAD[23] *****
*****1*****
Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[64]->out) 0
.nodeset V(sram[64]->outb) vsp
.eom
.subckt grid[1][0]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[7]_mode[io_phy]_iopad[0]
Xdirect_interc[60] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[61] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][0], Capactity: 8 *****
***** Top Protocol *****
.subckt grid[1][0]
+ top_height[0]_pin[0]
+ top_height[0]_pin[1]
+ top_height[0]_pin[2]
+ top_height[0]_pin[3]
+ top_height[0]_pin[4]
+ top_height[0]_pin[5]
+ top_height[0]_pin[6]
+ top_height[0]_pin[7]
+ top_height[0]_pin[8]
+ top_height[0]_pin[9]
+ top_height[0]_pin[10]
+ top_height[0]_pin[11]
+ top_height[0]_pin[12]
+ top_height[0]_pin[13]
+ top_height[0]_pin[14]
+ top_height[0]_pin[15]
+ svdd sgnd
Xgrid[1][0][0]
+ top_height[0]_pin[0]
+ top_height[0]_pin[1]
+ svdd sgnd grid[1][0]_io[0]_mode[io_phy]
Xgrid[1][0][1]
+ top_height[0]_pin[2]
+ top_height[0]_pin[3]
+ svdd sgnd grid[1][0]_io[1]_mode[io_phy]
Xgrid[1][0][2]
+ top_height[0]_pin[4]
+ top_height[0]_pin[5]
+ svdd sgnd grid[1][0]_io[2]_mode[io_phy]
Xgrid[1][0][3]
+ top_height[0]_pin[6]
+ top_height[0]_pin[7]
+ svdd sgnd grid[1][0]_io[3]_mode[io_phy]
Xgrid[1][0][4]
+ top_height[0]_pin[8]
+ top_height[0]_pin[9]
+ svdd sgnd grid[1][0]_io[4]_mode[io_phy]
Xgrid[1][0][5]
+ top_height[0]_pin[10]
+ top_height[0]_pin[11]
+ svdd sgnd grid[1][0]_io[5]_mode[io_phy]
Xgrid[1][0][6]
+ top_height[0]_pin[12]
+ top_height[0]_pin[13]
+ svdd sgnd grid[1][0]_io[6]_mode[io_phy]
Xgrid[1][0][7]
+ top_height[0]_pin[14]
+ top_height[0]_pin[15]
+ svdd sgnd grid[1][0]_io[7]_mode[io_phy]
.eom

209
examples/spice_test_example_1/subckt/grid_1_1.sp
View File

@ -1,209 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Logic Block [1][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Grid[1][1] type_descriptor: clb[0] *****
***** Logical block mapped to this LUT: n7 *****
.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_lut4[0] lut4[0]->in[0] lut4[0]->in[1] lut4[0]->in[2] lut4[0]->in[3] lut4[0]->out[0] svdd sgnd
***** Truth Table for LUT[0], size=4. *****
* 0--- 1 *
***** SRAM bits for LUT[0], size=4, num_sram=16. *****
*****0101010101010101*****
Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[0]->out) 0
.nodeset V(sram[0]->outb) vsp
Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[1]->out) 0
.nodeset V(sram[1]->outb) vsp
Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[2]->out) 0
.nodeset V(sram[2]->outb) vsp
Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[3]->out) 0
.nodeset V(sram[3]->outb) vsp
Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[4]->out) 0
.nodeset V(sram[4]->outb) vsp
Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[5]->out) 0
.nodeset V(sram[5]->outb) vsp
Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[6]->out) 0
.nodeset V(sram[6]->outb) vsp
Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[7]->out) 0
.nodeset V(sram[7]->outb) vsp
Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[8]->out) 0
.nodeset V(sram[8]->outb) vsp
Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[9]->out) 0
.nodeset V(sram[9]->outb) vsp
Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[10]->out) 0
.nodeset V(sram[10]->outb) vsp
Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[11]->out) 0
.nodeset V(sram[11]->outb) vsp
Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[12]->out) 0
.nodeset V(sram[12]->outb) vsp
Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[13]->out) 0
.nodeset V(sram[13]->outb) vsp
Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[14]->out) 0
.nodeset V(sram[14]->outb) vsp
Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram_luts sgnd sram6T
.nodeset V(sram[15]->out) 0
.nodeset V(sram[15]->outb) vsp
Xlut4[0] lut4[0]->in[0] lut4[0]->in[1] lut4[0]->in[2] lut4[0]->in[3] lut4[0]->out[0] sram[0]->out sram[1]->outb sram[2]->out sram[3]->outb sram[4]->out sram[5]->outb sram[6]->out sram[7]->outb sram[8]->out sram[9]->outb sram[10]->out sram[11]->outb sram[12]->out sram[13]->outb sram[14]->out sram[15]->outb gvdd_lut4[0] sgnd lut4
.eom
***** Logical block mapped to this FF: Q0 *****
.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd
Xdff[0]
***** BEGIN Global ports of SPICE_MODEL(static_dff) *****
+ Set[0] Reset[0] clk[0]
***** END Global ports of SPICE_MODEL(static_dff) *****
+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[0] sgnd static_dff
.nodeset V(ff[0]->Q[0]) 0
.eom
.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4] mode[ble4]->in[0] mode[ble4]->in[1] mode[ble4]->in[2] mode[ble4]->in[3] mode[ble4]->out[0] mode[ble4]->clk[0] svdd sgnd
Xlut4[0] lut4[0]->in[0] lut4[0]->in[1] lut4[0]->in[2] lut4[0]->in[3] lut4[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_lut4[0]
Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_ff[0]
Xmux_1level_tapbuf_size2[0] ff[0]->Q[0] lut4[0]->out[0] mode[ble4]->out[0] sram[16]->outb sram[16]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[0], level=1, select_path_id=0. *****
*****1*****
Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[16]->out) 0
.nodeset V(sram[16]->outb) vsp
Xdirect_interc[0] mode[ble4]->in[0] lut4[0]->in[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[1] mode[ble4]->in[1] lut4[0]->in[1] gvdd_local_interc sgnd direct_interc
Xdirect_interc[2] mode[ble4]->in[2] lut4[0]->in[2] gvdd_local_interc sgnd direct_interc
Xdirect_interc[3] mode[ble4]->in[3] lut4[0]->in[3] gvdd_local_interc sgnd direct_interc
Xdirect_interc[4] lut4[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[5] mode[ble4]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc
.eom
.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4] mode[n1_lut4]->in[0] mode[n1_lut4]->in[1] mode[n1_lut4]->in[2] mode[n1_lut4]->in[3] mode[n1_lut4]->out[0] mode[n1_lut4]->clk[0] svdd sgnd
Xble4[0] ble4[0]->in[0] ble4[0]->in[1] ble4[0]->in[2] ble4[0]->in[3] ble4[0]->out[0] ble4[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]
Xdirect_interc[6] ble4[0]->out[0] mode[n1_lut4]->out[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[7] mode[n1_lut4]->in[0] ble4[0]->in[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[8] mode[n1_lut4]->in[1] ble4[0]->in[1] gvdd_local_interc sgnd direct_interc
Xdirect_interc[9] mode[n1_lut4]->in[2] ble4[0]->in[2] gvdd_local_interc sgnd direct_interc
Xdirect_interc[10] mode[n1_lut4]->in[3] ble4[0]->in[3] gvdd_local_interc sgnd direct_interc
Xdirect_interc[11] mode[n1_lut4]->clk[0] ble4[0]->clk[0] gvdd_local_interc sgnd direct_interc
.eom
.subckt grid[1][1]_clb[0]_mode[clb] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->O[0] mode[clb]->clk[0] svdd sgnd
Xfle[0] fle[0]->in[0] fle[0]->in[1] fle[0]->in[2] fle[0]->in[3] fle[0]->out[0] fle[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]
Xdirect_interc[12] fle[0]->out[0] mode[clb]->O[0] gvdd_local_interc sgnd direct_interc
Xmux_2level_size5[0] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] fle[0]->out[0] fle[0]->in[0] sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->out sram[22]->outb gvdd_local_interc sgnd mux_2level_size5
***** SRAM bits for MUX[0], level=2, select_path_id=3. *****
*****010100*****
Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[17]->out) 0
.nodeset V(sram[17]->outb) vsp
Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[18]->out) 0
.nodeset V(sram[18]->outb) vsp
Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[19]->out) 0
.nodeset V(sram[19]->outb) vsp
Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[20]->out) 0
.nodeset V(sram[20]->outb) vsp
Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[21]->out) 0
.nodeset V(sram[21]->outb) vsp
Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[22]->out) 0
.nodeset V(sram[22]->outb) vsp
Xmux_2level_size5[1] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] fle[0]->out[0] fle[0]->in[1] sram[23]->outb sram[23]->out sram[24]->out sram[24]->outb sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb sram[28]->out sram[28]->outb gvdd_local_interc sgnd mux_2level_size5
***** SRAM bits for MUX[1], level=2, select_path_id=0. *****
*****100100*****
Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[23]->out) 0
.nodeset V(sram[23]->outb) vsp
Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[24]->out) 0
.nodeset V(sram[24]->outb) vsp
Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[25]->out) 0
.nodeset V(sram[25]->outb) vsp
Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[26]->out) 0
.nodeset V(sram[26]->outb) vsp
Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[27]->out) 0
.nodeset V(sram[27]->outb) vsp
Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[28]->out) 0
.nodeset V(sram[28]->outb) vsp
Xmux_2level_size5[2] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] fle[0]->out[0] fle[0]->in[2] sram[29]->outb sram[29]->out sram[30]->out sram[30]->outb sram[31]->out sram[31]->outb sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->out sram[34]->outb gvdd_local_interc sgnd mux_2level_size5
***** SRAM bits for MUX[2], level=2, select_path_id=0. *****
*****100100*****
Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[29]->out) 0
.nodeset V(sram[29]->outb) vsp
Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[30]->out) 0
.nodeset V(sram[30]->outb) vsp
Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[31]->out) 0
.nodeset V(sram[31]->outb) vsp
Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[32]->out) 0
.nodeset V(sram[32]->outb) vsp
Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[33]->out) 0
.nodeset V(sram[33]->outb) vsp
Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[34]->out) 0
.nodeset V(sram[34]->outb) vsp
Xmux_2level_size5[3] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] fle[0]->out[0] fle[0]->in[3] sram[35]->outb sram[35]->out sram[36]->out sram[36]->outb sram[37]->out sram[37]->outb sram[38]->outb sram[38]->out sram[39]->out sram[39]->outb sram[40]->out sram[40]->outb gvdd_local_interc sgnd mux_2level_size5
***** SRAM bits for MUX[3], level=2, select_path_id=0. *****
*****100100*****
Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[35]->out) 0
.nodeset V(sram[35]->outb) vsp
Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[36]->out) 0
.nodeset V(sram[36]->outb) vsp
Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[37]->out) 0
.nodeset V(sram[37]->outb) vsp
Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[38]->out) 0
.nodeset V(sram[38]->outb) vsp
Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[39]->out) 0
.nodeset V(sram[39]->outb) vsp
Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram_local_routing sgnd sram6T
.nodeset V(sram[40]->out) 0
.nodeset V(sram[40]->outb) vsp
Xdirect_interc[13] mode[clb]->clk[0] fle[0]->clk[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][1], Capactity: 1 *****
***** Top Protocol *****
.subckt grid[1][1]
+ top_height[0]_pin[0]
+ top_height[0]_pin[4]
+ right_height[0]_pin[1]
+ right_height[0]_pin[5]
+ bottom_height[0]_pin[2]
+ left_height[0]_pin[3]
+ svdd sgnd
Xgrid[1][1][0]
+ top_height[0]_pin[0]
+ right_height[0]_pin[1]
+ bottom_height[0]_pin[2]
+ left_height[0]_pin[3]
+ top_height[0]_pin[4]
+ right_height[0]_pin[5]
+ svdd sgnd grid[1][1]_clb[0]_mode[clb]
.eom

223
examples/spice_test_example_1/subckt/grid_1_2.sp
View File

@ -1,223 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Phyiscal Logic Block [1][2] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Grid[1][2] type_descriptor: io[0] *****
.subckt grid[1][2]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[24]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[24] sram[65]->outb sram[65]->out gvdd_iopad[24] sgnd iopad
***** SRAM bits for IOPAD[24] *****
*****1*****
Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[65]->out) 0
.nodeset V(sram[65]->outb) vsp
.eom
.subckt grid[1][2]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[0]_mode[io_phy]_iopad[0]
Xdirect_interc[62] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[63] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][2] type_descriptor: io[1] *****
***** Logical block mapped to this IO: out_Q0 *****
.subckt grid[1][2]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[25]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[25] sram[66]->out sram[66]->outb gvdd_iopad[25] sgnd iopad
***** SRAM bits for IOPAD[25] *****
*****0*****
Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[66]->out) 0
.nodeset V(sram[66]->outb) vsp
.eom
.subckt grid[1][2]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[1]_mode[io_phy]_iopad[0]
Xdirect_interc[64] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[65] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][2] type_descriptor: io[2] *****
.subckt grid[1][2]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[26]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[26] sram[67]->outb sram[67]->out gvdd_iopad[26] sgnd iopad
***** SRAM bits for IOPAD[26] *****
*****1*****
Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[67]->out) 0
.nodeset V(sram[67]->outb) vsp
.eom
.subckt grid[1][2]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[2]_mode[io_phy]_iopad[0]
Xdirect_interc[66] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[67] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][2] type_descriptor: io[3] *****
.subckt grid[1][2]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[27]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[27] sram[68]->outb sram[68]->out gvdd_iopad[27] sgnd iopad
***** SRAM bits for IOPAD[27] *****
*****1*****
Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[68]->out) 0
.nodeset V(sram[68]->outb) vsp
.eom
.subckt grid[1][2]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[3]_mode[io_phy]_iopad[0]
Xdirect_interc[68] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[69] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][2] type_descriptor: io[4] *****
.subckt grid[1][2]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[28]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[28] sram[69]->outb sram[69]->out gvdd_iopad[28] sgnd iopad
***** SRAM bits for IOPAD[28] *****
*****1*****
Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[69]->out) 0
.nodeset V(sram[69]->outb) vsp
.eom
.subckt grid[1][2]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[4]_mode[io_phy]_iopad[0]
Xdirect_interc[70] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[71] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][2] type_descriptor: io[5] *****
.subckt grid[1][2]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[29]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[29] sram[70]->outb sram[70]->out gvdd_iopad[29] sgnd iopad
***** SRAM bits for IOPAD[29] *****
*****1*****
Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[70]->out) 0
.nodeset V(sram[70]->outb) vsp
.eom
.subckt grid[1][2]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[5]_mode[io_phy]_iopad[0]
Xdirect_interc[72] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[73] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][2] type_descriptor: io[6] *****
***** Logical block mapped to this IO: I0 *****
.subckt grid[1][2]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[30]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[30] sram[71]->outb sram[71]->out gvdd_iopad[30] sgnd iopad
***** SRAM bits for IOPAD[30] *****
*****1*****
Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[71]->out) 0
.nodeset V(sram[71]->outb) vsp
.eom
.subckt grid[1][2]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[6]_mode[io_phy]_iopad[0]
Xdirect_interc[74] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[75] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][2] type_descriptor: io[7] *****
.subckt grid[1][2]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[31]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[31] sram[72]->outb sram[72]->out gvdd_iopad[31] sgnd iopad
***** SRAM bits for IOPAD[31] *****
*****1*****
Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[72]->out) 0
.nodeset V(sram[72]->outb) vsp
.eom
.subckt grid[1][2]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[7]_mode[io_phy]_iopad[0]
Xdirect_interc[76] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[77] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[1][2], Capactity: 8 *****
***** Top Protocol *****
.subckt grid[1][2]
+ bottom_height[0]_pin[0]
+ bottom_height[0]_pin[1]
+ bottom_height[0]_pin[2]
+ bottom_height[0]_pin[3]
+ bottom_height[0]_pin[4]
+ bottom_height[0]_pin[5]
+ bottom_height[0]_pin[6]
+ bottom_height[0]_pin[7]
+ bottom_height[0]_pin[8]
+ bottom_height[0]_pin[9]
+ bottom_height[0]_pin[10]
+ bottom_height[0]_pin[11]
+ bottom_height[0]_pin[12]
+ bottom_height[0]_pin[13]
+ bottom_height[0]_pin[14]
+ bottom_height[0]_pin[15]
+ svdd sgnd
Xgrid[1][2][0]
+ bottom_height[0]_pin[0]
+ bottom_height[0]_pin[1]
+ svdd sgnd grid[1][2]_io[0]_mode[io_phy]
Xgrid[1][2][1]
+ bottom_height[0]_pin[2]
+ bottom_height[0]_pin[3]
+ svdd sgnd grid[1][2]_io[1]_mode[io_phy]
Xgrid[1][2][2]
+ bottom_height[0]_pin[4]
+ bottom_height[0]_pin[5]
+ svdd sgnd grid[1][2]_io[2]_mode[io_phy]
Xgrid[1][2][3]
+ bottom_height[0]_pin[6]
+ bottom_height[0]_pin[7]
+ svdd sgnd grid[1][2]_io[3]_mode[io_phy]
Xgrid[1][2][4]
+ bottom_height[0]_pin[8]
+ bottom_height[0]_pin[9]
+ svdd sgnd grid[1][2]_io[4]_mode[io_phy]
Xgrid[1][2][5]
+ bottom_height[0]_pin[10]
+ bottom_height[0]_pin[11]
+ svdd sgnd grid[1][2]_io[5]_mode[io_phy]
Xgrid[1][2][6]
+ bottom_height[0]_pin[12]
+ bottom_height[0]_pin[13]
+ svdd sgnd grid[1][2]_io[6]_mode[io_phy]
Xgrid[1][2][7]
+ bottom_height[0]_pin[14]
+ bottom_height[0]_pin[15]
+ svdd sgnd grid[1][2]_io[7]_mode[io_phy]
.eom

222
examples/spice_test_example_1/subckt/grid_2_1.sp
View File

@ -1,222 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Phyiscal Logic Block [2][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Grid[2][1] type_descriptor: io[0] *****
.subckt grid[2][1]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[8]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[8] sram[49]->outb sram[49]->out gvdd_iopad[8] sgnd iopad
***** SRAM bits for IOPAD[8] *****
*****1*****
Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[49]->out) 0
.nodeset V(sram[49]->outb) vsp
.eom
.subckt grid[2][1]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[0]_mode[io_phy]_iopad[0]
Xdirect_interc[30] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[31] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[2][1] type_descriptor: io[1] *****
.subckt grid[2][1]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[9]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[9] sram[50]->outb sram[50]->out gvdd_iopad[9] sgnd iopad
***** SRAM bits for IOPAD[9] *****
*****1*****
Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[50]->out) 0
.nodeset V(sram[50]->outb) vsp
.eom
.subckt grid[2][1]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[1]_mode[io_phy]_iopad[0]
Xdirect_interc[32] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[33] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[2][1] type_descriptor: io[2] *****
.subckt grid[2][1]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[10]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[10] sram[51]->outb sram[51]->out gvdd_iopad[10] sgnd iopad
***** SRAM bits for IOPAD[10] *****
*****1*****
Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[51]->out) 0
.nodeset V(sram[51]->outb) vsp
.eom
.subckt grid[2][1]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[2]_mode[io_phy]_iopad[0]
Xdirect_interc[34] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[35] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[2][1] type_descriptor: io[3] *****
.subckt grid[2][1]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[11]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[11] sram[52]->outb sram[52]->out gvdd_iopad[11] sgnd iopad
***** SRAM bits for IOPAD[11] *****
*****1*****
Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[52]->out) 0
.nodeset V(sram[52]->outb) vsp
.eom
.subckt grid[2][1]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[3]_mode[io_phy]_iopad[0]
Xdirect_interc[36] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[37] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[2][1] type_descriptor: io[4] *****
.subckt grid[2][1]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[12]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[12] sram[53]->outb sram[53]->out gvdd_iopad[12] sgnd iopad
***** SRAM bits for IOPAD[12] *****
*****1*****
Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[53]->out) 0
.nodeset V(sram[53]->outb) vsp
.eom
.subckt grid[2][1]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[4]_mode[io_phy]_iopad[0]
Xdirect_interc[38] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[39] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[2][1] type_descriptor: io[5] *****
.subckt grid[2][1]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[13]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[13] sram[54]->outb sram[54]->out gvdd_iopad[13] sgnd iopad
***** SRAM bits for IOPAD[13] *****
*****1*****
Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[54]->out) 0
.nodeset V(sram[54]->outb) vsp
.eom
.subckt grid[2][1]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[5]_mode[io_phy]_iopad[0]
Xdirect_interc[40] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[41] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[2][1] type_descriptor: io[6] *****
.subckt grid[2][1]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[14]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[14] sram[55]->outb sram[55]->out gvdd_iopad[14] sgnd iopad
***** SRAM bits for IOPAD[14] *****
*****1*****
Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[55]->out) 0
.nodeset V(sram[55]->outb) vsp
.eom
.subckt grid[2][1]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[6]_mode[io_phy]_iopad[0]
Xdirect_interc[42] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[43] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[2][1] type_descriptor: io[7] *****
***** Logical block mapped to this IO: clk *****
.subckt grid[2][1]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd
Xiopad[15]
***** BEGIN Global ports of SPICE_MODEL(iopad) *****
+ zin[0]
***** END Global ports of SPICE_MODEL(iopad) *****
+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[15] sram[56]->outb sram[56]->out gvdd_iopad[15] sgnd iopad
***** SRAM bits for IOPAD[15] *****
*****1*****
Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram_io sgnd sram6T
.nodeset V(sram[56]->out) 0
.nodeset V(sram[56]->outb) vsp
.eom
.subckt grid[2][1]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd
Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[7]_mode[io_phy]_iopad[0]
Xdirect_interc[44] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc
Xdirect_interc[45] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc
.eom
***** END *****
***** Grid[2][1], Capactity: 8 *****
***** Top Protocol *****
.subckt grid[2][1]
+ left_height[0]_pin[0]
+ left_height[0]_pin[1]
+ left_height[0]_pin[2]
+ left_height[0]_pin[3]
+ left_height[0]_pin[4]
+ left_height[0]_pin[5]
+ left_height[0]_pin[6]
+ left_height[0]_pin[7]
+ left_height[0]_pin[8]
+ left_height[0]_pin[9]
+ left_height[0]_pin[10]
+ left_height[0]_pin[11]
+ left_height[0]_pin[12]
+ left_height[0]_pin[13]
+ left_height[0]_pin[14]
+ left_height[0]_pin[15]
+ svdd sgnd
Xgrid[2][1][0]
+ left_height[0]_pin[0]
+ left_height[0]_pin[1]
+ svdd sgnd grid[2][1]_io[0]_mode[io_phy]
Xgrid[2][1][1]
+ left_height[0]_pin[2]
+ left_height[0]_pin[3]
+ svdd sgnd grid[2][1]_io[1]_mode[io_phy]
Xgrid[2][1][2]
+ left_height[0]_pin[4]
+ left_height[0]_pin[5]
+ svdd sgnd grid[2][1]_io[2]_mode[io_phy]
Xgrid[2][1][3]
+ left_height[0]_pin[6]
+ left_height[0]_pin[7]
+ svdd sgnd grid[2][1]_io[3]_mode[io_phy]
Xgrid[2][1][4]
+ left_height[0]_pin[8]
+ left_height[0]_pin[9]
+ svdd sgnd grid[2][1]_io[4]_mode[io_phy]
Xgrid[2][1][5]
+ left_height[0]_pin[10]
+ left_height[0]_pin[11]
+ svdd sgnd grid[2][1]_io[5]_mode[io_phy]
Xgrid[2][1][6]
+ left_height[0]_pin[12]
+ left_height[0]_pin[13]
+ svdd sgnd grid[2][1]_io[6]_mode[io_phy]
Xgrid[2][1][7]
+ left_height[0]_pin[14]
+ left_height[0]_pin[15]
+ svdd sgnd grid[2][1]_io[7]_mode[io_phy]
.eom

13
examples/spice_test_example_1/subckt/grid_header.sp
View File

@ -1,13 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Header file *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
.include './spice_test_example_1/subckt/grid_1_2.sp'
.include './spice_test_example_1/subckt/grid_1_0.sp'
.include './spice_test_example_1/subckt/grid_2_1.sp'
.include './spice_test_example_1/subckt/grid_0_1.sp'
.include './spice_test_example_1/subckt/grid_1_1.sp'

76
examples/spice_test_example_1/subckt/inv_buf_trans_gate.sp
View File

@ -1,76 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Inverter, Buffer, Trans. Gate *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
* Inverter
.subckt inv in out svdd sgnd size=1
Xn0_inv out in sgnd sgnd vpr_nmos L=nl W='size*wn'
Xp0_inv out in svdd svdd vpr_pmos L=pl W='size*beta*wp'
.eom inv
* Powergated Inverter
.subckt pg_inv en enb in out svdd sgnd size=1 pg_size=1
Xn0_inv out in sgnd_pg sgnd vpr_nmos L=nl W='size*wn'
Xp0_inv out in svdd_pg svdd vpr_pmos L=pl W='size*beta*wp'
Xn0_inv_pg sgnd_pg en sgnd sgnd vpr_nmos L=nl W='pg_size*wn'
Xp0_inv_pg svdd_pg enb svdd svdd vpr_pmos L=pl W='pg_size*beta*wp'
.eom inv
* Buffer
.subckt buf in out svdd sgnd size=2 base_size=1
Xinv0 in mid svdd sgnd inv base_size='base_size'
Xinv1 mid out svdd sgnd inv size='size*base_size'
.eom buf
* Power-gated Buffer
.subckt pg_buf en enb in out svdd sgnd size=2 pg_size=2
Xinv0 en enb in mid svdd sgnd pg_inv size=1 pg_size=1
Xinv1 en enb mid out svdd sgnd pg_inv size=size pg_size=size
.eom buf
* Transmission Gate (Complementary Pass Transistor)
.subckt cpt in out sel sel_inv svdd sgnd nmos_size=1 pmos_size=1
Xn0_cpt in sel out sgnd vpr_nmos L=nl W='nmos_size*wn'
Xp0_cpt in sel_inv out svdd vpr_pmos L=pl W='pmos_size*wp'
.eom cpt
.subckt tapbuf_level2_f4 in out svdd sgnd
Rinv_in in in_lvl0 0
Xinv_lvl0_no0 in_lvl0 in_lvl1 svdd sgnd inv
Xinv_lvl1_no0 in_lvl1 in_lvl2 svdd sgnd inv
Xinv_lvl1_no1 in_lvl1 in_lvl2 svdd sgnd inv
Xinv_lvl1_no2 in_lvl1 in_lvl2 svdd sgnd inv
Xinv_lvl1_no3 in_lvl1 in_lvl2 svdd sgnd inv
Rinv_out in_lvl2 out 0
.eom
.subckt tapbuf_level3_f4 in out svdd sgnd
Rinv_in in in_lvl0 0
Xinv_lvl0_no0 in_lvl0 in_lvl1 svdd sgnd inv
Xinv_lvl1_no0 in_lvl1 in_lvl2 svdd sgnd inv
Xinv_lvl1_no1 in_lvl1 in_lvl2 svdd sgnd inv
Xinv_lvl1_no2 in_lvl1 in_lvl2 svdd sgnd inv
Xinv_lvl1_no3 in_lvl1 in_lvl2 svdd sgnd inv
Xinv_lvl2_no0 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no1 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no2 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no3 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no4 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no5 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no6 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no7 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no8 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no9 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no10 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no11 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no12 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no13 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no14 in_lvl2 in_lvl3 svdd sgnd inv
Xinv_lvl2_no15 in_lvl2 in_lvl3 svdd sgnd inv
Rinv_out in_lvl3 out 0
.eom

24
examples/spice_test_example_1/subckt/luts.sp
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@ -1,24 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: LUTs *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Auto-generated LUT info: spice_model_name = lut4, size = 4 *****
.subckt lut4 in0 in1 in2 in3 out sram0 sram1 sram2 sram3 sram4 sram5 sram6 sram7 sram8 sram9 sram10 sram11 sram12 sram13 sram14 sram15 svdd sgnd
Xinv0_in0_no0 in0 lut_mux_in0_inv svdd sgnd inv size='4'
Xbuf4_in0 in0 lut_mux_in0 svdd sgnd tapbuf_level2_f4
Xinv0_in1_no0 in1 lut_mux_in1_inv svdd sgnd inv size='4'
Xbuf4_in1 in1 lut_mux_in1 svdd sgnd tapbuf_level2_f4
Xinv0_in2_no0 in2 lut_mux_in2_inv svdd sgnd inv size='4'
Xbuf4_in2 in2 lut_mux_in2 svdd sgnd tapbuf_level2_f4
Xinv0_in3_no0 in3 lut_mux_in3_inv svdd sgnd inv size='4'
Xbuf4_in3 in3 lut_mux_in3 svdd sgnd tapbuf_level2_f4
Xlut_mux sram0 sram1 sram2 sram3 sram4 sram5 sram6 sram7 sram8 sram9 sram10 sram11 sram12 sram13 sram14 sram15 out lut_mux_in0 lut_mux_in0_inv lut_mux_in1 lut_mux_in1_inv lut_mux_in2 lut_mux_in2_inv lut_mux_in3 lut_mux_in3_inv svdd sgnd lut4_mux_size16
.eom

117
examples/spice_test_example_1/subckt/muxes.sp
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*****************************
* FPGA SPICE Netlist *
* Description: MUXes used in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
.subckt mux_2level_tapbuf_size4_basis in0 in1 out sel0 sel_inv0 sel1 sel_inv1 svdd sgnd
Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_2level_tapbuf_pgl_nmos_size' pmos_size='mux_2level_tapbuf_pgl_pmos_size'
Xcpt_1 in1 out sel1 sel_inv1 svdd sgnd cpt nmos_size='mux_2level_tapbuf_pgl_nmos_size' pmos_size='mux_2level_tapbuf_pgl_pmos_size'
.eom
***** CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=4, structure: multi-level *****
.subckt mux_2level_tapbuf_size4 in0 in1 in2 in3 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 svdd sgnd
Xmux_basis_no0 mux2_l2_in0 mux2_l2_in1 mux2_l1_in0 sram2 sram_inv2 sram3 sram_inv3 svdd sgnd mux_2level_tapbuf_size4_basis
Xmux_basis_no1 mux2_l2_in2 mux2_l2_in3 mux2_l1_in1 sram2 sram_inv2 sram3 sram_inv3 svdd sgnd mux_2level_tapbuf_size4_basis
Xmux_basis_no2 mux2_l1_in0 mux2_l1_in1 mux2_l0_in0 sram0 sram_inv0 sram1 sram_inv1 svdd sgnd mux_2level_tapbuf_size4_basis
Xinv0 in0 mux2_l2_in0 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size'
Xinv1 in1 mux2_l2_in1 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size'
Xinv2 in2 mux2_l2_in2 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size'
Xinv3 in3 mux2_l2_in3 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size'
Xbuf_out mux2_l0_in0 out svdd sgnd tapbuf_level3_f4
.eom
***** END CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=4 *****
.subckt lut4_size16_basis in0 in1 out sel0 sel_inv0 svdd sgnd
Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='lut4_pgl_nmos_size' pmos_size='lut4_pgl_pmos_size'
Xcpt_1 in1 out sel_inv0 sel0 svdd sgnd cpt nmos_size='lut4_pgl_nmos_size' pmos_size='lut4_pgl_pmos_size'
.eom
***** CMOS MUX info: spice_model_name= lut4_MUX, size=16 *****
.subckt lut4_mux_size16 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 in15 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 svdd sgnd
Xmux_basis_no0 mux2_l4_in0 mux2_l4_in1 mux2_l3_in0 sram0 sram_inv0 svdd sgnd lut4_size16_basis
Xmux_basis_no1 mux2_l4_in2 mux2_l4_in3 mux2_l3_in1 sram0 sram_inv0 svdd sgnd lut4_size16_basis
Xmux_basis_no2 mux2_l4_in4 mux2_l4_in5 mux2_l3_in2 sram0 sram_inv0 svdd sgnd lut4_size16_basis
Xmux_basis_no3 mux2_l4_in6 mux2_l4_in7 mux2_l3_in3 sram0 sram_inv0 svdd sgnd lut4_size16_basis
Xmux_basis_no4 mux2_l4_in8 mux2_l4_in9 mux2_l3_in4 sram0 sram_inv0 svdd sgnd lut4_size16_basis
Xmux_basis_no5 mux2_l4_in10 mux2_l4_in11 mux2_l3_in5 sram0 sram_inv0 svdd sgnd lut4_size16_basis
Xmux_basis_no6 mux2_l4_in12 mux2_l4_in13 mux2_l3_in6 sram0 sram_inv0 svdd sgnd lut4_size16_basis
Xmux_basis_no7 mux2_l4_in14 mux2_l4_in15 mux2_l3_in7 sram0 sram_inv0 svdd sgnd lut4_size16_basis
Xmux_basis_no8 mux2_l3_in0 mux2_l3_in1 mux2_l2_in0 sram1 sram_inv1 svdd sgnd lut4_size16_basis
Xmux_basis_no9 mux2_l3_in2 mux2_l3_in3 mux2_l2_in1 sram1 sram_inv1 svdd sgnd lut4_size16_basis
Xmux_basis_no10 mux2_l3_in4 mux2_l3_in5 mux2_l2_in2 sram1 sram_inv1 svdd sgnd lut4_size16_basis
Xmux_basis_no11 mux2_l3_in6 mux2_l3_in7 mux2_l2_in3 sram1 sram_inv1 svdd sgnd lut4_size16_basis
Xmux_basis_no12 mux2_l2_in0 mux2_l2_in1 mux2_l1_in0 sram2 sram_inv2 svdd sgnd lut4_size16_basis
Xmux_basis_no13 mux2_l2_in2 mux2_l2_in3 mux2_l1_in1 sram2 sram_inv2 svdd sgnd lut4_size16_basis
Xmux_basis_no14 mux2_l1_in0 mux2_l1_in1 mux2_l0_in0 sram3 sram_inv3 svdd sgnd lut4_size16_basis
Xinv0 in0 mux2_l4_in0 svdd sgnd inv size='lut4_input_buf_size'
Xinv1 in1 mux2_l4_in1 svdd sgnd inv size='lut4_input_buf_size'
Xinv2 in2 mux2_l4_in2 svdd sgnd inv size='lut4_input_buf_size'
Xinv3 in3 mux2_l4_in3 svdd sgnd inv size='lut4_input_buf_size'
Xinv4 in4 mux2_l4_in4 svdd sgnd inv size='lut4_input_buf_size'
Xinv5 in5 mux2_l4_in5 svdd sgnd inv size='lut4_input_buf_size'
Xinv6 in6 mux2_l4_in6 svdd sgnd inv size='lut4_input_buf_size'
Xinv7 in7 mux2_l4_in7 svdd sgnd inv size='lut4_input_buf_size'
Xinv8 in8 mux2_l4_in8 svdd sgnd inv size='lut4_input_buf_size'
Xinv9 in9 mux2_l4_in9 svdd sgnd inv size='lut4_input_buf_size'
Xinv10 in10 mux2_l4_in10 svdd sgnd inv size='lut4_input_buf_size'
Xinv11 in11 mux2_l4_in11 svdd sgnd inv size='lut4_input_buf_size'
Xinv12 in12 mux2_l4_in12 svdd sgnd inv size='lut4_input_buf_size'
Xinv13 in13 mux2_l4_in13 svdd sgnd inv size='lut4_input_buf_size'
Xinv14 in14 mux2_l4_in14 svdd sgnd inv size='lut4_input_buf_size'
Xinv15 in15 mux2_l4_in15 svdd sgnd inv size='lut4_input_buf_size'
Xinv_out mux2_l0_in0 out svdd sgnd inv size='lut4_output_buf_size'
.eom
***** END CMOS MUX info: spice_model_name=lut4, size=16 *****
.subckt mux_2level_size5_basis in0 in1 in2 out sel0 sel_inv0 sel1 sel_inv1 sel2 sel_inv2 svdd sgnd
Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size'
Xcpt_1 in1 out sel1 sel_inv1 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size'
Xcpt_2 in2 out sel2 sel_inv2 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size'
.eom
***** CMOS MUX info: spice_model_name=mux_2level, size=5, structure: multi-level *****
.subckt mux_2level_size5 in0 in1 in2 in3 in4 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 sram4 sram_inv4 sram5 sram_inv5 svdd sgnd
Xmux_basis_no0 mux2_l2_in0 mux2_l2_in1 mux2_l2_in2 mux2_l1_in0 sram3 sram_inv3 sram4 sram_inv4 sram5 sram_inv5 svdd sgnd mux_2level_size5_basis
Xmux_basis_no1 mux2_l1_in0 mux2_l1_in1 mux2_l1_in2 mux2_l0_in0 sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 svdd sgnd mux_2level_size5_basis
Xinv0 in0 mux2_l2_in0 svdd sgnd inv size='mux_2level_input_buf_size'
Xinv1 in1 mux2_l2_in1 svdd sgnd inv size='mux_2level_input_buf_size'
Xinv2 in2 mux2_l2_in2 svdd sgnd inv size='mux_2level_input_buf_size'
Xinv3 in3 mux2_l1_in1 svdd sgnd inv size='mux_2level_input_buf_size'
Xinv4 in4 mux2_l1_in2 svdd sgnd inv size='mux_2level_input_buf_size'
Xinv_out mux2_l0_in0 out svdd sgnd inv size='mux_2level_output_buf_size'
.eom
***** END CMOS MUX info: spice_model_name=mux_2level, size=5 *****
.subckt mux_1level_tapbuf_size2_basis in0 in1 out sel0 sel_inv0 svdd sgnd
Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size'
Xcpt_1 in1 out sel_inv0 sel0 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size'
.eom
***** CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2, structure: one-level *****
.subckt mux_1level_tapbuf_size2 in0 in1 out sram0 sram_inv0 svdd sgnd
Xmux_basis_no0 mux2_l1_in0 mux2_l1_in1 mux2_l0_in0 sram0 sram_inv0 svdd sgnd mux_1level_tapbuf_size2_basis
Xinv0 in0 mux2_l1_in0 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size'
Xinv1 in1 mux2_l1_in1 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size'
Xbuf_out mux2_l0_in0 out svdd sgnd tapbuf_level3_f4
.eom
***** END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2 *****
.subckt mux_1level_tapbuf_size3_basis in0 in1 in2 out sel0 sel_inv0 sel1 sel_inv1 sel2 sel_inv2 svdd sgnd
Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size'
Xcpt_1 in1 out sel1 sel_inv1 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size'
Xcpt_2 in2 out sel2 sel_inv2 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size'
.eom
***** CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3, structure: one-level *****
.subckt mux_1level_tapbuf_size3 in0 in1 in2 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 svdd sgnd
Xmux_basis_no0 mux2_l1_in0 mux2_l1_in1 mux2_l1_in2 mux2_l0_in0 sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 svdd sgnd mux_1level_tapbuf_size3_basis
Xinv0 in0 mux2_l1_in0 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size'
Xinv1 in1 mux2_l1_in1 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size'
Xinv2 in2 mux2_l1_in2 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size'
Xbuf_out mux2_l0_in0 out svdd sgnd tapbuf_level3_f4
.eom
***** END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3 *****

25
examples/spice_test_example_1/subckt/nmos_pmos.sp
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@ -1,25 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Standard and I/O NMOS and PMOS *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
* Standard NMOS
.subckt vpr_nmos drain gate source bulk L=nl W=wn
M1 drain gate source bulk nch L=L W=W
.eom vpr_nmos
* Standard PMOS
.subckt vpr_pmos drain gate source bulk L=pl W=wp
M1 drain gate source bulk pch L=L W=W
.eom vpr_pmos
* I/O NMOS
.subckt vpr_io_nmos drain gate source bulk L=io_nl W=io_wn
M1 drain gate source bulk nch_25 L=L W=W
.eom vpr_io_nmos
* I/O PMOS
.subckt vpr_io_pmos drain gate source bulk L=io_pl W=io_wp
M1 drain gate source bulk pch_25 L=L W=W
.eom vpr_io_pmos

20
examples/spice_test_example_1/subckt/routing_header.sp
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*****************************
* FPGA SPICE Netlist *
* Description: Header file *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
.include './spice_test_example_1/subckt/cby_1_1.sp'
.include './spice_test_example_1/subckt/cby_0_1.sp'
.include './spice_test_example_1/subckt/cbx_1_1.sp'
.include './spice_test_example_1/subckt/cbx_1_0.sp'
.include './spice_test_example_1/subckt/sb_1_1.sp'
.include './spice_test_example_1/subckt/sb_1_0.sp'
.include './spice_test_example_1/subckt/sb_0_1.sp'
.include './spice_test_example_1/subckt/sb_0_0.sp'
.include './spice_test_example_1/subckt/chany_1_1.sp'
.include './spice_test_example_1/subckt/chany_0_1.sp'
.include './spice_test_example_1/subckt/chanx_1_1.sp'
.include './spice_test_example_1/subckt/chanx_1_0.sp'

220
examples/spice_test_example_1/subckt/sb_0_0.sp
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@ -1,220 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Switch Block [0][0] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Switch Box[0][0] Sub-Circuit *****
.subckt sb[0][0]
***** Inputs/outputs of top side *****
+ chany[0][1]_out[0] chany[0][1]_in[1] chany[0][1]_out[2] chany[0][1]_in[3] chany[0][1]_out[4] chany[0][1]_in[5] chany[0][1]_out[6] chany[0][1]_in[7] chany[0][1]_out[8] chany[0][1]_in[9] chany[0][1]_out[10] chany[0][1]_in[11] chany[0][1]_out[12] chany[0][1]_in[13] chany[0][1]_out[14] chany[0][1]_in[15] chany[0][1]_out[16] chany[0][1]_in[17] chany[0][1]_out[18] chany[0][1]_in[19] chany[0][1]_out[20] chany[0][1]_in[21] chany[0][1]_out[22] chany[0][1]_in[23] chany[0][1]_out[24] chany[0][1]_in[25] chany[0][1]_out[26] chany[0][1]_in[27] chany[0][1]_out[28] chany[0][1]_in[29]
+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15]
+ ***** Inputs/outputs of right side *****
+ chanx[1][0]_out[0] chanx[1][0]_in[1] chanx[1][0]_out[2] chanx[1][0]_in[3] chanx[1][0]_out[4] chanx[1][0]_in[5] chanx[1][0]_out[6] chanx[1][0]_in[7] chanx[1][0]_out[8] chanx[1][0]_in[9] chanx[1][0]_out[10] chanx[1][0]_in[11] chanx[1][0]_out[12] chanx[1][0]_in[13] chanx[1][0]_out[14] chanx[1][0]_in[15] chanx[1][0]_out[16] chanx[1][0]_in[17] chanx[1][0]_out[18] chanx[1][0]_in[19] chanx[1][0]_out[20] chanx[1][0]_in[21] chanx[1][0]_out[22] chanx[1][0]_in[23] chanx[1][0]_out[24] chanx[1][0]_in[25] chanx[1][0]_out[26] chanx[1][0]_in[27] chanx[1][0]_out[28] chanx[1][0]_in[29]
+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15]
+ ***** Inputs/outputs of bottom side *****
+
+
+ ***** Inputs/outputs of left side *****
+
+
+ svdd sgnd
***** top side Multiplexers *****
Xmux_1level_tapbuf_size3[1] grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][15] chanx[1][0]_in[3] chany[0][1]_out[0] sram[73]->outb sram[73]->out sram[74]->out sram[74]->outb sram[75]->out sram[75]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[1], level=1, select_path_id=0. *****
*****100*****
Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[73]->out) 0
.nodeset V(sram[73]->outb) vsp
Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[74]->out) 0
.nodeset V(sram[74]->outb) vsp
Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[75]->out) 0
.nodeset V(sram[75]->outb) vsp
Xmux_1level_tapbuf_size2[2] grid[0][1]_pin[0][1][1] chanx[1][0]_in[5] chany[0][1]_out[2] sram[76]->outb sram[76]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[2], level=1, select_path_id=0. *****
*****1*****
Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[76]->out) 0
.nodeset V(sram[76]->outb) vsp
Xmux_1level_tapbuf_size2[3] grid[0][1]_pin[0][1][3] chanx[1][0]_in[7] chany[0][1]_out[4] sram[77]->outb sram[77]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[3], level=1, select_path_id=0. *****
*****1*****
Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[77]->out) 0
.nodeset V(sram[77]->outb) vsp
Xmux_1level_tapbuf_size2[4] grid[0][1]_pin[0][1][3] chanx[1][0]_in[9] chany[0][1]_out[6] sram[78]->outb sram[78]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[4], level=1, select_path_id=0. *****
*****1*****
Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[78]->out) 0
.nodeset V(sram[78]->outb) vsp
Xmux_1level_tapbuf_size2[5] grid[0][1]_pin[0][1][5] chanx[1][0]_in[11] chany[0][1]_out[8] sram[79]->outb sram[79]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[5], level=1, select_path_id=0. *****
*****1*****
Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[79]->out) 0
.nodeset V(sram[79]->outb) vsp
Xmux_1level_tapbuf_size2[6] grid[0][1]_pin[0][1][5] chanx[1][0]_in[13] chany[0][1]_out[10] sram[80]->outb sram[80]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[6], level=1, select_path_id=0. *****
*****1*****
Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[80]->out) 0
.nodeset V(sram[80]->outb) vsp
Xmux_1level_tapbuf_size2[7] grid[0][1]_pin[0][1][7] chanx[1][0]_in[15] chany[0][1]_out[12] sram[81]->outb sram[81]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[7], level=1, select_path_id=0. *****
*****1*****
Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[81]->out) 0
.nodeset V(sram[81]->outb) vsp
Xmux_1level_tapbuf_size2[8] grid[0][1]_pin[0][1][7] chanx[1][0]_in[17] chany[0][1]_out[14] sram[82]->outb sram[82]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[8], level=1, select_path_id=0. *****
*****1*****
Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[82]->out) 0
.nodeset V(sram[82]->outb) vsp
Xmux_1level_tapbuf_size2[9] grid[0][1]_pin[0][1][9] chanx[1][0]_in[19] chany[0][1]_out[16] sram[83]->outb sram[83]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[9], level=1, select_path_id=0. *****
*****1*****
Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[83]->out) 0
.nodeset V(sram[83]->outb) vsp
Xmux_1level_tapbuf_size2[10] grid[0][1]_pin[0][1][9] chanx[1][0]_in[21] chany[0][1]_out[18] sram[84]->outb sram[84]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[10], level=1, select_path_id=0. *****
*****1*****
Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[84]->out) 0
.nodeset V(sram[84]->outb) vsp
Xmux_1level_tapbuf_size2[11] grid[0][1]_pin[0][1][11] chanx[1][0]_in[23] chany[0][1]_out[20] sram[85]->outb sram[85]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[11], level=1, select_path_id=0. *****
*****1*****
Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[85]->out) 0
.nodeset V(sram[85]->outb) vsp
Xmux_1level_tapbuf_size2[12] grid[0][1]_pin[0][1][11] chanx[1][0]_in[25] chany[0][1]_out[22] sram[86]->outb sram[86]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[12], level=1, select_path_id=0. *****
*****1*****
Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[86]->out) 0
.nodeset V(sram[86]->outb) vsp
Xmux_1level_tapbuf_size2[13] grid[0][1]_pin[0][1][13] chanx[1][0]_in[27] chany[0][1]_out[24] sram[87]->outb sram[87]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[13], level=1, select_path_id=0. *****
*****1*****
Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[87]->out) 0
.nodeset V(sram[87]->outb) vsp
Xmux_1level_tapbuf_size2[14] grid[0][1]_pin[0][1][13] chanx[1][0]_in[29] chany[0][1]_out[26] sram[88]->outb sram[88]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[14], level=1, select_path_id=0. *****
*****1*****
Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[88]->out) 0
.nodeset V(sram[88]->outb) vsp
Xmux_1level_tapbuf_size2[15] grid[0][1]_pin[0][1][15] chanx[1][0]_in[1] chany[0][1]_out[28] sram[89]->outb sram[89]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[15], level=1, select_path_id=0. *****
*****1*****
Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[89]->out) 0
.nodeset V(sram[89]->outb) vsp
***** right side Multiplexers *****
Xmux_1level_tapbuf_size3[16] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][15] chany[0][1]_in[29] chanx[1][0]_out[0] sram[90]->outb sram[90]->out sram[91]->out sram[91]->outb sram[92]->out sram[92]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[16], level=1, select_path_id=0. *****
*****100*****
Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[90]->out) 0
.nodeset V(sram[90]->outb) vsp
Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[91]->out) 0
.nodeset V(sram[91]->outb) vsp
Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[92]->out) 0
.nodeset V(sram[92]->outb) vsp
Xmux_1level_tapbuf_size2[17] grid[1][0]_pin[0][0][1] chany[0][1]_in[1] chanx[1][0]_out[2] sram[93]->outb sram[93]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[17], level=1, select_path_id=0. *****
*****1*****
Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[93]->out) 0
.nodeset V(sram[93]->outb) vsp
Xmux_1level_tapbuf_size2[18] grid[1][0]_pin[0][0][3] chany[0][1]_in[3] chanx[1][0]_out[4] sram[94]->outb sram[94]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[18], level=1, select_path_id=0. *****
*****1*****
Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[94]->out) 0
.nodeset V(sram[94]->outb) vsp
Xmux_1level_tapbuf_size2[19] grid[1][0]_pin[0][0][3] chany[0][1]_in[5] chanx[1][0]_out[6] sram[95]->outb sram[95]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[19], level=1, select_path_id=0. *****
*****1*****
Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[95]->out) 0
.nodeset V(sram[95]->outb) vsp
Xmux_1level_tapbuf_size2[20] grid[1][0]_pin[0][0][5] chany[0][1]_in[7] chanx[1][0]_out[8] sram[96]->outb sram[96]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[20], level=1, select_path_id=0. *****
*****1*****
Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[96]->out) 0
.nodeset V(sram[96]->outb) vsp
Xmux_1level_tapbuf_size2[21] grid[1][0]_pin[0][0][5] chany[0][1]_in[9] chanx[1][0]_out[10] sram[97]->outb sram[97]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[21], level=1, select_path_id=0. *****
*****1*****
Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[97]->out) 0
.nodeset V(sram[97]->outb) vsp
Xmux_1level_tapbuf_size2[22] grid[1][0]_pin[0][0][7] chany[0][1]_in[11] chanx[1][0]_out[12] sram[98]->outb sram[98]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[22], level=1, select_path_id=0. *****
*****1*****
Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[98]->out) 0
.nodeset V(sram[98]->outb) vsp
Xmux_1level_tapbuf_size2[23] grid[1][0]_pin[0][0][7] chany[0][1]_in[13] chanx[1][0]_out[14] sram[99]->outb sram[99]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[23], level=1, select_path_id=0. *****
*****1*****
Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[99]->out) 0
.nodeset V(sram[99]->outb) vsp
Xmux_1level_tapbuf_size2[24] grid[1][0]_pin[0][0][9] chany[0][1]_in[15] chanx[1][0]_out[16] sram[100]->outb sram[100]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[24], level=1, select_path_id=0. *****
*****1*****
Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[100]->out) 0
.nodeset V(sram[100]->outb) vsp
Xmux_1level_tapbuf_size2[25] grid[1][0]_pin[0][0][9] chany[0][1]_in[17] chanx[1][0]_out[18] sram[101]->outb sram[101]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[25], level=1, select_path_id=0. *****
*****1*****
Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[101]->out) 0
.nodeset V(sram[101]->outb) vsp
Xmux_1level_tapbuf_size2[26] grid[1][0]_pin[0][0][11] chany[0][1]_in[19] chanx[1][0]_out[20] sram[102]->outb sram[102]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[26], level=1, select_path_id=0. *****
*****1*****
Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[102]->out) 0
.nodeset V(sram[102]->outb) vsp
Xmux_1level_tapbuf_size2[27] grid[1][0]_pin[0][0][11] chany[0][1]_in[21] chanx[1][0]_out[22] sram[103]->outb sram[103]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[27], level=1, select_path_id=0. *****
*****1*****
Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[103]->out) 0
.nodeset V(sram[103]->outb) vsp
Xmux_1level_tapbuf_size2[28] grid[1][0]_pin[0][0][13] chany[0][1]_in[23] chanx[1][0]_out[24] sram[104]->outb sram[104]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[28], level=1, select_path_id=0. *****
*****1*****
Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[104]->out) 0
.nodeset V(sram[104]->outb) vsp
Xmux_1level_tapbuf_size2[29] grid[1][0]_pin[0][0][13] chany[0][1]_in[25] chanx[1][0]_out[26] sram[105]->outb sram[105]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[29], level=1, select_path_id=0. *****
*****1*****
Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[105]->out) 0
.nodeset V(sram[105]->outb) vsp
Xmux_1level_tapbuf_size2[30] grid[1][0]_pin[0][0][15] chany[0][1]_in[27] chanx[1][0]_out[28] sram[106]->outb sram[106]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[30], level=1, select_path_id=0. *****
*****1*****
Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[106]->out) 0
.nodeset V(sram[106]->outb) vsp
***** bottom side Multiplexers *****
***** left side Multiplexers *****
.eom

232
examples/spice_test_example_1/subckt/sb_0_1.sp
View File

@ -1,232 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Switch Block [0][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Switch Box[0][1] Sub-Circuit *****
.subckt sb[0][1]
***** Inputs/outputs of top side *****
+
+
+ ***** Inputs/outputs of right side *****
+ chanx[1][1]_out[0] chanx[1][1]_in[1] chanx[1][1]_out[2] chanx[1][1]_in[3] chanx[1][1]_out[4] chanx[1][1]_in[5] chanx[1][1]_out[6] chanx[1][1]_in[7] chanx[1][1]_out[8] chanx[1][1]_in[9] chanx[1][1]_out[10] chanx[1][1]_in[11] chanx[1][1]_out[12] chanx[1][1]_in[13] chanx[1][1]_out[14] chanx[1][1]_in[15] chanx[1][1]_out[16] chanx[1][1]_in[17] chanx[1][1]_out[18] chanx[1][1]_in[19] chanx[1][1]_out[20] chanx[1][1]_in[21] chanx[1][1]_out[22] chanx[1][1]_in[23] chanx[1][1]_out[24] chanx[1][1]_in[25] chanx[1][1]_out[26] chanx[1][1]_in[27] chanx[1][1]_out[28] chanx[1][1]_in[29]
+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4]
+ ***** Inputs/outputs of bottom side *****
+ chany[0][1]_in[0] chany[0][1]_out[1] chany[0][1]_in[2] chany[0][1]_out[3] chany[0][1]_in[4] chany[0][1]_out[5] chany[0][1]_in[6] chany[0][1]_out[7] chany[0][1]_in[8] chany[0][1]_out[9] chany[0][1]_in[10] chany[0][1]_out[11] chany[0][1]_in[12] chany[0][1]_out[13] chany[0][1]_in[14] chany[0][1]_out[15] chany[0][1]_in[16] chany[0][1]_out[17] chany[0][1]_in[18] chany[0][1]_out[19] chany[0][1]_in[20] chany[0][1]_out[21] chany[0][1]_in[22] chany[0][1]_out[23] chany[0][1]_in[24] chany[0][1]_out[25] chany[0][1]_in[26] chany[0][1]_out[27] chany[0][1]_in[28] chany[0][1]_out[29]
+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15]
+ ***** Inputs/outputs of left side *****
+
+
+ svdd sgnd
***** top side Multiplexers *****
***** right side Multiplexers *****
Xmux_1level_tapbuf_size3[31] grid[1][1]_pin[0][0][4] grid[1][2]_pin[0][2][13] chany[0][1]_in[26] chanx[1][1]_out[0] sram[107]->outb sram[107]->out sram[108]->out sram[108]->outb sram[109]->out sram[109]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[31], level=1, select_path_id=0. *****
*****100*****
Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[107]->out) 0
.nodeset V(sram[107]->outb) vsp
Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[108]->out) 0
.nodeset V(sram[108]->outb) vsp
Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[109]->out) 0
.nodeset V(sram[109]->outb) vsp
Xmux_1level_tapbuf_size3[32] grid[1][1]_pin[0][0][4] grid[1][2]_pin[0][2][15] chany[0][1]_in[24] chanx[1][1]_out[2] sram[110]->outb sram[110]->out sram[111]->out sram[111]->outb sram[112]->out sram[112]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[32], level=1, select_path_id=0. *****
*****100*****
Xsram[110] sram->in sram[110]->out sram[110]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[110]->out) 0
.nodeset V(sram[110]->outb) vsp
Xsram[111] sram->in sram[111]->out sram[111]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[111]->out) 0
.nodeset V(sram[111]->outb) vsp
Xsram[112] sram->in sram[112]->out sram[112]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[112]->out) 0
.nodeset V(sram[112]->outb) vsp
Xmux_1level_tapbuf_size3[33] grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][15] chany[0][1]_in[22] chanx[1][1]_out[4] sram[113]->outb sram[113]->out sram[114]->out sram[114]->outb sram[115]->out sram[115]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[33], level=1, select_path_id=0. *****
*****100*****
Xsram[113] sram->in sram[113]->out sram[113]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[113]->out) 0
.nodeset V(sram[113]->outb) vsp
Xsram[114] sram->in sram[114]->out sram[114]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[114]->out) 0
.nodeset V(sram[114]->outb) vsp
Xsram[115] sram->in sram[115]->out sram[115]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[115]->out) 0
.nodeset V(sram[115]->outb) vsp
Xmux_1level_tapbuf_size2[34] grid[1][2]_pin[0][2][1] chany[0][1]_in[20] chanx[1][1]_out[6] sram[116]->outb sram[116]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[34], level=1, select_path_id=0. *****
*****1*****
Xsram[116] sram->in sram[116]->out sram[116]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[116]->out) 0
.nodeset V(sram[116]->outb) vsp
Xmux_1level_tapbuf_size2[35] grid[1][2]_pin[0][2][3] chany[0][1]_in[18] chanx[1][1]_out[8] sram[117]->outb sram[117]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[35], level=1, select_path_id=0. *****
*****1*****
Xsram[117] sram->in sram[117]->out sram[117]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[117]->out) 0
.nodeset V(sram[117]->outb) vsp
Xmux_1level_tapbuf_size2[36] grid[1][2]_pin[0][2][3] chany[0][1]_in[16] chanx[1][1]_out[10] sram[118]->outb sram[118]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[36], level=1, select_path_id=0. *****
*****1*****
Xsram[118] sram->in sram[118]->out sram[118]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[118]->out) 0
.nodeset V(sram[118]->outb) vsp
Xmux_1level_tapbuf_size2[37] grid[1][2]_pin[0][2][5] chany[0][1]_in[14] chanx[1][1]_out[12] sram[119]->outb sram[119]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[37], level=1, select_path_id=0. *****
*****1*****
Xsram[119] sram->in sram[119]->out sram[119]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[119]->out) 0
.nodeset V(sram[119]->outb) vsp
Xmux_1level_tapbuf_size2[38] grid[1][2]_pin[0][2][5] chany[0][1]_in[12] chanx[1][1]_out[14] sram[120]->outb sram[120]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[38], level=1, select_path_id=0. *****
*****1*****
Xsram[120] sram->in sram[120]->out sram[120]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[120]->out) 0
.nodeset V(sram[120]->outb) vsp
Xmux_1level_tapbuf_size2[39] grid[1][2]_pin[0][2][7] chany[0][1]_in[10] chanx[1][1]_out[16] sram[121]->outb sram[121]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[39], level=1, select_path_id=0. *****
*****1*****
Xsram[121] sram->in sram[121]->out sram[121]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[121]->out) 0
.nodeset V(sram[121]->outb) vsp
Xmux_1level_tapbuf_size2[40] grid[1][2]_pin[0][2][7] chany[0][1]_in[8] chanx[1][1]_out[18] sram[122]->outb sram[122]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[40], level=1, select_path_id=0. *****
*****1*****
Xsram[122] sram->in sram[122]->out sram[122]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[122]->out) 0
.nodeset V(sram[122]->outb) vsp
Xmux_1level_tapbuf_size2[41] grid[1][2]_pin[0][2][9] chany[0][1]_in[6] chanx[1][1]_out[20] sram[123]->outb sram[123]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[41], level=1, select_path_id=0. *****
*****1*****
Xsram[123] sram->in sram[123]->out sram[123]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[123]->out) 0
.nodeset V(sram[123]->outb) vsp
Xmux_1level_tapbuf_size2[42] grid[1][2]_pin[0][2][9] chany[0][1]_in[4] chanx[1][1]_out[22] sram[124]->outb sram[124]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[42], level=1, select_path_id=0. *****
*****1*****
Xsram[124] sram->in sram[124]->out sram[124]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[124]->out) 0
.nodeset V(sram[124]->outb) vsp
Xmux_1level_tapbuf_size2[43] grid[1][2]_pin[0][2][11] chany[0][1]_in[2] chanx[1][1]_out[24] sram[125]->outb sram[125]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[43], level=1, select_path_id=0. *****
*****1*****
Xsram[125] sram->in sram[125]->out sram[125]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[125]->out) 0
.nodeset V(sram[125]->outb) vsp
Xmux_1level_tapbuf_size2[44] grid[1][2]_pin[0][2][11] chany[0][1]_in[0] chanx[1][1]_out[26] sram[126]->outb sram[126]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[44], level=1, select_path_id=0. *****
*****1*****
Xsram[126] sram->in sram[126]->out sram[126]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[126]->out) 0
.nodeset V(sram[126]->outb) vsp
Xmux_1level_tapbuf_size2[45] grid[1][2]_pin[0][2][13] chany[0][1]_in[28] chanx[1][1]_out[28] sram[127]->outb sram[127]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[45], level=1, select_path_id=0. *****
*****1*****
Xsram[127] sram->in sram[127]->out sram[127]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[127]->out) 0
.nodeset V(sram[127]->outb) vsp
***** bottom side Multiplexers *****
Xmux_1level_tapbuf_size3[46] grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][15] chanx[1][1]_in[27] chany[0][1]_out[1] sram[128]->outb sram[128]->out sram[129]->out sram[129]->outb sram[130]->out sram[130]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[46], level=1, select_path_id=0. *****
*****100*****
Xsram[128] sram->in sram[128]->out sram[128]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[128]->out) 0
.nodeset V(sram[128]->outb) vsp
Xsram[129] sram->in sram[129]->out sram[129]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[129]->out) 0
.nodeset V(sram[129]->outb) vsp
Xsram[130] sram->in sram[130]->out sram[130]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[130]->out) 0
.nodeset V(sram[130]->outb) vsp
Xmux_1level_tapbuf_size2[47] grid[0][1]_pin[0][1][1] chanx[1][1]_in[25] chany[0][1]_out[3] sram[131]->outb sram[131]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[47], level=1, select_path_id=0. *****
*****1*****
Xsram[131] sram->in sram[131]->out sram[131]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[131]->out) 0
.nodeset V(sram[131]->outb) vsp
Xmux_1level_tapbuf_size2[48] grid[0][1]_pin[0][1][3] chanx[1][1]_in[23] chany[0][1]_out[5] sram[132]->outb sram[132]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[48], level=1, select_path_id=0. *****
*****1*****
Xsram[132] sram->in sram[132]->out sram[132]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[132]->out) 0
.nodeset V(sram[132]->outb) vsp
Xmux_1level_tapbuf_size2[49] grid[0][1]_pin[0][1][3] chanx[1][1]_in[21] chany[0][1]_out[7] sram[133]->outb sram[133]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[49], level=1, select_path_id=0. *****
*****1*****
Xsram[133] sram->in sram[133]->out sram[133]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[133]->out) 0
.nodeset V(sram[133]->outb) vsp
Xmux_1level_tapbuf_size2[50] grid[0][1]_pin[0][1][5] chanx[1][1]_in[19] chany[0][1]_out[9] sram[134]->outb sram[134]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[50], level=1, select_path_id=0. *****
*****1*****
Xsram[134] sram->in sram[134]->out sram[134]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[134]->out) 0
.nodeset V(sram[134]->outb) vsp
Xmux_1level_tapbuf_size2[51] grid[0][1]_pin[0][1][5] chanx[1][1]_in[17] chany[0][1]_out[11] sram[135]->outb sram[135]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[51], level=1, select_path_id=0. *****
*****1*****
Xsram[135] sram->in sram[135]->out sram[135]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[135]->out) 0
.nodeset V(sram[135]->outb) vsp
Xmux_1level_tapbuf_size2[52] grid[0][1]_pin[0][1][7] chanx[1][1]_in[15] chany[0][1]_out[13] sram[136]->outb sram[136]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[52], level=1, select_path_id=0. *****
*****1*****
Xsram[136] sram->in sram[136]->out sram[136]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[136]->out) 0
.nodeset V(sram[136]->outb) vsp
Xmux_1level_tapbuf_size2[53] grid[0][1]_pin[0][1][7] chanx[1][1]_in[13] chany[0][1]_out[15] sram[137]->outb sram[137]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[53], level=1, select_path_id=0. *****
*****1*****
Xsram[137] sram->in sram[137]->out sram[137]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[137]->out) 0
.nodeset V(sram[137]->outb) vsp
Xmux_1level_tapbuf_size2[54] grid[0][1]_pin[0][1][9] chanx[1][1]_in[11] chany[0][1]_out[17] sram[138]->outb sram[138]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[54], level=1, select_path_id=0. *****
*****1*****
Xsram[138] sram->in sram[138]->out sram[138]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[138]->out) 0
.nodeset V(sram[138]->outb) vsp
Xmux_1level_tapbuf_size2[55] grid[0][1]_pin[0][1][9] chanx[1][1]_in[9] chany[0][1]_out[19] sram[139]->outb sram[139]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[55], level=1, select_path_id=0. *****
*****1*****
Xsram[139] sram->in sram[139]->out sram[139]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[139]->out) 0
.nodeset V(sram[139]->outb) vsp
Xmux_1level_tapbuf_size2[56] grid[0][1]_pin[0][1][11] chanx[1][1]_in[7] chany[0][1]_out[21] sram[140]->outb sram[140]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[56], level=1, select_path_id=0. *****
*****1*****
Xsram[140] sram->in sram[140]->out sram[140]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[140]->out) 0
.nodeset V(sram[140]->outb) vsp
Xmux_1level_tapbuf_size2[57] grid[0][1]_pin[0][1][11] chanx[1][1]_in[5] chany[0][1]_out[23] sram[141]->outb sram[141]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[57], level=1, select_path_id=0. *****
*****1*****
Xsram[141] sram->in sram[141]->out sram[141]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[141]->out) 0
.nodeset V(sram[141]->outb) vsp
Xmux_1level_tapbuf_size2[58] grid[0][1]_pin[0][1][13] chanx[1][1]_in[3] chany[0][1]_out[25] sram[142]->outb sram[142]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[58], level=1, select_path_id=0. *****
*****1*****
Xsram[142] sram->in sram[142]->out sram[142]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[142]->out) 0
.nodeset V(sram[142]->outb) vsp
Xmux_1level_tapbuf_size2[59] grid[0][1]_pin[0][1][13] chanx[1][1]_in[1] chany[0][1]_out[27] sram[143]->out sram[143]->outb svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[59], level=1, select_path_id=1. *****
*****0*****
Xsram[143] sram->in sram[143]->out sram[143]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[143]->out) 0
.nodeset V(sram[143]->outb) vsp
Xmux_1level_tapbuf_size2[60] grid[0][1]_pin[0][1][15] chanx[1][1]_in[29] chany[0][1]_out[29] sram[144]->outb sram[144]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[60], level=1, select_path_id=0. *****
*****1*****
Xsram[144] sram->in sram[144]->out sram[144]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[144]->out) 0
.nodeset V(sram[144]->outb) vsp
***** left side Multiplexers *****
.eom

220
examples/spice_test_example_1/subckt/sb_1_0.sp
View File

@ -1,220 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Switch Block [1][0] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Switch Box[1][0] Sub-Circuit *****
.subckt sb[1][0]
***** Inputs/outputs of top side *****
+ chany[1][1]_out[0] chany[1][1]_in[1] chany[1][1]_out[2] chany[1][1]_in[3] chany[1][1]_out[4] chany[1][1]_in[5] chany[1][1]_out[6] chany[1][1]_in[7] chany[1][1]_out[8] chany[1][1]_in[9] chany[1][1]_out[10] chany[1][1]_in[11] chany[1][1]_out[12] chany[1][1]_in[13] chany[1][1]_out[14] chany[1][1]_in[15] chany[1][1]_out[16] chany[1][1]_in[17] chany[1][1]_out[18] chany[1][1]_in[19] chany[1][1]_out[20] chany[1][1]_in[21] chany[1][1]_out[22] chany[1][1]_in[23] chany[1][1]_out[24] chany[1][1]_in[25] chany[1][1]_out[26] chany[1][1]_in[27] chany[1][1]_out[28] chany[1][1]_in[29]
+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15]
+ ***** Inputs/outputs of right side *****
+
+
+ ***** Inputs/outputs of bottom side *****
+
+
+ ***** Inputs/outputs of left side *****
+ chanx[1][0]_in[0] chanx[1][0]_out[1] chanx[1][0]_in[2] chanx[1][0]_out[3] chanx[1][0]_in[4] chanx[1][0]_out[5] chanx[1][0]_in[6] chanx[1][0]_out[7] chanx[1][0]_in[8] chanx[1][0]_out[9] chanx[1][0]_in[10] chanx[1][0]_out[11] chanx[1][0]_in[12] chanx[1][0]_out[13] chanx[1][0]_in[14] chanx[1][0]_out[15] chanx[1][0]_in[16] chanx[1][0]_out[17] chanx[1][0]_in[18] chanx[1][0]_out[19] chanx[1][0]_in[20] chanx[1][0]_out[21] chanx[1][0]_in[22] chanx[1][0]_out[23] chanx[1][0]_in[24] chanx[1][0]_out[25] chanx[1][0]_in[26] chanx[1][0]_out[27] chanx[1][0]_in[28] chanx[1][0]_out[29]
+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15]
+ svdd sgnd
***** top side Multiplexers *****
Xmux_1level_tapbuf_size3[61] grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][15] chanx[1][0]_in[0] chany[1][1]_out[0] sram[145]->outb sram[145]->out sram[146]->out sram[146]->outb sram[147]->out sram[147]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[61], level=1, select_path_id=0. *****
*****100*****
Xsram[145] sram->in sram[145]->out sram[145]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[145]->out) 0
.nodeset V(sram[145]->outb) vsp
Xsram[146] sram->in sram[146]->out sram[146]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[146]->out) 0
.nodeset V(sram[146]->outb) vsp
Xsram[147] sram->in sram[147]->out sram[147]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[147]->out) 0
.nodeset V(sram[147]->outb) vsp
Xmux_1level_tapbuf_size2[62] grid[2][1]_pin[0][3][1] chanx[1][0]_in[28] chany[1][1]_out[2] sram[148]->outb sram[148]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[62], level=1, select_path_id=0. *****
*****1*****
Xsram[148] sram->in sram[148]->out sram[148]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[148]->out) 0
.nodeset V(sram[148]->outb) vsp
Xmux_1level_tapbuf_size2[63] grid[2][1]_pin[0][3][3] chanx[1][0]_in[26] chany[1][1]_out[4] sram[149]->outb sram[149]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[63], level=1, select_path_id=0. *****
*****1*****
Xsram[149] sram->in sram[149]->out sram[149]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[149]->out) 0
.nodeset V(sram[149]->outb) vsp
Xmux_1level_tapbuf_size2[64] grid[2][1]_pin[0][3][3] chanx[1][0]_in[24] chany[1][1]_out[6] sram[150]->outb sram[150]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[64], level=1, select_path_id=0. *****
*****1*****
Xsram[150] sram->in sram[150]->out sram[150]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[150]->out) 0
.nodeset V(sram[150]->outb) vsp
Xmux_1level_tapbuf_size2[65] grid[2][1]_pin[0][3][5] chanx[1][0]_in[22] chany[1][1]_out[8] sram[151]->outb sram[151]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[65], level=1, select_path_id=0. *****
*****1*****
Xsram[151] sram->in sram[151]->out sram[151]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[151]->out) 0
.nodeset V(sram[151]->outb) vsp
Xmux_1level_tapbuf_size2[66] grid[2][1]_pin[0][3][5] chanx[1][0]_in[20] chany[1][1]_out[10] sram[152]->outb sram[152]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[66], level=1, select_path_id=0. *****
*****1*****
Xsram[152] sram->in sram[152]->out sram[152]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[152]->out) 0
.nodeset V(sram[152]->outb) vsp
Xmux_1level_tapbuf_size2[67] grid[2][1]_pin[0][3][7] chanx[1][0]_in[18] chany[1][1]_out[12] sram[153]->outb sram[153]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[67], level=1, select_path_id=0. *****
*****1*****
Xsram[153] sram->in sram[153]->out sram[153]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[153]->out) 0
.nodeset V(sram[153]->outb) vsp
Xmux_1level_tapbuf_size2[68] grid[2][1]_pin[0][3][7] chanx[1][0]_in[16] chany[1][1]_out[14] sram[154]->outb sram[154]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[68], level=1, select_path_id=0. *****
*****1*****
Xsram[154] sram->in sram[154]->out sram[154]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[154]->out) 0
.nodeset V(sram[154]->outb) vsp
Xmux_1level_tapbuf_size2[69] grid[2][1]_pin[0][3][9] chanx[1][0]_in[14] chany[1][1]_out[16] sram[155]->outb sram[155]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[69], level=1, select_path_id=0. *****
*****1*****
Xsram[155] sram->in sram[155]->out sram[155]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[155]->out) 0
.nodeset V(sram[155]->outb) vsp
Xmux_1level_tapbuf_size2[70] grid[2][1]_pin[0][3][9] chanx[1][0]_in[12] chany[1][1]_out[18] sram[156]->outb sram[156]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[70], level=1, select_path_id=0. *****
*****1*****
Xsram[156] sram->in sram[156]->out sram[156]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[156]->out) 0
.nodeset V(sram[156]->outb) vsp
Xmux_1level_tapbuf_size2[71] grid[2][1]_pin[0][3][11] chanx[1][0]_in[10] chany[1][1]_out[20] sram[157]->outb sram[157]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[71], level=1, select_path_id=0. *****
*****1*****
Xsram[157] sram->in sram[157]->out sram[157]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[157]->out) 0
.nodeset V(sram[157]->outb) vsp
Xmux_1level_tapbuf_size2[72] grid[2][1]_pin[0][3][11] chanx[1][0]_in[8] chany[1][1]_out[22] sram[158]->outb sram[158]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[72], level=1, select_path_id=0. *****
*****1*****
Xsram[158] sram->in sram[158]->out sram[158]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[158]->out) 0
.nodeset V(sram[158]->outb) vsp
Xmux_1level_tapbuf_size2[73] grid[2][1]_pin[0][3][13] chanx[1][0]_in[6] chany[1][1]_out[24] sram[159]->outb sram[159]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[73], level=1, select_path_id=0. *****
*****1*****
Xsram[159] sram->in sram[159]->out sram[159]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[159]->out) 0
.nodeset V(sram[159]->outb) vsp
Xmux_1level_tapbuf_size2[74] grid[2][1]_pin[0][3][13] chanx[1][0]_in[4] chany[1][1]_out[26] sram[160]->outb sram[160]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[74], level=1, select_path_id=0. *****
*****1*****
Xsram[160] sram->in sram[160]->out sram[160]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[160]->out) 0
.nodeset V(sram[160]->outb) vsp
Xmux_1level_tapbuf_size2[75] grid[2][1]_pin[0][3][15] chanx[1][0]_in[2] chany[1][1]_out[28] sram[161]->outb sram[161]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[75], level=1, select_path_id=0. *****
*****1*****
Xsram[161] sram->in sram[161]->out sram[161]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[161]->out) 0
.nodeset V(sram[161]->outb) vsp
***** right side Multiplexers *****
***** bottom side Multiplexers *****
***** left side Multiplexers *****
Xmux_1level_tapbuf_size3[76] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][15] chany[1][1]_in[1] chanx[1][0]_out[1] sram[162]->outb sram[162]->out sram[163]->out sram[163]->outb sram[164]->out sram[164]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[76], level=1, select_path_id=0. *****
*****100*****
Xsram[162] sram->in sram[162]->out sram[162]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[162]->out) 0
.nodeset V(sram[162]->outb) vsp
Xsram[163] sram->in sram[163]->out sram[163]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[163]->out) 0
.nodeset V(sram[163]->outb) vsp
Xsram[164] sram->in sram[164]->out sram[164]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[164]->out) 0
.nodeset V(sram[164]->outb) vsp
Xmux_1level_tapbuf_size2[77] grid[1][0]_pin[0][0][1] chany[1][1]_in[29] chanx[1][0]_out[3] sram[165]->outb sram[165]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[77], level=1, select_path_id=0. *****
*****1*****
Xsram[165] sram->in sram[165]->out sram[165]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[165]->out) 0
.nodeset V(sram[165]->outb) vsp
Xmux_1level_tapbuf_size2[78] grid[1][0]_pin[0][0][3] chany[1][1]_in[27] chanx[1][0]_out[5] sram[166]->outb sram[166]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[78], level=1, select_path_id=0. *****
*****1*****
Xsram[166] sram->in sram[166]->out sram[166]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[166]->out) 0
.nodeset V(sram[166]->outb) vsp
Xmux_1level_tapbuf_size2[79] grid[1][0]_pin[0][0][3] chany[1][1]_in[25] chanx[1][0]_out[7] sram[167]->outb sram[167]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[79], level=1, select_path_id=0. *****
*****1*****
Xsram[167] sram->in sram[167]->out sram[167]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[167]->out) 0
.nodeset V(sram[167]->outb) vsp
Xmux_1level_tapbuf_size2[80] grid[1][0]_pin[0][0][5] chany[1][1]_in[23] chanx[1][0]_out[9] sram[168]->outb sram[168]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[80], level=1, select_path_id=0. *****
*****1*****
Xsram[168] sram->in sram[168]->out sram[168]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[168]->out) 0
.nodeset V(sram[168]->outb) vsp
Xmux_1level_tapbuf_size2[81] grid[1][0]_pin[0][0][5] chany[1][1]_in[21] chanx[1][0]_out[11] sram[169]->outb sram[169]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[81], level=1, select_path_id=0. *****
*****1*****
Xsram[169] sram->in sram[169]->out sram[169]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[169]->out) 0
.nodeset V(sram[169]->outb) vsp
Xmux_1level_tapbuf_size2[82] grid[1][0]_pin[0][0][7] chany[1][1]_in[19] chanx[1][0]_out[13] sram[170]->outb sram[170]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[82], level=1, select_path_id=0. *****
*****1*****
Xsram[170] sram->in sram[170]->out sram[170]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[170]->out) 0
.nodeset V(sram[170]->outb) vsp
Xmux_1level_tapbuf_size2[83] grid[1][0]_pin[0][0][7] chany[1][1]_in[17] chanx[1][0]_out[15] sram[171]->outb sram[171]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[83], level=1, select_path_id=0. *****
*****1*****
Xsram[171] sram->in sram[171]->out sram[171]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[171]->out) 0
.nodeset V(sram[171]->outb) vsp
Xmux_1level_tapbuf_size2[84] grid[1][0]_pin[0][0][9] chany[1][1]_in[15] chanx[1][0]_out[17] sram[172]->outb sram[172]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[84], level=1, select_path_id=0. *****
*****1*****
Xsram[172] sram->in sram[172]->out sram[172]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[172]->out) 0
.nodeset V(sram[172]->outb) vsp
Xmux_1level_tapbuf_size2[85] grid[1][0]_pin[0][0][9] chany[1][1]_in[13] chanx[1][0]_out[19] sram[173]->outb sram[173]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[85], level=1, select_path_id=0. *****
*****1*****
Xsram[173] sram->in sram[173]->out sram[173]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[173]->out) 0
.nodeset V(sram[173]->outb) vsp
Xmux_1level_tapbuf_size2[86] grid[1][0]_pin[0][0][11] chany[1][1]_in[11] chanx[1][0]_out[21] sram[174]->outb sram[174]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[86], level=1, select_path_id=0. *****
*****1*****
Xsram[174] sram->in sram[174]->out sram[174]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[174]->out) 0
.nodeset V(sram[174]->outb) vsp
Xmux_1level_tapbuf_size2[87] grid[1][0]_pin[0][0][11] chany[1][1]_in[9] chanx[1][0]_out[23] sram[175]->outb sram[175]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[87], level=1, select_path_id=0. *****
*****1*****
Xsram[175] sram->in sram[175]->out sram[175]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[175]->out) 0
.nodeset V(sram[175]->outb) vsp
Xmux_1level_tapbuf_size2[88] grid[1][0]_pin[0][0][13] chany[1][1]_in[7] chanx[1][0]_out[25] sram[176]->outb sram[176]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[88], level=1, select_path_id=0. *****
*****1*****
Xsram[176] sram->in sram[176]->out sram[176]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[176]->out) 0
.nodeset V(sram[176]->outb) vsp
Xmux_1level_tapbuf_size2[89] grid[1][0]_pin[0][0][13] chany[1][1]_in[5] chanx[1][0]_out[27] sram[177]->outb sram[177]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[89], level=1, select_path_id=0. *****
*****1*****
Xsram[177] sram->in sram[177]->out sram[177]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[177]->out) 0
.nodeset V(sram[177]->outb) vsp
Xmux_1level_tapbuf_size2[90] grid[1][0]_pin[0][0][15] chany[1][1]_in[3] chanx[1][0]_out[29] sram[178]->outb sram[178]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[90], level=1, select_path_id=0. *****
*****1*****
Xsram[178] sram->in sram[178]->out sram[178]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[178]->out) 0
.nodeset V(sram[178]->outb) vsp
.eom

232
examples/spice_test_example_1/subckt/sb_1_1.sp
View File

@ -1,232 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Switch Block [1][1] in FPGA *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
***** Switch Box[1][1] Sub-Circuit *****
.subckt sb[1][1]
***** Inputs/outputs of top side *****
+
+
+ ***** Inputs/outputs of right side *****
+
+
+ ***** Inputs/outputs of bottom side *****
+ chany[1][1]_in[0] chany[1][1]_out[1] chany[1][1]_in[2] chany[1][1]_out[3] chany[1][1]_in[4] chany[1][1]_out[5] chany[1][1]_in[6] chany[1][1]_out[7] chany[1][1]_in[8] chany[1][1]_out[9] chany[1][1]_in[10] chany[1][1]_out[11] chany[1][1]_in[12] chany[1][1]_out[13] chany[1][1]_in[14] chany[1][1]_out[15] chany[1][1]_in[16] chany[1][1]_out[17] chany[1][1]_in[18] chany[1][1]_out[19] chany[1][1]_in[20] chany[1][1]_out[21] chany[1][1]_in[22] chany[1][1]_out[23] chany[1][1]_in[24] chany[1][1]_out[25] chany[1][1]_in[26] chany[1][1]_out[27] chany[1][1]_in[28] chany[1][1]_out[29]
+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15]
+ ***** Inputs/outputs of left side *****
+ chanx[1][1]_in[0] chanx[1][1]_out[1] chanx[1][1]_in[2] chanx[1][1]_out[3] chanx[1][1]_in[4] chanx[1][1]_out[5] chanx[1][1]_in[6] chanx[1][1]_out[7] chanx[1][1]_in[8] chanx[1][1]_out[9] chanx[1][1]_in[10] chanx[1][1]_out[11] chanx[1][1]_in[12] chanx[1][1]_out[13] chanx[1][1]_in[14] chanx[1][1]_out[15] chanx[1][1]_in[16] chanx[1][1]_out[17] chanx[1][1]_in[18] chanx[1][1]_out[19] chanx[1][1]_in[20] chanx[1][1]_out[21] chanx[1][1]_in[22] chanx[1][1]_out[23] chanx[1][1]_in[24] chanx[1][1]_out[25] chanx[1][1]_in[26] chanx[1][1]_out[27] chanx[1][1]_in[28] chanx[1][1]_out[29]
+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4]
+ svdd sgnd
***** top side Multiplexers *****
***** right side Multiplexers *****
***** bottom side Multiplexers *****
Xmux_1level_tapbuf_size3[91] grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][15] chanx[1][1]_in[2] chany[1][1]_out[1] sram[179]->outb sram[179]->out sram[180]->out sram[180]->outb sram[181]->out sram[181]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[91], level=1, select_path_id=0. *****
*****100*****
Xsram[179] sram->in sram[179]->out sram[179]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[179]->out) 0
.nodeset V(sram[179]->outb) vsp
Xsram[180] sram->in sram[180]->out sram[180]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[180]->out) 0
.nodeset V(sram[180]->outb) vsp
Xsram[181] sram->in sram[181]->out sram[181]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[181]->out) 0
.nodeset V(sram[181]->outb) vsp
Xmux_1level_tapbuf_size2[92] grid[2][1]_pin[0][3][1] chanx[1][1]_in[4] chany[1][1]_out[3] sram[182]->outb sram[182]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[92], level=1, select_path_id=0. *****
*****1*****
Xsram[182] sram->in sram[182]->out sram[182]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[182]->out) 0
.nodeset V(sram[182]->outb) vsp
Xmux_1level_tapbuf_size2[93] grid[2][1]_pin[0][3][3] chanx[1][1]_in[6] chany[1][1]_out[5] sram[183]->outb sram[183]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[93], level=1, select_path_id=0. *****
*****1*****
Xsram[183] sram->in sram[183]->out sram[183]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[183]->out) 0
.nodeset V(sram[183]->outb) vsp
Xmux_1level_tapbuf_size2[94] grid[2][1]_pin[0][3][3] chanx[1][1]_in[8] chany[1][1]_out[7] sram[184]->outb sram[184]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[94], level=1, select_path_id=0. *****
*****1*****
Xsram[184] sram->in sram[184]->out sram[184]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[184]->out) 0
.nodeset V(sram[184]->outb) vsp
Xmux_1level_tapbuf_size2[95] grid[2][1]_pin[0][3][5] chanx[1][1]_in[10] chany[1][1]_out[9] sram[185]->outb sram[185]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[95], level=1, select_path_id=0. *****
*****1*****
Xsram[185] sram->in sram[185]->out sram[185]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[185]->out) 0
.nodeset V(sram[185]->outb) vsp
Xmux_1level_tapbuf_size2[96] grid[2][1]_pin[0][3][5] chanx[1][1]_in[12] chany[1][1]_out[11] sram[186]->outb sram[186]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[96], level=1, select_path_id=0. *****
*****1*****
Xsram[186] sram->in sram[186]->out sram[186]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[186]->out) 0
.nodeset V(sram[186]->outb) vsp
Xmux_1level_tapbuf_size2[97] grid[2][1]_pin[0][3][7] chanx[1][1]_in[14] chany[1][1]_out[13] sram[187]->outb sram[187]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[97], level=1, select_path_id=0. *****
*****1*****
Xsram[187] sram->in sram[187]->out sram[187]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[187]->out) 0
.nodeset V(sram[187]->outb) vsp
Xmux_1level_tapbuf_size2[98] grid[2][1]_pin[0][3][7] chanx[1][1]_in[16] chany[1][1]_out[15] sram[188]->outb sram[188]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[98], level=1, select_path_id=0. *****
*****1*****
Xsram[188] sram->in sram[188]->out sram[188]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[188]->out) 0
.nodeset V(sram[188]->outb) vsp
Xmux_1level_tapbuf_size2[99] grid[2][1]_pin[0][3][9] chanx[1][1]_in[18] chany[1][1]_out[17] sram[189]->outb sram[189]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[99], level=1, select_path_id=0. *****
*****1*****
Xsram[189] sram->in sram[189]->out sram[189]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[189]->out) 0
.nodeset V(sram[189]->outb) vsp
Xmux_1level_tapbuf_size2[100] grid[2][1]_pin[0][3][9] chanx[1][1]_in[20] chany[1][1]_out[19] sram[190]->outb sram[190]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[100], level=1, select_path_id=0. *****
*****1*****
Xsram[190] sram->in sram[190]->out sram[190]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[190]->out) 0
.nodeset V(sram[190]->outb) vsp
Xmux_1level_tapbuf_size2[101] grid[2][1]_pin[0][3][11] chanx[1][1]_in[22] chany[1][1]_out[21] sram[191]->outb sram[191]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[101], level=1, select_path_id=0. *****
*****1*****
Xsram[191] sram->in sram[191]->out sram[191]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[191]->out) 0
.nodeset V(sram[191]->outb) vsp
Xmux_1level_tapbuf_size2[102] grid[2][1]_pin[0][3][11] chanx[1][1]_in[24] chany[1][1]_out[23] sram[192]->outb sram[192]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[102], level=1, select_path_id=0. *****
*****1*****
Xsram[192] sram->in sram[192]->out sram[192]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[192]->out) 0
.nodeset V(sram[192]->outb) vsp
Xmux_1level_tapbuf_size2[103] grid[2][1]_pin[0][3][13] chanx[1][1]_in[26] chany[1][1]_out[25] sram[193]->outb sram[193]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[103], level=1, select_path_id=0. *****
*****1*****
Xsram[193] sram->in sram[193]->out sram[193]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[193]->out) 0
.nodeset V(sram[193]->outb) vsp
Xmux_1level_tapbuf_size2[104] grid[2][1]_pin[0][3][13] chanx[1][1]_in[28] chany[1][1]_out[27] sram[194]->outb sram[194]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[104], level=1, select_path_id=0. *****
*****1*****
Xsram[194] sram->in sram[194]->out sram[194]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[194]->out) 0
.nodeset V(sram[194]->outb) vsp
Xmux_1level_tapbuf_size2[105] grid[2][1]_pin[0][3][15] chanx[1][1]_in[0] chany[1][1]_out[29] sram[195]->outb sram[195]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[105], level=1, select_path_id=0. *****
*****1*****
Xsram[195] sram->in sram[195]->out sram[195]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[195]->out) 0
.nodeset V(sram[195]->outb) vsp
***** left side Multiplexers *****
Xmux_1level_tapbuf_size3[106] grid[1][1]_pin[0][0][4] grid[1][2]_pin[0][2][13] chany[1][1]_in[28] chanx[1][1]_out[1] sram[196]->out sram[196]->outb sram[197]->outb sram[197]->out sram[198]->out sram[198]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[106], level=1, select_path_id=1. *****
*****010*****
Xsram[196] sram->in sram[196]->out sram[196]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[196]->out) 0
.nodeset V(sram[196]->outb) vsp
Xsram[197] sram->in sram[197]->out sram[197]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[197]->out) 0
.nodeset V(sram[197]->outb) vsp
Xsram[198] sram->in sram[198]->out sram[198]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[198]->out) 0
.nodeset V(sram[198]->outb) vsp
Xmux_1level_tapbuf_size3[107] grid[1][1]_pin[0][0][4] grid[1][2]_pin[0][2][15] chany[1][1]_in[0] chanx[1][1]_out[3] sram[199]->outb sram[199]->out sram[200]->out sram[200]->outb sram[201]->out sram[201]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[107], level=1, select_path_id=0. *****
*****100*****
Xsram[199] sram->in sram[199]->out sram[199]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[199]->out) 0
.nodeset V(sram[199]->outb) vsp
Xsram[200] sram->in sram[200]->out sram[200]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[200]->out) 0
.nodeset V(sram[200]->outb) vsp
Xsram[201] sram->in sram[201]->out sram[201]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[201]->out) 0
.nodeset V(sram[201]->outb) vsp
Xmux_1level_tapbuf_size3[108] grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][15] chany[1][1]_in[2] chanx[1][1]_out[5] sram[202]->outb sram[202]->out sram[203]->out sram[203]->outb sram[204]->out sram[204]->outb svdd sgnd mux_1level_tapbuf_size3
***** SRAM bits for MUX[108], level=1, select_path_id=0. *****
*****100*****
Xsram[202] sram->in sram[202]->out sram[202]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[202]->out) 0
.nodeset V(sram[202]->outb) vsp
Xsram[203] sram->in sram[203]->out sram[203]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[203]->out) 0
.nodeset V(sram[203]->outb) vsp
Xsram[204] sram->in sram[204]->out sram[204]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[204]->out) 0
.nodeset V(sram[204]->outb) vsp
Xmux_1level_tapbuf_size2[109] grid[1][2]_pin[0][2][1] chany[1][1]_in[4] chanx[1][1]_out[7] sram[205]->outb sram[205]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[109], level=1, select_path_id=0. *****
*****1*****
Xsram[205] sram->in sram[205]->out sram[205]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[205]->out) 0
.nodeset V(sram[205]->outb) vsp
Xmux_1level_tapbuf_size2[110] grid[1][2]_pin[0][2][3] chany[1][1]_in[6] chanx[1][1]_out[9] sram[206]->outb sram[206]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[110], level=1, select_path_id=0. *****
*****1*****
Xsram[206] sram->in sram[206]->out sram[206]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[206]->out) 0
.nodeset V(sram[206]->outb) vsp
Xmux_1level_tapbuf_size2[111] grid[1][2]_pin[0][2][3] chany[1][1]_in[8] chanx[1][1]_out[11] sram[207]->outb sram[207]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[111], level=1, select_path_id=0. *****
*****1*****
Xsram[207] sram->in sram[207]->out sram[207]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[207]->out) 0
.nodeset V(sram[207]->outb) vsp
Xmux_1level_tapbuf_size2[112] grid[1][2]_pin[0][2][5] chany[1][1]_in[10] chanx[1][1]_out[13] sram[208]->outb sram[208]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[112], level=1, select_path_id=0. *****
*****1*****
Xsram[208] sram->in sram[208]->out sram[208]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[208]->out) 0
.nodeset V(sram[208]->outb) vsp
Xmux_1level_tapbuf_size2[113] grid[1][2]_pin[0][2][5] chany[1][1]_in[12] chanx[1][1]_out[15] sram[209]->outb sram[209]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[113], level=1, select_path_id=0. *****
*****1*****
Xsram[209] sram->in sram[209]->out sram[209]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[209]->out) 0
.nodeset V(sram[209]->outb) vsp
Xmux_1level_tapbuf_size2[114] grid[1][2]_pin[0][2][7] chany[1][1]_in[14] chanx[1][1]_out[17] sram[210]->outb sram[210]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[114], level=1, select_path_id=0. *****
*****1*****
Xsram[210] sram->in sram[210]->out sram[210]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[210]->out) 0
.nodeset V(sram[210]->outb) vsp
Xmux_1level_tapbuf_size2[115] grid[1][2]_pin[0][2][7] chany[1][1]_in[16] chanx[1][1]_out[19] sram[211]->outb sram[211]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[115], level=1, select_path_id=0. *****
*****1*****
Xsram[211] sram->in sram[211]->out sram[211]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[211]->out) 0
.nodeset V(sram[211]->outb) vsp
Xmux_1level_tapbuf_size2[116] grid[1][2]_pin[0][2][9] chany[1][1]_in[18] chanx[1][1]_out[21] sram[212]->outb sram[212]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[116], level=1, select_path_id=0. *****
*****1*****
Xsram[212] sram->in sram[212]->out sram[212]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[212]->out) 0
.nodeset V(sram[212]->outb) vsp
Xmux_1level_tapbuf_size2[117] grid[1][2]_pin[0][2][9] chany[1][1]_in[20] chanx[1][1]_out[23] sram[213]->outb sram[213]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[117], level=1, select_path_id=0. *****
*****1*****
Xsram[213] sram->in sram[213]->out sram[213]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[213]->out) 0
.nodeset V(sram[213]->outb) vsp
Xmux_1level_tapbuf_size2[118] grid[1][2]_pin[0][2][11] chany[1][1]_in[22] chanx[1][1]_out[25] sram[214]->outb sram[214]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[118], level=1, select_path_id=0. *****
*****1*****
Xsram[214] sram->in sram[214]->out sram[214]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[214]->out) 0
.nodeset V(sram[214]->outb) vsp
Xmux_1level_tapbuf_size2[119] grid[1][2]_pin[0][2][11] chany[1][1]_in[24] chanx[1][1]_out[27] sram[215]->outb sram[215]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[119], level=1, select_path_id=0. *****
*****1*****
Xsram[215] sram->in sram[215]->out sram[215]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[215]->out) 0
.nodeset V(sram[215]->outb) vsp
Xmux_1level_tapbuf_size2[120] grid[1][2]_pin[0][2][13] chany[1][1]_in[26] chanx[1][1]_out[29] sram[216]->outb sram[216]->out svdd sgnd mux_1level_tapbuf_size2
***** SRAM bits for MUX[120], level=1, select_path_id=0. *****
*****1*****
Xsram[216] sram->in sram[216]->out sram[216]->outb gvdd_sram_sbs sgnd sram6T
.nodeset V(sram[216]->out) 0
.nodeset V(sram[216]->outb) vsp
.eom

50
examples/spice_test_example_1/subckt/wires.sp
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@ -1,50 +0,0 @@
*****************************
* FPGA SPICE Netlist *
* Description: Wires *
* Author: Xifan TANG *
* Organization: EPFL/IC/LSI *
* Date: Thu Nov 15 14:26:04 2018
*
*****************************
* Wire, spice_model_name=direct_interc
.subckt direct_interc in out svdd sgnd
Rshortcut in out 0
.eom
* Wire models for segments in routing
* Wire, spice_model_name=chan_segment
.subckt chan_segment_seg0 in out mid_out svdd sgnd
Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2'
Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2'
Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2'
Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2'
* Connect the output of middle point
Vmid_out_ckt pie_wire_in0_inter mid_out 0
Rin in pie_wire_in0 0
Rout pie_wire_in1 out 0
.eom
* Wire, spice_model_name=chan_segment
.subckt chan_segment_seg1 in out mid_out svdd sgnd
Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2'
Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2'
Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2'
Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2'
* Connect the output of middle point
Vmid_out_ckt pie_wire_in0_inter mid_out 0
Rin in pie_wire_in0 0
Rout pie_wire_in1 out 0
.eom
* Wire, spice_model_name=chan_segment
.subckt chan_segment_seg2 in out mid_out svdd sgnd
Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2'
Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2'
Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2'
Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2'
* Connect the output of middle point
Vmid_out_ckt pie_wire_in0_inter mid_out 0
Rin in pie_wire_in0 0
Rout pie_wire_in1 out 0
.eom

1300
examples/spice_test_example_1/top_tb/example_1_top.sp
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2762
examples/spice_test_example_2/cb_mux_tb/example_2_cbx1_0_cbmux_testbench.sp
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examples/spice_test_example_2/cb_mux_tb/example_2_cbx1_1_cbmux_testbench.sp
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examples/spice_test_example_2/cb_mux_tb/example_2_cby0_1_cbmux_testbench.sp
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2754
examples/spice_test_example_2/cb_mux_tb/example_2_cby1_1_cbmux_testbench.sp
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examples/spice_test_example_2/cb_tb/example_2_cbx1_0_cb_testbench.sp
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1182
examples/spice_test_example_2/cb_tb/example_2_cbx1_1_cb_testbench.sp
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