tangxifan
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af0646260c
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[Test] Bug fix in pin constraints
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2021-01-19 17:44:05 -07:00 |
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tangxifan
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186f2f1968
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[Test] Use pin constraint in multi-clock test case
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2021-01-19 17:42:40 -07:00 |
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tangxifan
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e17a5cbbf2
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[Test] Rename to pin constraint to comply with libpcf requirement
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2021-01-19 15:52:51 -07:00 |
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tangxifan
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ab25e1af5f
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[Test] Add example XML for net mapping between benchmark to FPGA
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2021-01-19 09:29:21 -07:00 |
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tangxifan
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ea9d6bfe91
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[Flow] Update the design constraint file to follow bug fix in parser
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2021-01-17 10:41:01 -07:00 |
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tangxifan
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dd74f05a31
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[Test] Add repack constraints to tests
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2021-01-17 10:35:36 -07:00 |
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tangxifan
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d0e05b3575
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[Lib] Now use pb_type in design constraints instead of physical tiles
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2021-01-16 21:35:43 -07:00 |
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tangxifan
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8578c1ecac
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[Flow] Rename the design contraint file syntax
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2021-01-16 15:35:13 -07:00 |
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tangxifan
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9154cfdeec
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[Flow] Add comments for the design constraint file
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2021-01-16 15:34:01 -07:00 |
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tangxifan
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6ab0f71896
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[Test] Add an example of repack pin constraints file
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2021-01-16 14:38:39 -07:00 |
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tangxifan
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3b5394b45f
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[Test] Now use dedicated simulation settings for the 4-clock architecture
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2021-01-14 15:40:16 -07:00 |
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tangxifan
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314e458632
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[Test] Update task configuration to use post-yosys .v file in verification
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2021-01-13 15:42:45 -07:00 |
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tangxifan
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91f12071d5
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[Test] Use counter4bit in the multi-clock test
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2021-01-13 13:34:59 -07:00 |
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tangxifan
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250adb01cf
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[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
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2021-01-13 13:18:31 -07:00 |
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tangxifan
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99e2a068fb
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[Test] Add a test case for multi-clock
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2021-01-12 18:06:25 -07:00 |
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tangxifan
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e58e1e86c2
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[Test] Update test case to use new shell script
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2021-01-10 11:09:10 -07:00 |
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tangxifan
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1c68e43acf
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[Test] Add new test case for registerable I/O architecture
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2021-01-10 11:00:21 -07:00 |
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tangxifan
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43418cd76b
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[Test] Deploy pipeplined and2 to test cases
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2021-01-10 10:28:22 -07:00 |
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tangxifan
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06af30ef10
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[Test] Add test case for the SCFF usage in configuration chain
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2021-01-04 17:30:19 -07:00 |
Lalit Sharma
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2484721a45
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Updating write_verilog_testbench by removing option explicit_port_mapping
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2020-12-22 22:17:50 -08:00 |
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Lalit Sharma
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3c9e4919b4
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Updating variable name in ys to call BLIF output file.
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2020-12-18 03:18:46 -08:00 |
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Lalit Sharma
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891e2f8aa3
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Adding arch xml from SOFA repo. Also updating the script with its file location
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2020-12-16 04:14:18 -08:00 |
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Lalit Sharma
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0ee3efb306
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Adding a testcase to run yosys quicklogic flow
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2020-12-10 02:41:43 -08:00 |
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tangxifan
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6b50bbf986
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Merge pull request #134 from lnis-uofu/ganesh_dev
Support Delay Customization in OpenFPGA Task Configuration File
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2020-12-08 15:32:48 -07:00 |
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tangxifan
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0cb8457e21
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[Test] Add test case for tileable I/O
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2020-12-04 16:02:47 -07:00 |
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tangxifan
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179b0ce304
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[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
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2020-11-30 18:11:47 -07:00 |
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tangxifan
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27a480b5f8
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[Test] arch name fix in the test case
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2020-11-30 17:45:54 -07:00 |
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tangxifan
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a1d3b439d3
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[Test] Add a new test case to define a global reset port from a global tile port
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2020-11-30 17:19:12 -07:00 |
ganeshgore
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7db030018c
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[Bug] Fixed variable file location
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2020-11-25 22:44:40 -07:00 |
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tangxifan
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b8559249dc
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[Test] Bug fix in task configuration file
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2020-11-25 22:23:27 -07:00 |
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tangxifan
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26e4db56ad
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[Test] Add new test case for the native fracturable LUT4
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2020-11-25 22:21:23 -07:00 |
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ganeshgore
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fefba0db59
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Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
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2020-11-25 17:29:53 -07:00 |
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ganeshgore
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1d993296d8
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[Flow] Example of using test variable in task conf
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2020-11-25 17:25:12 -07:00 |
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tangxifan
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617f7e3062
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[Flow] disable signal initialization for behavioral verilog generation
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2020-11-22 21:13:22 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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845436fa71
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[Test] Add sequential benchmark for global tile clock test case
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2020-11-17 14:34:54 -07:00 |
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tangxifan
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485258a9ea
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[Test] Add test case for global clock from tiles
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2020-11-10 19:24:25 -07:00 |
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tangxifan
|
6b48ee7f0b
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[Test] Add new test for caravel io support
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2020-11-04 20:58:40 -07:00 |
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tangxifan
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61376a2979
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[Test] Add test cases for various tile organization
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2020-11-04 16:32:52 -07:00 |
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tangxifan
|
65ca53ac98
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[Test] Update test case with the new arch name
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2020-11-02 13:16:42 -07:00 |
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tangxifan
|
bc00dee858
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[Test] Add test case for embedded I/O
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2020-11-02 12:28:25 -07:00 |
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tangxifan
|
4c14428400
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[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
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2020-10-30 10:50:00 -06:00 |
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tangxifan
|
ca7d43275d
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[Test] Add test case for multi_region configuration frame
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2020-10-30 10:48:29 -06:00 |
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tangxifan
|
241ebf054a
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[Test] Add a test case for validating fast configuration techniques on multi-region memory banks
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2020-10-29 16:29:46 -06:00 |
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tangxifan
|
ff386001c4
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[Test] Add openfpga task for multi-region memory banks
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2020-10-29 13:56:32 -06:00 |
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tangxifan
|
179ae355d0
|
[Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops
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2020-10-13 12:02:26 -06:00 |
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tangxifan
|
97c3bf7ea0
|
[Test] Add a test case for non-constant input multiplexers
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2020-10-13 11:58:17 -06:00 |
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tangxifan
|
570b494df7
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[Test] Add test case for using GND signal as constant input for routing multiplexers
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2020-10-13 11:38:54 -06:00 |
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tangxifan
|
dc68c52d0a
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[Test] Now use a light architecture to speed up the test case runtime
|
2020-10-12 12:53:34 -06:00 |
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tangxifan
|
8941e38613
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[Test] Enable verification in the new test case
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2020-10-12 12:50:08 -06:00 |