tangxifan
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373566416c
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-16 16:47:21 -07:00 |
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tangxifan
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1c2192a87d
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[engine] fixed a few bugs
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2022-09-12 16:50:32 -07:00 |
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tangxifan
|
0d6e4e3979
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[test] add a new example for the repack options
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2022-09-12 16:21:49 -07:00 |
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tangxifan
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56619f9a47
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-07 15:04:05 -07:00 |
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tangxifan
|
477e2119d7
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[test] remove abs paths in golden outputs without time stamps
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2022-09-06 15:24:43 -07:00 |
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tangxifan
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561d0a6545
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[test] add more test case to track golden outputs for representative fpga sizes
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2022-09-06 14:04:23 -07:00 |
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tangxifan
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c691eb0e95
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Merge branch 'master' into vtr_upgrade
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2022-09-01 15:54:14 -07:00 |
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tangxifan
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51dc082bd4
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[test] force a fixed routing chan W for no time stamp test case
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2022-09-01 15:02:40 -07:00 |
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tangxifan
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d86eb04c5d
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[test] now no timestamp test case covers gsb files
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2022-09-01 14:03:51 -07:00 |
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tangxifan
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dbacee8a0a
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[script] turn off equivalent for soft adder architecture as we do not expect any routing optimization
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2022-08-27 20:25:50 -07:00 |
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tangxifan
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ef3381a1b2
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[script] also turn off pb_pin_fixup in vpr for quicklogic tests
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2022-08-27 20:07:49 -07:00 |
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tangxifan
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b9fade4c76
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[script] turn off the pb_pin_fix_up in vpr run for mcnc and vtr benchmarks
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2022-08-27 20:04:29 -07:00 |
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tangxifan
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e9d6e7e38a
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[engine] update vtr and enable more debugging info
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2022-08-27 19:12:43 -07:00 |
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tangxifan
|
ec31e124b7
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[test] reworked test case on pcf2place
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2022-07-28 11:51:56 -07:00 |
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tangxifan
|
23f98d6a3b
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[engine] fixed a few bugs
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2022-07-26 13:55:29 -07:00 |
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tangxifan
|
353de4546f
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[test] add 'write_fabric_io_info' command to test cases
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2022-07-26 13:48:54 -07:00 |
taoli4rs
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3762a3aae4
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Code clean up based on review.
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2022-07-20 14:34:44 -07:00 |
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taoli4rs
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cfc0d08060
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Add constrain_pin_location command in openfpga; add full flow test.
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2022-07-20 11:51:00 -07:00 |
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tangxifan
|
4b9431b132
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[test] avoid XML bitstream output when can go beyond github runners' disk space
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2022-05-25 18:45:26 +08:00 |
Ganesh Gore
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e845b62322
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Update regession tasks
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2022-05-05 01:46:19 -06:00 |
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tangxifan
|
5beefda3bd
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[Test] Add a new test case to validate the fix_pins option
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2022-04-13 15:55:21 +08:00 |
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tangxifan
|
576b9c2d8f
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[Script] Disable SDC writer in multiclock examples
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2022-03-20 11:05:29 +08:00 |
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tangxifan
|
c897a64ad5
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[Script] Add a new example script to test full testbenches using bus group features
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2022-02-18 15:37:42 -08:00 |
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tangxifan
|
a4d5172b7c
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[Test] Fixed bugs that causes VPR failed
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2022-02-18 12:31:29 -08:00 |
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tangxifan
|
73e6ee964d
|
[Script] Add a new example script showing how to use bus group features
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2022-02-18 12:25:34 -08:00 |
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tangxifan
|
074811a612
|
[Script] Now counter benchmarks should pass on the implicit verilog test case
|
2022-02-15 16:47:14 -08:00 |
|
tangxifan
|
1370be0817
|
[Script] Fixing bugs
|
2022-02-15 16:44:51 -08:00 |
|
tangxifan
|
8be0868a3b
|
[Test] Update test case which uses counter benchmarks: adding pin constraints
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2022-02-15 16:29:06 -08:00 |
|
tangxifan
|
d0fe8d96fa
|
[Test] Update template scripts and assoicated test cases by offering more options
|
2022-02-14 16:03:48 -08:00 |
|
tangxifan
|
2fb1df11bb
|
[Script] Add a new example script
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2022-02-14 15:54:07 -08:00 |
|
tangxifan
|
1d3c9ff192
|
[Script] Adapt python scripts to support include directory
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2022-02-01 13:55:25 -08:00 |
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tangxifan
|
35c7968c98
|
[Script] Add a new example openfpga shell script
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2022-02-01 13:40:22 -08:00 |
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tangxifan
|
09ef516de8
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[Script] Tune OpenFPGA shell script to enable testing on relative paths
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2022-01-31 14:23:13 -08:00 |
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tangxifan
|
da8fc0f5d4
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[Test] Add a new test case to validate ``--use_relative_path``
|
2022-01-31 13:02:19 -08:00 |
|
tangxifan
|
e59ea91ad6
|
[Script] Fixed a bug which causes errors
|
2022-01-26 11:49:32 -08:00 |
|
tangxifan
|
f8ef3df560
|
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
|
2022-01-26 11:41:48 -08:00 |
|
tangxifan
|
5db049522d
|
[Script] Add an example script about write GSB
|
2022-01-26 11:22:23 -08:00 |
|
tangxifan
|
fedb1bd2e3
|
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
|
2022-01-25 16:41:36 -08:00 |
|
tangxifan
|
e4cfa2222f
|
[Script] Add an example script to test option ``--no_time_stamp``
|
2022-01-25 16:16:39 -08:00 |
|
tangxifan
|
ff264c00a2
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-31 11:51:34 -07:00 |
|
tangxifan
|
335347a74f
|
[Test] Bug fix
|
2021-10-30 15:48:25 -07:00 |
|
tangxifan
|
40d11a45d9
|
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
|
2021-10-30 14:49:56 -07:00 |
|
tangxifan
|
16de60e943
|
[Test] Turn off ACE2 run in bitstream generation only flows
|
2021-10-30 12:31:14 -07:00 |
|
tangxifan
|
4add9781d5
|
[Script] Add a new openfpga shell script for don't care bits outputting
|
2021-10-05 19:13:50 -07:00 |
|
tangxifan
|
f32ffb6d61
|
[Test] Bug fix
|
2021-06-29 18:51:28 -06:00 |
|
tangxifan
|
56b0428eba
|
[Misc] Bug fix
|
2021-06-29 18:48:19 -06:00 |
|
tangxifan
|
c6089385b0
|
[Misc] Bug fix
|
2021-06-29 18:34:41 -06:00 |
|
tangxifan
|
5f5a03f17f
|
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
|
2021-06-29 18:28:38 -06:00 |
|
tangxifan
|
4fb34642ca
|
[Script] Add a new example script for global tile clock running full testbench
|
2021-06-29 17:53:56 -06:00 |
|
tangxifan
|
9655bc35cb
|
[Script] Bug fix due to the full testbench generation changes
|
2021-06-29 17:04:19 -06:00 |